1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "ARMDisassembler.h" 13 #include "ARM.h" 14 #include "ARMRegisterInfo.h" 15 #include "MCTargetDesc/ARMAddressingModes.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "llvm/MC/EDInstInfo.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCExpr.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/Target/TargetRegistry.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/MemoryObject.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/raw_ostream.h" 26 27 // Pull DecodeStatus and its enum values into the global namespace. 28 typedef llvm::MCDisassembler::DecodeStatus DecodeStatus; 29 #define Success llvm::MCDisassembler::Success 30 #define Unpredictable llvm::MCDisassembler::SoftFail 31 #define Fail llvm::MCDisassembler::Fail 32 33 // Helper macro to perform setwise reduction of the current running status 34 // and another status, and return if the new status is Fail. 35 #define CHECK(S,X) do { \ 36 S = (DecodeStatus) ((int)S & (X)); \ 37 if (S == Fail) return Fail; \ 38 } while(0) 39 40 // Forward declare these because the autogenerated code will reference them. 41 // Definitions are further down. 42 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 43 uint64_t Address, const void *Decoder); 44 static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, 45 unsigned RegNo, uint64_t Address, 46 const void *Decoder); 47 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 48 uint64_t Address, const void *Decoder); 49 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 50 uint64_t Address, const void *Decoder); 51 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 52 uint64_t Address, const void *Decoder); 53 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 54 uint64_t Address, const void *Decoder); 55 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 56 uint64_t Address, const void *Decoder); 57 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 58 uint64_t Address, const void *Decoder); 59 static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, 60 unsigned RegNo, 61 uint64_t Address, 62 const void *Decoder); 63 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 64 uint64_t Address, const void *Decoder); 65 66 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 67 uint64_t Address, const void *Decoder); 68 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 69 uint64_t Address, const void *Decoder); 70 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 71 uint64_t Address, const void *Decoder); 72 static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 73 uint64_t Address, const void *Decoder); 74 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 75 uint64_t Address, const void *Decoder); 76 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 77 uint64_t Address, const void *Decoder); 78 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 79 uint64_t Address, const void *Decoder); 80 81 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 82 uint64_t Address, const void *Decoder); 83 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 84 uint64_t Address, const void *Decoder); 85 static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, 86 unsigned Insn, 87 uint64_t Address, 88 const void *Decoder); 89 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 90 uint64_t Address, const void *Decoder); 91 static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn, 92 uint64_t Address, const void *Decoder); 93 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 94 uint64_t Address, const void *Decoder); 95 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 96 uint64_t Address, const void *Decoder); 97 98 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 99 unsigned Insn, 100 uint64_t Adddress, 101 const void *Decoder); 102 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 103 uint64_t Address, const void *Decoder); 104 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 105 uint64_t Address, const void *Decoder); 106 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 107 uint64_t Address, const void *Decoder); 108 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 109 uint64_t Address, const void *Decoder); 110 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 111 uint64_t Address, const void *Decoder); 112 static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn, 113 uint64_t Address, const void *Decoder); 114 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 115 uint64_t Address, const void *Decoder); 116 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 117 uint64_t Address, const void *Decoder); 118 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 119 uint64_t Address, const void *Decoder); 120 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 121 uint64_t Address, const void *Decoder); 122 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 123 uint64_t Address, const void *Decoder); 124 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 125 uint64_t Address, const void *Decoder); 126 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 127 uint64_t Address, const void *Decoder); 128 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 129 uint64_t Address, const void *Decoder); 130 static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val, 131 uint64_t Address, const void *Decoder); 132 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 133 uint64_t Address, const void *Decoder); 134 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 135 uint64_t Address, const void *Decoder); 136 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 137 uint64_t Address, const void *Decoder); 138 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 139 uint64_t Address, const void *Decoder); 140 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 141 uint64_t Address, const void *Decoder); 142 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 143 uint64_t Address, const void *Decoder); 144 static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 145 uint64_t Address, const void *Decoder); 146 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 147 uint64_t Address, const void *Decoder); 148 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 149 uint64_t Address, const void *Decoder); 150 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 151 uint64_t Address, const void *Decoder); 152 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, 153 uint64_t Address, const void *Decoder); 154 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 155 uint64_t Address, const void *Decoder); 156 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 157 uint64_t Address, const void *Decoder); 158 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 159 uint64_t Address, const void *Decoder); 160 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 161 uint64_t Address, const void *Decoder); 162 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 163 uint64_t Address, const void *Decoder); 164 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 165 uint64_t Address, const void *Decoder); 166 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 167 uint64_t Address, const void *Decoder); 168 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 169 uint64_t Address, const void *Decoder); 170 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 171 uint64_t Address, const void *Decoder); 172 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 173 uint64_t Address, const void *Decoder); 174 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 175 uint64_t Address, const void *Decoder); 176 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 177 uint64_t Address, const void *Decoder); 178 179 180 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 181 uint64_t Address, const void *Decoder); 182 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 183 uint64_t Address, const void *Decoder); 184 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 185 uint64_t Address, const void *Decoder); 186 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 193 uint64_t Address, const void *Decoder); 194 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 195 uint64_t Address, const void *Decoder); 196 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 197 uint64_t Address, const void *Decoder); 198 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 199 uint64_t Address, const void *Decoder); 200 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 201 uint64_t Address, const void *Decoder); 202 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 203 uint64_t Address, const void *Decoder); 204 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 205 uint64_t Address, const void *Decoder); 206 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 207 uint64_t Address, const void *Decoder); 208 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 209 uint64_t Address, const void *Decoder); 210 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 211 uint64_t Address, const void *Decoder); 212 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 213 uint64_t Address, const void *Decoder); 214 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 215 uint64_t Address, const void *Decoder); 216 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 217 uint64_t Address, const void *Decoder); 218 static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 219 uint64_t Address, const void *Decoder); 220 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 221 uint64_t Address, const void *Decoder); 222 static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val, 223 uint64_t Address, const void *Decoder); 224 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 225 uint64_t Address, const void *Decoder); 226 227 #include "ARMGenDisassemblerTables.inc" 228 #include "ARMGenInstrInfo.inc" 229 #include "ARMGenEDInfo.inc" 230 231 using namespace llvm; 232 233 static MCDisassembler *createARMDisassembler(const Target &T) { 234 return new ARMDisassembler; 235 } 236 237 static MCDisassembler *createThumbDisassembler(const Target &T) { 238 return new ThumbDisassembler; 239 } 240 241 EDInstInfo *ARMDisassembler::getEDInfo() const { 242 return instInfoARM; 243 } 244 245 EDInstInfo *ThumbDisassembler::getEDInfo() const { 246 return instInfoARM; 247 } 248 249 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 250 const MemoryObject &Region, 251 uint64_t Address, 252 raw_ostream &os) const { 253 uint8_t bytes[4]; 254 255 // We want to read exactly 4 bytes of data. 256 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 257 return Fail; 258 259 // Encoded as a small-endian 32-bit word in the stream. 260 uint32_t insn = (bytes[3] << 24) | 261 (bytes[2] << 16) | 262 (bytes[1] << 8) | 263 (bytes[0] << 0); 264 265 // Calling the auto-generated decoder function. 266 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this); 267 if (result != Fail) { 268 Size = 4; 269 return result; 270 } 271 272 // Instructions that are shared between ARM and Thumb modes. 273 // FIXME: This shouldn't really exist. It's an artifact of the 274 // fact that we fail to encode a few instructions properly for Thumb. 275 MI.clear(); 276 result = decodeCommonInstruction32(MI, insn, Address, this); 277 if (result != Fail) { 278 Size = 4; 279 return result; 280 } 281 282 // VFP and NEON instructions, similarly, are shared between ARM 283 // and Thumb modes. 284 MI.clear(); 285 result = decodeVFPInstruction32(MI, insn, Address, this); 286 if (result != Fail) { 287 Size = 4; 288 return result; 289 } 290 291 MI.clear(); 292 result = decodeNEONDataInstruction32(MI, insn, Address, this); 293 if (result != Fail) { 294 Size = 4; 295 // Add a fake predicate operand, because we share these instruction 296 // definitions with Thumb2 where these instructions are predicable. 297 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail; 298 return result; 299 } 300 301 MI.clear(); 302 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this); 303 if (result != Fail) { 304 Size = 4; 305 // Add a fake predicate operand, because we share these instruction 306 // definitions with Thumb2 where these instructions are predicable. 307 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail; 308 return result; 309 } 310 311 MI.clear(); 312 result = decodeNEONDupInstruction32(MI, insn, Address, this); 313 if (result != Fail) { 314 Size = 4; 315 // Add a fake predicate operand, because we share these instruction 316 // definitions with Thumb2 where these instructions are predicable. 317 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail; 318 return result; 319 } 320 321 MI.clear(); 322 323 return Fail; 324 } 325 326 namespace llvm { 327 extern MCInstrDesc ARMInsts[]; 328 } 329 330 // Thumb1 instructions don't have explicit S bits. Rather, they 331 // implicitly set CPSR. Since it's not represented in the encoding, the 332 // auto-generated decoder won't inject the CPSR operand. We need to fix 333 // that as a post-pass. 334 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 335 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 336 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 337 MCInst::iterator I = MI.begin(); 338 for (unsigned i = 0; i < NumOps; ++i, ++I) { 339 if (I == MI.end()) break; 340 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 341 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 342 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 343 return; 344 } 345 } 346 347 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 348 } 349 350 // Most Thumb instructions don't have explicit predicates in the 351 // encoding, but rather get their predicates from IT context. We need 352 // to fix up the predicate operands using this context information as a 353 // post-pass. 354 void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 355 // A few instructions actually have predicates encoded in them. Don't 356 // try to overwrite it if we're seeing one of those. 357 switch (MI.getOpcode()) { 358 case ARM::tBcc: 359 case ARM::t2Bcc: 360 return; 361 default: 362 break; 363 } 364 365 // If we're in an IT block, base the predicate on that. Otherwise, 366 // assume a predicate of AL. 367 unsigned CC; 368 if (!ITBlock.empty()) { 369 CC = ITBlock.back(); 370 ITBlock.pop_back(); 371 } else 372 CC = ARMCC::AL; 373 374 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 375 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 376 MCInst::iterator I = MI.begin(); 377 for (unsigned i = 0; i < NumOps; ++i, ++I) { 378 if (I == MI.end()) break; 379 if (OpInfo[i].isPredicate()) { 380 I = MI.insert(I, MCOperand::CreateImm(CC)); 381 ++I; 382 if (CC == ARMCC::AL) 383 MI.insert(I, MCOperand::CreateReg(0)); 384 else 385 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 386 return; 387 } 388 } 389 390 I = MI.insert(I, MCOperand::CreateImm(CC)); 391 ++I; 392 if (CC == ARMCC::AL) 393 MI.insert(I, MCOperand::CreateReg(0)); 394 else 395 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 396 } 397 398 // Thumb VFP instructions are a special case. Because we share their 399 // encodings between ARM and Thumb modes, and they are predicable in ARM 400 // mode, the auto-generated decoder will give them an (incorrect) 401 // predicate operand. We need to rewrite these operands based on the IT 402 // context as a post-pass. 403 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 404 unsigned CC; 405 if (!ITBlock.empty()) { 406 CC = ITBlock.back(); 407 ITBlock.pop_back(); 408 } else 409 CC = ARMCC::AL; 410 411 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 412 MCInst::iterator I = MI.begin(); 413 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 414 if (OpInfo[i].isPredicate() ) { 415 I->setImm(CC); 416 ++I; 417 if (CC == ARMCC::AL) 418 I->setReg(0); 419 else 420 I->setReg(ARM::CPSR); 421 return; 422 } 423 } 424 } 425 426 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 427 const MemoryObject &Region, 428 uint64_t Address, 429 raw_ostream &os) const { 430 uint8_t bytes[4]; 431 432 // We want to read exactly 2 bytes of data. 433 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) 434 return Fail; 435 436 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 437 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this); 438 if (result != Fail) { 439 Size = 2; 440 AddThumbPredicate(MI); 441 return result; 442 } 443 444 MI.clear(); 445 result = decodeThumbSBitInstruction16(MI, insn16, Address, this); 446 if (result) { 447 Size = 2; 448 bool InITBlock = !ITBlock.empty(); 449 AddThumbPredicate(MI); 450 AddThumb1SBit(MI, InITBlock); 451 return result; 452 } 453 454 MI.clear(); 455 result = decodeThumb2Instruction16(MI, insn16, Address, this); 456 if (result != Fail) { 457 Size = 2; 458 AddThumbPredicate(MI); 459 460 // If we find an IT instruction, we need to parse its condition 461 // code and mask operands so that we can apply them correctly 462 // to the subsequent instructions. 463 if (MI.getOpcode() == ARM::t2IT) { 464 unsigned firstcond = MI.getOperand(0).getImm(); 465 uint32_t mask = MI.getOperand(1).getImm(); 466 unsigned zeros = CountTrailingZeros_32(mask); 467 mask >>= zeros+1; 468 469 for (unsigned i = 0; i < 4 - (zeros+1); ++i) { 470 if (firstcond ^ (mask & 1)) 471 ITBlock.push_back(firstcond ^ 1); 472 else 473 ITBlock.push_back(firstcond); 474 mask >>= 1; 475 } 476 ITBlock.push_back(firstcond); 477 } 478 479 return result; 480 } 481 482 // We want to read exactly 4 bytes of data. 483 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 484 return Fail; 485 486 uint32_t insn32 = (bytes[3] << 8) | 487 (bytes[2] << 0) | 488 (bytes[1] << 24) | 489 (bytes[0] << 16); 490 MI.clear(); 491 result = decodeThumbInstruction32(MI, insn32, Address, this); 492 if (result != Fail) { 493 Size = 4; 494 bool InITBlock = ITBlock.size(); 495 AddThumbPredicate(MI); 496 AddThumb1SBit(MI, InITBlock); 497 return result; 498 } 499 500 MI.clear(); 501 result = decodeThumb2Instruction32(MI, insn32, Address, this); 502 if (result != Fail) { 503 Size = 4; 504 AddThumbPredicate(MI); 505 return result; 506 } 507 508 MI.clear(); 509 result = decodeCommonInstruction32(MI, insn32, Address, this); 510 if (result != Fail) { 511 Size = 4; 512 AddThumbPredicate(MI); 513 return result; 514 } 515 516 MI.clear(); 517 result = decodeVFPInstruction32(MI, insn32, Address, this); 518 if (result != Fail) { 519 Size = 4; 520 UpdateThumbVFPPredicate(MI); 521 return result; 522 } 523 524 MI.clear(); 525 result = decodeNEONDupInstruction32(MI, insn32, Address, this); 526 if (result != Fail) { 527 Size = 4; 528 AddThumbPredicate(MI); 529 return result; 530 } 531 532 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { 533 MI.clear(); 534 uint32_t NEONLdStInsn = insn32; 535 NEONLdStInsn &= 0xF0FFFFFF; 536 NEONLdStInsn |= 0x04000000; 537 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this); 538 if (result != Fail) { 539 Size = 4; 540 AddThumbPredicate(MI); 541 return result; 542 } 543 } 544 545 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 546 MI.clear(); 547 uint32_t NEONDataInsn = insn32; 548 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 549 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 550 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 551 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this); 552 if (result != Fail) { 553 Size = 4; 554 AddThumbPredicate(MI); 555 return result; 556 } 557 } 558 559 return Fail; 560 } 561 562 563 extern "C" void LLVMInitializeARMDisassembler() { 564 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 565 createARMDisassembler); 566 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 567 createThumbDisassembler); 568 } 569 570 static const unsigned GPRDecoderTable[] = { 571 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 572 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 573 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 574 ARM::R12, ARM::SP, ARM::LR, ARM::PC 575 }; 576 577 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 578 uint64_t Address, const void *Decoder) { 579 if (RegNo > 15) 580 return Fail; 581 582 unsigned Register = GPRDecoderTable[RegNo]; 583 Inst.addOperand(MCOperand::CreateReg(Register)); 584 return Success; 585 } 586 587 static DecodeStatus 588 DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 589 uint64_t Address, const void *Decoder) { 590 if (RegNo == 15) return Fail; 591 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 592 } 593 594 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 595 uint64_t Address, const void *Decoder) { 596 if (RegNo > 7) 597 return Fail; 598 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 599 } 600 601 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 602 uint64_t Address, const void *Decoder) { 603 unsigned Register = 0; 604 switch (RegNo) { 605 case 0: 606 Register = ARM::R0; 607 break; 608 case 1: 609 Register = ARM::R1; 610 break; 611 case 2: 612 Register = ARM::R2; 613 break; 614 case 3: 615 Register = ARM::R3; 616 break; 617 case 9: 618 Register = ARM::R9; 619 break; 620 case 12: 621 Register = ARM::R12; 622 break; 623 default: 624 return Fail; 625 } 626 627 Inst.addOperand(MCOperand::CreateReg(Register)); 628 return Success; 629 } 630 631 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 632 uint64_t Address, const void *Decoder) { 633 if (RegNo == 13 || RegNo == 15) return Fail; 634 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 635 } 636 637 static const unsigned SPRDecoderTable[] = { 638 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 639 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 640 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 641 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 642 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 643 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 644 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 645 ARM::S28, ARM::S29, ARM::S30, ARM::S31 646 }; 647 648 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 649 uint64_t Address, const void *Decoder) { 650 if (RegNo > 31) 651 return Fail; 652 653 unsigned Register = SPRDecoderTable[RegNo]; 654 Inst.addOperand(MCOperand::CreateReg(Register)); 655 return Success; 656 } 657 658 static const unsigned DPRDecoderTable[] = { 659 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 660 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 661 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 662 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 663 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 664 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 665 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 666 ARM::D28, ARM::D29, ARM::D30, ARM::D31 667 }; 668 669 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 670 uint64_t Address, const void *Decoder) { 671 if (RegNo > 31) 672 return Fail; 673 674 unsigned Register = DPRDecoderTable[RegNo]; 675 Inst.addOperand(MCOperand::CreateReg(Register)); 676 return Success; 677 } 678 679 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 680 uint64_t Address, const void *Decoder) { 681 if (RegNo > 7) 682 return Fail; 683 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 684 } 685 686 static DecodeStatus 687 DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 688 uint64_t Address, const void *Decoder) { 689 if (RegNo > 15) 690 return Fail; 691 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 692 } 693 694 static const unsigned QPRDecoderTable[] = { 695 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 696 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 697 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 698 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 699 }; 700 701 702 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 703 uint64_t Address, const void *Decoder) { 704 if (RegNo > 31) 705 return Fail; 706 RegNo >>= 1; 707 708 unsigned Register = QPRDecoderTable[RegNo]; 709 Inst.addOperand(MCOperand::CreateReg(Register)); 710 return Success; 711 } 712 713 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 714 uint64_t Address, const void *Decoder) { 715 if (Val == 0xF) return Fail; 716 // AL predicate is not allowed on Thumb1 branches. 717 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 718 return Fail; 719 Inst.addOperand(MCOperand::CreateImm(Val)); 720 if (Val == ARMCC::AL) { 721 Inst.addOperand(MCOperand::CreateReg(0)); 722 } else 723 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 724 return Success; 725 } 726 727 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 728 uint64_t Address, const void *Decoder) { 729 if (Val) 730 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 731 else 732 Inst.addOperand(MCOperand::CreateReg(0)); 733 return Success; 734 } 735 736 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 737 uint64_t Address, const void *Decoder) { 738 uint32_t imm = Val & 0xFF; 739 uint32_t rot = (Val & 0xF00) >> 7; 740 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot)); 741 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 742 return Success; 743 } 744 745 static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 746 uint64_t Address, const void *Decoder) { 747 Val <<= 2; 748 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(Val))); 749 return Success; 750 } 751 752 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 753 uint64_t Address, const void *Decoder) { 754 DecodeStatus S = Success; 755 756 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 757 unsigned type = fieldFromInstruction32(Val, 5, 2); 758 unsigned imm = fieldFromInstruction32(Val, 7, 5); 759 760 // Register-immediate 761 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 762 763 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 764 switch (type) { 765 case 0: 766 Shift = ARM_AM::lsl; 767 break; 768 case 1: 769 Shift = ARM_AM::lsr; 770 break; 771 case 2: 772 Shift = ARM_AM::asr; 773 break; 774 case 3: 775 Shift = ARM_AM::ror; 776 break; 777 } 778 779 if (Shift == ARM_AM::ror && imm == 0) 780 Shift = ARM_AM::rrx; 781 782 unsigned Op = Shift | (imm << 3); 783 Inst.addOperand(MCOperand::CreateImm(Op)); 784 785 return S; 786 } 787 788 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 789 uint64_t Address, const void *Decoder) { 790 DecodeStatus S = Success; 791 792 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 793 unsigned type = fieldFromInstruction32(Val, 5, 2); 794 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 795 796 // Register-register 797 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)); 798 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)); 799 800 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 801 switch (type) { 802 case 0: 803 Shift = ARM_AM::lsl; 804 break; 805 case 1: 806 Shift = ARM_AM::lsr; 807 break; 808 case 2: 809 Shift = ARM_AM::asr; 810 break; 811 case 3: 812 Shift = ARM_AM::ror; 813 break; 814 } 815 816 Inst.addOperand(MCOperand::CreateImm(Shift)); 817 818 return S; 819 } 820 821 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 822 uint64_t Address, const void *Decoder) { 823 DecodeStatus S = Success; 824 825 // Empty register lists are not allowed. 826 if (CountPopulation_32(Val) == 0) return Fail; 827 for (unsigned i = 0; i < 16; ++i) { 828 if (Val & (1 << i)) { 829 CHECK(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)); 830 } 831 } 832 833 return S; 834 } 835 836 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 837 uint64_t Address, const void *Decoder) { 838 DecodeStatus S = Success; 839 840 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 841 unsigned regs = Val & 0xFF; 842 843 CHECK(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)); 844 for (unsigned i = 0; i < (regs - 1); ++i) { 845 CHECK(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)); 846 } 847 848 return S; 849 } 850 851 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 852 uint64_t Address, const void *Decoder) { 853 DecodeStatus S = Success; 854 855 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 856 unsigned regs = (Val & 0xFF) / 2; 857 858 CHECK(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)); 859 for (unsigned i = 0; i < (regs - 1); ++i) { 860 CHECK(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)); 861 } 862 863 return S; 864 } 865 866 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 867 uint64_t Address, const void *Decoder) { 868 // This operand encodes a mask of contiguous zeros between a specified MSB 869 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 870 // the mask of all bits LSB-and-lower, and then xor them to create 871 // the mask of that's all ones on [msb, lsb]. Finally we not it to 872 // create the final mask. 873 unsigned msb = fieldFromInstruction32(Val, 5, 5); 874 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 875 uint32_t msb_mask = (1 << (msb+1)) - 1; 876 uint32_t lsb_mask = (1 << lsb) - 1; 877 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 878 return Success; 879 } 880 881 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 882 uint64_t Address, const void *Decoder) { 883 DecodeStatus S = Success; 884 885 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 886 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 887 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 888 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 889 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 890 unsigned U = fieldFromInstruction32(Insn, 23, 1); 891 892 switch (Inst.getOpcode()) { 893 case ARM::LDC_OFFSET: 894 case ARM::LDC_PRE: 895 case ARM::LDC_POST: 896 case ARM::LDC_OPTION: 897 case ARM::LDCL_OFFSET: 898 case ARM::LDCL_PRE: 899 case ARM::LDCL_POST: 900 case ARM::LDCL_OPTION: 901 case ARM::STC_OFFSET: 902 case ARM::STC_PRE: 903 case ARM::STC_POST: 904 case ARM::STC_OPTION: 905 case ARM::STCL_OFFSET: 906 case ARM::STCL_PRE: 907 case ARM::STCL_POST: 908 case ARM::STCL_OPTION: 909 if (coproc == 0xA || coproc == 0xB) 910 return Fail; 911 break; 912 default: 913 break; 914 } 915 916 Inst.addOperand(MCOperand::CreateImm(coproc)); 917 Inst.addOperand(MCOperand::CreateImm(CRd)); 918 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 919 switch (Inst.getOpcode()) { 920 case ARM::LDC_OPTION: 921 case ARM::LDCL_OPTION: 922 case ARM::LDC2_OPTION: 923 case ARM::LDC2L_OPTION: 924 case ARM::STC_OPTION: 925 case ARM::STCL_OPTION: 926 case ARM::STC2_OPTION: 927 case ARM::STC2L_OPTION: 928 case ARM::LDCL_POST: 929 case ARM::STCL_POST: 930 break; 931 default: 932 Inst.addOperand(MCOperand::CreateReg(0)); 933 break; 934 } 935 936 unsigned P = fieldFromInstruction32(Insn, 24, 1); 937 unsigned W = fieldFromInstruction32(Insn, 21, 1); 938 939 bool writeback = (P == 0) || (W == 1); 940 unsigned idx_mode = 0; 941 if (P && writeback) 942 idx_mode = ARMII::IndexModePre; 943 else if (!P && writeback) 944 idx_mode = ARMII::IndexModePost; 945 946 switch (Inst.getOpcode()) { 947 case ARM::LDCL_POST: 948 case ARM::STCL_POST: 949 imm |= U << 8; 950 case ARM::LDC_OPTION: 951 case ARM::LDCL_OPTION: 952 case ARM::LDC2_OPTION: 953 case ARM::LDC2L_OPTION: 954 case ARM::STC_OPTION: 955 case ARM::STCL_OPTION: 956 case ARM::STC2_OPTION: 957 case ARM::STC2L_OPTION: 958 Inst.addOperand(MCOperand::CreateImm(imm)); 959 break; 960 default: 961 if (U) 962 Inst.addOperand(MCOperand::CreateImm( 963 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode))); 964 else 965 Inst.addOperand(MCOperand::CreateImm( 966 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode))); 967 break; 968 } 969 970 switch (Inst.getOpcode()) { 971 case ARM::LDC_OFFSET: 972 case ARM::LDC_PRE: 973 case ARM::LDC_POST: 974 case ARM::LDC_OPTION: 975 case ARM::LDCL_OFFSET: 976 case ARM::LDCL_PRE: 977 case ARM::LDCL_POST: 978 case ARM::LDCL_OPTION: 979 case ARM::STC_OFFSET: 980 case ARM::STC_PRE: 981 case ARM::STC_POST: 982 case ARM::STC_OPTION: 983 case ARM::STCL_OFFSET: 984 case ARM::STCL_PRE: 985 case ARM::STCL_POST: 986 case ARM::STCL_OPTION: 987 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 988 break; 989 default: 990 break; 991 } 992 993 return S; 994 } 995 996 static DecodeStatus 997 DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 998 uint64_t Address, const void *Decoder) { 999 DecodeStatus S = Success; 1000 1001 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1002 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1003 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1004 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 1005 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1006 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 1007 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1008 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1009 1010 // On stores, the writeback operand precedes Rt. 1011 switch (Inst.getOpcode()) { 1012 case ARM::STR_POST_IMM: 1013 case ARM::STR_POST_REG: 1014 case ARM::STRB_POST_IMM: 1015 case ARM::STRB_POST_REG: 1016 case ARM::STRT_POST_REG: 1017 case ARM::STRT_POST_IMM: 1018 case ARM::STRBT_POST_REG: 1019 case ARM::STRBT_POST_IMM: 1020 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1021 break; 1022 default: 1023 break; 1024 } 1025 1026 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 1027 1028 // On loads, the writeback operand comes after Rt. 1029 switch (Inst.getOpcode()) { 1030 case ARM::LDR_POST_IMM: 1031 case ARM::LDR_POST_REG: 1032 case ARM::LDRB_POST_IMM: 1033 case ARM::LDRB_POST_REG: 1034 case ARM::LDR_PRE: 1035 case ARM::LDRB_PRE: 1036 case ARM::LDRBT_POST_REG: 1037 case ARM::LDRBT_POST_IMM: 1038 case ARM::LDRT_POST_REG: 1039 case ARM::LDRT_POST_IMM: 1040 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1041 break; 1042 default: 1043 break; 1044 } 1045 1046 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1047 1048 ARM_AM::AddrOpc Op = ARM_AM::add; 1049 if (!fieldFromInstruction32(Insn, 23, 1)) 1050 Op = ARM_AM::sub; 1051 1052 bool writeback = (P == 0) || (W == 1); 1053 unsigned idx_mode = 0; 1054 if (P && writeback) 1055 idx_mode = ARMII::IndexModePre; 1056 else if (!P && writeback) 1057 idx_mode = ARMII::IndexModePost; 1058 1059 if (writeback && (Rn == 15 || Rn == Rt)) S = Unpredictable; // UNPREDICTABLE 1060 1061 if (reg) { 1062 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)); 1063 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1064 switch( fieldFromInstruction32(Insn, 5, 2)) { 1065 case 0: 1066 Opc = ARM_AM::lsl; 1067 break; 1068 case 1: 1069 Opc = ARM_AM::lsr; 1070 break; 1071 case 2: 1072 Opc = ARM_AM::asr; 1073 break; 1074 case 3: 1075 Opc = ARM_AM::ror; 1076 break; 1077 default: 1078 return Fail; 1079 } 1080 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1081 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1082 1083 Inst.addOperand(MCOperand::CreateImm(imm)); 1084 } else { 1085 Inst.addOperand(MCOperand::CreateReg(0)); 1086 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1087 Inst.addOperand(MCOperand::CreateImm(tmp)); 1088 } 1089 1090 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1091 1092 return S; 1093 } 1094 1095 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1096 uint64_t Address, const void *Decoder) { 1097 DecodeStatus S = Success; 1098 1099 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1100 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1101 unsigned type = fieldFromInstruction32(Val, 5, 2); 1102 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1103 unsigned U = fieldFromInstruction32(Val, 12, 1); 1104 1105 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1106 switch (type) { 1107 case 0: 1108 ShOp = ARM_AM::lsl; 1109 break; 1110 case 1: 1111 ShOp = ARM_AM::lsr; 1112 break; 1113 case 2: 1114 ShOp = ARM_AM::asr; 1115 break; 1116 case 3: 1117 ShOp = ARM_AM::ror; 1118 break; 1119 } 1120 1121 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1122 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1123 unsigned shift; 1124 if (U) 1125 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1126 else 1127 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1128 Inst.addOperand(MCOperand::CreateImm(shift)); 1129 1130 return S; 1131 } 1132 1133 static DecodeStatus 1134 DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1135 uint64_t Address, const void *Decoder) { 1136 DecodeStatus S = Success; 1137 1138 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1139 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1140 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1141 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1142 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1143 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1144 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1145 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1146 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1147 1148 bool writeback = (W == 1) | (P == 0); 1149 1150 // For {LD,ST}RD, Rt must be even, else undefined. 1151 switch (Inst.getOpcode()) { 1152 case ARM::STRD: 1153 case ARM::STRD_PRE: 1154 case ARM::STRD_POST: 1155 case ARM::LDRD: 1156 case ARM::LDRD_PRE: 1157 case ARM::LDRD_POST: 1158 if (Rt & 0x1) return Fail; 1159 break; 1160 default: 1161 break; 1162 } 1163 1164 if (writeback) { // Writeback 1165 if (P) 1166 U |= ARMII::IndexModePre << 9; 1167 else 1168 U |= ARMII::IndexModePost << 9; 1169 1170 // On stores, the writeback operand precedes Rt. 1171 switch (Inst.getOpcode()) { 1172 case ARM::STRD: 1173 case ARM::STRD_PRE: 1174 case ARM::STRD_POST: 1175 case ARM::STRH: 1176 case ARM::STRH_PRE: 1177 case ARM::STRH_POST: 1178 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1179 break; 1180 default: 1181 break; 1182 } 1183 } 1184 1185 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 1186 switch (Inst.getOpcode()) { 1187 case ARM::STRD: 1188 case ARM::STRD_PRE: 1189 case ARM::STRD_POST: 1190 case ARM::LDRD: 1191 case ARM::LDRD_PRE: 1192 case ARM::LDRD_POST: 1193 CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)); 1194 break; 1195 default: 1196 break; 1197 } 1198 1199 if (writeback) { 1200 // On loads, the writeback operand comes after Rt. 1201 switch (Inst.getOpcode()) { 1202 case ARM::LDRD: 1203 case ARM::LDRD_PRE: 1204 case ARM::LDRD_POST: 1205 case ARM::LDRH: 1206 case ARM::LDRH_PRE: 1207 case ARM::LDRH_POST: 1208 case ARM::LDRSH: 1209 case ARM::LDRSH_PRE: 1210 case ARM::LDRSH_POST: 1211 case ARM::LDRSB: 1212 case ARM::LDRSB_PRE: 1213 case ARM::LDRSB_POST: 1214 case ARM::LDRHTr: 1215 case ARM::LDRSBTr: 1216 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1217 break; 1218 default: 1219 break; 1220 } 1221 } 1222 1223 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1224 1225 if (type) { 1226 Inst.addOperand(MCOperand::CreateReg(0)); 1227 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1228 } else { 1229 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1230 Inst.addOperand(MCOperand::CreateImm(U)); 1231 } 1232 1233 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1234 1235 return S; 1236 } 1237 1238 static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1239 uint64_t Address, const void *Decoder) { 1240 DecodeStatus S = Success; 1241 1242 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1243 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1244 1245 switch (mode) { 1246 case 0: 1247 mode = ARM_AM::da; 1248 break; 1249 case 1: 1250 mode = ARM_AM::ia; 1251 break; 1252 case 2: 1253 mode = ARM_AM::db; 1254 break; 1255 case 3: 1256 mode = ARM_AM::ib; 1257 break; 1258 } 1259 1260 Inst.addOperand(MCOperand::CreateImm(mode)); 1261 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1262 1263 return S; 1264 } 1265 1266 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1267 unsigned Insn, 1268 uint64_t Address, const void *Decoder) { 1269 DecodeStatus S = Success; 1270 1271 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1272 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1273 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1274 1275 if (pred == 0xF) { 1276 switch (Inst.getOpcode()) { 1277 case ARM::LDMDA: 1278 Inst.setOpcode(ARM::RFEDA); 1279 break; 1280 case ARM::LDMDA_UPD: 1281 Inst.setOpcode(ARM::RFEDA_UPD); 1282 break; 1283 case ARM::LDMDB: 1284 Inst.setOpcode(ARM::RFEDB); 1285 break; 1286 case ARM::LDMDB_UPD: 1287 Inst.setOpcode(ARM::RFEDB_UPD); 1288 break; 1289 case ARM::LDMIA: 1290 Inst.setOpcode(ARM::RFEIA); 1291 break; 1292 case ARM::LDMIA_UPD: 1293 Inst.setOpcode(ARM::RFEIA_UPD); 1294 break; 1295 case ARM::LDMIB: 1296 Inst.setOpcode(ARM::RFEIB); 1297 break; 1298 case ARM::LDMIB_UPD: 1299 Inst.setOpcode(ARM::RFEIB_UPD); 1300 break; 1301 case ARM::STMDA: 1302 Inst.setOpcode(ARM::SRSDA); 1303 break; 1304 case ARM::STMDA_UPD: 1305 Inst.setOpcode(ARM::SRSDA_UPD); 1306 break; 1307 case ARM::STMDB: 1308 Inst.setOpcode(ARM::SRSDB); 1309 break; 1310 case ARM::STMDB_UPD: 1311 Inst.setOpcode(ARM::SRSDB_UPD); 1312 break; 1313 case ARM::STMIA: 1314 Inst.setOpcode(ARM::SRSIA); 1315 break; 1316 case ARM::STMIA_UPD: 1317 Inst.setOpcode(ARM::SRSIA_UPD); 1318 break; 1319 case ARM::STMIB: 1320 Inst.setOpcode(ARM::SRSIB); 1321 break; 1322 case ARM::STMIB_UPD: 1323 Inst.setOpcode(ARM::SRSIB_UPD); 1324 break; 1325 default: 1326 CHECK(S, Fail); 1327 } 1328 1329 // For stores (which become SRS's, the only operand is the mode. 1330 if (fieldFromInstruction32(Insn, 20, 1) == 0) { 1331 Inst.addOperand( 1332 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4))); 1333 return S; 1334 } 1335 1336 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1337 } 1338 1339 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1340 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); // Tied 1341 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1342 CHECK(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)); 1343 1344 return S; 1345 } 1346 1347 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1348 uint64_t Address, const void *Decoder) { 1349 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1350 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1351 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1352 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1353 1354 DecodeStatus S = Success; 1355 1356 // imod == '01' --> UNPREDICTABLE 1357 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1358 // return failure here. The '01' imod value is unprintable, so there's 1359 // nothing useful we could do even if we returned UNPREDICTABLE. 1360 1361 if (imod == 1) CHECK(S, Fail); 1362 1363 if (imod && M) { 1364 Inst.setOpcode(ARM::CPS3p); 1365 Inst.addOperand(MCOperand::CreateImm(imod)); 1366 Inst.addOperand(MCOperand::CreateImm(iflags)); 1367 Inst.addOperand(MCOperand::CreateImm(mode)); 1368 } else if (imod && !M) { 1369 Inst.setOpcode(ARM::CPS2p); 1370 Inst.addOperand(MCOperand::CreateImm(imod)); 1371 Inst.addOperand(MCOperand::CreateImm(iflags)); 1372 if (mode) CHECK(S, Unpredictable); 1373 } else if (!imod && M) { 1374 Inst.setOpcode(ARM::CPS1p); 1375 Inst.addOperand(MCOperand::CreateImm(mode)); 1376 if (iflags) CHECK(S, Unpredictable); 1377 } else { 1378 // imod == '00' && M == '0' --> UNPREDICTABLE 1379 Inst.setOpcode(ARM::CPS1p); 1380 Inst.addOperand(MCOperand::CreateImm(mode)); 1381 CHECK(S, Unpredictable); 1382 } 1383 1384 return S; 1385 } 1386 1387 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1388 uint64_t Address, const void *Decoder) { 1389 DecodeStatus S = Success; 1390 1391 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1392 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1393 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1394 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1395 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1396 1397 if (pred == 0xF) 1398 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1399 1400 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)); 1401 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)); 1402 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)); 1403 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)); 1404 1405 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1406 1407 return S; 1408 } 1409 1410 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1411 uint64_t Address, const void *Decoder) { 1412 DecodeStatus S = Success; 1413 1414 unsigned add = fieldFromInstruction32(Val, 12, 1); 1415 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1416 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1417 1418 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1419 1420 if (!add) imm *= -1; 1421 if (imm == 0 && !add) imm = INT32_MIN; 1422 Inst.addOperand(MCOperand::CreateImm(imm)); 1423 1424 return S; 1425 } 1426 1427 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1428 uint64_t Address, const void *Decoder) { 1429 DecodeStatus S = Success; 1430 1431 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1432 unsigned U = fieldFromInstruction32(Val, 8, 1); 1433 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1434 1435 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1436 1437 if (U) 1438 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1439 else 1440 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1441 1442 return S; 1443 } 1444 1445 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1446 uint64_t Address, const void *Decoder) { 1447 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1448 } 1449 1450 static DecodeStatus 1451 DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1452 uint64_t Address, const void *Decoder) { 1453 DecodeStatus S = Success; 1454 1455 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1456 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1457 1458 if (pred == 0xF) { 1459 Inst.setOpcode(ARM::BLXi); 1460 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1461 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1462 return S; 1463 } 1464 1465 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1466 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1467 1468 return S; 1469 } 1470 1471 1472 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 1473 uint64_t Address, const void *Decoder) { 1474 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 1475 return Success; 1476 } 1477 1478 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1479 uint64_t Address, const void *Decoder) { 1480 DecodeStatus S = Success; 1481 1482 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1483 unsigned align = fieldFromInstruction32(Val, 4, 2); 1484 1485 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1486 if (!align) 1487 Inst.addOperand(MCOperand::CreateImm(0)); 1488 else 1489 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1490 1491 return S; 1492 } 1493 1494 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1495 uint64_t Address, const void *Decoder) { 1496 DecodeStatus S = Success; 1497 1498 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1499 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1500 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1501 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1502 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1503 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1504 1505 // First output register 1506 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 1507 1508 // Second output register 1509 switch (Inst.getOpcode()) { 1510 case ARM::VLD1q8: 1511 case ARM::VLD1q16: 1512 case ARM::VLD1q32: 1513 case ARM::VLD1q64: 1514 case ARM::VLD1q8_UPD: 1515 case ARM::VLD1q16_UPD: 1516 case ARM::VLD1q32_UPD: 1517 case ARM::VLD1q64_UPD: 1518 case ARM::VLD1d8T: 1519 case ARM::VLD1d16T: 1520 case ARM::VLD1d32T: 1521 case ARM::VLD1d64T: 1522 case ARM::VLD1d8T_UPD: 1523 case ARM::VLD1d16T_UPD: 1524 case ARM::VLD1d32T_UPD: 1525 case ARM::VLD1d64T_UPD: 1526 case ARM::VLD1d8Q: 1527 case ARM::VLD1d16Q: 1528 case ARM::VLD1d32Q: 1529 case ARM::VLD1d64Q: 1530 case ARM::VLD1d8Q_UPD: 1531 case ARM::VLD1d16Q_UPD: 1532 case ARM::VLD1d32Q_UPD: 1533 case ARM::VLD1d64Q_UPD: 1534 case ARM::VLD2d8: 1535 case ARM::VLD2d16: 1536 case ARM::VLD2d32: 1537 case ARM::VLD2d8_UPD: 1538 case ARM::VLD2d16_UPD: 1539 case ARM::VLD2d32_UPD: 1540 case ARM::VLD2q8: 1541 case ARM::VLD2q16: 1542 case ARM::VLD2q32: 1543 case ARM::VLD2q8_UPD: 1544 case ARM::VLD2q16_UPD: 1545 case ARM::VLD2q32_UPD: 1546 case ARM::VLD3d8: 1547 case ARM::VLD3d16: 1548 case ARM::VLD3d32: 1549 case ARM::VLD3d8_UPD: 1550 case ARM::VLD3d16_UPD: 1551 case ARM::VLD3d32_UPD: 1552 case ARM::VLD4d8: 1553 case ARM::VLD4d16: 1554 case ARM::VLD4d32: 1555 case ARM::VLD4d8_UPD: 1556 case ARM::VLD4d16_UPD: 1557 case ARM::VLD4d32_UPD: 1558 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)); 1559 break; 1560 case ARM::VLD2b8: 1561 case ARM::VLD2b16: 1562 case ARM::VLD2b32: 1563 case ARM::VLD2b8_UPD: 1564 case ARM::VLD2b16_UPD: 1565 case ARM::VLD2b32_UPD: 1566 case ARM::VLD3q8: 1567 case ARM::VLD3q16: 1568 case ARM::VLD3q32: 1569 case ARM::VLD3q8_UPD: 1570 case ARM::VLD3q16_UPD: 1571 case ARM::VLD3q32_UPD: 1572 case ARM::VLD4q8: 1573 case ARM::VLD4q16: 1574 case ARM::VLD4q32: 1575 case ARM::VLD4q8_UPD: 1576 case ARM::VLD4q16_UPD: 1577 case ARM::VLD4q32_UPD: 1578 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); 1579 default: 1580 break; 1581 } 1582 1583 // Third output register 1584 switch(Inst.getOpcode()) { 1585 case ARM::VLD1d8T: 1586 case ARM::VLD1d16T: 1587 case ARM::VLD1d32T: 1588 case ARM::VLD1d64T: 1589 case ARM::VLD1d8T_UPD: 1590 case ARM::VLD1d16T_UPD: 1591 case ARM::VLD1d32T_UPD: 1592 case ARM::VLD1d64T_UPD: 1593 case ARM::VLD1d8Q: 1594 case ARM::VLD1d16Q: 1595 case ARM::VLD1d32Q: 1596 case ARM::VLD1d64Q: 1597 case ARM::VLD1d8Q_UPD: 1598 case ARM::VLD1d16Q_UPD: 1599 case ARM::VLD1d32Q_UPD: 1600 case ARM::VLD1d64Q_UPD: 1601 case ARM::VLD2q8: 1602 case ARM::VLD2q16: 1603 case ARM::VLD2q32: 1604 case ARM::VLD2q8_UPD: 1605 case ARM::VLD2q16_UPD: 1606 case ARM::VLD2q32_UPD: 1607 case ARM::VLD3d8: 1608 case ARM::VLD3d16: 1609 case ARM::VLD3d32: 1610 case ARM::VLD3d8_UPD: 1611 case ARM::VLD3d16_UPD: 1612 case ARM::VLD3d32_UPD: 1613 case ARM::VLD4d8: 1614 case ARM::VLD4d16: 1615 case ARM::VLD4d32: 1616 case ARM::VLD4d8_UPD: 1617 case ARM::VLD4d16_UPD: 1618 case ARM::VLD4d32_UPD: 1619 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); 1620 break; 1621 case ARM::VLD3q8: 1622 case ARM::VLD3q16: 1623 case ARM::VLD3q32: 1624 case ARM::VLD3q8_UPD: 1625 case ARM::VLD3q16_UPD: 1626 case ARM::VLD3q32_UPD: 1627 case ARM::VLD4q8: 1628 case ARM::VLD4q16: 1629 case ARM::VLD4q32: 1630 case ARM::VLD4q8_UPD: 1631 case ARM::VLD4q16_UPD: 1632 case ARM::VLD4q32_UPD: 1633 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)); 1634 break; 1635 default: 1636 break; 1637 } 1638 1639 // Fourth output register 1640 switch (Inst.getOpcode()) { 1641 case ARM::VLD1d8Q: 1642 case ARM::VLD1d16Q: 1643 case ARM::VLD1d32Q: 1644 case ARM::VLD1d64Q: 1645 case ARM::VLD1d8Q_UPD: 1646 case ARM::VLD1d16Q_UPD: 1647 case ARM::VLD1d32Q_UPD: 1648 case ARM::VLD1d64Q_UPD: 1649 case ARM::VLD2q8: 1650 case ARM::VLD2q16: 1651 case ARM::VLD2q32: 1652 case ARM::VLD2q8_UPD: 1653 case ARM::VLD2q16_UPD: 1654 case ARM::VLD2q32_UPD: 1655 case ARM::VLD4d8: 1656 case ARM::VLD4d16: 1657 case ARM::VLD4d32: 1658 case ARM::VLD4d8_UPD: 1659 case ARM::VLD4d16_UPD: 1660 case ARM::VLD4d32_UPD: 1661 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)); 1662 break; 1663 case ARM::VLD4q8: 1664 case ARM::VLD4q16: 1665 case ARM::VLD4q32: 1666 case ARM::VLD4q8_UPD: 1667 case ARM::VLD4q16_UPD: 1668 case ARM::VLD4q32_UPD: 1669 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)); 1670 break; 1671 default: 1672 break; 1673 } 1674 1675 // Writeback operand 1676 switch (Inst.getOpcode()) { 1677 case ARM::VLD1d8_UPD: 1678 case ARM::VLD1d16_UPD: 1679 case ARM::VLD1d32_UPD: 1680 case ARM::VLD1d64_UPD: 1681 case ARM::VLD1q8_UPD: 1682 case ARM::VLD1q16_UPD: 1683 case ARM::VLD1q32_UPD: 1684 case ARM::VLD1q64_UPD: 1685 case ARM::VLD1d8T_UPD: 1686 case ARM::VLD1d16T_UPD: 1687 case ARM::VLD1d32T_UPD: 1688 case ARM::VLD1d64T_UPD: 1689 case ARM::VLD1d8Q_UPD: 1690 case ARM::VLD1d16Q_UPD: 1691 case ARM::VLD1d32Q_UPD: 1692 case ARM::VLD1d64Q_UPD: 1693 case ARM::VLD2d8_UPD: 1694 case ARM::VLD2d16_UPD: 1695 case ARM::VLD2d32_UPD: 1696 case ARM::VLD2q8_UPD: 1697 case ARM::VLD2q16_UPD: 1698 case ARM::VLD2q32_UPD: 1699 case ARM::VLD2b8_UPD: 1700 case ARM::VLD2b16_UPD: 1701 case ARM::VLD2b32_UPD: 1702 case ARM::VLD3d8_UPD: 1703 case ARM::VLD3d16_UPD: 1704 case ARM::VLD3d32_UPD: 1705 case ARM::VLD3q8_UPD: 1706 case ARM::VLD3q16_UPD: 1707 case ARM::VLD3q32_UPD: 1708 case ARM::VLD4d8_UPD: 1709 case ARM::VLD4d16_UPD: 1710 case ARM::VLD4d32_UPD: 1711 case ARM::VLD4q8_UPD: 1712 case ARM::VLD4q16_UPD: 1713 case ARM::VLD4q32_UPD: 1714 CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)); 1715 break; 1716 default: 1717 break; 1718 } 1719 1720 // AddrMode6 Base (register+alignment) 1721 CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)); 1722 1723 // AddrMode6 Offset (register) 1724 if (Rm == 0xD) 1725 Inst.addOperand(MCOperand::CreateReg(0)); 1726 else if (Rm != 0xF) { 1727 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1728 } 1729 1730 return S; 1731 } 1732 1733 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 1734 uint64_t Address, const void *Decoder) { 1735 DecodeStatus S = Success; 1736 1737 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1738 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1739 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1740 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1741 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1742 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1743 1744 // Writeback Operand 1745 switch (Inst.getOpcode()) { 1746 case ARM::VST1d8_UPD: 1747 case ARM::VST1d16_UPD: 1748 case ARM::VST1d32_UPD: 1749 case ARM::VST1d64_UPD: 1750 case ARM::VST1q8_UPD: 1751 case ARM::VST1q16_UPD: 1752 case ARM::VST1q32_UPD: 1753 case ARM::VST1q64_UPD: 1754 case ARM::VST1d8T_UPD: 1755 case ARM::VST1d16T_UPD: 1756 case ARM::VST1d32T_UPD: 1757 case ARM::VST1d64T_UPD: 1758 case ARM::VST1d8Q_UPD: 1759 case ARM::VST1d16Q_UPD: 1760 case ARM::VST1d32Q_UPD: 1761 case ARM::VST1d64Q_UPD: 1762 case ARM::VST2d8_UPD: 1763 case ARM::VST2d16_UPD: 1764 case ARM::VST2d32_UPD: 1765 case ARM::VST2q8_UPD: 1766 case ARM::VST2q16_UPD: 1767 case ARM::VST2q32_UPD: 1768 case ARM::VST2b8_UPD: 1769 case ARM::VST2b16_UPD: 1770 case ARM::VST2b32_UPD: 1771 case ARM::VST3d8_UPD: 1772 case ARM::VST3d16_UPD: 1773 case ARM::VST3d32_UPD: 1774 case ARM::VST3q8_UPD: 1775 case ARM::VST3q16_UPD: 1776 case ARM::VST3q32_UPD: 1777 case ARM::VST4d8_UPD: 1778 case ARM::VST4d16_UPD: 1779 case ARM::VST4d32_UPD: 1780 case ARM::VST4q8_UPD: 1781 case ARM::VST4q16_UPD: 1782 case ARM::VST4q32_UPD: 1783 CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)); 1784 break; 1785 default: 1786 break; 1787 } 1788 1789 // AddrMode6 Base (register+alignment) 1790 CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)); 1791 1792 // AddrMode6 Offset (register) 1793 if (Rm == 0xD) 1794 Inst.addOperand(MCOperand::CreateReg(0)); 1795 else if (Rm != 0xF) { 1796 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1797 } 1798 1799 // First input register 1800 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 1801 1802 // Second input register 1803 switch (Inst.getOpcode()) { 1804 case ARM::VST1q8: 1805 case ARM::VST1q16: 1806 case ARM::VST1q32: 1807 case ARM::VST1q64: 1808 case ARM::VST1q8_UPD: 1809 case ARM::VST1q16_UPD: 1810 case ARM::VST1q32_UPD: 1811 case ARM::VST1q64_UPD: 1812 case ARM::VST1d8T: 1813 case ARM::VST1d16T: 1814 case ARM::VST1d32T: 1815 case ARM::VST1d64T: 1816 case ARM::VST1d8T_UPD: 1817 case ARM::VST1d16T_UPD: 1818 case ARM::VST1d32T_UPD: 1819 case ARM::VST1d64T_UPD: 1820 case ARM::VST1d8Q: 1821 case ARM::VST1d16Q: 1822 case ARM::VST1d32Q: 1823 case ARM::VST1d64Q: 1824 case ARM::VST1d8Q_UPD: 1825 case ARM::VST1d16Q_UPD: 1826 case ARM::VST1d32Q_UPD: 1827 case ARM::VST1d64Q_UPD: 1828 case ARM::VST2d8: 1829 case ARM::VST2d16: 1830 case ARM::VST2d32: 1831 case ARM::VST2d8_UPD: 1832 case ARM::VST2d16_UPD: 1833 case ARM::VST2d32_UPD: 1834 case ARM::VST2q8: 1835 case ARM::VST2q16: 1836 case ARM::VST2q32: 1837 case ARM::VST2q8_UPD: 1838 case ARM::VST2q16_UPD: 1839 case ARM::VST2q32_UPD: 1840 case ARM::VST3d8: 1841 case ARM::VST3d16: 1842 case ARM::VST3d32: 1843 case ARM::VST3d8_UPD: 1844 case ARM::VST3d16_UPD: 1845 case ARM::VST3d32_UPD: 1846 case ARM::VST4d8: 1847 case ARM::VST4d16: 1848 case ARM::VST4d32: 1849 case ARM::VST4d8_UPD: 1850 case ARM::VST4d16_UPD: 1851 case ARM::VST4d32_UPD: 1852 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)); 1853 break; 1854 case ARM::VST2b8: 1855 case ARM::VST2b16: 1856 case ARM::VST2b32: 1857 case ARM::VST2b8_UPD: 1858 case ARM::VST2b16_UPD: 1859 case ARM::VST2b32_UPD: 1860 case ARM::VST3q8: 1861 case ARM::VST3q16: 1862 case ARM::VST3q32: 1863 case ARM::VST3q8_UPD: 1864 case ARM::VST3q16_UPD: 1865 case ARM::VST3q32_UPD: 1866 case ARM::VST4q8: 1867 case ARM::VST4q16: 1868 case ARM::VST4q32: 1869 case ARM::VST4q8_UPD: 1870 case ARM::VST4q16_UPD: 1871 case ARM::VST4q32_UPD: 1872 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); 1873 break; 1874 default: 1875 break; 1876 } 1877 1878 // Third input register 1879 switch (Inst.getOpcode()) { 1880 case ARM::VST1d8T: 1881 case ARM::VST1d16T: 1882 case ARM::VST1d32T: 1883 case ARM::VST1d64T: 1884 case ARM::VST1d8T_UPD: 1885 case ARM::VST1d16T_UPD: 1886 case ARM::VST1d32T_UPD: 1887 case ARM::VST1d64T_UPD: 1888 case ARM::VST1d8Q: 1889 case ARM::VST1d16Q: 1890 case ARM::VST1d32Q: 1891 case ARM::VST1d64Q: 1892 case ARM::VST1d8Q_UPD: 1893 case ARM::VST1d16Q_UPD: 1894 case ARM::VST1d32Q_UPD: 1895 case ARM::VST1d64Q_UPD: 1896 case ARM::VST2q8: 1897 case ARM::VST2q16: 1898 case ARM::VST2q32: 1899 case ARM::VST2q8_UPD: 1900 case ARM::VST2q16_UPD: 1901 case ARM::VST2q32_UPD: 1902 case ARM::VST3d8: 1903 case ARM::VST3d16: 1904 case ARM::VST3d32: 1905 case ARM::VST3d8_UPD: 1906 case ARM::VST3d16_UPD: 1907 case ARM::VST3d32_UPD: 1908 case ARM::VST4d8: 1909 case ARM::VST4d16: 1910 case ARM::VST4d32: 1911 case ARM::VST4d8_UPD: 1912 case ARM::VST4d16_UPD: 1913 case ARM::VST4d32_UPD: 1914 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); 1915 break; 1916 case ARM::VST3q8: 1917 case ARM::VST3q16: 1918 case ARM::VST3q32: 1919 case ARM::VST3q8_UPD: 1920 case ARM::VST3q16_UPD: 1921 case ARM::VST3q32_UPD: 1922 case ARM::VST4q8: 1923 case ARM::VST4q16: 1924 case ARM::VST4q32: 1925 case ARM::VST4q8_UPD: 1926 case ARM::VST4q16_UPD: 1927 case ARM::VST4q32_UPD: 1928 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)); 1929 break; 1930 default: 1931 break; 1932 } 1933 1934 // Fourth input register 1935 switch (Inst.getOpcode()) { 1936 case ARM::VST1d8Q: 1937 case ARM::VST1d16Q: 1938 case ARM::VST1d32Q: 1939 case ARM::VST1d64Q: 1940 case ARM::VST1d8Q_UPD: 1941 case ARM::VST1d16Q_UPD: 1942 case ARM::VST1d32Q_UPD: 1943 case ARM::VST1d64Q_UPD: 1944 case ARM::VST2q8: 1945 case ARM::VST2q16: 1946 case ARM::VST2q32: 1947 case ARM::VST2q8_UPD: 1948 case ARM::VST2q16_UPD: 1949 case ARM::VST2q32_UPD: 1950 case ARM::VST4d8: 1951 case ARM::VST4d16: 1952 case ARM::VST4d32: 1953 case ARM::VST4d8_UPD: 1954 case ARM::VST4d16_UPD: 1955 case ARM::VST4d32_UPD: 1956 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)); 1957 break; 1958 case ARM::VST4q8: 1959 case ARM::VST4q16: 1960 case ARM::VST4q32: 1961 case ARM::VST4q8_UPD: 1962 case ARM::VST4q16_UPD: 1963 case ARM::VST4q32_UPD: 1964 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)); 1965 break; 1966 default: 1967 break; 1968 } 1969 1970 return S; 1971 } 1972 1973 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1974 uint64_t Address, const void *Decoder) { 1975 DecodeStatus S = Success; 1976 1977 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1978 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1979 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1980 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1981 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1982 unsigned size = fieldFromInstruction32(Insn, 6, 2); 1983 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1; 1984 1985 align *= (1 << size); 1986 1987 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 1988 if (regs == 2) { 1989 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)); 1990 } 1991 if (Rm == 0xD) { 1992 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1993 } 1994 1995 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1996 Inst.addOperand(MCOperand::CreateImm(align)); 1997 1998 if (Rm == 0xD) 1999 Inst.addOperand(MCOperand::CreateReg(0)); 2000 else if (Rm != 0xF) { 2001 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2002 } 2003 2004 return S; 2005 } 2006 2007 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2008 uint64_t Address, const void *Decoder) { 2009 DecodeStatus S = Success; 2010 2011 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2012 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2013 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2014 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2015 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2016 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 2017 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2018 align *= 2*size; 2019 2020 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2021 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)); 2022 if (Rm == 0xD) { 2023 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2024 } 2025 2026 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2027 Inst.addOperand(MCOperand::CreateImm(align)); 2028 2029 if (Rm == 0xD) 2030 Inst.addOperand(MCOperand::CreateReg(0)); 2031 else if (Rm != 0xF) { 2032 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2033 } 2034 2035 return S; 2036 } 2037 2038 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2039 uint64_t Address, const void *Decoder) { 2040 DecodeStatus S = Success; 2041 2042 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2043 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2044 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2045 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2046 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2047 2048 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2049 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)); 2050 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)); 2051 if (Rm == 0xD) { 2052 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2053 } 2054 2055 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2056 Inst.addOperand(MCOperand::CreateImm(0)); 2057 2058 if (Rm == 0xD) 2059 Inst.addOperand(MCOperand::CreateReg(0)); 2060 else if (Rm != 0xF) { 2061 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2062 } 2063 2064 return S; 2065 } 2066 2067 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2068 uint64_t Address, const void *Decoder) { 2069 DecodeStatus S = Success; 2070 2071 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2072 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2073 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2074 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2075 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2076 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2077 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2078 2079 if (size == 0x3) { 2080 size = 4; 2081 align = 16; 2082 } else { 2083 if (size == 2) { 2084 size = 1 << size; 2085 align *= 8; 2086 } else { 2087 size = 1 << size; 2088 align *= 4*size; 2089 } 2090 } 2091 2092 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2093 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)); 2094 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)); 2095 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)); 2096 if (Rm == 0xD) { 2097 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2098 } 2099 2100 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2101 Inst.addOperand(MCOperand::CreateImm(align)); 2102 2103 if (Rm == 0xD) 2104 Inst.addOperand(MCOperand::CreateReg(0)); 2105 else if (Rm != 0xF) { 2106 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2107 } 2108 2109 return S; 2110 } 2111 2112 static DecodeStatus 2113 DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 2114 uint64_t Address, const void *Decoder) { 2115 DecodeStatus S = Success; 2116 2117 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2118 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2119 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2120 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 2121 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 2122 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 2123 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 2124 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 2125 2126 if (Q) { 2127 CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)); 2128 } else { 2129 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2130 } 2131 2132 Inst.addOperand(MCOperand::CreateImm(imm)); 2133 2134 switch (Inst.getOpcode()) { 2135 case ARM::VORRiv4i16: 2136 case ARM::VORRiv2i32: 2137 case ARM::VBICiv4i16: 2138 case ARM::VBICiv2i32: 2139 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2140 break; 2141 case ARM::VORRiv8i16: 2142 case ARM::VORRiv4i32: 2143 case ARM::VBICiv8i16: 2144 case ARM::VBICiv4i32: 2145 CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)); 2146 break; 2147 default: 2148 break; 2149 } 2150 2151 return S; 2152 } 2153 2154 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 2155 uint64_t Address, const void *Decoder) { 2156 DecodeStatus S = Success; 2157 2158 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2159 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2160 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2161 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2162 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2163 2164 CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)); 2165 CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)); 2166 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2167 2168 return S; 2169 } 2170 2171 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 2172 uint64_t Address, const void *Decoder) { 2173 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2174 return Success; 2175 } 2176 2177 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2178 uint64_t Address, const void *Decoder) { 2179 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2180 return Success; 2181 } 2182 2183 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2184 uint64_t Address, const void *Decoder) { 2185 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2186 return Success; 2187 } 2188 2189 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2190 uint64_t Address, const void *Decoder) { 2191 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2192 return Success; 2193 } 2194 2195 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2196 uint64_t Address, const void *Decoder) { 2197 DecodeStatus S = Success; 2198 2199 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2200 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2201 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2202 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2203 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2204 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2205 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2206 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; 2207 2208 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2209 if (op) { 2210 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); // Writeback 2211 } 2212 2213 for (unsigned i = 0; i < length; ++i) { 2214 CHECK(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)); 2215 } 2216 2217 CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)); 2218 2219 return S; 2220 } 2221 2222 static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 2223 uint64_t Address, const void *Decoder) { 2224 // The immediate needs to be a fully instantiated float. However, the 2225 // auto-generated decoder is only able to fill in some of the bits 2226 // necessary. For instance, the 'b' bit is replicated multiple times, 2227 // and is even present in inverted form in one bit. We do a little 2228 // binary parsing here to fill in those missing bits, and then 2229 // reinterpret it all as a float. 2230 union { 2231 uint32_t integer; 2232 float fp; 2233 } fp_conv; 2234 2235 fp_conv.integer = Val; 2236 uint32_t b = fieldFromInstruction32(Val, 25, 1); 2237 fp_conv.integer |= b << 26; 2238 fp_conv.integer |= b << 27; 2239 fp_conv.integer |= b << 28; 2240 fp_conv.integer |= b << 29; 2241 fp_conv.integer |= (~b & 0x1) << 30; 2242 2243 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp)); 2244 return Success; 2245 } 2246 2247 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2248 uint64_t Address, const void *Decoder) { 2249 DecodeStatus S = Success; 2250 2251 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2252 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2253 2254 CHECK(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)); 2255 2256 if (Inst.getOpcode() == ARM::tADR) 2257 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2258 else if (Inst.getOpcode() == ARM::tADDrSPi) 2259 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2260 else 2261 return Fail; 2262 2263 Inst.addOperand(MCOperand::CreateImm(imm)); 2264 return S; 2265 } 2266 2267 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2268 uint64_t Address, const void *Decoder) { 2269 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2270 return Success; 2271 } 2272 2273 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2274 uint64_t Address, const void *Decoder) { 2275 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2276 return Success; 2277 } 2278 2279 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2280 uint64_t Address, const void *Decoder) { 2281 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2282 return Success; 2283 } 2284 2285 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2286 uint64_t Address, const void *Decoder) { 2287 DecodeStatus S = Success; 2288 2289 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2290 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2291 2292 CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)); 2293 CHECK(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)); 2294 2295 return S; 2296 } 2297 2298 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2299 uint64_t Address, const void *Decoder) { 2300 DecodeStatus S = Success; 2301 2302 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2303 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2304 2305 CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)); 2306 Inst.addOperand(MCOperand::CreateImm(imm)); 2307 2308 return S; 2309 } 2310 2311 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2312 uint64_t Address, const void *Decoder) { 2313 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2314 2315 return Success; 2316 } 2317 2318 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2319 uint64_t Address, const void *Decoder) { 2320 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2321 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2322 2323 return Success; 2324 } 2325 2326 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2327 uint64_t Address, const void *Decoder) { 2328 DecodeStatus S = Success; 2329 2330 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2331 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2332 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2333 2334 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2335 CHECK(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)); 2336 Inst.addOperand(MCOperand::CreateImm(imm)); 2337 2338 return S; 2339 } 2340 2341 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2342 uint64_t Address, const void *Decoder) { 2343 DecodeStatus S = Success; 2344 2345 if (Inst.getOpcode() != ARM::t2PLDs) { 2346 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2347 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2348 } 2349 2350 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2351 if (Rn == 0xF) { 2352 switch (Inst.getOpcode()) { 2353 case ARM::t2LDRBs: 2354 Inst.setOpcode(ARM::t2LDRBpci); 2355 break; 2356 case ARM::t2LDRHs: 2357 Inst.setOpcode(ARM::t2LDRHpci); 2358 break; 2359 case ARM::t2LDRSHs: 2360 Inst.setOpcode(ARM::t2LDRSHpci); 2361 break; 2362 case ARM::t2LDRSBs: 2363 Inst.setOpcode(ARM::t2LDRSBpci); 2364 break; 2365 case ARM::t2PLDs: 2366 Inst.setOpcode(ARM::t2PLDi12); 2367 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2368 break; 2369 default: 2370 return Fail; 2371 } 2372 2373 int imm = fieldFromInstruction32(Insn, 0, 12); 2374 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2375 Inst.addOperand(MCOperand::CreateImm(imm)); 2376 2377 return S; 2378 } 2379 2380 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2381 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2382 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2383 CHECK(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)); 2384 2385 return S; 2386 } 2387 2388 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2389 uint64_t Address, const void *Decoder) { 2390 int imm = Val & 0xFF; 2391 if (!(Val & 0x100)) imm *= -1; 2392 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2393 2394 return Success; 2395 } 2396 2397 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2398 uint64_t Address, const void *Decoder) { 2399 DecodeStatus S = Success; 2400 2401 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2402 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2403 2404 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2405 CHECK(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)); 2406 2407 return S; 2408 } 2409 2410 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2411 uint64_t Address, const void *Decoder) { 2412 int imm = Val & 0xFF; 2413 if (!(Val & 0x100)) imm *= -1; 2414 Inst.addOperand(MCOperand::CreateImm(imm)); 2415 2416 return Success; 2417 } 2418 2419 2420 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 2421 uint64_t Address, const void *Decoder) { 2422 DecodeStatus S = Success; 2423 2424 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2425 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2426 2427 // Some instructions always use an additive offset. 2428 switch (Inst.getOpcode()) { 2429 case ARM::t2LDRT: 2430 case ARM::t2LDRBT: 2431 case ARM::t2LDRHT: 2432 case ARM::t2LDRSBT: 2433 case ARM::t2LDRSHT: 2434 imm |= 0x100; 2435 break; 2436 default: 2437 break; 2438 } 2439 2440 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2441 CHECK(S, DecodeT2Imm8(Inst, imm, Address, Decoder)); 2442 2443 return S; 2444 } 2445 2446 2447 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 2448 uint64_t Address, const void *Decoder) { 2449 DecodeStatus S = Success; 2450 2451 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2452 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2453 2454 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2455 Inst.addOperand(MCOperand::CreateImm(imm)); 2456 2457 return S; 2458 } 2459 2460 2461 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 2462 uint64_t Address, const void *Decoder) { 2463 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 2464 2465 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2466 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2467 Inst.addOperand(MCOperand::CreateImm(imm)); 2468 2469 return Success; 2470 } 2471 2472 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 2473 uint64_t Address, const void *Decoder) { 2474 DecodeStatus S = Success; 2475 2476 if (Inst.getOpcode() == ARM::tADDrSP) { 2477 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 2478 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 2479 2480 CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)); 2481 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2482 CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)); 2483 } else if (Inst.getOpcode() == ARM::tADDspr) { 2484 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 2485 2486 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2487 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2488 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2489 } 2490 2491 return S; 2492 } 2493 2494 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 2495 uint64_t Address, const void *Decoder) { 2496 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 2497 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 2498 2499 Inst.addOperand(MCOperand::CreateImm(imod)); 2500 Inst.addOperand(MCOperand::CreateImm(flags)); 2501 2502 return Success; 2503 } 2504 2505 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 2506 uint64_t Address, const void *Decoder) { 2507 DecodeStatus S = Success; 2508 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2509 unsigned add = fieldFromInstruction32(Insn, 4, 1); 2510 2511 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) ; 2512 Inst.addOperand(MCOperand::CreateImm(add)); 2513 2514 return S; 2515 } 2516 2517 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 2518 uint64_t Address, const void *Decoder) { 2519 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2520 return Success; 2521 } 2522 2523 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 2524 uint64_t Address, const void *Decoder) { 2525 if (Val == 0xA || Val == 0xB) 2526 return Fail; 2527 2528 Inst.addOperand(MCOperand::CreateImm(Val)); 2529 return Success; 2530 } 2531 2532 static DecodeStatus 2533 DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 2534 uint64_t Address, const void *Decoder) { 2535 DecodeStatus S = Success; 2536 2537 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 2538 if (pred == 0xE || pred == 0xF) { 2539 unsigned opc = fieldFromInstruction32(Insn, 4, 2); 2540 switch (opc) { 2541 default: 2542 return Fail; 2543 case 0: 2544 Inst.setOpcode(ARM::t2DSB); 2545 break; 2546 case 1: 2547 Inst.setOpcode(ARM::t2DMB); 2548 break; 2549 case 2: 2550 Inst.setOpcode(ARM::t2ISB); 2551 return Success; 2552 } 2553 2554 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2555 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 2556 } 2557 2558 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 2559 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 2560 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 2561 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 2562 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 2563 2564 CHECK(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)); 2565 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2566 2567 return S; 2568 } 2569 2570 // Decode a shifted immediate operand. These basically consist 2571 // of an 8-bit value, and a 4-bit directive that specifies either 2572 // a splat operation or a rotation. 2573 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 2574 uint64_t Address, const void *Decoder) { 2575 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 2576 if (ctrl == 0) { 2577 unsigned byte = fieldFromInstruction32(Val, 8, 2); 2578 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2579 switch (byte) { 2580 case 0: 2581 Inst.addOperand(MCOperand::CreateImm(imm)); 2582 break; 2583 case 1: 2584 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 2585 break; 2586 case 2: 2587 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 2588 break; 2589 case 3: 2590 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 2591 (imm << 8) | imm)); 2592 break; 2593 } 2594 } else { 2595 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 2596 unsigned rot = fieldFromInstruction32(Val, 7, 5); 2597 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 2598 Inst.addOperand(MCOperand::CreateImm(imm)); 2599 } 2600 2601 return Success; 2602 } 2603 2604 static DecodeStatus 2605 DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 2606 uint64_t Address, const void *Decoder){ 2607 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 2608 return Success; 2609 } 2610 2611 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 2612 uint64_t Address, const void *Decoder){ 2613 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2614 return Success; 2615 } 2616 2617 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 2618 uint64_t Address, const void *Decoder) { 2619 switch (Val) { 2620 default: 2621 return Fail; 2622 case 0xF: // SY 2623 case 0xE: // ST 2624 case 0xB: // ISH 2625 case 0xA: // ISHST 2626 case 0x7: // NSH 2627 case 0x6: // NSHST 2628 case 0x3: // OSH 2629 case 0x2: // OSHST 2630 break; 2631 } 2632 2633 Inst.addOperand(MCOperand::CreateImm(Val)); 2634 return Success; 2635 } 2636 2637 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, 2638 uint64_t Address, const void *Decoder) { 2639 if (!Val) return Fail; 2640 Inst.addOperand(MCOperand::CreateImm(Val)); 2641 return Success; 2642 } 2643 2644 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 2645 uint64_t Address, const void *Decoder) { 2646 DecodeStatus S = Success; 2647 2648 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2649 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2650 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2651 2652 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail; 2653 2654 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2655 CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)); 2656 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2657 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2658 2659 return S; 2660 } 2661 2662 2663 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 2664 uint64_t Address, const void *Decoder){ 2665 DecodeStatus S = Success; 2666 2667 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2668 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 2669 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2670 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2671 2672 CHECK(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)); 2673 2674 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail; 2675 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return Fail; 2676 2677 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2678 CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)); 2679 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2680 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2681 2682 return S; 2683 } 2684 2685 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 2686 uint64_t Address, const void *Decoder) { 2687 DecodeStatus S = Success; 2688 2689 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2690 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2691 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2692 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2693 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2694 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2695 2696 if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable); 2697 2698 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2699 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2700 CHECK(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)); 2701 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2702 2703 return S; 2704 } 2705 2706 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 2707 uint64_t Address, const void *Decoder) { 2708 DecodeStatus S = Success; 2709 2710 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2711 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2712 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2713 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2714 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2715 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2716 2717 if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable); 2718 2719 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2720 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2721 CHECK(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)); 2722 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2723 2724 return S; 2725 } 2726 2727 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 2728 uint64_t Address, const void *Decoder) { 2729 DecodeStatus S = Success; 2730 2731 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2732 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2733 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2734 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2735 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2736 2737 unsigned align = 0; 2738 unsigned index = 0; 2739 switch (size) { 2740 default: 2741 return Fail; 2742 case 0: 2743 if (fieldFromInstruction32(Insn, 4, 1)) 2744 return Fail; // UNDEFINED 2745 index = fieldFromInstruction32(Insn, 5, 3); 2746 break; 2747 case 1: 2748 if (fieldFromInstruction32(Insn, 5, 1)) 2749 return Fail; // UNDEFINED 2750 index = fieldFromInstruction32(Insn, 6, 2); 2751 if (fieldFromInstruction32(Insn, 4, 1)) 2752 align = 2; 2753 break; 2754 case 2: 2755 if (fieldFromInstruction32(Insn, 6, 1)) 2756 return Fail; // UNDEFINED 2757 index = fieldFromInstruction32(Insn, 7, 1); 2758 if (fieldFromInstruction32(Insn, 4, 2) != 0) 2759 align = 4; 2760 } 2761 2762 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2763 if (Rm != 0xF) { // Writeback 2764 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2765 } 2766 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2767 Inst.addOperand(MCOperand::CreateImm(align)); 2768 if (Rm != 0xF && Rm != 0xD) { 2769 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2770 } 2771 2772 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2773 Inst.addOperand(MCOperand::CreateImm(index)); 2774 2775 return S; 2776 } 2777 2778 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 2779 uint64_t Address, const void *Decoder) { 2780 DecodeStatus S = Success; 2781 2782 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2783 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2784 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2785 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2786 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2787 2788 unsigned align = 0; 2789 unsigned index = 0; 2790 switch (size) { 2791 default: 2792 return Fail; 2793 case 0: 2794 if (fieldFromInstruction32(Insn, 4, 1)) 2795 return Fail; // UNDEFINED 2796 index = fieldFromInstruction32(Insn, 5, 3); 2797 break; 2798 case 1: 2799 if (fieldFromInstruction32(Insn, 5, 1)) 2800 return Fail; // UNDEFINED 2801 index = fieldFromInstruction32(Insn, 6, 2); 2802 if (fieldFromInstruction32(Insn, 4, 1)) 2803 align = 2; 2804 break; 2805 case 2: 2806 if (fieldFromInstruction32(Insn, 6, 1)) 2807 return Fail; // UNDEFINED 2808 index = fieldFromInstruction32(Insn, 7, 1); 2809 if (fieldFromInstruction32(Insn, 4, 2) != 0) 2810 align = 4; 2811 } 2812 2813 if (Rm != 0xF) { // Writeback 2814 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2815 } 2816 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2817 Inst.addOperand(MCOperand::CreateImm(align)); 2818 if (Rm != 0xF && Rm != 0xD) { 2819 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2820 } 2821 2822 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2823 Inst.addOperand(MCOperand::CreateImm(index)); 2824 2825 return S; 2826 } 2827 2828 2829 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 2830 uint64_t Address, const void *Decoder) { 2831 DecodeStatus S = Success; 2832 2833 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2834 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2835 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2836 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2837 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2838 2839 unsigned align = 0; 2840 unsigned index = 0; 2841 unsigned inc = 1; 2842 switch (size) { 2843 default: 2844 return Fail; 2845 case 0: 2846 index = fieldFromInstruction32(Insn, 5, 3); 2847 if (fieldFromInstruction32(Insn, 4, 1)) 2848 align = 2; 2849 break; 2850 case 1: 2851 index = fieldFromInstruction32(Insn, 6, 2); 2852 if (fieldFromInstruction32(Insn, 4, 1)) 2853 align = 4; 2854 if (fieldFromInstruction32(Insn, 5, 1)) 2855 inc = 2; 2856 break; 2857 case 2: 2858 if (fieldFromInstruction32(Insn, 5, 1)) 2859 return Fail; // UNDEFINED 2860 index = fieldFromInstruction32(Insn, 7, 1); 2861 if (fieldFromInstruction32(Insn, 4, 1) != 0) 2862 align = 8; 2863 if (fieldFromInstruction32(Insn, 6, 1)) 2864 inc = 2; 2865 break; 2866 } 2867 2868 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2869 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 2870 if (Rm != 0xF) { // Writeback 2871 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2872 } 2873 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2874 Inst.addOperand(MCOperand::CreateImm(align)); 2875 if (Rm != 0xF && Rm != 0xD) { 2876 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2877 } 2878 2879 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2880 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 2881 Inst.addOperand(MCOperand::CreateImm(index)); 2882 2883 return S; 2884 } 2885 2886 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 2887 uint64_t Address, const void *Decoder) { 2888 DecodeStatus S = Success; 2889 2890 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2891 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2892 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2893 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2894 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2895 2896 unsigned align = 0; 2897 unsigned index = 0; 2898 unsigned inc = 1; 2899 switch (size) { 2900 default: 2901 return Fail; 2902 case 0: 2903 index = fieldFromInstruction32(Insn, 5, 3); 2904 if (fieldFromInstruction32(Insn, 4, 1)) 2905 align = 2; 2906 break; 2907 case 1: 2908 index = fieldFromInstruction32(Insn, 6, 2); 2909 if (fieldFromInstruction32(Insn, 4, 1)) 2910 align = 4; 2911 if (fieldFromInstruction32(Insn, 5, 1)) 2912 inc = 2; 2913 break; 2914 case 2: 2915 if (fieldFromInstruction32(Insn, 5, 1)) 2916 return Fail; // UNDEFINED 2917 index = fieldFromInstruction32(Insn, 7, 1); 2918 if (fieldFromInstruction32(Insn, 4, 1) != 0) 2919 align = 8; 2920 if (fieldFromInstruction32(Insn, 6, 1)) 2921 inc = 2; 2922 break; 2923 } 2924 2925 if (Rm != 0xF) { // Writeback 2926 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2927 } 2928 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2929 Inst.addOperand(MCOperand::CreateImm(align)); 2930 if (Rm != 0xF && Rm != 0xD) { 2931 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2932 } 2933 2934 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2935 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 2936 Inst.addOperand(MCOperand::CreateImm(index)); 2937 2938 return S; 2939 } 2940 2941 2942 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 2943 uint64_t Address, const void *Decoder) { 2944 DecodeStatus S = Success; 2945 2946 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2947 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2948 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2949 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2950 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2951 2952 unsigned align = 0; 2953 unsigned index = 0; 2954 unsigned inc = 1; 2955 switch (size) { 2956 default: 2957 return Fail; 2958 case 0: 2959 if (fieldFromInstruction32(Insn, 4, 1)) 2960 return Fail; // UNDEFINED 2961 index = fieldFromInstruction32(Insn, 5, 3); 2962 break; 2963 case 1: 2964 if (fieldFromInstruction32(Insn, 4, 1)) 2965 return Fail; // UNDEFINED 2966 index = fieldFromInstruction32(Insn, 6, 2); 2967 if (fieldFromInstruction32(Insn, 5, 1)) 2968 inc = 2; 2969 break; 2970 case 2: 2971 if (fieldFromInstruction32(Insn, 4, 2)) 2972 return Fail; // UNDEFINED 2973 index = fieldFromInstruction32(Insn, 7, 1); 2974 if (fieldFromInstruction32(Insn, 6, 1)) 2975 inc = 2; 2976 break; 2977 } 2978 2979 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2980 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 2981 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 2982 2983 if (Rm != 0xF) { // Writeback 2984 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2985 } 2986 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2987 Inst.addOperand(MCOperand::CreateImm(align)); 2988 if (Rm != 0xF && Rm != 0xD) { 2989 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2990 } 2991 2992 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2993 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 2994 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 2995 Inst.addOperand(MCOperand::CreateImm(index)); 2996 2997 return S; 2998 } 2999 3000 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 3001 uint64_t Address, const void *Decoder) { 3002 DecodeStatus S = Success; 3003 3004 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3005 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3006 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3007 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3008 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3009 3010 unsigned align = 0; 3011 unsigned index = 0; 3012 unsigned inc = 1; 3013 switch (size) { 3014 default: 3015 return Fail; 3016 case 0: 3017 if (fieldFromInstruction32(Insn, 4, 1)) 3018 return Fail; // UNDEFINED 3019 index = fieldFromInstruction32(Insn, 5, 3); 3020 break; 3021 case 1: 3022 if (fieldFromInstruction32(Insn, 4, 1)) 3023 return Fail; // UNDEFINED 3024 index = fieldFromInstruction32(Insn, 6, 2); 3025 if (fieldFromInstruction32(Insn, 5, 1)) 3026 inc = 2; 3027 break; 3028 case 2: 3029 if (fieldFromInstruction32(Insn, 4, 2)) 3030 return Fail; // UNDEFINED 3031 index = fieldFromInstruction32(Insn, 7, 1); 3032 if (fieldFromInstruction32(Insn, 6, 1)) 3033 inc = 2; 3034 break; 3035 } 3036 3037 if (Rm != 0xF) { // Writeback 3038 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3039 } 3040 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3041 Inst.addOperand(MCOperand::CreateImm(align)); 3042 if (Rm != 0xF && Rm != 0xD) { 3043 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 3044 } 3045 3046 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 3047 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 3048 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 3049 Inst.addOperand(MCOperand::CreateImm(index)); 3050 3051 return S; 3052 } 3053 3054 3055 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 3056 uint64_t Address, const void *Decoder) { 3057 DecodeStatus S = Success; 3058 3059 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3060 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3061 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3062 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3063 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3064 3065 unsigned align = 0; 3066 unsigned index = 0; 3067 unsigned inc = 1; 3068 switch (size) { 3069 default: 3070 return Fail; 3071 case 0: 3072 if (fieldFromInstruction32(Insn, 4, 1)) 3073 align = 4; 3074 index = fieldFromInstruction32(Insn, 5, 3); 3075 break; 3076 case 1: 3077 if (fieldFromInstruction32(Insn, 4, 1)) 3078 align = 8; 3079 index = fieldFromInstruction32(Insn, 6, 2); 3080 if (fieldFromInstruction32(Insn, 5, 1)) 3081 inc = 2; 3082 break; 3083 case 2: 3084 if (fieldFromInstruction32(Insn, 4, 2)) 3085 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3086 index = fieldFromInstruction32(Insn, 7, 1); 3087 if (fieldFromInstruction32(Insn, 6, 1)) 3088 inc = 2; 3089 break; 3090 } 3091 3092 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 3093 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 3094 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 3095 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)); 3096 3097 if (Rm != 0xF) { // Writeback 3098 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3099 } 3100 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3101 Inst.addOperand(MCOperand::CreateImm(align)); 3102 if (Rm != 0xF && Rm != 0xD) { 3103 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 3104 } 3105 3106 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 3107 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 3108 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 3109 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)); 3110 Inst.addOperand(MCOperand::CreateImm(index)); 3111 3112 return S; 3113 } 3114 3115 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 3116 uint64_t Address, const void *Decoder) { 3117 DecodeStatus S = Success; 3118 3119 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3120 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3121 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3122 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3123 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3124 3125 unsigned align = 0; 3126 unsigned index = 0; 3127 unsigned inc = 1; 3128 switch (size) { 3129 default: 3130 return Fail; 3131 case 0: 3132 if (fieldFromInstruction32(Insn, 4, 1)) 3133 align = 4; 3134 index = fieldFromInstruction32(Insn, 5, 3); 3135 break; 3136 case 1: 3137 if (fieldFromInstruction32(Insn, 4, 1)) 3138 align = 8; 3139 index = fieldFromInstruction32(Insn, 6, 2); 3140 if (fieldFromInstruction32(Insn, 5, 1)) 3141 inc = 2; 3142 break; 3143 case 2: 3144 if (fieldFromInstruction32(Insn, 4, 2)) 3145 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3146 index = fieldFromInstruction32(Insn, 7, 1); 3147 if (fieldFromInstruction32(Insn, 6, 1)) 3148 inc = 2; 3149 break; 3150 } 3151 3152 if (Rm != 0xF) { // Writeback 3153 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3154 } 3155 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3156 Inst.addOperand(MCOperand::CreateImm(align)); 3157 if (Rm != 0xF && Rm != 0xD) { 3158 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 3159 } 3160 3161 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 3162 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 3163 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 3164 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)); 3165 Inst.addOperand(MCOperand::CreateImm(index)); 3166 3167 return S; 3168 } 3169 3170