1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "ARM.h" 13 #include "ARMSubtarget.h" 14 #include "MCTargetDesc/ARMAddressingModes.h" 15 #include "MCTargetDesc/ARMMCExpr.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "llvm/MC/EDInstInfo.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/MC/MCExpr.h" 21 #include "llvm/MC/MCContext.h" 22 #include "llvm/MC/MCDisassembler.h" 23 #include "llvm/Support/Debug.h" 24 #include "llvm/Support/MemoryObject.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/TargetRegistry.h" 27 #include "llvm/Support/raw_ostream.h" 28 29 using namespace llvm; 30 31 typedef MCDisassembler::DecodeStatus DecodeStatus; 32 33 namespace { 34 /// ARMDisassembler - ARM disassembler for all ARM platforms. 35 class ARMDisassembler : public MCDisassembler { 36 public: 37 /// Constructor - Initializes the disassembler. 38 /// 39 ARMDisassembler(const MCSubtargetInfo &STI) : 40 MCDisassembler(STI) { 41 } 42 43 ~ARMDisassembler() { 44 } 45 46 /// getInstruction - See MCDisassembler. 47 DecodeStatus getInstruction(MCInst &instr, 48 uint64_t &size, 49 const MemoryObject ®ion, 50 uint64_t address, 51 raw_ostream &vStream, 52 raw_ostream &cStream) const; 53 54 /// getEDInfo - See MCDisassembler. 55 const EDInstInfo *getEDInfo() const; 56 private: 57 }; 58 59 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 60 class ThumbDisassembler : public MCDisassembler { 61 public: 62 /// Constructor - Initializes the disassembler. 63 /// 64 ThumbDisassembler(const MCSubtargetInfo &STI) : 65 MCDisassembler(STI) { 66 } 67 68 ~ThumbDisassembler() { 69 } 70 71 /// getInstruction - See MCDisassembler. 72 DecodeStatus getInstruction(MCInst &instr, 73 uint64_t &size, 74 const MemoryObject ®ion, 75 uint64_t address, 76 raw_ostream &vStream, 77 raw_ostream &cStream) const; 78 79 /// getEDInfo - See MCDisassembler. 80 const EDInstInfo *getEDInfo() const; 81 private: 82 mutable std::vector<unsigned> ITBlock; 83 DecodeStatus AddThumbPredicate(MCInst&) const; 84 void UpdateThumbVFPPredicate(MCInst&) const; 85 }; 86 } 87 88 static bool Check(DecodeStatus &Out, DecodeStatus In) { 89 switch (In) { 90 case MCDisassembler::Success: 91 // Out stays the same. 92 return true; 93 case MCDisassembler::SoftFail: 94 Out = In; 95 return true; 96 case MCDisassembler::Fail: 97 Out = In; 98 return false; 99 } 100 llvm_unreachable("Invalid DecodeStatus!"); 101 } 102 103 104 // Forward declare these because the autogenerated code will reference them. 105 // Definitions are further down. 106 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 107 uint64_t Address, const void *Decoder); 108 static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, 109 unsigned RegNo, uint64_t Address, 110 const void *Decoder); 111 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 112 uint64_t Address, const void *Decoder); 113 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 114 uint64_t Address, const void *Decoder); 115 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 116 uint64_t Address, const void *Decoder); 117 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 118 uint64_t Address, const void *Decoder); 119 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 120 uint64_t Address, const void *Decoder); 121 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 122 uint64_t Address, const void *Decoder); 123 static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, 124 unsigned RegNo, 125 uint64_t Address, 126 const void *Decoder); 127 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 128 uint64_t Address, const void *Decoder); 129 static DecodeStatus DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 130 uint64_t Address, const void *Decoder); 131 static DecodeStatus DecodeDPairSpacedRegisterClass(llvm::MCInst &Inst, 132 unsigned RegNo, uint64_t Address, 133 const void *Decoder); 134 135 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 136 uint64_t Address, const void *Decoder); 137 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 138 uint64_t Address, const void *Decoder); 139 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 140 uint64_t Address, const void *Decoder); 141 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 142 uint64_t Address, const void *Decoder); 143 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 144 uint64_t Address, const void *Decoder); 145 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 146 uint64_t Address, const void *Decoder); 147 148 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 149 uint64_t Address, const void *Decoder); 150 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 151 uint64_t Address, const void *Decoder); 152 static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, 153 unsigned Insn, 154 uint64_t Address, 155 const void *Decoder); 156 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 157 uint64_t Address, const void *Decoder); 158 static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn, 159 uint64_t Address, const void *Decoder); 160 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 161 uint64_t Address, const void *Decoder); 162 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 163 uint64_t Address, const void *Decoder); 164 165 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 166 unsigned Insn, 167 uint64_t Adddress, 168 const void *Decoder); 169 static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 170 uint64_t Address, const void *Decoder); 171 static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 172 uint64_t Address, const void *Decoder); 173 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 174 uint64_t Address, const void *Decoder); 175 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 176 uint64_t Address, const void *Decoder); 177 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 178 uint64_t Address, const void *Decoder); 179 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 180 uint64_t Address, const void *Decoder); 181 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 182 uint64_t Address, const void *Decoder); 183 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 184 uint64_t Address, const void *Decoder); 185 static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn, 186 uint64_t Address, const void *Decoder); 187 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 188 uint64_t Address, const void *Decoder); 189 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 190 uint64_t Address, const void *Decoder); 191 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 192 uint64_t Address, const void *Decoder); 193 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 194 uint64_t Address, const void *Decoder); 195 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 196 uint64_t Address, const void *Decoder); 197 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 198 uint64_t Address, const void *Decoder); 199 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 200 uint64_t Address, const void *Decoder); 201 static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 204 uint64_t Address, const void *Decoder); 205 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 206 uint64_t Address, const void *Decoder); 207 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 208 uint64_t Address, const void *Decoder); 209 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 214 uint64_t Address, const void *Decoder); 215 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 216 uint64_t Address, const void *Decoder); 217 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 218 uint64_t Address, const void *Decoder); 219 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 220 uint64_t Address, const void *Decoder); 221 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, 222 uint64_t Address, const void *Decoder); 223 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 224 uint64_t Address, const void *Decoder); 225 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 226 uint64_t Address, const void *Decoder); 227 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 228 uint64_t Address, const void *Decoder); 229 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 230 uint64_t Address, const void *Decoder); 231 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 232 uint64_t Address, const void *Decoder); 233 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 234 uint64_t Address, const void *Decoder); 235 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 236 uint64_t Address, const void *Decoder); 237 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 238 uint64_t Address, const void *Decoder); 239 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 240 uint64_t Address, const void *Decoder); 241 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 242 uint64_t Address, const void *Decoder); 243 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 244 uint64_t Address, const void *Decoder); 245 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 246 uint64_t Address, const void *Decoder); 247 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 248 uint64_t Address, const void *Decoder); 249 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 250 uint64_t Address, const void *Decoder); 251 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 252 uint64_t Address, const void *Decoder); 253 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 254 uint64_t Address, const void *Decoder); 255 static DecodeStatus DecodeSwap(llvm::MCInst &Inst, unsigned Insn, 256 uint64_t Address, const void *Decoder); 257 static DecodeStatus DecodeVCVTD(llvm::MCInst &Inst, unsigned Insn, 258 uint64_t Address, const void *Decoder); 259 static DecodeStatus DecodeVCVTQ(llvm::MCInst &Inst, unsigned Insn, 260 uint64_t Address, const void *Decoder); 261 262 263 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 264 uint64_t Address, const void *Decoder); 265 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 266 uint64_t Address, const void *Decoder); 267 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 268 uint64_t Address, const void *Decoder); 269 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 270 uint64_t Address, const void *Decoder); 271 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 272 uint64_t Address, const void *Decoder); 273 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 274 uint64_t Address, const void *Decoder); 275 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 276 uint64_t Address, const void *Decoder); 277 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 278 uint64_t Address, const void *Decoder); 279 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 280 uint64_t Address, const void *Decoder); 281 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 282 uint64_t Address, const void *Decoder); 283 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 284 uint64_t Address, const void *Decoder); 285 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 286 uint64_t Address, const void *Decoder); 287 static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val, 288 uint64_t Address, const void *Decoder); 289 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 290 uint64_t Address, const void *Decoder); 291 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 292 uint64_t Address, const void *Decoder); 293 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 294 uint64_t Address, const void *Decoder); 295 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 296 uint64_t Address, const void *Decoder); 297 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 298 uint64_t Address, const void *Decoder); 299 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 300 uint64_t Address, const void *Decoder); 301 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 302 uint64_t Address, const void *Decoder); 303 static DecodeStatus DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Val, 304 uint64_t Address, const void *Decoder); 305 static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 306 uint64_t Address, const void *Decoder); 307 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 308 uint64_t Address, const void *Decoder); 309 static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val, 310 uint64_t Address, const void *Decoder); 311 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 312 uint64_t Address, const void *Decoder); 313 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val, 314 uint64_t Address, const void *Decoder); 315 static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, 316 uint64_t Address, const void *Decoder); 317 static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, 318 uint64_t Address, const void *Decoder); 319 static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val, 320 uint64_t Address, const void *Decoder); 321 static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val, 322 uint64_t Address, const void *Decoder); 323 static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, unsigned Val, 324 uint64_t Address, const void *Decoder); 325 326 327 328 #include "ARMGenDisassemblerTables.inc" 329 #include "ARMGenInstrInfo.inc" 330 #include "ARMGenEDInfo.inc" 331 332 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 333 return new ARMDisassembler(STI); 334 } 335 336 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 337 return new ThumbDisassembler(STI); 338 } 339 340 const EDInstInfo *ARMDisassembler::getEDInfo() const { 341 return instInfoARM; 342 } 343 344 const EDInstInfo *ThumbDisassembler::getEDInfo() const { 345 return instInfoARM; 346 } 347 348 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 349 const MemoryObject &Region, 350 uint64_t Address, 351 raw_ostream &os, 352 raw_ostream &cs) const { 353 CommentStream = &cs; 354 355 uint8_t bytes[4]; 356 357 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 358 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 359 360 // We want to read exactly 4 bytes of data. 361 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 362 Size = 0; 363 return MCDisassembler::Fail; 364 } 365 366 // Encoded as a small-endian 32-bit word in the stream. 367 uint32_t insn = (bytes[3] << 24) | 368 (bytes[2] << 16) | 369 (bytes[1] << 8) | 370 (bytes[0] << 0); 371 372 // Calling the auto-generated decoder function. 373 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI); 374 if (result != MCDisassembler::Fail) { 375 Size = 4; 376 return result; 377 } 378 379 // VFP and NEON instructions, similarly, are shared between ARM 380 // and Thumb modes. 381 MI.clear(); 382 result = decodeVFPInstruction32(MI, insn, Address, this, STI); 383 if (result != MCDisassembler::Fail) { 384 Size = 4; 385 return result; 386 } 387 388 MI.clear(); 389 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI); 390 if (result != MCDisassembler::Fail) { 391 Size = 4; 392 // Add a fake predicate operand, because we share these instruction 393 // definitions with Thumb2 where these instructions are predicable. 394 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 395 return MCDisassembler::Fail; 396 return result; 397 } 398 399 MI.clear(); 400 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI); 401 if (result != MCDisassembler::Fail) { 402 Size = 4; 403 // Add a fake predicate operand, because we share these instruction 404 // definitions with Thumb2 where these instructions are predicable. 405 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 406 return MCDisassembler::Fail; 407 return result; 408 } 409 410 MI.clear(); 411 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI); 412 if (result != MCDisassembler::Fail) { 413 Size = 4; 414 // Add a fake predicate operand, because we share these instruction 415 // definitions with Thumb2 where these instructions are predicable. 416 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 417 return MCDisassembler::Fail; 418 return result; 419 } 420 421 MI.clear(); 422 423 Size = 0; 424 return MCDisassembler::Fail; 425 } 426 427 namespace llvm { 428 extern const MCInstrDesc ARMInsts[]; 429 } 430 431 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 432 /// immediate Value in the MCInst. The immediate Value has had any PC 433 /// adjustment made by the caller. If the instruction is a branch instruction 434 /// then isBranch is true, else false. If the getOpInfo() function was set as 435 /// part of the setupForSymbolicDisassembly() call then that function is called 436 /// to get any symbolic information at the Address for this instruction. If 437 /// that returns non-zero then the symbolic information it returns is used to 438 /// create an MCExpr and that is added as an operand to the MCInst. If 439 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 440 /// Value is done and if a symbol is found an MCExpr is created with that, else 441 /// an MCExpr with Value is created. This function returns true if it adds an 442 /// operand to the MCInst and false otherwise. 443 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 444 bool isBranch, uint64_t InstSize, 445 MCInst &MI, const void *Decoder) { 446 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 447 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback(); 448 struct LLVMOpInfo1 SymbolicOp; 449 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1)); 450 SymbolicOp.Value = Value; 451 void *DisInfo = Dis->getDisInfoBlock(); 452 453 if (!getOpInfo || 454 !getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) { 455 // Clear SymbolicOp.Value from above and also all other fields. 456 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1)); 457 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 458 if (!SymbolLookUp) 459 return false; 460 uint64_t ReferenceType; 461 if (isBranch) 462 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch; 463 else 464 ReferenceType = LLVMDisassembler_ReferenceType_InOut_None; 465 const char *ReferenceName; 466 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address, 467 &ReferenceName); 468 if (Name) { 469 SymbolicOp.AddSymbol.Name = Name; 470 SymbolicOp.AddSymbol.Present = true; 471 } 472 // For branches always create an MCExpr so it gets printed as hex address. 473 else if (isBranch) { 474 SymbolicOp.Value = Value; 475 } 476 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub) 477 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName; 478 if (!Name && !isBranch) 479 return false; 480 } 481 482 MCContext *Ctx = Dis->getMCContext(); 483 const MCExpr *Add = NULL; 484 if (SymbolicOp.AddSymbol.Present) { 485 if (SymbolicOp.AddSymbol.Name) { 486 StringRef Name(SymbolicOp.AddSymbol.Name); 487 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 488 Add = MCSymbolRefExpr::Create(Sym, *Ctx); 489 } else { 490 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx); 491 } 492 } 493 494 const MCExpr *Sub = NULL; 495 if (SymbolicOp.SubtractSymbol.Present) { 496 if (SymbolicOp.SubtractSymbol.Name) { 497 StringRef Name(SymbolicOp.SubtractSymbol.Name); 498 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 499 Sub = MCSymbolRefExpr::Create(Sym, *Ctx); 500 } else { 501 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx); 502 } 503 } 504 505 const MCExpr *Off = NULL; 506 if (SymbolicOp.Value != 0) 507 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx); 508 509 const MCExpr *Expr; 510 if (Sub) { 511 const MCExpr *LHS; 512 if (Add) 513 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx); 514 else 515 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx); 516 if (Off != 0) 517 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx); 518 else 519 Expr = LHS; 520 } else if (Add) { 521 if (Off != 0) 522 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx); 523 else 524 Expr = Add; 525 } else { 526 if (Off != 0) 527 Expr = Off; 528 else 529 Expr = MCConstantExpr::Create(0, *Ctx); 530 } 531 532 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16) 533 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx))); 534 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16) 535 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx))); 536 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None) 537 MI.addOperand(MCOperand::CreateExpr(Expr)); 538 else 539 llvm_unreachable("bad SymbolicOp.VariantKind"); 540 541 return true; 542 } 543 544 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 545 /// referenced by a load instruction with the base register that is the Pc. 546 /// These can often be values in a literal pool near the Address of the 547 /// instruction. The Address of the instruction and its immediate Value are 548 /// used as a possible literal pool entry. The SymbolLookUp call back will 549 /// return the name of a symbol referenced by the the literal pool's entry if 550 /// the referenced address is that of a symbol. Or it will return a pointer to 551 /// a literal 'C' string if the referenced address of the literal pool's entry 552 /// is an address into a section with 'C' string literals. 553 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 554 const void *Decoder) { 555 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 556 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 557 if (SymbolLookUp) { 558 void *DisInfo = Dis->getDisInfoBlock(); 559 uint64_t ReferenceType; 560 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load; 561 const char *ReferenceName; 562 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName); 563 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr || 564 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr) 565 (*Dis->CommentStream) << "literal pool for: " << ReferenceName; 566 } 567 } 568 569 // Thumb1 instructions don't have explicit S bits. Rather, they 570 // implicitly set CPSR. Since it's not represented in the encoding, the 571 // auto-generated decoder won't inject the CPSR operand. We need to fix 572 // that as a post-pass. 573 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 574 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 575 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 576 MCInst::iterator I = MI.begin(); 577 for (unsigned i = 0; i < NumOps; ++i, ++I) { 578 if (I == MI.end()) break; 579 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 580 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 581 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 582 return; 583 } 584 } 585 586 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 587 } 588 589 // Most Thumb instructions don't have explicit predicates in the 590 // encoding, but rather get their predicates from IT context. We need 591 // to fix up the predicate operands using this context information as a 592 // post-pass. 593 MCDisassembler::DecodeStatus 594 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 595 MCDisassembler::DecodeStatus S = Success; 596 597 // A few instructions actually have predicates encoded in them. Don't 598 // try to overwrite it if we're seeing one of those. 599 switch (MI.getOpcode()) { 600 case ARM::tBcc: 601 case ARM::t2Bcc: 602 case ARM::tCBZ: 603 case ARM::tCBNZ: 604 case ARM::tCPS: 605 case ARM::t2CPS3p: 606 case ARM::t2CPS2p: 607 case ARM::t2CPS1p: 608 case ARM::tMOVSr: 609 case ARM::tSETEND: 610 // Some instructions (mostly conditional branches) are not 611 // allowed in IT blocks. 612 if (!ITBlock.empty()) 613 S = SoftFail; 614 else 615 return Success; 616 break; 617 case ARM::tB: 618 case ARM::t2B: 619 case ARM::t2TBB: 620 case ARM::t2TBH: 621 // Some instructions (mostly unconditional branches) can 622 // only appears at the end of, or outside of, an IT. 623 if (ITBlock.size() > 1) 624 S = SoftFail; 625 break; 626 default: 627 break; 628 } 629 630 // If we're in an IT block, base the predicate on that. Otherwise, 631 // assume a predicate of AL. 632 unsigned CC; 633 if (!ITBlock.empty()) { 634 CC = ITBlock.back(); 635 if (CC == 0xF) 636 CC = ARMCC::AL; 637 ITBlock.pop_back(); 638 } else 639 CC = ARMCC::AL; 640 641 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 642 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 643 MCInst::iterator I = MI.begin(); 644 for (unsigned i = 0; i < NumOps; ++i, ++I) { 645 if (I == MI.end()) break; 646 if (OpInfo[i].isPredicate()) { 647 I = MI.insert(I, MCOperand::CreateImm(CC)); 648 ++I; 649 if (CC == ARMCC::AL) 650 MI.insert(I, MCOperand::CreateReg(0)); 651 else 652 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 653 return S; 654 } 655 } 656 657 I = MI.insert(I, MCOperand::CreateImm(CC)); 658 ++I; 659 if (CC == ARMCC::AL) 660 MI.insert(I, MCOperand::CreateReg(0)); 661 else 662 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 663 664 return S; 665 } 666 667 // Thumb VFP instructions are a special case. Because we share their 668 // encodings between ARM and Thumb modes, and they are predicable in ARM 669 // mode, the auto-generated decoder will give them an (incorrect) 670 // predicate operand. We need to rewrite these operands based on the IT 671 // context as a post-pass. 672 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 673 unsigned CC; 674 if (!ITBlock.empty()) { 675 CC = ITBlock.back(); 676 ITBlock.pop_back(); 677 } else 678 CC = ARMCC::AL; 679 680 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 681 MCInst::iterator I = MI.begin(); 682 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 683 for (unsigned i = 0; i < NumOps; ++i, ++I) { 684 if (OpInfo[i].isPredicate() ) { 685 I->setImm(CC); 686 ++I; 687 if (CC == ARMCC::AL) 688 I->setReg(0); 689 else 690 I->setReg(ARM::CPSR); 691 return; 692 } 693 } 694 } 695 696 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 697 const MemoryObject &Region, 698 uint64_t Address, 699 raw_ostream &os, 700 raw_ostream &cs) const { 701 CommentStream = &cs; 702 703 uint8_t bytes[4]; 704 705 assert((STI.getFeatureBits() & ARM::ModeThumb) && 706 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 707 708 // We want to read exactly 2 bytes of data. 709 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) { 710 Size = 0; 711 return MCDisassembler::Fail; 712 } 713 714 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 715 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI); 716 if (result != MCDisassembler::Fail) { 717 Size = 2; 718 Check(result, AddThumbPredicate(MI)); 719 return result; 720 } 721 722 MI.clear(); 723 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI); 724 if (result) { 725 Size = 2; 726 bool InITBlock = !ITBlock.empty(); 727 Check(result, AddThumbPredicate(MI)); 728 AddThumb1SBit(MI, InITBlock); 729 return result; 730 } 731 732 MI.clear(); 733 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI); 734 if (result != MCDisassembler::Fail) { 735 Size = 2; 736 737 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 738 // the Thumb predicate. 739 if (MI.getOpcode() == ARM::t2IT && !ITBlock.empty()) 740 result = MCDisassembler::SoftFail; 741 742 Check(result, AddThumbPredicate(MI)); 743 744 // If we find an IT instruction, we need to parse its condition 745 // code and mask operands so that we can apply them correctly 746 // to the subsequent instructions. 747 if (MI.getOpcode() == ARM::t2IT) { 748 749 // (3 - the number of trailing zeros) is the number of then / else. 750 unsigned firstcond = MI.getOperand(0).getImm(); 751 unsigned Mask = MI.getOperand(1).getImm(); 752 unsigned CondBit0 = Mask >> 4 & 1; 753 unsigned NumTZ = CountTrailingZeros_32(Mask); 754 assert(NumTZ <= 3 && "Invalid IT mask!"); 755 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) { 756 bool T = ((Mask >> Pos) & 1) == CondBit0; 757 if (T) 758 ITBlock.insert(ITBlock.begin(), firstcond); 759 else 760 ITBlock.insert(ITBlock.begin(), firstcond ^ 1); 761 } 762 763 ITBlock.push_back(firstcond); 764 } 765 766 return result; 767 } 768 769 // We want to read exactly 4 bytes of data. 770 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 771 Size = 0; 772 return MCDisassembler::Fail; 773 } 774 775 uint32_t insn32 = (bytes[3] << 8) | 776 (bytes[2] << 0) | 777 (bytes[1] << 24) | 778 (bytes[0] << 16); 779 MI.clear(); 780 result = decodeThumbInstruction32(MI, insn32, Address, this, STI); 781 if (result != MCDisassembler::Fail) { 782 Size = 4; 783 bool InITBlock = ITBlock.size(); 784 Check(result, AddThumbPredicate(MI)); 785 AddThumb1SBit(MI, InITBlock); 786 return result; 787 } 788 789 MI.clear(); 790 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI); 791 if (result != MCDisassembler::Fail) { 792 Size = 4; 793 Check(result, AddThumbPredicate(MI)); 794 return result; 795 } 796 797 MI.clear(); 798 result = decodeVFPInstruction32(MI, insn32, Address, this, STI); 799 if (result != MCDisassembler::Fail) { 800 Size = 4; 801 UpdateThumbVFPPredicate(MI); 802 return result; 803 } 804 805 MI.clear(); 806 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI); 807 if (result != MCDisassembler::Fail) { 808 Size = 4; 809 Check(result, AddThumbPredicate(MI)); 810 return result; 811 } 812 813 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { 814 MI.clear(); 815 uint32_t NEONLdStInsn = insn32; 816 NEONLdStInsn &= 0xF0FFFFFF; 817 NEONLdStInsn |= 0x04000000; 818 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI); 819 if (result != MCDisassembler::Fail) { 820 Size = 4; 821 Check(result, AddThumbPredicate(MI)); 822 return result; 823 } 824 } 825 826 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 827 MI.clear(); 828 uint32_t NEONDataInsn = insn32; 829 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 830 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 831 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 832 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI); 833 if (result != MCDisassembler::Fail) { 834 Size = 4; 835 Check(result, AddThumbPredicate(MI)); 836 return result; 837 } 838 } 839 840 Size = 0; 841 return MCDisassembler::Fail; 842 } 843 844 845 extern "C" void LLVMInitializeARMDisassembler() { 846 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 847 createARMDisassembler); 848 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 849 createThumbDisassembler); 850 } 851 852 static const unsigned GPRDecoderTable[] = { 853 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 854 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 855 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 856 ARM::R12, ARM::SP, ARM::LR, ARM::PC 857 }; 858 859 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 860 uint64_t Address, const void *Decoder) { 861 if (RegNo > 15) 862 return MCDisassembler::Fail; 863 864 unsigned Register = GPRDecoderTable[RegNo]; 865 Inst.addOperand(MCOperand::CreateReg(Register)); 866 return MCDisassembler::Success; 867 } 868 869 static DecodeStatus 870 DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 871 uint64_t Address, const void *Decoder) { 872 if (RegNo == 15) return MCDisassembler::Fail; 873 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 874 } 875 876 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 877 uint64_t Address, const void *Decoder) { 878 if (RegNo > 7) 879 return MCDisassembler::Fail; 880 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 881 } 882 883 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 884 uint64_t Address, const void *Decoder) { 885 unsigned Register = 0; 886 switch (RegNo) { 887 case 0: 888 Register = ARM::R0; 889 break; 890 case 1: 891 Register = ARM::R1; 892 break; 893 case 2: 894 Register = ARM::R2; 895 break; 896 case 3: 897 Register = ARM::R3; 898 break; 899 case 9: 900 Register = ARM::R9; 901 break; 902 case 12: 903 Register = ARM::R12; 904 break; 905 default: 906 return MCDisassembler::Fail; 907 } 908 909 Inst.addOperand(MCOperand::CreateReg(Register)); 910 return MCDisassembler::Success; 911 } 912 913 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 914 uint64_t Address, const void *Decoder) { 915 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 916 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 917 } 918 919 static const unsigned SPRDecoderTable[] = { 920 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 921 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 922 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 923 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 924 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 925 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 926 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 927 ARM::S28, ARM::S29, ARM::S30, ARM::S31 928 }; 929 930 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 931 uint64_t Address, const void *Decoder) { 932 if (RegNo > 31) 933 return MCDisassembler::Fail; 934 935 unsigned Register = SPRDecoderTable[RegNo]; 936 Inst.addOperand(MCOperand::CreateReg(Register)); 937 return MCDisassembler::Success; 938 } 939 940 static const unsigned DPRDecoderTable[] = { 941 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 942 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 943 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 944 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 945 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 946 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 947 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 948 ARM::D28, ARM::D29, ARM::D30, ARM::D31 949 }; 950 951 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 952 uint64_t Address, const void *Decoder) { 953 if (RegNo > 31) 954 return MCDisassembler::Fail; 955 956 unsigned Register = DPRDecoderTable[RegNo]; 957 Inst.addOperand(MCOperand::CreateReg(Register)); 958 return MCDisassembler::Success; 959 } 960 961 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 962 uint64_t Address, const void *Decoder) { 963 if (RegNo > 7) 964 return MCDisassembler::Fail; 965 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 966 } 967 968 static DecodeStatus 969 DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 970 uint64_t Address, const void *Decoder) { 971 if (RegNo > 15) 972 return MCDisassembler::Fail; 973 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 974 } 975 976 static const unsigned QPRDecoderTable[] = { 977 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 978 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 979 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 980 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 981 }; 982 983 984 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 985 uint64_t Address, const void *Decoder) { 986 if (RegNo > 31) 987 return MCDisassembler::Fail; 988 RegNo >>= 1; 989 990 unsigned Register = QPRDecoderTable[RegNo]; 991 Inst.addOperand(MCOperand::CreateReg(Register)); 992 return MCDisassembler::Success; 993 } 994 995 static const unsigned DPairDecoderTable[] = { 996 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 997 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 998 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 999 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1000 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1001 ARM::Q15 1002 }; 1003 1004 static DecodeStatus DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 1005 uint64_t Address, const void *Decoder) { 1006 if (RegNo > 30) 1007 return MCDisassembler::Fail; 1008 1009 unsigned Register = DPairDecoderTable[RegNo]; 1010 Inst.addOperand(MCOperand::CreateReg(Register)); 1011 return MCDisassembler::Success; 1012 } 1013 1014 static const unsigned DPairSpacedDecoderTable[] = { 1015 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1016 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1017 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1018 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1019 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1020 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1021 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1022 ARM::D28_D30, ARM::D29_D31 1023 }; 1024 1025 static DecodeStatus DecodeDPairSpacedRegisterClass(llvm::MCInst &Inst, 1026 unsigned RegNo, 1027 uint64_t Address, 1028 const void *Decoder) { 1029 if (RegNo > 29) 1030 return MCDisassembler::Fail; 1031 1032 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1033 Inst.addOperand(MCOperand::CreateReg(Register)); 1034 return MCDisassembler::Success; 1035 } 1036 1037 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 1038 uint64_t Address, const void *Decoder) { 1039 if (Val == 0xF) return MCDisassembler::Fail; 1040 // AL predicate is not allowed on Thumb1 branches. 1041 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1042 return MCDisassembler::Fail; 1043 Inst.addOperand(MCOperand::CreateImm(Val)); 1044 if (Val == ARMCC::AL) { 1045 Inst.addOperand(MCOperand::CreateReg(0)); 1046 } else 1047 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1048 return MCDisassembler::Success; 1049 } 1050 1051 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 1052 uint64_t Address, const void *Decoder) { 1053 if (Val) 1054 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1055 else 1056 Inst.addOperand(MCOperand::CreateReg(0)); 1057 return MCDisassembler::Success; 1058 } 1059 1060 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 1061 uint64_t Address, const void *Decoder) { 1062 uint32_t imm = Val & 0xFF; 1063 uint32_t rot = (Val & 0xF00) >> 7; 1064 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 1065 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 1066 return MCDisassembler::Success; 1067 } 1068 1069 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 1070 uint64_t Address, const void *Decoder) { 1071 DecodeStatus S = MCDisassembler::Success; 1072 1073 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1074 unsigned type = fieldFromInstruction32(Val, 5, 2); 1075 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1076 1077 // Register-immediate 1078 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1079 return MCDisassembler::Fail; 1080 1081 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1082 switch (type) { 1083 case 0: 1084 Shift = ARM_AM::lsl; 1085 break; 1086 case 1: 1087 Shift = ARM_AM::lsr; 1088 break; 1089 case 2: 1090 Shift = ARM_AM::asr; 1091 break; 1092 case 3: 1093 Shift = ARM_AM::ror; 1094 break; 1095 } 1096 1097 if (Shift == ARM_AM::ror && imm == 0) 1098 Shift = ARM_AM::rrx; 1099 1100 unsigned Op = Shift | (imm << 3); 1101 Inst.addOperand(MCOperand::CreateImm(Op)); 1102 1103 return S; 1104 } 1105 1106 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 1107 uint64_t Address, const void *Decoder) { 1108 DecodeStatus S = MCDisassembler::Success; 1109 1110 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1111 unsigned type = fieldFromInstruction32(Val, 5, 2); 1112 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 1113 1114 // Register-register 1115 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1116 return MCDisassembler::Fail; 1117 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1118 return MCDisassembler::Fail; 1119 1120 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1121 switch (type) { 1122 case 0: 1123 Shift = ARM_AM::lsl; 1124 break; 1125 case 1: 1126 Shift = ARM_AM::lsr; 1127 break; 1128 case 2: 1129 Shift = ARM_AM::asr; 1130 break; 1131 case 3: 1132 Shift = ARM_AM::ror; 1133 break; 1134 } 1135 1136 Inst.addOperand(MCOperand::CreateImm(Shift)); 1137 1138 return S; 1139 } 1140 1141 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 1142 uint64_t Address, const void *Decoder) { 1143 DecodeStatus S = MCDisassembler::Success; 1144 1145 bool writebackLoad = false; 1146 unsigned writebackReg = 0; 1147 switch (Inst.getOpcode()) { 1148 default: 1149 break; 1150 case ARM::LDMIA_UPD: 1151 case ARM::LDMDB_UPD: 1152 case ARM::LDMIB_UPD: 1153 case ARM::LDMDA_UPD: 1154 case ARM::t2LDMIA_UPD: 1155 case ARM::t2LDMDB_UPD: 1156 writebackLoad = true; 1157 writebackReg = Inst.getOperand(0).getReg(); 1158 break; 1159 } 1160 1161 // Empty register lists are not allowed. 1162 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail; 1163 for (unsigned i = 0; i < 16; ++i) { 1164 if (Val & (1 << i)) { 1165 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1166 return MCDisassembler::Fail; 1167 // Writeback not allowed if Rn is in the target list. 1168 if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) 1169 Check(S, MCDisassembler::SoftFail); 1170 } 1171 } 1172 1173 return S; 1174 } 1175 1176 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 1177 uint64_t Address, const void *Decoder) { 1178 DecodeStatus S = MCDisassembler::Success; 1179 1180 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 1181 unsigned regs = Val & 0xFF; 1182 1183 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1184 return MCDisassembler::Fail; 1185 for (unsigned i = 0; i < (regs - 1); ++i) { 1186 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1187 return MCDisassembler::Fail; 1188 } 1189 1190 return S; 1191 } 1192 1193 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 1194 uint64_t Address, const void *Decoder) { 1195 DecodeStatus S = MCDisassembler::Success; 1196 1197 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 1198 unsigned regs = (Val & 0xFF) / 2; 1199 1200 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1201 return MCDisassembler::Fail; 1202 for (unsigned i = 0; i < (regs - 1); ++i) { 1203 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1204 return MCDisassembler::Fail; 1205 } 1206 1207 return S; 1208 } 1209 1210 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 1211 uint64_t Address, const void *Decoder) { 1212 // This operand encodes a mask of contiguous zeros between a specified MSB 1213 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1214 // the mask of all bits LSB-and-lower, and then xor them to create 1215 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1216 // create the final mask. 1217 unsigned msb = fieldFromInstruction32(Val, 5, 5); 1218 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 1219 1220 DecodeStatus S = MCDisassembler::Success; 1221 if (lsb > msb) Check(S, MCDisassembler::SoftFail); 1222 1223 uint32_t msb_mask = 0xFFFFFFFF; 1224 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1225 uint32_t lsb_mask = (1U << lsb) - 1; 1226 1227 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1228 return S; 1229 } 1230 1231 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 1232 uint64_t Address, const void *Decoder) { 1233 DecodeStatus S = MCDisassembler::Success; 1234 1235 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1236 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 1237 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 1238 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 1239 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1240 unsigned U = fieldFromInstruction32(Insn, 23, 1); 1241 1242 switch (Inst.getOpcode()) { 1243 case ARM::LDC_OFFSET: 1244 case ARM::LDC_PRE: 1245 case ARM::LDC_POST: 1246 case ARM::LDC_OPTION: 1247 case ARM::LDCL_OFFSET: 1248 case ARM::LDCL_PRE: 1249 case ARM::LDCL_POST: 1250 case ARM::LDCL_OPTION: 1251 case ARM::STC_OFFSET: 1252 case ARM::STC_PRE: 1253 case ARM::STC_POST: 1254 case ARM::STC_OPTION: 1255 case ARM::STCL_OFFSET: 1256 case ARM::STCL_PRE: 1257 case ARM::STCL_POST: 1258 case ARM::STCL_OPTION: 1259 case ARM::t2LDC_OFFSET: 1260 case ARM::t2LDC_PRE: 1261 case ARM::t2LDC_POST: 1262 case ARM::t2LDC_OPTION: 1263 case ARM::t2LDCL_OFFSET: 1264 case ARM::t2LDCL_PRE: 1265 case ARM::t2LDCL_POST: 1266 case ARM::t2LDCL_OPTION: 1267 case ARM::t2STC_OFFSET: 1268 case ARM::t2STC_PRE: 1269 case ARM::t2STC_POST: 1270 case ARM::t2STC_OPTION: 1271 case ARM::t2STCL_OFFSET: 1272 case ARM::t2STCL_PRE: 1273 case ARM::t2STCL_POST: 1274 case ARM::t2STCL_OPTION: 1275 if (coproc == 0xA || coproc == 0xB) 1276 return MCDisassembler::Fail; 1277 break; 1278 default: 1279 break; 1280 } 1281 1282 Inst.addOperand(MCOperand::CreateImm(coproc)); 1283 Inst.addOperand(MCOperand::CreateImm(CRd)); 1284 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1285 return MCDisassembler::Fail; 1286 1287 switch (Inst.getOpcode()) { 1288 case ARM::t2LDC2_OFFSET: 1289 case ARM::t2LDC2L_OFFSET: 1290 case ARM::t2LDC2_PRE: 1291 case ARM::t2LDC2L_PRE: 1292 case ARM::t2STC2_OFFSET: 1293 case ARM::t2STC2L_OFFSET: 1294 case ARM::t2STC2_PRE: 1295 case ARM::t2STC2L_PRE: 1296 case ARM::LDC2_OFFSET: 1297 case ARM::LDC2L_OFFSET: 1298 case ARM::LDC2_PRE: 1299 case ARM::LDC2L_PRE: 1300 case ARM::STC2_OFFSET: 1301 case ARM::STC2L_OFFSET: 1302 case ARM::STC2_PRE: 1303 case ARM::STC2L_PRE: 1304 case ARM::t2LDC_OFFSET: 1305 case ARM::t2LDCL_OFFSET: 1306 case ARM::t2LDC_PRE: 1307 case ARM::t2LDCL_PRE: 1308 case ARM::t2STC_OFFSET: 1309 case ARM::t2STCL_OFFSET: 1310 case ARM::t2STC_PRE: 1311 case ARM::t2STCL_PRE: 1312 case ARM::LDC_OFFSET: 1313 case ARM::LDCL_OFFSET: 1314 case ARM::LDC_PRE: 1315 case ARM::LDCL_PRE: 1316 case ARM::STC_OFFSET: 1317 case ARM::STCL_OFFSET: 1318 case ARM::STC_PRE: 1319 case ARM::STCL_PRE: 1320 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1321 Inst.addOperand(MCOperand::CreateImm(imm)); 1322 break; 1323 case ARM::t2LDC2_POST: 1324 case ARM::t2LDC2L_POST: 1325 case ARM::t2STC2_POST: 1326 case ARM::t2STC2L_POST: 1327 case ARM::LDC2_POST: 1328 case ARM::LDC2L_POST: 1329 case ARM::STC2_POST: 1330 case ARM::STC2L_POST: 1331 case ARM::t2LDC_POST: 1332 case ARM::t2LDCL_POST: 1333 case ARM::t2STC_POST: 1334 case ARM::t2STCL_POST: 1335 case ARM::LDC_POST: 1336 case ARM::LDCL_POST: 1337 case ARM::STC_POST: 1338 case ARM::STCL_POST: 1339 imm |= U << 8; 1340 // fall through. 1341 default: 1342 // The 'option' variant doesn't encode 'U' in the immediate since 1343 // the immediate is unsigned [0,255]. 1344 Inst.addOperand(MCOperand::CreateImm(imm)); 1345 break; 1346 } 1347 1348 switch (Inst.getOpcode()) { 1349 case ARM::LDC_OFFSET: 1350 case ARM::LDC_PRE: 1351 case ARM::LDC_POST: 1352 case ARM::LDC_OPTION: 1353 case ARM::LDCL_OFFSET: 1354 case ARM::LDCL_PRE: 1355 case ARM::LDCL_POST: 1356 case ARM::LDCL_OPTION: 1357 case ARM::STC_OFFSET: 1358 case ARM::STC_PRE: 1359 case ARM::STC_POST: 1360 case ARM::STC_OPTION: 1361 case ARM::STCL_OFFSET: 1362 case ARM::STCL_PRE: 1363 case ARM::STCL_POST: 1364 case ARM::STCL_OPTION: 1365 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1366 return MCDisassembler::Fail; 1367 break; 1368 default: 1369 break; 1370 } 1371 1372 return S; 1373 } 1374 1375 static DecodeStatus 1376 DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 1377 uint64_t Address, const void *Decoder) { 1378 DecodeStatus S = MCDisassembler::Success; 1379 1380 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1381 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1382 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1383 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 1384 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1385 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 1386 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1387 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1388 1389 // On stores, the writeback operand precedes Rt. 1390 switch (Inst.getOpcode()) { 1391 case ARM::STR_POST_IMM: 1392 case ARM::STR_POST_REG: 1393 case ARM::STRB_POST_IMM: 1394 case ARM::STRB_POST_REG: 1395 case ARM::STRT_POST_REG: 1396 case ARM::STRT_POST_IMM: 1397 case ARM::STRBT_POST_REG: 1398 case ARM::STRBT_POST_IMM: 1399 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1400 return MCDisassembler::Fail; 1401 break; 1402 default: 1403 break; 1404 } 1405 1406 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1407 return MCDisassembler::Fail; 1408 1409 // On loads, the writeback operand comes after Rt. 1410 switch (Inst.getOpcode()) { 1411 case ARM::LDR_POST_IMM: 1412 case ARM::LDR_POST_REG: 1413 case ARM::LDRB_POST_IMM: 1414 case ARM::LDRB_POST_REG: 1415 case ARM::LDRBT_POST_REG: 1416 case ARM::LDRBT_POST_IMM: 1417 case ARM::LDRT_POST_REG: 1418 case ARM::LDRT_POST_IMM: 1419 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1420 return MCDisassembler::Fail; 1421 break; 1422 default: 1423 break; 1424 } 1425 1426 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1427 return MCDisassembler::Fail; 1428 1429 ARM_AM::AddrOpc Op = ARM_AM::add; 1430 if (!fieldFromInstruction32(Insn, 23, 1)) 1431 Op = ARM_AM::sub; 1432 1433 bool writeback = (P == 0) || (W == 1); 1434 unsigned idx_mode = 0; 1435 if (P && writeback) 1436 idx_mode = ARMII::IndexModePre; 1437 else if (!P && writeback) 1438 idx_mode = ARMII::IndexModePost; 1439 1440 if (writeback && (Rn == 15 || Rn == Rt)) 1441 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1442 1443 if (reg) { 1444 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1445 return MCDisassembler::Fail; 1446 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1447 switch( fieldFromInstruction32(Insn, 5, 2)) { 1448 case 0: 1449 Opc = ARM_AM::lsl; 1450 break; 1451 case 1: 1452 Opc = ARM_AM::lsr; 1453 break; 1454 case 2: 1455 Opc = ARM_AM::asr; 1456 break; 1457 case 3: 1458 Opc = ARM_AM::ror; 1459 break; 1460 default: 1461 return MCDisassembler::Fail; 1462 } 1463 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1464 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1465 1466 Inst.addOperand(MCOperand::CreateImm(imm)); 1467 } else { 1468 Inst.addOperand(MCOperand::CreateReg(0)); 1469 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1470 Inst.addOperand(MCOperand::CreateImm(tmp)); 1471 } 1472 1473 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1474 return MCDisassembler::Fail; 1475 1476 return S; 1477 } 1478 1479 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1480 uint64_t Address, const void *Decoder) { 1481 DecodeStatus S = MCDisassembler::Success; 1482 1483 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1484 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1485 unsigned type = fieldFromInstruction32(Val, 5, 2); 1486 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1487 unsigned U = fieldFromInstruction32(Val, 12, 1); 1488 1489 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1490 switch (type) { 1491 case 0: 1492 ShOp = ARM_AM::lsl; 1493 break; 1494 case 1: 1495 ShOp = ARM_AM::lsr; 1496 break; 1497 case 2: 1498 ShOp = ARM_AM::asr; 1499 break; 1500 case 3: 1501 ShOp = ARM_AM::ror; 1502 break; 1503 } 1504 1505 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1506 return MCDisassembler::Fail; 1507 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1508 return MCDisassembler::Fail; 1509 unsigned shift; 1510 if (U) 1511 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1512 else 1513 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1514 Inst.addOperand(MCOperand::CreateImm(shift)); 1515 1516 return S; 1517 } 1518 1519 static DecodeStatus 1520 DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1521 uint64_t Address, const void *Decoder) { 1522 DecodeStatus S = MCDisassembler::Success; 1523 1524 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1525 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1526 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1527 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1528 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1529 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1530 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1531 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1532 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1533 1534 bool writeback = (W == 1) | (P == 0); 1535 1536 // For {LD,ST}RD, Rt must be even, else undefined. 1537 switch (Inst.getOpcode()) { 1538 case ARM::STRD: 1539 case ARM::STRD_PRE: 1540 case ARM::STRD_POST: 1541 case ARM::LDRD: 1542 case ARM::LDRD_PRE: 1543 case ARM::LDRD_POST: 1544 if (Rt & 0x1) return MCDisassembler::Fail; 1545 break; 1546 default: 1547 break; 1548 } 1549 1550 if (writeback) { // Writeback 1551 if (P) 1552 U |= ARMII::IndexModePre << 9; 1553 else 1554 U |= ARMII::IndexModePost << 9; 1555 1556 // On stores, the writeback operand precedes Rt. 1557 switch (Inst.getOpcode()) { 1558 case ARM::STRD: 1559 case ARM::STRD_PRE: 1560 case ARM::STRD_POST: 1561 case ARM::STRH: 1562 case ARM::STRH_PRE: 1563 case ARM::STRH_POST: 1564 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1565 return MCDisassembler::Fail; 1566 break; 1567 default: 1568 break; 1569 } 1570 } 1571 1572 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1573 return MCDisassembler::Fail; 1574 switch (Inst.getOpcode()) { 1575 case ARM::STRD: 1576 case ARM::STRD_PRE: 1577 case ARM::STRD_POST: 1578 case ARM::LDRD: 1579 case ARM::LDRD_PRE: 1580 case ARM::LDRD_POST: 1581 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1582 return MCDisassembler::Fail; 1583 break; 1584 default: 1585 break; 1586 } 1587 1588 if (writeback) { 1589 // On loads, the writeback operand comes after Rt. 1590 switch (Inst.getOpcode()) { 1591 case ARM::LDRD: 1592 case ARM::LDRD_PRE: 1593 case ARM::LDRD_POST: 1594 case ARM::LDRH: 1595 case ARM::LDRH_PRE: 1596 case ARM::LDRH_POST: 1597 case ARM::LDRSH: 1598 case ARM::LDRSH_PRE: 1599 case ARM::LDRSH_POST: 1600 case ARM::LDRSB: 1601 case ARM::LDRSB_PRE: 1602 case ARM::LDRSB_POST: 1603 case ARM::LDRHTr: 1604 case ARM::LDRSBTr: 1605 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1606 return MCDisassembler::Fail; 1607 break; 1608 default: 1609 break; 1610 } 1611 } 1612 1613 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1614 return MCDisassembler::Fail; 1615 1616 if (type) { 1617 Inst.addOperand(MCOperand::CreateReg(0)); 1618 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1619 } else { 1620 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1621 return MCDisassembler::Fail; 1622 Inst.addOperand(MCOperand::CreateImm(U)); 1623 } 1624 1625 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1626 return MCDisassembler::Fail; 1627 1628 return S; 1629 } 1630 1631 static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1632 uint64_t Address, const void *Decoder) { 1633 DecodeStatus S = MCDisassembler::Success; 1634 1635 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1636 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1637 1638 switch (mode) { 1639 case 0: 1640 mode = ARM_AM::da; 1641 break; 1642 case 1: 1643 mode = ARM_AM::ia; 1644 break; 1645 case 2: 1646 mode = ARM_AM::db; 1647 break; 1648 case 3: 1649 mode = ARM_AM::ib; 1650 break; 1651 } 1652 1653 Inst.addOperand(MCOperand::CreateImm(mode)); 1654 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1655 return MCDisassembler::Fail; 1656 1657 return S; 1658 } 1659 1660 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1661 unsigned Insn, 1662 uint64_t Address, const void *Decoder) { 1663 DecodeStatus S = MCDisassembler::Success; 1664 1665 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1666 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1667 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1668 1669 if (pred == 0xF) { 1670 switch (Inst.getOpcode()) { 1671 case ARM::LDMDA: 1672 Inst.setOpcode(ARM::RFEDA); 1673 break; 1674 case ARM::LDMDA_UPD: 1675 Inst.setOpcode(ARM::RFEDA_UPD); 1676 break; 1677 case ARM::LDMDB: 1678 Inst.setOpcode(ARM::RFEDB); 1679 break; 1680 case ARM::LDMDB_UPD: 1681 Inst.setOpcode(ARM::RFEDB_UPD); 1682 break; 1683 case ARM::LDMIA: 1684 Inst.setOpcode(ARM::RFEIA); 1685 break; 1686 case ARM::LDMIA_UPD: 1687 Inst.setOpcode(ARM::RFEIA_UPD); 1688 break; 1689 case ARM::LDMIB: 1690 Inst.setOpcode(ARM::RFEIB); 1691 break; 1692 case ARM::LDMIB_UPD: 1693 Inst.setOpcode(ARM::RFEIB_UPD); 1694 break; 1695 case ARM::STMDA: 1696 Inst.setOpcode(ARM::SRSDA); 1697 break; 1698 case ARM::STMDA_UPD: 1699 Inst.setOpcode(ARM::SRSDA_UPD); 1700 break; 1701 case ARM::STMDB: 1702 Inst.setOpcode(ARM::SRSDB); 1703 break; 1704 case ARM::STMDB_UPD: 1705 Inst.setOpcode(ARM::SRSDB_UPD); 1706 break; 1707 case ARM::STMIA: 1708 Inst.setOpcode(ARM::SRSIA); 1709 break; 1710 case ARM::STMIA_UPD: 1711 Inst.setOpcode(ARM::SRSIA_UPD); 1712 break; 1713 case ARM::STMIB: 1714 Inst.setOpcode(ARM::SRSIB); 1715 break; 1716 case ARM::STMIB_UPD: 1717 Inst.setOpcode(ARM::SRSIB_UPD); 1718 break; 1719 default: 1720 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail; 1721 } 1722 1723 // For stores (which become SRS's, the only operand is the mode. 1724 if (fieldFromInstruction32(Insn, 20, 1) == 0) { 1725 Inst.addOperand( 1726 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4))); 1727 return S; 1728 } 1729 1730 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1731 } 1732 1733 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1734 return MCDisassembler::Fail; 1735 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1736 return MCDisassembler::Fail; // Tied 1737 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1738 return MCDisassembler::Fail; 1739 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1740 return MCDisassembler::Fail; 1741 1742 return S; 1743 } 1744 1745 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1746 uint64_t Address, const void *Decoder) { 1747 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1748 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1749 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1750 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1751 1752 DecodeStatus S = MCDisassembler::Success; 1753 1754 // imod == '01' --> UNPREDICTABLE 1755 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1756 // return failure here. The '01' imod value is unprintable, so there's 1757 // nothing useful we could do even if we returned UNPREDICTABLE. 1758 1759 if (imod == 1) return MCDisassembler::Fail; 1760 1761 if (imod && M) { 1762 Inst.setOpcode(ARM::CPS3p); 1763 Inst.addOperand(MCOperand::CreateImm(imod)); 1764 Inst.addOperand(MCOperand::CreateImm(iflags)); 1765 Inst.addOperand(MCOperand::CreateImm(mode)); 1766 } else if (imod && !M) { 1767 Inst.setOpcode(ARM::CPS2p); 1768 Inst.addOperand(MCOperand::CreateImm(imod)); 1769 Inst.addOperand(MCOperand::CreateImm(iflags)); 1770 if (mode) S = MCDisassembler::SoftFail; 1771 } else if (!imod && M) { 1772 Inst.setOpcode(ARM::CPS1p); 1773 Inst.addOperand(MCOperand::CreateImm(mode)); 1774 if (iflags) S = MCDisassembler::SoftFail; 1775 } else { 1776 // imod == '00' && M == '0' --> UNPREDICTABLE 1777 Inst.setOpcode(ARM::CPS1p); 1778 Inst.addOperand(MCOperand::CreateImm(mode)); 1779 S = MCDisassembler::SoftFail; 1780 } 1781 1782 return S; 1783 } 1784 1785 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1786 uint64_t Address, const void *Decoder) { 1787 unsigned imod = fieldFromInstruction32(Insn, 9, 2); 1788 unsigned M = fieldFromInstruction32(Insn, 8, 1); 1789 unsigned iflags = fieldFromInstruction32(Insn, 5, 3); 1790 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1791 1792 DecodeStatus S = MCDisassembler::Success; 1793 1794 // imod == '01' --> UNPREDICTABLE 1795 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1796 // return failure here. The '01' imod value is unprintable, so there's 1797 // nothing useful we could do even if we returned UNPREDICTABLE. 1798 1799 if (imod == 1) return MCDisassembler::Fail; 1800 1801 if (imod && M) { 1802 Inst.setOpcode(ARM::t2CPS3p); 1803 Inst.addOperand(MCOperand::CreateImm(imod)); 1804 Inst.addOperand(MCOperand::CreateImm(iflags)); 1805 Inst.addOperand(MCOperand::CreateImm(mode)); 1806 } else if (imod && !M) { 1807 Inst.setOpcode(ARM::t2CPS2p); 1808 Inst.addOperand(MCOperand::CreateImm(imod)); 1809 Inst.addOperand(MCOperand::CreateImm(iflags)); 1810 if (mode) S = MCDisassembler::SoftFail; 1811 } else if (!imod && M) { 1812 Inst.setOpcode(ARM::t2CPS1p); 1813 Inst.addOperand(MCOperand::CreateImm(mode)); 1814 if (iflags) S = MCDisassembler::SoftFail; 1815 } else { 1816 // imod == '00' && M == '0' --> UNPREDICTABLE 1817 Inst.setOpcode(ARM::t2CPS1p); 1818 Inst.addOperand(MCOperand::CreateImm(mode)); 1819 S = MCDisassembler::SoftFail; 1820 } 1821 1822 return S; 1823 } 1824 1825 static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 1826 uint64_t Address, const void *Decoder) { 1827 DecodeStatus S = MCDisassembler::Success; 1828 1829 unsigned Rd = fieldFromInstruction32(Insn, 8, 4); 1830 unsigned imm = 0; 1831 1832 imm |= (fieldFromInstruction32(Insn, 0, 8) << 0); 1833 imm |= (fieldFromInstruction32(Insn, 12, 3) << 8); 1834 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12); 1835 imm |= (fieldFromInstruction32(Insn, 26, 1) << 11); 1836 1837 if (Inst.getOpcode() == ARM::t2MOVTi16) 1838 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1839 return MCDisassembler::Fail; 1840 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1841 return MCDisassembler::Fail; 1842 1843 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1844 Inst.addOperand(MCOperand::CreateImm(imm)); 1845 1846 return S; 1847 } 1848 1849 static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 1850 uint64_t Address, const void *Decoder) { 1851 DecodeStatus S = MCDisassembler::Success; 1852 1853 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1854 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1855 unsigned imm = 0; 1856 1857 imm |= (fieldFromInstruction32(Insn, 0, 12) << 0); 1858 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12); 1859 1860 if (Inst.getOpcode() == ARM::MOVTi16) 1861 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1862 return MCDisassembler::Fail; 1863 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1864 return MCDisassembler::Fail; 1865 1866 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1867 Inst.addOperand(MCOperand::CreateImm(imm)); 1868 1869 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1870 return MCDisassembler::Fail; 1871 1872 return S; 1873 } 1874 1875 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1876 uint64_t Address, const void *Decoder) { 1877 DecodeStatus S = MCDisassembler::Success; 1878 1879 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1880 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1881 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1882 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1883 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1884 1885 if (pred == 0xF) 1886 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1887 1888 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1889 return MCDisassembler::Fail; 1890 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1891 return MCDisassembler::Fail; 1892 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1893 return MCDisassembler::Fail; 1894 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 1895 return MCDisassembler::Fail; 1896 1897 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1898 return MCDisassembler::Fail; 1899 1900 return S; 1901 } 1902 1903 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1904 uint64_t Address, const void *Decoder) { 1905 DecodeStatus S = MCDisassembler::Success; 1906 1907 unsigned add = fieldFromInstruction32(Val, 12, 1); 1908 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1909 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1910 1911 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1912 return MCDisassembler::Fail; 1913 1914 if (!add) imm *= -1; 1915 if (imm == 0 && !add) imm = INT32_MIN; 1916 Inst.addOperand(MCOperand::CreateImm(imm)); 1917 if (Rn == 15) 1918 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 1919 1920 return S; 1921 } 1922 1923 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1924 uint64_t Address, const void *Decoder) { 1925 DecodeStatus S = MCDisassembler::Success; 1926 1927 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1928 unsigned U = fieldFromInstruction32(Val, 8, 1); 1929 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1930 1931 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1932 return MCDisassembler::Fail; 1933 1934 if (U) 1935 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1936 else 1937 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1938 1939 return S; 1940 } 1941 1942 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1943 uint64_t Address, const void *Decoder) { 1944 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1945 } 1946 1947 static DecodeStatus 1948 DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1949 uint64_t Address, const void *Decoder) { 1950 DecodeStatus S = MCDisassembler::Success; 1951 1952 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1953 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1954 1955 if (pred == 0xF) { 1956 Inst.setOpcode(ARM::BLXi); 1957 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1958 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 1959 true, 4, Inst, Decoder)) 1960 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1961 return S; 1962 } 1963 1964 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 1965 true, 4, Inst, Decoder)) 1966 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1967 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1968 return MCDisassembler::Fail; 1969 1970 return S; 1971 } 1972 1973 1974 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1975 uint64_t Address, const void *Decoder) { 1976 DecodeStatus S = MCDisassembler::Success; 1977 1978 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1979 unsigned align = fieldFromInstruction32(Val, 4, 2); 1980 1981 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1982 return MCDisassembler::Fail; 1983 if (!align) 1984 Inst.addOperand(MCOperand::CreateImm(0)); 1985 else 1986 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1987 1988 return S; 1989 } 1990 1991 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1992 uint64_t Address, const void *Decoder) { 1993 DecodeStatus S = MCDisassembler::Success; 1994 1995 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1996 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1997 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1998 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1999 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 2000 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2001 2002 // First output register 2003 switch (Inst.getOpcode()) { 2004 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2005 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2006 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2007 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2008 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2009 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2010 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2011 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2012 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2013 2014 // FIXME: These go in the VLDnDup* functions, not here. 2015 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2016 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2017 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2018 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2019 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2020 return MCDisassembler::Fail; 2021 break; 2022 case ARM::VLD2b16: 2023 case ARM::VLD2b32: 2024 case ARM::VLD2b8: 2025 case ARM::VLD2b16wb_fixed: 2026 case ARM::VLD2b16wb_register: 2027 case ARM::VLD2b32wb_fixed: 2028 case ARM::VLD2b32wb_register: 2029 case ARM::VLD2b8wb_fixed: 2030 case ARM::VLD2b8wb_register: 2031 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2032 return MCDisassembler::Fail; 2033 break; 2034 default: 2035 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2036 return MCDisassembler::Fail; 2037 } 2038 2039 // Second output register 2040 switch (Inst.getOpcode()) { 2041 case ARM::VLD3d8: 2042 case ARM::VLD3d16: 2043 case ARM::VLD3d32: 2044 case ARM::VLD3d8_UPD: 2045 case ARM::VLD3d16_UPD: 2046 case ARM::VLD3d32_UPD: 2047 case ARM::VLD4d8: 2048 case ARM::VLD4d16: 2049 case ARM::VLD4d32: 2050 case ARM::VLD4d8_UPD: 2051 case ARM::VLD4d16_UPD: 2052 case ARM::VLD4d32_UPD: 2053 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2054 return MCDisassembler::Fail; 2055 break; 2056 case ARM::VLD3q8: 2057 case ARM::VLD3q16: 2058 case ARM::VLD3q32: 2059 case ARM::VLD3q8_UPD: 2060 case ARM::VLD3q16_UPD: 2061 case ARM::VLD3q32_UPD: 2062 case ARM::VLD4q8: 2063 case ARM::VLD4q16: 2064 case ARM::VLD4q32: 2065 case ARM::VLD4q8_UPD: 2066 case ARM::VLD4q16_UPD: 2067 case ARM::VLD4q32_UPD: 2068 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2069 return MCDisassembler::Fail; 2070 default: 2071 break; 2072 } 2073 2074 // Third output register 2075 switch(Inst.getOpcode()) { 2076 case ARM::VLD3d8: 2077 case ARM::VLD3d16: 2078 case ARM::VLD3d32: 2079 case ARM::VLD3d8_UPD: 2080 case ARM::VLD3d16_UPD: 2081 case ARM::VLD3d32_UPD: 2082 case ARM::VLD4d8: 2083 case ARM::VLD4d16: 2084 case ARM::VLD4d32: 2085 case ARM::VLD4d8_UPD: 2086 case ARM::VLD4d16_UPD: 2087 case ARM::VLD4d32_UPD: 2088 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2089 return MCDisassembler::Fail; 2090 break; 2091 case ARM::VLD3q8: 2092 case ARM::VLD3q16: 2093 case ARM::VLD3q32: 2094 case ARM::VLD3q8_UPD: 2095 case ARM::VLD3q16_UPD: 2096 case ARM::VLD3q32_UPD: 2097 case ARM::VLD4q8: 2098 case ARM::VLD4q16: 2099 case ARM::VLD4q32: 2100 case ARM::VLD4q8_UPD: 2101 case ARM::VLD4q16_UPD: 2102 case ARM::VLD4q32_UPD: 2103 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2104 return MCDisassembler::Fail; 2105 break; 2106 default: 2107 break; 2108 } 2109 2110 // Fourth output register 2111 switch (Inst.getOpcode()) { 2112 case ARM::VLD4d8: 2113 case ARM::VLD4d16: 2114 case ARM::VLD4d32: 2115 case ARM::VLD4d8_UPD: 2116 case ARM::VLD4d16_UPD: 2117 case ARM::VLD4d32_UPD: 2118 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2119 return MCDisassembler::Fail; 2120 break; 2121 case ARM::VLD4q8: 2122 case ARM::VLD4q16: 2123 case ARM::VLD4q32: 2124 case ARM::VLD4q8_UPD: 2125 case ARM::VLD4q16_UPD: 2126 case ARM::VLD4q32_UPD: 2127 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2128 return MCDisassembler::Fail; 2129 break; 2130 default: 2131 break; 2132 } 2133 2134 // Writeback operand 2135 switch (Inst.getOpcode()) { 2136 case ARM::VLD1d8wb_fixed: 2137 case ARM::VLD1d16wb_fixed: 2138 case ARM::VLD1d32wb_fixed: 2139 case ARM::VLD1d64wb_fixed: 2140 case ARM::VLD1d8wb_register: 2141 case ARM::VLD1d16wb_register: 2142 case ARM::VLD1d32wb_register: 2143 case ARM::VLD1d64wb_register: 2144 case ARM::VLD1q8wb_fixed: 2145 case ARM::VLD1q16wb_fixed: 2146 case ARM::VLD1q32wb_fixed: 2147 case ARM::VLD1q64wb_fixed: 2148 case ARM::VLD1q8wb_register: 2149 case ARM::VLD1q16wb_register: 2150 case ARM::VLD1q32wb_register: 2151 case ARM::VLD1q64wb_register: 2152 case ARM::VLD1d8Twb_fixed: 2153 case ARM::VLD1d8Twb_register: 2154 case ARM::VLD1d16Twb_fixed: 2155 case ARM::VLD1d16Twb_register: 2156 case ARM::VLD1d32Twb_fixed: 2157 case ARM::VLD1d32Twb_register: 2158 case ARM::VLD1d64Twb_fixed: 2159 case ARM::VLD1d64Twb_register: 2160 case ARM::VLD1d8Qwb_fixed: 2161 case ARM::VLD1d8Qwb_register: 2162 case ARM::VLD1d16Qwb_fixed: 2163 case ARM::VLD1d16Qwb_register: 2164 case ARM::VLD1d32Qwb_fixed: 2165 case ARM::VLD1d32Qwb_register: 2166 case ARM::VLD1d64Qwb_fixed: 2167 case ARM::VLD1d64Qwb_register: 2168 case ARM::VLD2d8wb_fixed: 2169 case ARM::VLD2d16wb_fixed: 2170 case ARM::VLD2d32wb_fixed: 2171 case ARM::VLD2q8wb_fixed: 2172 case ARM::VLD2q16wb_fixed: 2173 case ARM::VLD2q32wb_fixed: 2174 case ARM::VLD2d8wb_register: 2175 case ARM::VLD2d16wb_register: 2176 case ARM::VLD2d32wb_register: 2177 case ARM::VLD2q8wb_register: 2178 case ARM::VLD2q16wb_register: 2179 case ARM::VLD2q32wb_register: 2180 case ARM::VLD2b8wb_fixed: 2181 case ARM::VLD2b16wb_fixed: 2182 case ARM::VLD2b32wb_fixed: 2183 case ARM::VLD2b8wb_register: 2184 case ARM::VLD2b16wb_register: 2185 case ARM::VLD2b32wb_register: 2186 case ARM::VLD3d8_UPD: 2187 case ARM::VLD3d16_UPD: 2188 case ARM::VLD3d32_UPD: 2189 case ARM::VLD3q8_UPD: 2190 case ARM::VLD3q16_UPD: 2191 case ARM::VLD3q32_UPD: 2192 case ARM::VLD4d8_UPD: 2193 case ARM::VLD4d16_UPD: 2194 case ARM::VLD4d32_UPD: 2195 case ARM::VLD4q8_UPD: 2196 case ARM::VLD4q16_UPD: 2197 case ARM::VLD4q32_UPD: 2198 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2199 return MCDisassembler::Fail; 2200 break; 2201 default: 2202 break; 2203 } 2204 2205 // AddrMode6 Base (register+alignment) 2206 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2207 return MCDisassembler::Fail; 2208 2209 // AddrMode6 Offset (register) 2210 switch (Inst.getOpcode()) { 2211 default: 2212 // The below have been updated to have explicit am6offset split 2213 // between fixed and register offset. For those instructions not 2214 // yet updated, we need to add an additional reg0 operand for the 2215 // fixed variant. 2216 // 2217 // The fixed offset encodes as Rm == 0xd, so we check for that. 2218 if (Rm == 0xd) { 2219 Inst.addOperand(MCOperand::CreateReg(0)); 2220 break; 2221 } 2222 // Fall through to handle the register offset variant. 2223 case ARM::VLD1d8wb_fixed: 2224 case ARM::VLD1d16wb_fixed: 2225 case ARM::VLD1d32wb_fixed: 2226 case ARM::VLD1d64wb_fixed: 2227 case ARM::VLD1d8Twb_fixed: 2228 case ARM::VLD1d16Twb_fixed: 2229 case ARM::VLD1d32Twb_fixed: 2230 case ARM::VLD1d64Twb_fixed: 2231 case ARM::VLD1d8Qwb_fixed: 2232 case ARM::VLD1d16Qwb_fixed: 2233 case ARM::VLD1d32Qwb_fixed: 2234 case ARM::VLD1d64Qwb_fixed: 2235 case ARM::VLD1d8wb_register: 2236 case ARM::VLD1d16wb_register: 2237 case ARM::VLD1d32wb_register: 2238 case ARM::VLD1d64wb_register: 2239 case ARM::VLD1q8wb_fixed: 2240 case ARM::VLD1q16wb_fixed: 2241 case ARM::VLD1q32wb_fixed: 2242 case ARM::VLD1q64wb_fixed: 2243 case ARM::VLD1q8wb_register: 2244 case ARM::VLD1q16wb_register: 2245 case ARM::VLD1q32wb_register: 2246 case ARM::VLD1q64wb_register: 2247 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2248 // variant encodes Rm == 0xf. Anything else is a register offset post- 2249 // increment and we need to add the register operand to the instruction. 2250 if (Rm != 0xD && Rm != 0xF && 2251 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2252 return MCDisassembler::Fail; 2253 break; 2254 } 2255 2256 return S; 2257 } 2258 2259 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 2260 uint64_t Address, const void *Decoder) { 2261 DecodeStatus S = MCDisassembler::Success; 2262 2263 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2264 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2265 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 2266 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2267 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 2268 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2269 2270 // Writeback Operand 2271 switch (Inst.getOpcode()) { 2272 case ARM::VST1d8wb_fixed: 2273 case ARM::VST1d16wb_fixed: 2274 case ARM::VST1d32wb_fixed: 2275 case ARM::VST1d64wb_fixed: 2276 case ARM::VST1d8wb_register: 2277 case ARM::VST1d16wb_register: 2278 case ARM::VST1d32wb_register: 2279 case ARM::VST1d64wb_register: 2280 case ARM::VST1q8wb_fixed: 2281 case ARM::VST1q16wb_fixed: 2282 case ARM::VST1q32wb_fixed: 2283 case ARM::VST1q64wb_fixed: 2284 case ARM::VST1q8wb_register: 2285 case ARM::VST1q16wb_register: 2286 case ARM::VST1q32wb_register: 2287 case ARM::VST1q64wb_register: 2288 case ARM::VST1d8Twb_fixed: 2289 case ARM::VST1d16Twb_fixed: 2290 case ARM::VST1d32Twb_fixed: 2291 case ARM::VST1d64Twb_fixed: 2292 case ARM::VST1d8Twb_register: 2293 case ARM::VST1d16Twb_register: 2294 case ARM::VST1d32Twb_register: 2295 case ARM::VST1d64Twb_register: 2296 case ARM::VST1d8Qwb_fixed: 2297 case ARM::VST1d16Qwb_fixed: 2298 case ARM::VST1d32Qwb_fixed: 2299 case ARM::VST1d64Qwb_fixed: 2300 case ARM::VST1d8Qwb_register: 2301 case ARM::VST1d16Qwb_register: 2302 case ARM::VST1d32Qwb_register: 2303 case ARM::VST1d64Qwb_register: 2304 case ARM::VST2d8wb_fixed: 2305 case ARM::VST2d16wb_fixed: 2306 case ARM::VST2d32wb_fixed: 2307 case ARM::VST2d8wb_register: 2308 case ARM::VST2d16wb_register: 2309 case ARM::VST2d32wb_register: 2310 case ARM::VST2q8wb_fixed: 2311 case ARM::VST2q16wb_fixed: 2312 case ARM::VST2q32wb_fixed: 2313 case ARM::VST2q8wb_register: 2314 case ARM::VST2q16wb_register: 2315 case ARM::VST2q32wb_register: 2316 case ARM::VST2b8wb_fixed: 2317 case ARM::VST2b16wb_fixed: 2318 case ARM::VST2b32wb_fixed: 2319 case ARM::VST2b8wb_register: 2320 case ARM::VST2b16wb_register: 2321 case ARM::VST2b32wb_register: 2322 case ARM::VST3d8_UPD: 2323 case ARM::VST3d16_UPD: 2324 case ARM::VST3d32_UPD: 2325 case ARM::VST3q8_UPD: 2326 case ARM::VST3q16_UPD: 2327 case ARM::VST3q32_UPD: 2328 case ARM::VST4d8_UPD: 2329 case ARM::VST4d16_UPD: 2330 case ARM::VST4d32_UPD: 2331 case ARM::VST4q8_UPD: 2332 case ARM::VST4q16_UPD: 2333 case ARM::VST4q32_UPD: 2334 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2335 return MCDisassembler::Fail; 2336 break; 2337 default: 2338 break; 2339 } 2340 2341 // AddrMode6 Base (register+alignment) 2342 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2343 return MCDisassembler::Fail; 2344 2345 // AddrMode6 Offset (register) 2346 switch (Inst.getOpcode()) { 2347 default: 2348 if (Rm == 0xD) 2349 Inst.addOperand(MCOperand::CreateReg(0)); 2350 else if (Rm != 0xF) { 2351 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2352 return MCDisassembler::Fail; 2353 } 2354 break; 2355 case ARM::VST1d8wb_fixed: 2356 case ARM::VST1d16wb_fixed: 2357 case ARM::VST1d32wb_fixed: 2358 case ARM::VST1d64wb_fixed: 2359 case ARM::VST1q8wb_fixed: 2360 case ARM::VST1q16wb_fixed: 2361 case ARM::VST1q32wb_fixed: 2362 case ARM::VST1q64wb_fixed: 2363 break; 2364 } 2365 2366 2367 // First input register 2368 switch (Inst.getOpcode()) { 2369 case ARM::VST1q16: 2370 case ARM::VST1q32: 2371 case ARM::VST1q64: 2372 case ARM::VST1q8: 2373 case ARM::VST1q16wb_fixed: 2374 case ARM::VST1q16wb_register: 2375 case ARM::VST1q32wb_fixed: 2376 case ARM::VST1q32wb_register: 2377 case ARM::VST1q64wb_fixed: 2378 case ARM::VST1q64wb_register: 2379 case ARM::VST1q8wb_fixed: 2380 case ARM::VST1q8wb_register: 2381 case ARM::VST2d16: 2382 case ARM::VST2d32: 2383 case ARM::VST2d8: 2384 case ARM::VST2d16wb_fixed: 2385 case ARM::VST2d16wb_register: 2386 case ARM::VST2d32wb_fixed: 2387 case ARM::VST2d32wb_register: 2388 case ARM::VST2d8wb_fixed: 2389 case ARM::VST2d8wb_register: 2390 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2391 return MCDisassembler::Fail; 2392 break; 2393 case ARM::VST2b16: 2394 case ARM::VST2b32: 2395 case ARM::VST2b8: 2396 case ARM::VST2b16wb_fixed: 2397 case ARM::VST2b16wb_register: 2398 case ARM::VST2b32wb_fixed: 2399 case ARM::VST2b32wb_register: 2400 case ARM::VST2b8wb_fixed: 2401 case ARM::VST2b8wb_register: 2402 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2403 return MCDisassembler::Fail; 2404 break; 2405 default: 2406 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2407 return MCDisassembler::Fail; 2408 } 2409 2410 // Second input register 2411 switch (Inst.getOpcode()) { 2412 case ARM::VST3d8: 2413 case ARM::VST3d16: 2414 case ARM::VST3d32: 2415 case ARM::VST3d8_UPD: 2416 case ARM::VST3d16_UPD: 2417 case ARM::VST3d32_UPD: 2418 case ARM::VST4d8: 2419 case ARM::VST4d16: 2420 case ARM::VST4d32: 2421 case ARM::VST4d8_UPD: 2422 case ARM::VST4d16_UPD: 2423 case ARM::VST4d32_UPD: 2424 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2425 return MCDisassembler::Fail; 2426 break; 2427 case ARM::VST3q8: 2428 case ARM::VST3q16: 2429 case ARM::VST3q32: 2430 case ARM::VST3q8_UPD: 2431 case ARM::VST3q16_UPD: 2432 case ARM::VST3q32_UPD: 2433 case ARM::VST4q8: 2434 case ARM::VST4q16: 2435 case ARM::VST4q32: 2436 case ARM::VST4q8_UPD: 2437 case ARM::VST4q16_UPD: 2438 case ARM::VST4q32_UPD: 2439 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2440 return MCDisassembler::Fail; 2441 break; 2442 default: 2443 break; 2444 } 2445 2446 // Third input register 2447 switch (Inst.getOpcode()) { 2448 case ARM::VST3d8: 2449 case ARM::VST3d16: 2450 case ARM::VST3d32: 2451 case ARM::VST3d8_UPD: 2452 case ARM::VST3d16_UPD: 2453 case ARM::VST3d32_UPD: 2454 case ARM::VST4d8: 2455 case ARM::VST4d16: 2456 case ARM::VST4d32: 2457 case ARM::VST4d8_UPD: 2458 case ARM::VST4d16_UPD: 2459 case ARM::VST4d32_UPD: 2460 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2461 return MCDisassembler::Fail; 2462 break; 2463 case ARM::VST3q8: 2464 case ARM::VST3q16: 2465 case ARM::VST3q32: 2466 case ARM::VST3q8_UPD: 2467 case ARM::VST3q16_UPD: 2468 case ARM::VST3q32_UPD: 2469 case ARM::VST4q8: 2470 case ARM::VST4q16: 2471 case ARM::VST4q32: 2472 case ARM::VST4q8_UPD: 2473 case ARM::VST4q16_UPD: 2474 case ARM::VST4q32_UPD: 2475 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2476 return MCDisassembler::Fail; 2477 break; 2478 default: 2479 break; 2480 } 2481 2482 // Fourth input register 2483 switch (Inst.getOpcode()) { 2484 case ARM::VST4d8: 2485 case ARM::VST4d16: 2486 case ARM::VST4d32: 2487 case ARM::VST4d8_UPD: 2488 case ARM::VST4d16_UPD: 2489 case ARM::VST4d32_UPD: 2490 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2491 return MCDisassembler::Fail; 2492 break; 2493 case ARM::VST4q8: 2494 case ARM::VST4q16: 2495 case ARM::VST4q32: 2496 case ARM::VST4q8_UPD: 2497 case ARM::VST4q16_UPD: 2498 case ARM::VST4q32_UPD: 2499 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2500 return MCDisassembler::Fail; 2501 break; 2502 default: 2503 break; 2504 } 2505 2506 return S; 2507 } 2508 2509 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2510 uint64_t Address, const void *Decoder) { 2511 DecodeStatus S = MCDisassembler::Success; 2512 2513 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2514 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2515 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2516 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2517 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2518 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2519 2520 align *= (1 << size); 2521 2522 switch (Inst.getOpcode()) { 2523 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2524 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2525 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2526 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2527 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2528 return MCDisassembler::Fail; 2529 break; 2530 default: 2531 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2532 return MCDisassembler::Fail; 2533 break; 2534 } 2535 if (Rm != 0xF) { 2536 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2537 return MCDisassembler::Fail; 2538 } 2539 2540 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2541 return MCDisassembler::Fail; 2542 Inst.addOperand(MCOperand::CreateImm(align)); 2543 2544 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2545 // variant encodes Rm == 0xf. Anything else is a register offset post- 2546 // increment and we need to add the register operand to the instruction. 2547 if (Rm != 0xD && Rm != 0xF && 2548 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2549 return MCDisassembler::Fail; 2550 2551 return S; 2552 } 2553 2554 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2555 uint64_t Address, const void *Decoder) { 2556 DecodeStatus S = MCDisassembler::Success; 2557 2558 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2559 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2560 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2561 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2562 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2563 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 2564 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 2565 align *= 2*size; 2566 2567 switch (Inst.getOpcode()) { 2568 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2569 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2570 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2571 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2572 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2573 return MCDisassembler::Fail; 2574 break; 2575 default: 2576 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2577 return MCDisassembler::Fail; 2578 break; 2579 } 2580 2581 if (Rm != 0xF) 2582 Inst.addOperand(MCOperand::CreateImm(0)); 2583 2584 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2585 return MCDisassembler::Fail; 2586 Inst.addOperand(MCOperand::CreateImm(align)); 2587 2588 if (Rm == 0xD) 2589 Inst.addOperand(MCOperand::CreateReg(0)); 2590 else if (Rm != 0xF) { 2591 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2592 return MCDisassembler::Fail; 2593 } 2594 2595 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2596 return MCDisassembler::Fail; 2597 2598 return S; 2599 } 2600 2601 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2602 uint64_t Address, const void *Decoder) { 2603 DecodeStatus S = MCDisassembler::Success; 2604 2605 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2606 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2607 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2608 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2609 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2610 2611 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2612 return MCDisassembler::Fail; 2613 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2614 return MCDisassembler::Fail; 2615 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2616 return MCDisassembler::Fail; 2617 if (Rm != 0xF) { 2618 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2619 return MCDisassembler::Fail; 2620 } 2621 2622 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2623 return MCDisassembler::Fail; 2624 Inst.addOperand(MCOperand::CreateImm(0)); 2625 2626 if (Rm == 0xD) 2627 Inst.addOperand(MCOperand::CreateReg(0)); 2628 else if (Rm != 0xF) { 2629 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2630 return MCDisassembler::Fail; 2631 } 2632 2633 return S; 2634 } 2635 2636 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2637 uint64_t Address, const void *Decoder) { 2638 DecodeStatus S = MCDisassembler::Success; 2639 2640 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2641 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2642 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2643 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2644 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2645 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2646 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2647 2648 if (size == 0x3) { 2649 size = 4; 2650 align = 16; 2651 } else { 2652 if (size == 2) { 2653 size = 1 << size; 2654 align *= 8; 2655 } else { 2656 size = 1 << size; 2657 align *= 4*size; 2658 } 2659 } 2660 2661 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2662 return MCDisassembler::Fail; 2663 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2664 return MCDisassembler::Fail; 2665 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2666 return MCDisassembler::Fail; 2667 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2668 return MCDisassembler::Fail; 2669 if (Rm != 0xF) { 2670 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2671 return MCDisassembler::Fail; 2672 } 2673 2674 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2675 return MCDisassembler::Fail; 2676 Inst.addOperand(MCOperand::CreateImm(align)); 2677 2678 if (Rm == 0xD) 2679 Inst.addOperand(MCOperand::CreateReg(0)); 2680 else if (Rm != 0xF) { 2681 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2682 return MCDisassembler::Fail; 2683 } 2684 2685 return S; 2686 } 2687 2688 static DecodeStatus 2689 DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 2690 uint64_t Address, const void *Decoder) { 2691 DecodeStatus S = MCDisassembler::Success; 2692 2693 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2694 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2695 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2696 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 2697 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 2698 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 2699 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 2700 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 2701 2702 if (Q) { 2703 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2704 return MCDisassembler::Fail; 2705 } else { 2706 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2707 return MCDisassembler::Fail; 2708 } 2709 2710 Inst.addOperand(MCOperand::CreateImm(imm)); 2711 2712 switch (Inst.getOpcode()) { 2713 case ARM::VORRiv4i16: 2714 case ARM::VORRiv2i32: 2715 case ARM::VBICiv4i16: 2716 case ARM::VBICiv2i32: 2717 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2718 return MCDisassembler::Fail; 2719 break; 2720 case ARM::VORRiv8i16: 2721 case ARM::VORRiv4i32: 2722 case ARM::VBICiv8i16: 2723 case ARM::VBICiv4i32: 2724 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2725 return MCDisassembler::Fail; 2726 break; 2727 default: 2728 break; 2729 } 2730 2731 return S; 2732 } 2733 2734 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 2735 uint64_t Address, const void *Decoder) { 2736 DecodeStatus S = MCDisassembler::Success; 2737 2738 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2739 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2740 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2741 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2742 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2743 2744 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2745 return MCDisassembler::Fail; 2746 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2747 return MCDisassembler::Fail; 2748 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2749 2750 return S; 2751 } 2752 2753 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 2754 uint64_t Address, const void *Decoder) { 2755 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2756 return MCDisassembler::Success; 2757 } 2758 2759 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2760 uint64_t Address, const void *Decoder) { 2761 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2762 return MCDisassembler::Success; 2763 } 2764 2765 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2766 uint64_t Address, const void *Decoder) { 2767 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2768 return MCDisassembler::Success; 2769 } 2770 2771 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2772 uint64_t Address, const void *Decoder) { 2773 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2774 return MCDisassembler::Success; 2775 } 2776 2777 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2778 uint64_t Address, const void *Decoder) { 2779 DecodeStatus S = MCDisassembler::Success; 2780 2781 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2782 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2783 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2784 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2785 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2786 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2787 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2788 2789 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2790 return MCDisassembler::Fail; 2791 if (op) { 2792 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2793 return MCDisassembler::Fail; // Writeback 2794 } 2795 2796 switch (Inst.getOpcode()) { 2797 case ARM::VTBL2: 2798 case ARM::VTBX2: 2799 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 2800 return MCDisassembler::Fail; 2801 break; 2802 default: 2803 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 2804 return MCDisassembler::Fail; 2805 } 2806 2807 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2808 return MCDisassembler::Fail; 2809 2810 return S; 2811 } 2812 2813 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2814 uint64_t Address, const void *Decoder) { 2815 DecodeStatus S = MCDisassembler::Success; 2816 2817 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2818 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2819 2820 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 2821 return MCDisassembler::Fail; 2822 2823 switch(Inst.getOpcode()) { 2824 default: 2825 return MCDisassembler::Fail; 2826 case ARM::tADR: 2827 break; // tADR does not explicitly represent the PC as an operand. 2828 case ARM::tADDrSPi: 2829 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2830 break; 2831 } 2832 2833 Inst.addOperand(MCOperand::CreateImm(imm)); 2834 return S; 2835 } 2836 2837 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2838 uint64_t Address, const void *Decoder) { 2839 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2840 return MCDisassembler::Success; 2841 } 2842 2843 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2844 uint64_t Address, const void *Decoder) { 2845 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2846 return MCDisassembler::Success; 2847 } 2848 2849 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2850 uint64_t Address, const void *Decoder) { 2851 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2852 return MCDisassembler::Success; 2853 } 2854 2855 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2856 uint64_t Address, const void *Decoder) { 2857 DecodeStatus S = MCDisassembler::Success; 2858 2859 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2860 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2861 2862 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2863 return MCDisassembler::Fail; 2864 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 2865 return MCDisassembler::Fail; 2866 2867 return S; 2868 } 2869 2870 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2871 uint64_t Address, const void *Decoder) { 2872 DecodeStatus S = MCDisassembler::Success; 2873 2874 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2875 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2876 2877 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2878 return MCDisassembler::Fail; 2879 Inst.addOperand(MCOperand::CreateImm(imm)); 2880 2881 return S; 2882 } 2883 2884 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2885 uint64_t Address, const void *Decoder) { 2886 unsigned imm = Val << 2; 2887 2888 Inst.addOperand(MCOperand::CreateImm(imm)); 2889 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 2890 2891 return MCDisassembler::Success; 2892 } 2893 2894 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2895 uint64_t Address, const void *Decoder) { 2896 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2897 Inst.addOperand(MCOperand::CreateImm(Val)); 2898 2899 return MCDisassembler::Success; 2900 } 2901 2902 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2903 uint64_t Address, const void *Decoder) { 2904 DecodeStatus S = MCDisassembler::Success; 2905 2906 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2907 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2908 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2909 2910 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2911 return MCDisassembler::Fail; 2912 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 2913 return MCDisassembler::Fail; 2914 Inst.addOperand(MCOperand::CreateImm(imm)); 2915 2916 return S; 2917 } 2918 2919 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2920 uint64_t Address, const void *Decoder) { 2921 DecodeStatus S = MCDisassembler::Success; 2922 2923 switch (Inst.getOpcode()) { 2924 case ARM::t2PLDs: 2925 case ARM::t2PLDWs: 2926 case ARM::t2PLIs: 2927 break; 2928 default: { 2929 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2930 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 2931 return MCDisassembler::Fail; 2932 } 2933 } 2934 2935 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2936 if (Rn == 0xF) { 2937 switch (Inst.getOpcode()) { 2938 case ARM::t2LDRBs: 2939 Inst.setOpcode(ARM::t2LDRBpci); 2940 break; 2941 case ARM::t2LDRHs: 2942 Inst.setOpcode(ARM::t2LDRHpci); 2943 break; 2944 case ARM::t2LDRSHs: 2945 Inst.setOpcode(ARM::t2LDRSHpci); 2946 break; 2947 case ARM::t2LDRSBs: 2948 Inst.setOpcode(ARM::t2LDRSBpci); 2949 break; 2950 case ARM::t2PLDs: 2951 Inst.setOpcode(ARM::t2PLDi12); 2952 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2953 break; 2954 default: 2955 return MCDisassembler::Fail; 2956 } 2957 2958 int imm = fieldFromInstruction32(Insn, 0, 12); 2959 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2960 Inst.addOperand(MCOperand::CreateImm(imm)); 2961 2962 return S; 2963 } 2964 2965 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2966 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2967 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2968 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 2969 return MCDisassembler::Fail; 2970 2971 return S; 2972 } 2973 2974 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2975 uint64_t Address, const void *Decoder) { 2976 int imm = Val & 0xFF; 2977 if (!(Val & 0x100)) imm *= -1; 2978 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2979 2980 return MCDisassembler::Success; 2981 } 2982 2983 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2984 uint64_t Address, const void *Decoder) { 2985 DecodeStatus S = MCDisassembler::Success; 2986 2987 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2988 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2989 2990 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2991 return MCDisassembler::Fail; 2992 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 2993 return MCDisassembler::Fail; 2994 2995 return S; 2996 } 2997 2998 static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val, 2999 uint64_t Address, const void *Decoder) { 3000 DecodeStatus S = MCDisassembler::Success; 3001 3002 unsigned Rn = fieldFromInstruction32(Val, 8, 4); 3003 unsigned imm = fieldFromInstruction32(Val, 0, 8); 3004 3005 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3006 return MCDisassembler::Fail; 3007 3008 Inst.addOperand(MCOperand::CreateImm(imm)); 3009 3010 return S; 3011 } 3012 3013 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 3014 uint64_t Address, const void *Decoder) { 3015 int imm = Val & 0xFF; 3016 if (Val == 0) 3017 imm = INT32_MIN; 3018 else if (!(Val & 0x100)) 3019 imm *= -1; 3020 Inst.addOperand(MCOperand::CreateImm(imm)); 3021 3022 return MCDisassembler::Success; 3023 } 3024 3025 3026 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 3027 uint64_t Address, const void *Decoder) { 3028 DecodeStatus S = MCDisassembler::Success; 3029 3030 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 3031 unsigned imm = fieldFromInstruction32(Val, 0, 9); 3032 3033 // Some instructions always use an additive offset. 3034 switch (Inst.getOpcode()) { 3035 case ARM::t2LDRT: 3036 case ARM::t2LDRBT: 3037 case ARM::t2LDRHT: 3038 case ARM::t2LDRSBT: 3039 case ARM::t2LDRSHT: 3040 case ARM::t2STRT: 3041 case ARM::t2STRBT: 3042 case ARM::t2STRHT: 3043 imm |= 0x100; 3044 break; 3045 default: 3046 break; 3047 } 3048 3049 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3050 return MCDisassembler::Fail; 3051 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3052 return MCDisassembler::Fail; 3053 3054 return S; 3055 } 3056 3057 static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn, 3058 uint64_t Address, const void *Decoder) { 3059 DecodeStatus S = MCDisassembler::Success; 3060 3061 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3062 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3063 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 3064 addr |= fieldFromInstruction32(Insn, 9, 1) << 8; 3065 addr |= Rn << 9; 3066 unsigned load = fieldFromInstruction32(Insn, 20, 1); 3067 3068 if (!load) { 3069 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3070 return MCDisassembler::Fail; 3071 } 3072 3073 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3074 return MCDisassembler::Fail; 3075 3076 if (load) { 3077 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3078 return MCDisassembler::Fail; 3079 } 3080 3081 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3082 return MCDisassembler::Fail; 3083 3084 return S; 3085 } 3086 3087 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 3088 uint64_t Address, const void *Decoder) { 3089 DecodeStatus S = MCDisassembler::Success; 3090 3091 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 3092 unsigned imm = fieldFromInstruction32(Val, 0, 12); 3093 3094 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3095 return MCDisassembler::Fail; 3096 Inst.addOperand(MCOperand::CreateImm(imm)); 3097 3098 return S; 3099 } 3100 3101 3102 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 3103 uint64_t Address, const void *Decoder) { 3104 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 3105 3106 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3107 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3108 Inst.addOperand(MCOperand::CreateImm(imm)); 3109 3110 return MCDisassembler::Success; 3111 } 3112 3113 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 3114 uint64_t Address, const void *Decoder) { 3115 DecodeStatus S = MCDisassembler::Success; 3116 3117 if (Inst.getOpcode() == ARM::tADDrSP) { 3118 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 3119 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 3120 3121 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3122 return MCDisassembler::Fail; 3123 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3124 return MCDisassembler::Fail; 3125 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3126 } else if (Inst.getOpcode() == ARM::tADDspr) { 3127 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 3128 3129 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3130 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3131 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3132 return MCDisassembler::Fail; 3133 } 3134 3135 return S; 3136 } 3137 3138 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 3139 uint64_t Address, const void *Decoder) { 3140 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 3141 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 3142 3143 Inst.addOperand(MCOperand::CreateImm(imod)); 3144 Inst.addOperand(MCOperand::CreateImm(flags)); 3145 3146 return MCDisassembler::Success; 3147 } 3148 3149 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 3150 uint64_t Address, const void *Decoder) { 3151 DecodeStatus S = MCDisassembler::Success; 3152 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3153 unsigned add = fieldFromInstruction32(Insn, 4, 1); 3154 3155 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3156 return MCDisassembler::Fail; 3157 Inst.addOperand(MCOperand::CreateImm(add)); 3158 3159 return S; 3160 } 3161 3162 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 3163 uint64_t Address, const void *Decoder) { 3164 if (!tryAddingSymbolicOperand(Address, 3165 (Address & ~2u) + SignExtend32<22>(Val << 1) + 4, 3166 true, 4, Inst, Decoder)) 3167 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 3168 return MCDisassembler::Success; 3169 } 3170 3171 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 3172 uint64_t Address, const void *Decoder) { 3173 if (Val == 0xA || Val == 0xB) 3174 return MCDisassembler::Fail; 3175 3176 Inst.addOperand(MCOperand::CreateImm(Val)); 3177 return MCDisassembler::Success; 3178 } 3179 3180 static DecodeStatus 3181 DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Insn, 3182 uint64_t Address, const void *Decoder) { 3183 DecodeStatus S = MCDisassembler::Success; 3184 3185 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3186 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3187 3188 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3189 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3190 return MCDisassembler::Fail; 3191 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3192 return MCDisassembler::Fail; 3193 return S; 3194 } 3195 3196 static DecodeStatus 3197 DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 3198 uint64_t Address, const void *Decoder) { 3199 DecodeStatus S = MCDisassembler::Success; 3200 3201 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 3202 if (pred == 0xE || pred == 0xF) { 3203 unsigned opc = fieldFromInstruction32(Insn, 4, 28); 3204 switch (opc) { 3205 default: 3206 return MCDisassembler::Fail; 3207 case 0xf3bf8f4: 3208 Inst.setOpcode(ARM::t2DSB); 3209 break; 3210 case 0xf3bf8f5: 3211 Inst.setOpcode(ARM::t2DMB); 3212 break; 3213 case 0xf3bf8f6: 3214 Inst.setOpcode(ARM::t2ISB); 3215 break; 3216 } 3217 3218 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 3219 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3220 } 3221 3222 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 3223 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 3224 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 3225 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 3226 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 3227 3228 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3229 return MCDisassembler::Fail; 3230 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3231 return MCDisassembler::Fail; 3232 3233 return S; 3234 } 3235 3236 // Decode a shifted immediate operand. These basically consist 3237 // of an 8-bit value, and a 4-bit directive that specifies either 3238 // a splat operation or a rotation. 3239 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 3240 uint64_t Address, const void *Decoder) { 3241 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 3242 if (ctrl == 0) { 3243 unsigned byte = fieldFromInstruction32(Val, 8, 2); 3244 unsigned imm = fieldFromInstruction32(Val, 0, 8); 3245 switch (byte) { 3246 case 0: 3247 Inst.addOperand(MCOperand::CreateImm(imm)); 3248 break; 3249 case 1: 3250 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 3251 break; 3252 case 2: 3253 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 3254 break; 3255 case 3: 3256 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 3257 (imm << 8) | imm)); 3258 break; 3259 } 3260 } else { 3261 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 3262 unsigned rot = fieldFromInstruction32(Val, 7, 5); 3263 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3264 Inst.addOperand(MCOperand::CreateImm(imm)); 3265 } 3266 3267 return MCDisassembler::Success; 3268 } 3269 3270 static DecodeStatus 3271 DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 3272 uint64_t Address, const void *Decoder){ 3273 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 3274 return MCDisassembler::Success; 3275 } 3276 3277 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 3278 uint64_t Address, const void *Decoder){ 3279 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<22>(Val<<1) + 4, 3280 true, 4, Inst, Decoder)) 3281 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 3282 return MCDisassembler::Success; 3283 } 3284 3285 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 3286 uint64_t Address, const void *Decoder) { 3287 switch (Val) { 3288 default: 3289 return MCDisassembler::Fail; 3290 case 0xF: // SY 3291 case 0xE: // ST 3292 case 0xB: // ISH 3293 case 0xA: // ISHST 3294 case 0x7: // NSH 3295 case 0x6: // NSHST 3296 case 0x3: // OSH 3297 case 0x2: // OSHST 3298 break; 3299 } 3300 3301 Inst.addOperand(MCOperand::CreateImm(Val)); 3302 return MCDisassembler::Success; 3303 } 3304 3305 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, 3306 uint64_t Address, const void *Decoder) { 3307 if (!Val) return MCDisassembler::Fail; 3308 Inst.addOperand(MCOperand::CreateImm(Val)); 3309 return MCDisassembler::Success; 3310 } 3311 3312 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 3313 uint64_t Address, const void *Decoder) { 3314 DecodeStatus S = MCDisassembler::Success; 3315 3316 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3317 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3318 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3319 3320 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3321 3322 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3323 return MCDisassembler::Fail; 3324 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3325 return MCDisassembler::Fail; 3326 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3327 return MCDisassembler::Fail; 3328 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3329 return MCDisassembler::Fail; 3330 3331 return S; 3332 } 3333 3334 3335 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 3336 uint64_t Address, const void *Decoder){ 3337 DecodeStatus S = MCDisassembler::Success; 3338 3339 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3340 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 3341 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3342 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3343 3344 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 3345 return MCDisassembler::Fail; 3346 3347 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3348 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail; 3349 3350 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3351 return MCDisassembler::Fail; 3352 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3353 return MCDisassembler::Fail; 3354 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3355 return MCDisassembler::Fail; 3356 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3357 return MCDisassembler::Fail; 3358 3359 return S; 3360 } 3361 3362 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 3363 uint64_t Address, const void *Decoder) { 3364 DecodeStatus S = MCDisassembler::Success; 3365 3366 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3367 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3368 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3369 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3370 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3371 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3372 3373 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3374 3375 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3376 return MCDisassembler::Fail; 3377 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3378 return MCDisassembler::Fail; 3379 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3380 return MCDisassembler::Fail; 3381 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3382 return MCDisassembler::Fail; 3383 3384 return S; 3385 } 3386 3387 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 3388 uint64_t Address, const void *Decoder) { 3389 DecodeStatus S = MCDisassembler::Success; 3390 3391 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3392 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3393 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3394 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3395 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3396 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3397 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3398 3399 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3400 if (Rm == 0xF) S = MCDisassembler::SoftFail; 3401 3402 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3403 return MCDisassembler::Fail; 3404 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3405 return MCDisassembler::Fail; 3406 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3407 return MCDisassembler::Fail; 3408 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3409 return MCDisassembler::Fail; 3410 3411 return S; 3412 } 3413 3414 3415 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 3416 uint64_t Address, const void *Decoder) { 3417 DecodeStatus S = MCDisassembler::Success; 3418 3419 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3420 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3421 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3422 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3423 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3424 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3425 3426 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3427 3428 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3429 return MCDisassembler::Fail; 3430 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3431 return MCDisassembler::Fail; 3432 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3433 return MCDisassembler::Fail; 3434 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3435 return MCDisassembler::Fail; 3436 3437 return S; 3438 } 3439 3440 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 3441 uint64_t Address, const void *Decoder) { 3442 DecodeStatus S = MCDisassembler::Success; 3443 3444 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3445 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3446 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3447 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3448 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3449 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3450 3451 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3452 3453 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3454 return MCDisassembler::Fail; 3455 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3456 return MCDisassembler::Fail; 3457 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3458 return MCDisassembler::Fail; 3459 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3460 return MCDisassembler::Fail; 3461 3462 return S; 3463 } 3464 3465 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 3466 uint64_t Address, const void *Decoder) { 3467 DecodeStatus S = MCDisassembler::Success; 3468 3469 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3470 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3471 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3472 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3473 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3474 3475 unsigned align = 0; 3476 unsigned index = 0; 3477 switch (size) { 3478 default: 3479 return MCDisassembler::Fail; 3480 case 0: 3481 if (fieldFromInstruction32(Insn, 4, 1)) 3482 return MCDisassembler::Fail; // UNDEFINED 3483 index = fieldFromInstruction32(Insn, 5, 3); 3484 break; 3485 case 1: 3486 if (fieldFromInstruction32(Insn, 5, 1)) 3487 return MCDisassembler::Fail; // UNDEFINED 3488 index = fieldFromInstruction32(Insn, 6, 2); 3489 if (fieldFromInstruction32(Insn, 4, 1)) 3490 align = 2; 3491 break; 3492 case 2: 3493 if (fieldFromInstruction32(Insn, 6, 1)) 3494 return MCDisassembler::Fail; // UNDEFINED 3495 index = fieldFromInstruction32(Insn, 7, 1); 3496 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3497 align = 4; 3498 } 3499 3500 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3501 return MCDisassembler::Fail; 3502 if (Rm != 0xF) { // Writeback 3503 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3504 return MCDisassembler::Fail; 3505 } 3506 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3507 return MCDisassembler::Fail; 3508 Inst.addOperand(MCOperand::CreateImm(align)); 3509 if (Rm != 0xF) { 3510 if (Rm != 0xD) { 3511 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3512 return MCDisassembler::Fail; 3513 } else 3514 Inst.addOperand(MCOperand::CreateReg(0)); 3515 } 3516 3517 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3518 return MCDisassembler::Fail; 3519 Inst.addOperand(MCOperand::CreateImm(index)); 3520 3521 return S; 3522 } 3523 3524 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 3525 uint64_t Address, const void *Decoder) { 3526 DecodeStatus S = MCDisassembler::Success; 3527 3528 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3529 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3530 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3531 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3532 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3533 3534 unsigned align = 0; 3535 unsigned index = 0; 3536 switch (size) { 3537 default: 3538 return MCDisassembler::Fail; 3539 case 0: 3540 if (fieldFromInstruction32(Insn, 4, 1)) 3541 return MCDisassembler::Fail; // UNDEFINED 3542 index = fieldFromInstruction32(Insn, 5, 3); 3543 break; 3544 case 1: 3545 if (fieldFromInstruction32(Insn, 5, 1)) 3546 return MCDisassembler::Fail; // UNDEFINED 3547 index = fieldFromInstruction32(Insn, 6, 2); 3548 if (fieldFromInstruction32(Insn, 4, 1)) 3549 align = 2; 3550 break; 3551 case 2: 3552 if (fieldFromInstruction32(Insn, 6, 1)) 3553 return MCDisassembler::Fail; // UNDEFINED 3554 index = fieldFromInstruction32(Insn, 7, 1); 3555 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3556 align = 4; 3557 } 3558 3559 if (Rm != 0xF) { // Writeback 3560 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3561 return MCDisassembler::Fail; 3562 } 3563 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3564 return MCDisassembler::Fail; 3565 Inst.addOperand(MCOperand::CreateImm(align)); 3566 if (Rm != 0xF) { 3567 if (Rm != 0xD) { 3568 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3569 return MCDisassembler::Fail; 3570 } else 3571 Inst.addOperand(MCOperand::CreateReg(0)); 3572 } 3573 3574 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3575 return MCDisassembler::Fail; 3576 Inst.addOperand(MCOperand::CreateImm(index)); 3577 3578 return S; 3579 } 3580 3581 3582 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 3583 uint64_t Address, const void *Decoder) { 3584 DecodeStatus S = MCDisassembler::Success; 3585 3586 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3587 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3588 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3589 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3590 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3591 3592 unsigned align = 0; 3593 unsigned index = 0; 3594 unsigned inc = 1; 3595 switch (size) { 3596 default: 3597 return MCDisassembler::Fail; 3598 case 0: 3599 index = fieldFromInstruction32(Insn, 5, 3); 3600 if (fieldFromInstruction32(Insn, 4, 1)) 3601 align = 2; 3602 break; 3603 case 1: 3604 index = fieldFromInstruction32(Insn, 6, 2); 3605 if (fieldFromInstruction32(Insn, 4, 1)) 3606 align = 4; 3607 if (fieldFromInstruction32(Insn, 5, 1)) 3608 inc = 2; 3609 break; 3610 case 2: 3611 if (fieldFromInstruction32(Insn, 5, 1)) 3612 return MCDisassembler::Fail; // UNDEFINED 3613 index = fieldFromInstruction32(Insn, 7, 1); 3614 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3615 align = 8; 3616 if (fieldFromInstruction32(Insn, 6, 1)) 3617 inc = 2; 3618 break; 3619 } 3620 3621 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3622 return MCDisassembler::Fail; 3623 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3624 return MCDisassembler::Fail; 3625 if (Rm != 0xF) { // Writeback 3626 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3627 return MCDisassembler::Fail; 3628 } 3629 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3630 return MCDisassembler::Fail; 3631 Inst.addOperand(MCOperand::CreateImm(align)); 3632 if (Rm != 0xF) { 3633 if (Rm != 0xD) { 3634 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3635 return MCDisassembler::Fail; 3636 } else 3637 Inst.addOperand(MCOperand::CreateReg(0)); 3638 } 3639 3640 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3641 return MCDisassembler::Fail; 3642 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3643 return MCDisassembler::Fail; 3644 Inst.addOperand(MCOperand::CreateImm(index)); 3645 3646 return S; 3647 } 3648 3649 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 3650 uint64_t Address, const void *Decoder) { 3651 DecodeStatus S = MCDisassembler::Success; 3652 3653 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3654 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3655 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3656 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3657 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3658 3659 unsigned align = 0; 3660 unsigned index = 0; 3661 unsigned inc = 1; 3662 switch (size) { 3663 default: 3664 return MCDisassembler::Fail; 3665 case 0: 3666 index = fieldFromInstruction32(Insn, 5, 3); 3667 if (fieldFromInstruction32(Insn, 4, 1)) 3668 align = 2; 3669 break; 3670 case 1: 3671 index = fieldFromInstruction32(Insn, 6, 2); 3672 if (fieldFromInstruction32(Insn, 4, 1)) 3673 align = 4; 3674 if (fieldFromInstruction32(Insn, 5, 1)) 3675 inc = 2; 3676 break; 3677 case 2: 3678 if (fieldFromInstruction32(Insn, 5, 1)) 3679 return MCDisassembler::Fail; // UNDEFINED 3680 index = fieldFromInstruction32(Insn, 7, 1); 3681 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3682 align = 8; 3683 if (fieldFromInstruction32(Insn, 6, 1)) 3684 inc = 2; 3685 break; 3686 } 3687 3688 if (Rm != 0xF) { // Writeback 3689 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3690 return MCDisassembler::Fail; 3691 } 3692 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3693 return MCDisassembler::Fail; 3694 Inst.addOperand(MCOperand::CreateImm(align)); 3695 if (Rm != 0xF) { 3696 if (Rm != 0xD) { 3697 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3698 return MCDisassembler::Fail; 3699 } else 3700 Inst.addOperand(MCOperand::CreateReg(0)); 3701 } 3702 3703 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3704 return MCDisassembler::Fail; 3705 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3706 return MCDisassembler::Fail; 3707 Inst.addOperand(MCOperand::CreateImm(index)); 3708 3709 return S; 3710 } 3711 3712 3713 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 3714 uint64_t Address, const void *Decoder) { 3715 DecodeStatus S = MCDisassembler::Success; 3716 3717 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3718 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3719 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3720 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3721 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3722 3723 unsigned align = 0; 3724 unsigned index = 0; 3725 unsigned inc = 1; 3726 switch (size) { 3727 default: 3728 return MCDisassembler::Fail; 3729 case 0: 3730 if (fieldFromInstruction32(Insn, 4, 1)) 3731 return MCDisassembler::Fail; // UNDEFINED 3732 index = fieldFromInstruction32(Insn, 5, 3); 3733 break; 3734 case 1: 3735 if (fieldFromInstruction32(Insn, 4, 1)) 3736 return MCDisassembler::Fail; // UNDEFINED 3737 index = fieldFromInstruction32(Insn, 6, 2); 3738 if (fieldFromInstruction32(Insn, 5, 1)) 3739 inc = 2; 3740 break; 3741 case 2: 3742 if (fieldFromInstruction32(Insn, 4, 2)) 3743 return MCDisassembler::Fail; // UNDEFINED 3744 index = fieldFromInstruction32(Insn, 7, 1); 3745 if (fieldFromInstruction32(Insn, 6, 1)) 3746 inc = 2; 3747 break; 3748 } 3749 3750 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3751 return MCDisassembler::Fail; 3752 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3753 return MCDisassembler::Fail; 3754 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3755 return MCDisassembler::Fail; 3756 3757 if (Rm != 0xF) { // Writeback 3758 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3759 return MCDisassembler::Fail; 3760 } 3761 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3762 return MCDisassembler::Fail; 3763 Inst.addOperand(MCOperand::CreateImm(align)); 3764 if (Rm != 0xF) { 3765 if (Rm != 0xD) { 3766 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3767 return MCDisassembler::Fail; 3768 } else 3769 Inst.addOperand(MCOperand::CreateReg(0)); 3770 } 3771 3772 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3773 return MCDisassembler::Fail; 3774 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3775 return MCDisassembler::Fail; 3776 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3777 return MCDisassembler::Fail; 3778 Inst.addOperand(MCOperand::CreateImm(index)); 3779 3780 return S; 3781 } 3782 3783 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 3784 uint64_t Address, const void *Decoder) { 3785 DecodeStatus S = MCDisassembler::Success; 3786 3787 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3788 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3789 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3790 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3791 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3792 3793 unsigned align = 0; 3794 unsigned index = 0; 3795 unsigned inc = 1; 3796 switch (size) { 3797 default: 3798 return MCDisassembler::Fail; 3799 case 0: 3800 if (fieldFromInstruction32(Insn, 4, 1)) 3801 return MCDisassembler::Fail; // UNDEFINED 3802 index = fieldFromInstruction32(Insn, 5, 3); 3803 break; 3804 case 1: 3805 if (fieldFromInstruction32(Insn, 4, 1)) 3806 return MCDisassembler::Fail; // UNDEFINED 3807 index = fieldFromInstruction32(Insn, 6, 2); 3808 if (fieldFromInstruction32(Insn, 5, 1)) 3809 inc = 2; 3810 break; 3811 case 2: 3812 if (fieldFromInstruction32(Insn, 4, 2)) 3813 return MCDisassembler::Fail; // UNDEFINED 3814 index = fieldFromInstruction32(Insn, 7, 1); 3815 if (fieldFromInstruction32(Insn, 6, 1)) 3816 inc = 2; 3817 break; 3818 } 3819 3820 if (Rm != 0xF) { // Writeback 3821 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3822 return MCDisassembler::Fail; 3823 } 3824 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3825 return MCDisassembler::Fail; 3826 Inst.addOperand(MCOperand::CreateImm(align)); 3827 if (Rm != 0xF) { 3828 if (Rm != 0xD) { 3829 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3830 return MCDisassembler::Fail; 3831 } else 3832 Inst.addOperand(MCOperand::CreateReg(0)); 3833 } 3834 3835 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3836 return MCDisassembler::Fail; 3837 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3838 return MCDisassembler::Fail; 3839 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3840 return MCDisassembler::Fail; 3841 Inst.addOperand(MCOperand::CreateImm(index)); 3842 3843 return S; 3844 } 3845 3846 3847 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 3848 uint64_t Address, const void *Decoder) { 3849 DecodeStatus S = MCDisassembler::Success; 3850 3851 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3852 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3853 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3854 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3855 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3856 3857 unsigned align = 0; 3858 unsigned index = 0; 3859 unsigned inc = 1; 3860 switch (size) { 3861 default: 3862 return MCDisassembler::Fail; 3863 case 0: 3864 if (fieldFromInstruction32(Insn, 4, 1)) 3865 align = 4; 3866 index = fieldFromInstruction32(Insn, 5, 3); 3867 break; 3868 case 1: 3869 if (fieldFromInstruction32(Insn, 4, 1)) 3870 align = 8; 3871 index = fieldFromInstruction32(Insn, 6, 2); 3872 if (fieldFromInstruction32(Insn, 5, 1)) 3873 inc = 2; 3874 break; 3875 case 2: 3876 if (fieldFromInstruction32(Insn, 4, 2)) 3877 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3878 index = fieldFromInstruction32(Insn, 7, 1); 3879 if (fieldFromInstruction32(Insn, 6, 1)) 3880 inc = 2; 3881 break; 3882 } 3883 3884 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3885 return MCDisassembler::Fail; 3886 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3887 return MCDisassembler::Fail; 3888 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3889 return MCDisassembler::Fail; 3890 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3891 return MCDisassembler::Fail; 3892 3893 if (Rm != 0xF) { // Writeback 3894 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3895 return MCDisassembler::Fail; 3896 } 3897 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3898 return MCDisassembler::Fail; 3899 Inst.addOperand(MCOperand::CreateImm(align)); 3900 if (Rm != 0xF) { 3901 if (Rm != 0xD) { 3902 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3903 return MCDisassembler::Fail; 3904 } else 3905 Inst.addOperand(MCOperand::CreateReg(0)); 3906 } 3907 3908 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3909 return MCDisassembler::Fail; 3910 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3911 return MCDisassembler::Fail; 3912 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3913 return MCDisassembler::Fail; 3914 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3915 return MCDisassembler::Fail; 3916 Inst.addOperand(MCOperand::CreateImm(index)); 3917 3918 return S; 3919 } 3920 3921 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 3922 uint64_t Address, const void *Decoder) { 3923 DecodeStatus S = MCDisassembler::Success; 3924 3925 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3926 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3927 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3928 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3929 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3930 3931 unsigned align = 0; 3932 unsigned index = 0; 3933 unsigned inc = 1; 3934 switch (size) { 3935 default: 3936 return MCDisassembler::Fail; 3937 case 0: 3938 if (fieldFromInstruction32(Insn, 4, 1)) 3939 align = 4; 3940 index = fieldFromInstruction32(Insn, 5, 3); 3941 break; 3942 case 1: 3943 if (fieldFromInstruction32(Insn, 4, 1)) 3944 align = 8; 3945 index = fieldFromInstruction32(Insn, 6, 2); 3946 if (fieldFromInstruction32(Insn, 5, 1)) 3947 inc = 2; 3948 break; 3949 case 2: 3950 if (fieldFromInstruction32(Insn, 4, 2)) 3951 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3952 index = fieldFromInstruction32(Insn, 7, 1); 3953 if (fieldFromInstruction32(Insn, 6, 1)) 3954 inc = 2; 3955 break; 3956 } 3957 3958 if (Rm != 0xF) { // Writeback 3959 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3960 return MCDisassembler::Fail; 3961 } 3962 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3963 return MCDisassembler::Fail; 3964 Inst.addOperand(MCOperand::CreateImm(align)); 3965 if (Rm != 0xF) { 3966 if (Rm != 0xD) { 3967 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3968 return MCDisassembler::Fail; 3969 } else 3970 Inst.addOperand(MCOperand::CreateReg(0)); 3971 } 3972 3973 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3974 return MCDisassembler::Fail; 3975 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3976 return MCDisassembler::Fail; 3977 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3978 return MCDisassembler::Fail; 3979 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3980 return MCDisassembler::Fail; 3981 Inst.addOperand(MCOperand::CreateImm(index)); 3982 3983 return S; 3984 } 3985 3986 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 3987 uint64_t Address, const void *Decoder) { 3988 DecodeStatus S = MCDisassembler::Success; 3989 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3990 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3991 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3992 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3993 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3994 3995 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3996 S = MCDisassembler::SoftFail; 3997 3998 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 3999 return MCDisassembler::Fail; 4000 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4001 return MCDisassembler::Fail; 4002 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4003 return MCDisassembler::Fail; 4004 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4005 return MCDisassembler::Fail; 4006 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4007 return MCDisassembler::Fail; 4008 4009 return S; 4010 } 4011 4012 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 4013 uint64_t Address, const void *Decoder) { 4014 DecodeStatus S = MCDisassembler::Success; 4015 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4016 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 4017 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 4018 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 4019 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 4020 4021 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4022 S = MCDisassembler::SoftFail; 4023 4024 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4025 return MCDisassembler::Fail; 4026 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4027 return MCDisassembler::Fail; 4028 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4029 return MCDisassembler::Fail; 4030 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4031 return MCDisassembler::Fail; 4032 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4033 return MCDisassembler::Fail; 4034 4035 return S; 4036 } 4037 4038 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn, 4039 uint64_t Address, const void *Decoder) { 4040 DecodeStatus S = MCDisassembler::Success; 4041 unsigned pred = fieldFromInstruction16(Insn, 4, 4); 4042 // The InstPrinter needs to have the low bit of the predicate in 4043 // the mask operand to be able to print it properly. 4044 unsigned mask = fieldFromInstruction16(Insn, 0, 5); 4045 4046 if (pred == 0xF) { 4047 pred = 0xE; 4048 S = MCDisassembler::SoftFail; 4049 } 4050 4051 if ((mask & 0xF) == 0) { 4052 // Preserve the high bit of the mask, which is the low bit of 4053 // the predicate. 4054 mask &= 0x10; 4055 mask |= 0x8; 4056 S = MCDisassembler::SoftFail; 4057 } 4058 4059 Inst.addOperand(MCOperand::CreateImm(pred)); 4060 Inst.addOperand(MCOperand::CreateImm(mask)); 4061 return S; 4062 } 4063 4064 static DecodeStatus 4065 DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, 4066 uint64_t Address, const void *Decoder) { 4067 DecodeStatus S = MCDisassembler::Success; 4068 4069 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4070 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 4071 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4072 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 4073 unsigned W = fieldFromInstruction32(Insn, 21, 1); 4074 unsigned U = fieldFromInstruction32(Insn, 23, 1); 4075 unsigned P = fieldFromInstruction32(Insn, 24, 1); 4076 bool writeback = (W == 1) | (P == 0); 4077 4078 addr |= (U << 8) | (Rn << 9); 4079 4080 if (writeback && (Rn == Rt || Rn == Rt2)) 4081 Check(S, MCDisassembler::SoftFail); 4082 if (Rt == Rt2) 4083 Check(S, MCDisassembler::SoftFail); 4084 4085 // Rt 4086 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4087 return MCDisassembler::Fail; 4088 // Rt2 4089 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4090 return MCDisassembler::Fail; 4091 // Writeback operand 4092 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4093 return MCDisassembler::Fail; 4094 // addr 4095 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4096 return MCDisassembler::Fail; 4097 4098 return S; 4099 } 4100 4101 static DecodeStatus 4102 DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, 4103 uint64_t Address, const void *Decoder) { 4104 DecodeStatus S = MCDisassembler::Success; 4105 4106 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4107 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 4108 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4109 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 4110 unsigned W = fieldFromInstruction32(Insn, 21, 1); 4111 unsigned U = fieldFromInstruction32(Insn, 23, 1); 4112 unsigned P = fieldFromInstruction32(Insn, 24, 1); 4113 bool writeback = (W == 1) | (P == 0); 4114 4115 addr |= (U << 8) | (Rn << 9); 4116 4117 if (writeback && (Rn == Rt || Rn == Rt2)) 4118 Check(S, MCDisassembler::SoftFail); 4119 4120 // Writeback operand 4121 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4122 return MCDisassembler::Fail; 4123 // Rt 4124 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4125 return MCDisassembler::Fail; 4126 // Rt2 4127 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4128 return MCDisassembler::Fail; 4129 // addr 4130 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4131 return MCDisassembler::Fail; 4132 4133 return S; 4134 } 4135 4136 static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn, 4137 uint64_t Address, const void *Decoder) { 4138 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1); 4139 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1); 4140 if (sign1 != sign2) return MCDisassembler::Fail; 4141 4142 unsigned Val = fieldFromInstruction32(Insn, 0, 8); 4143 Val |= fieldFromInstruction32(Insn, 12, 3) << 8; 4144 Val |= fieldFromInstruction32(Insn, 26, 1) << 11; 4145 Val |= sign1 << 12; 4146 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 4147 4148 return MCDisassembler::Success; 4149 } 4150 4151 static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, uint32_t Val, 4152 uint64_t Address, 4153 const void *Decoder) { 4154 DecodeStatus S = MCDisassembler::Success; 4155 4156 // Shift of "asr #32" is not allowed in Thumb2 mode. 4157 if (Val == 0x20) S = MCDisassembler::SoftFail; 4158 Inst.addOperand(MCOperand::CreateImm(Val)); 4159 return S; 4160 } 4161 4162 static DecodeStatus DecodeSwap(llvm::MCInst &Inst, unsigned Insn, 4163 uint64_t Address, const void *Decoder) { 4164 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4165 unsigned Rt2 = fieldFromInstruction32(Insn, 0, 4); 4166 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4167 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 4168 4169 if (pred == 0xF) 4170 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 4171 4172 DecodeStatus S = MCDisassembler::Success; 4173 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4174 return MCDisassembler::Fail; 4175 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4176 return MCDisassembler::Fail; 4177 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4178 return MCDisassembler::Fail; 4179 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4180 return MCDisassembler::Fail; 4181 4182 return S; 4183 } 4184 4185 static DecodeStatus DecodeVCVTD(llvm::MCInst &Inst, unsigned Insn, 4186 uint64_t Address, const void *Decoder) { 4187 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0); 4188 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4); 4189 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0); 4190 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4); 4191 unsigned imm = fieldFromInstruction32(Insn, 16, 6); 4192 unsigned cmode = fieldFromInstruction32(Insn, 8, 4); 4193 4194 DecodeStatus S = MCDisassembler::Success; 4195 4196 // VMOVv2f32 is ambiguous with these decodings. 4197 if (!(imm & 0x38) && cmode == 0xF) { 4198 Inst.setOpcode(ARM::VMOVv2f32); 4199 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4200 } 4201 4202 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4203 4204 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 4205 return MCDisassembler::Fail; 4206 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 4207 return MCDisassembler::Fail; 4208 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4209 4210 return S; 4211 } 4212 4213 static DecodeStatus DecodeVCVTQ(llvm::MCInst &Inst, unsigned Insn, 4214 uint64_t Address, const void *Decoder) { 4215 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0); 4216 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4); 4217 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0); 4218 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4); 4219 unsigned imm = fieldFromInstruction32(Insn, 16, 6); 4220 unsigned cmode = fieldFromInstruction32(Insn, 8, 4); 4221 4222 DecodeStatus S = MCDisassembler::Success; 4223 4224 // VMOVv4f32 is ambiguous with these decodings. 4225 if (!(imm & 0x38) && cmode == 0xF) { 4226 Inst.setOpcode(ARM::VMOVv4f32); 4227 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4228 } 4229 4230 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4231 4232 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 4233 return MCDisassembler::Fail; 4234 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 4235 return MCDisassembler::Fail; 4236 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4237 4238 return S; 4239 } 4240