1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "ARM.h" 13 #include "ARMSubtarget.h" 14 #include "MCTargetDesc/ARMAddressingModes.h" 15 #include "MCTargetDesc/ARMMCExpr.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "llvm/MC/EDInstInfo.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/MC/MCExpr.h" 21 #include "llvm/MC/MCContext.h" 22 #include "llvm/MC/MCDisassembler.h" 23 #include "llvm/Support/Debug.h" 24 #include "llvm/Support/MemoryObject.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/TargetRegistry.h" 27 #include "llvm/Support/raw_ostream.h" 28 29 using namespace llvm; 30 31 typedef MCDisassembler::DecodeStatus DecodeStatus; 32 33 namespace { 34 /// ARMDisassembler - ARM disassembler for all ARM platforms. 35 class ARMDisassembler : public MCDisassembler { 36 public: 37 /// Constructor - Initializes the disassembler. 38 /// 39 ARMDisassembler(const MCSubtargetInfo &STI) : 40 MCDisassembler(STI) { 41 } 42 43 ~ARMDisassembler() { 44 } 45 46 /// getInstruction - See MCDisassembler. 47 DecodeStatus getInstruction(MCInst &instr, 48 uint64_t &size, 49 const MemoryObject ®ion, 50 uint64_t address, 51 raw_ostream &vStream, 52 raw_ostream &cStream) const; 53 54 /// getEDInfo - See MCDisassembler. 55 EDInstInfo *getEDInfo() const; 56 private: 57 }; 58 59 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 60 class ThumbDisassembler : public MCDisassembler { 61 public: 62 /// Constructor - Initializes the disassembler. 63 /// 64 ThumbDisassembler(const MCSubtargetInfo &STI) : 65 MCDisassembler(STI) { 66 } 67 68 ~ThumbDisassembler() { 69 } 70 71 /// getInstruction - See MCDisassembler. 72 DecodeStatus getInstruction(MCInst &instr, 73 uint64_t &size, 74 const MemoryObject ®ion, 75 uint64_t address, 76 raw_ostream &vStream, 77 raw_ostream &cStream) const; 78 79 /// getEDInfo - See MCDisassembler. 80 EDInstInfo *getEDInfo() const; 81 private: 82 mutable std::vector<unsigned> ITBlock; 83 DecodeStatus AddThumbPredicate(MCInst&) const; 84 void UpdateThumbVFPPredicate(MCInst&) const; 85 }; 86 } 87 88 static bool Check(DecodeStatus &Out, DecodeStatus In) { 89 switch (In) { 90 case MCDisassembler::Success: 91 // Out stays the same. 92 return true; 93 case MCDisassembler::SoftFail: 94 Out = In; 95 return true; 96 case MCDisassembler::Fail: 97 Out = In; 98 return false; 99 } 100 return false; 101 } 102 103 104 // Forward declare these because the autogenerated code will reference them. 105 // Definitions are further down. 106 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 107 uint64_t Address, const void *Decoder); 108 static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, 109 unsigned RegNo, uint64_t Address, 110 const void *Decoder); 111 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 112 uint64_t Address, const void *Decoder); 113 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 114 uint64_t Address, const void *Decoder); 115 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 116 uint64_t Address, const void *Decoder); 117 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 118 uint64_t Address, const void *Decoder); 119 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 120 uint64_t Address, const void *Decoder); 121 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 122 uint64_t Address, const void *Decoder); 123 static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, 124 unsigned RegNo, 125 uint64_t Address, 126 const void *Decoder); 127 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 128 uint64_t Address, const void *Decoder); 129 130 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 131 uint64_t Address, const void *Decoder); 132 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 133 uint64_t Address, const void *Decoder); 134 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 135 uint64_t Address, const void *Decoder); 136 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 137 uint64_t Address, const void *Decoder); 138 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 139 uint64_t Address, const void *Decoder); 140 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 141 uint64_t Address, const void *Decoder); 142 143 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 144 uint64_t Address, const void *Decoder); 145 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 146 uint64_t Address, const void *Decoder); 147 static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, 148 unsigned Insn, 149 uint64_t Address, 150 const void *Decoder); 151 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 152 uint64_t Address, const void *Decoder); 153 static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn, 154 uint64_t Address, const void *Decoder); 155 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 156 uint64_t Address, const void *Decoder); 157 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 158 uint64_t Address, const void *Decoder); 159 160 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 161 unsigned Insn, 162 uint64_t Adddress, 163 const void *Decoder); 164 static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 165 uint64_t Address, const void *Decoder); 166 static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 167 uint64_t Address, const void *Decoder); 168 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 169 uint64_t Address, const void *Decoder); 170 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 171 uint64_t Address, const void *Decoder); 172 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 173 uint64_t Address, const void *Decoder); 174 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 175 uint64_t Address, const void *Decoder); 176 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 177 uint64_t Address, const void *Decoder); 178 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 179 uint64_t Address, const void *Decoder); 180 static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn, 181 uint64_t Address, const void *Decoder); 182 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 183 uint64_t Address, const void *Decoder); 184 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 185 uint64_t Address, const void *Decoder); 186 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 193 uint64_t Address, const void *Decoder); 194 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 195 uint64_t Address, const void *Decoder); 196 static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val, 197 uint64_t Address, const void *Decoder); 198 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 199 uint64_t Address, const void *Decoder); 200 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 201 uint64_t Address, const void *Decoder); 202 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 203 uint64_t Address, const void *Decoder); 204 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 205 uint64_t Address, const void *Decoder); 206 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 207 uint64_t Address, const void *Decoder); 208 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 209 uint64_t Address, const void *Decoder); 210 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 211 uint64_t Address, const void *Decoder); 212 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 213 uint64_t Address, const void *Decoder); 214 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 215 uint64_t Address, const void *Decoder); 216 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, 217 uint64_t Address, const void *Decoder); 218 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 219 uint64_t Address, const void *Decoder); 220 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 221 uint64_t Address, const void *Decoder); 222 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 223 uint64_t Address, const void *Decoder); 224 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 225 uint64_t Address, const void *Decoder); 226 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 227 uint64_t Address, const void *Decoder); 228 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 229 uint64_t Address, const void *Decoder); 230 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 231 uint64_t Address, const void *Decoder); 232 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 233 uint64_t Address, const void *Decoder); 234 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 235 uint64_t Address, const void *Decoder); 236 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 237 uint64_t Address, const void *Decoder); 238 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 239 uint64_t Address, const void *Decoder); 240 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 241 uint64_t Address, const void *Decoder); 242 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 243 uint64_t Address, const void *Decoder); 244 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 245 uint64_t Address, const void *Decoder); 246 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 247 uint64_t Address, const void *Decoder); 248 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeSwap(llvm::MCInst &Inst, unsigned Insn, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeVCVTD(llvm::MCInst &Inst, unsigned Insn, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeVCVTQ(llvm::MCInst &Inst, unsigned Insn, 255 uint64_t Address, const void *Decoder); 256 257 258 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 259 uint64_t Address, const void *Decoder); 260 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 261 uint64_t Address, const void *Decoder); 262 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 263 uint64_t Address, const void *Decoder); 264 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 265 uint64_t Address, const void *Decoder); 266 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 269 uint64_t Address, const void *Decoder); 270 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Val, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val, 309 uint64_t Address, const void *Decoder); 310 static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, 311 uint64_t Address, const void *Decoder); 312 static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, 313 uint64_t Address, const void *Decoder); 314 static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val, 315 uint64_t Address, const void *Decoder); 316 static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val, 317 uint64_t Address, const void *Decoder); 318 static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, unsigned Val, 319 uint64_t Address, const void *Decoder); 320 321 322 323 #include "ARMGenDisassemblerTables.inc" 324 #include "ARMGenInstrInfo.inc" 325 #include "ARMGenEDInfo.inc" 326 327 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 328 return new ARMDisassembler(STI); 329 } 330 331 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 332 return new ThumbDisassembler(STI); 333 } 334 335 EDInstInfo *ARMDisassembler::getEDInfo() const { 336 return instInfoARM; 337 } 338 339 EDInstInfo *ThumbDisassembler::getEDInfo() const { 340 return instInfoARM; 341 } 342 343 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 344 const MemoryObject &Region, 345 uint64_t Address, 346 raw_ostream &os, 347 raw_ostream &cs) const { 348 CommentStream = &cs; 349 350 uint8_t bytes[4]; 351 352 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 353 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 354 355 // We want to read exactly 4 bytes of data. 356 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 357 Size = 0; 358 return MCDisassembler::Fail; 359 } 360 361 // Encoded as a small-endian 32-bit word in the stream. 362 uint32_t insn = (bytes[3] << 24) | 363 (bytes[2] << 16) | 364 (bytes[1] << 8) | 365 (bytes[0] << 0); 366 367 // Calling the auto-generated decoder function. 368 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI); 369 if (result != MCDisassembler::Fail) { 370 Size = 4; 371 return result; 372 } 373 374 // VFP and NEON instructions, similarly, are shared between ARM 375 // and Thumb modes. 376 MI.clear(); 377 result = decodeVFPInstruction32(MI, insn, Address, this, STI); 378 if (result != MCDisassembler::Fail) { 379 Size = 4; 380 return result; 381 } 382 383 MI.clear(); 384 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI); 385 if (result != MCDisassembler::Fail) { 386 Size = 4; 387 // Add a fake predicate operand, because we share these instruction 388 // definitions with Thumb2 where these instructions are predicable. 389 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 390 return MCDisassembler::Fail; 391 return result; 392 } 393 394 MI.clear(); 395 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI); 396 if (result != MCDisassembler::Fail) { 397 Size = 4; 398 // Add a fake predicate operand, because we share these instruction 399 // definitions with Thumb2 where these instructions are predicable. 400 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 401 return MCDisassembler::Fail; 402 return result; 403 } 404 405 MI.clear(); 406 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI); 407 if (result != MCDisassembler::Fail) { 408 Size = 4; 409 // Add a fake predicate operand, because we share these instruction 410 // definitions with Thumb2 where these instructions are predicable. 411 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 412 return MCDisassembler::Fail; 413 return result; 414 } 415 416 MI.clear(); 417 418 Size = 0; 419 return MCDisassembler::Fail; 420 } 421 422 namespace llvm { 423 extern const MCInstrDesc ARMInsts[]; 424 } 425 426 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 427 /// immediate Value in the MCInst. The immediate Value has had any PC 428 /// adjustment made by the caller. If the instruction is a branch instruction 429 /// then isBranch is true, else false. If the getOpInfo() function was set as 430 /// part of the setupForSymbolicDisassembly() call then that function is called 431 /// to get any symbolic information at the Address for this instruction. If 432 /// that returns non-zero then the symbolic information it returns is used to 433 /// create an MCExpr and that is added as an operand to the MCInst. If 434 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 435 /// Value is done and if a symbol is found an MCExpr is created with that, else 436 /// an MCExpr with Value is created. This function returns true if it adds an 437 /// operand to the MCInst and false otherwise. 438 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 439 bool isBranch, uint64_t InstSize, 440 MCInst &MI, const void *Decoder) { 441 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 442 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback(); 443 if (!getOpInfo) 444 return false; 445 446 struct LLVMOpInfo1 SymbolicOp; 447 SymbolicOp.Value = Value; 448 void *DisInfo = Dis->getDisInfoBlock(); 449 if (!getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) { 450 if (isBranch) { 451 LLVMSymbolLookupCallback SymbolLookUp = 452 Dis->getLLVMSymbolLookupCallback(); 453 if (SymbolLookUp) { 454 uint64_t ReferenceType; 455 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch; 456 const char *ReferenceName; 457 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address, 458 &ReferenceName); 459 if (Name) { 460 SymbolicOp.AddSymbol.Name = Name; 461 SymbolicOp.AddSymbol.Present = true; 462 SymbolicOp.Value = 0; 463 } 464 else { 465 SymbolicOp.Value = Value; 466 } 467 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub) 468 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName; 469 } 470 else { 471 return false; 472 } 473 } 474 else { 475 return false; 476 } 477 } 478 479 MCContext *Ctx = Dis->getMCContext(); 480 const MCExpr *Add = NULL; 481 if (SymbolicOp.AddSymbol.Present) { 482 if (SymbolicOp.AddSymbol.Name) { 483 StringRef Name(SymbolicOp.AddSymbol.Name); 484 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 485 Add = MCSymbolRefExpr::Create(Sym, *Ctx); 486 } else { 487 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx); 488 } 489 } 490 491 const MCExpr *Sub = NULL; 492 if (SymbolicOp.SubtractSymbol.Present) { 493 if (SymbolicOp.SubtractSymbol.Name) { 494 StringRef Name(SymbolicOp.SubtractSymbol.Name); 495 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 496 Sub = MCSymbolRefExpr::Create(Sym, *Ctx); 497 } else { 498 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx); 499 } 500 } 501 502 const MCExpr *Off = NULL; 503 if (SymbolicOp.Value != 0) 504 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx); 505 506 const MCExpr *Expr; 507 if (Sub) { 508 const MCExpr *LHS; 509 if (Add) 510 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx); 511 else 512 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx); 513 if (Off != 0) 514 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx); 515 else 516 Expr = LHS; 517 } else if (Add) { 518 if (Off != 0) 519 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx); 520 else 521 Expr = Add; 522 } else { 523 if (Off != 0) 524 Expr = Off; 525 else 526 Expr = MCConstantExpr::Create(0, *Ctx); 527 } 528 529 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16) 530 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx))); 531 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16) 532 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx))); 533 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None) 534 MI.addOperand(MCOperand::CreateExpr(Expr)); 535 else 536 assert(0 && "bad SymbolicOp.VariantKind"); 537 538 return true; 539 } 540 541 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 542 /// referenced by a load instruction with the base register that is the Pc. 543 /// These can often be values in a literal pool near the Address of the 544 /// instruction. The Address of the instruction and its immediate Value are 545 /// used as a possible literal pool entry. The SymbolLookUp call back will 546 /// return the name of a symbol referenced by the the literal pool's entry if 547 /// the referenced address is that of a symbol. Or it will return a pointer to 548 /// a literal 'C' string if the referenced address of the literal pool's entry 549 /// is an address into a section with 'C' string literals. 550 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 551 const void *Decoder) { 552 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 553 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 554 if (SymbolLookUp) { 555 void *DisInfo = Dis->getDisInfoBlock(); 556 uint64_t ReferenceType; 557 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load; 558 const char *ReferenceName; 559 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName); 560 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr || 561 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr) 562 (*Dis->CommentStream) << "literal pool for: " << ReferenceName; 563 } 564 } 565 566 // Thumb1 instructions don't have explicit S bits. Rather, they 567 // implicitly set CPSR. Since it's not represented in the encoding, the 568 // auto-generated decoder won't inject the CPSR operand. We need to fix 569 // that as a post-pass. 570 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 571 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 572 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 573 MCInst::iterator I = MI.begin(); 574 for (unsigned i = 0; i < NumOps; ++i, ++I) { 575 if (I == MI.end()) break; 576 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 577 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 578 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 579 return; 580 } 581 } 582 583 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 584 } 585 586 // Most Thumb instructions don't have explicit predicates in the 587 // encoding, but rather get their predicates from IT context. We need 588 // to fix up the predicate operands using this context information as a 589 // post-pass. 590 MCDisassembler::DecodeStatus 591 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 592 MCDisassembler::DecodeStatus S = Success; 593 594 // A few instructions actually have predicates encoded in them. Don't 595 // try to overwrite it if we're seeing one of those. 596 switch (MI.getOpcode()) { 597 case ARM::tBcc: 598 case ARM::t2Bcc: 599 case ARM::tCBZ: 600 case ARM::tCBNZ: 601 case ARM::tCPS: 602 case ARM::t2CPS3p: 603 case ARM::t2CPS2p: 604 case ARM::t2CPS1p: 605 case ARM::tMOVSr: 606 case ARM::tSETEND: 607 // Some instructions (mostly conditional branches) are not 608 // allowed in IT blocks. 609 if (!ITBlock.empty()) 610 S = SoftFail; 611 else 612 return Success; 613 break; 614 case ARM::tB: 615 case ARM::t2B: 616 case ARM::t2TBB: 617 case ARM::t2TBH: 618 // Some instructions (mostly unconditional branches) can 619 // only appears at the end of, or outside of, an IT. 620 if (ITBlock.size() > 1) 621 S = SoftFail; 622 break; 623 default: 624 break; 625 } 626 627 // If we're in an IT block, base the predicate on that. Otherwise, 628 // assume a predicate of AL. 629 unsigned CC; 630 if (!ITBlock.empty()) { 631 CC = ITBlock.back(); 632 if (CC == 0xF) 633 CC = ARMCC::AL; 634 ITBlock.pop_back(); 635 } else 636 CC = ARMCC::AL; 637 638 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 639 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 640 MCInst::iterator I = MI.begin(); 641 for (unsigned i = 0; i < NumOps; ++i, ++I) { 642 if (I == MI.end()) break; 643 if (OpInfo[i].isPredicate()) { 644 I = MI.insert(I, MCOperand::CreateImm(CC)); 645 ++I; 646 if (CC == ARMCC::AL) 647 MI.insert(I, MCOperand::CreateReg(0)); 648 else 649 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 650 return S; 651 } 652 } 653 654 I = MI.insert(I, MCOperand::CreateImm(CC)); 655 ++I; 656 if (CC == ARMCC::AL) 657 MI.insert(I, MCOperand::CreateReg(0)); 658 else 659 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 660 661 return S; 662 } 663 664 // Thumb VFP instructions are a special case. Because we share their 665 // encodings between ARM and Thumb modes, and they are predicable in ARM 666 // mode, the auto-generated decoder will give them an (incorrect) 667 // predicate operand. We need to rewrite these operands based on the IT 668 // context as a post-pass. 669 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 670 unsigned CC; 671 if (!ITBlock.empty()) { 672 CC = ITBlock.back(); 673 ITBlock.pop_back(); 674 } else 675 CC = ARMCC::AL; 676 677 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 678 MCInst::iterator I = MI.begin(); 679 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 680 for (unsigned i = 0; i < NumOps; ++i, ++I) { 681 if (OpInfo[i].isPredicate() ) { 682 I->setImm(CC); 683 ++I; 684 if (CC == ARMCC::AL) 685 I->setReg(0); 686 else 687 I->setReg(ARM::CPSR); 688 return; 689 } 690 } 691 } 692 693 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 694 const MemoryObject &Region, 695 uint64_t Address, 696 raw_ostream &os, 697 raw_ostream &cs) const { 698 CommentStream = &cs; 699 700 uint8_t bytes[4]; 701 702 assert((STI.getFeatureBits() & ARM::ModeThumb) && 703 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 704 705 // We want to read exactly 2 bytes of data. 706 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) { 707 Size = 0; 708 return MCDisassembler::Fail; 709 } 710 711 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 712 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI); 713 if (result != MCDisassembler::Fail) { 714 Size = 2; 715 Check(result, AddThumbPredicate(MI)); 716 return result; 717 } 718 719 MI.clear(); 720 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI); 721 if (result) { 722 Size = 2; 723 bool InITBlock = !ITBlock.empty(); 724 Check(result, AddThumbPredicate(MI)); 725 AddThumb1SBit(MI, InITBlock); 726 return result; 727 } 728 729 MI.clear(); 730 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI); 731 if (result != MCDisassembler::Fail) { 732 Size = 2; 733 734 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 735 // the Thumb predicate. 736 if (MI.getOpcode() == ARM::t2IT && !ITBlock.empty()) 737 result = MCDisassembler::SoftFail; 738 739 Check(result, AddThumbPredicate(MI)); 740 741 // If we find an IT instruction, we need to parse its condition 742 // code and mask operands so that we can apply them correctly 743 // to the subsequent instructions. 744 if (MI.getOpcode() == ARM::t2IT) { 745 746 // (3 - the number of trailing zeros) is the number of then / else. 747 unsigned firstcond = MI.getOperand(0).getImm(); 748 unsigned Mask = MI.getOperand(1).getImm(); 749 unsigned CondBit0 = Mask >> 4 & 1; 750 unsigned NumTZ = CountTrailingZeros_32(Mask); 751 assert(NumTZ <= 3 && "Invalid IT mask!"); 752 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) { 753 bool T = ((Mask >> Pos) & 1) == CondBit0; 754 if (T) 755 ITBlock.insert(ITBlock.begin(), firstcond); 756 else 757 ITBlock.insert(ITBlock.begin(), firstcond ^ 1); 758 } 759 760 ITBlock.push_back(firstcond); 761 } 762 763 return result; 764 } 765 766 // We want to read exactly 4 bytes of data. 767 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 768 Size = 0; 769 return MCDisassembler::Fail; 770 } 771 772 uint32_t insn32 = (bytes[3] << 8) | 773 (bytes[2] << 0) | 774 (bytes[1] << 24) | 775 (bytes[0] << 16); 776 MI.clear(); 777 result = decodeThumbInstruction32(MI, insn32, Address, this, STI); 778 if (result != MCDisassembler::Fail) { 779 Size = 4; 780 bool InITBlock = ITBlock.size(); 781 Check(result, AddThumbPredicate(MI)); 782 AddThumb1SBit(MI, InITBlock); 783 return result; 784 } 785 786 MI.clear(); 787 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI); 788 if (result != MCDisassembler::Fail) { 789 Size = 4; 790 Check(result, AddThumbPredicate(MI)); 791 return result; 792 } 793 794 MI.clear(); 795 result = decodeVFPInstruction32(MI, insn32, Address, this, STI); 796 if (result != MCDisassembler::Fail) { 797 Size = 4; 798 UpdateThumbVFPPredicate(MI); 799 return result; 800 } 801 802 MI.clear(); 803 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI); 804 if (result != MCDisassembler::Fail) { 805 Size = 4; 806 Check(result, AddThumbPredicate(MI)); 807 return result; 808 } 809 810 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { 811 MI.clear(); 812 uint32_t NEONLdStInsn = insn32; 813 NEONLdStInsn &= 0xF0FFFFFF; 814 NEONLdStInsn |= 0x04000000; 815 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI); 816 if (result != MCDisassembler::Fail) { 817 Size = 4; 818 Check(result, AddThumbPredicate(MI)); 819 return result; 820 } 821 } 822 823 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 824 MI.clear(); 825 uint32_t NEONDataInsn = insn32; 826 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 827 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 828 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 829 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI); 830 if (result != MCDisassembler::Fail) { 831 Size = 4; 832 Check(result, AddThumbPredicate(MI)); 833 return result; 834 } 835 } 836 837 Size = 0; 838 return MCDisassembler::Fail; 839 } 840 841 842 extern "C" void LLVMInitializeARMDisassembler() { 843 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 844 createARMDisassembler); 845 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 846 createThumbDisassembler); 847 } 848 849 static const unsigned GPRDecoderTable[] = { 850 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 851 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 852 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 853 ARM::R12, ARM::SP, ARM::LR, ARM::PC 854 }; 855 856 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 857 uint64_t Address, const void *Decoder) { 858 if (RegNo > 15) 859 return MCDisassembler::Fail; 860 861 unsigned Register = GPRDecoderTable[RegNo]; 862 Inst.addOperand(MCOperand::CreateReg(Register)); 863 return MCDisassembler::Success; 864 } 865 866 static DecodeStatus 867 DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 868 uint64_t Address, const void *Decoder) { 869 if (RegNo == 15) return MCDisassembler::Fail; 870 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 871 } 872 873 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 874 uint64_t Address, const void *Decoder) { 875 if (RegNo > 7) 876 return MCDisassembler::Fail; 877 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 878 } 879 880 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 881 uint64_t Address, const void *Decoder) { 882 unsigned Register = 0; 883 switch (RegNo) { 884 case 0: 885 Register = ARM::R0; 886 break; 887 case 1: 888 Register = ARM::R1; 889 break; 890 case 2: 891 Register = ARM::R2; 892 break; 893 case 3: 894 Register = ARM::R3; 895 break; 896 case 9: 897 Register = ARM::R9; 898 break; 899 case 12: 900 Register = ARM::R12; 901 break; 902 default: 903 return MCDisassembler::Fail; 904 } 905 906 Inst.addOperand(MCOperand::CreateReg(Register)); 907 return MCDisassembler::Success; 908 } 909 910 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 911 uint64_t Address, const void *Decoder) { 912 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 913 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 914 } 915 916 static const unsigned SPRDecoderTable[] = { 917 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 918 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 919 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 920 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 921 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 922 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 923 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 924 ARM::S28, ARM::S29, ARM::S30, ARM::S31 925 }; 926 927 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 928 uint64_t Address, const void *Decoder) { 929 if (RegNo > 31) 930 return MCDisassembler::Fail; 931 932 unsigned Register = SPRDecoderTable[RegNo]; 933 Inst.addOperand(MCOperand::CreateReg(Register)); 934 return MCDisassembler::Success; 935 } 936 937 static const unsigned DPRDecoderTable[] = { 938 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 939 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 940 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 941 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 942 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 943 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 944 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 945 ARM::D28, ARM::D29, ARM::D30, ARM::D31 946 }; 947 948 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 949 uint64_t Address, const void *Decoder) { 950 if (RegNo > 31) 951 return MCDisassembler::Fail; 952 953 unsigned Register = DPRDecoderTable[RegNo]; 954 Inst.addOperand(MCOperand::CreateReg(Register)); 955 return MCDisassembler::Success; 956 } 957 958 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 959 uint64_t Address, const void *Decoder) { 960 if (RegNo > 7) 961 return MCDisassembler::Fail; 962 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 963 } 964 965 static DecodeStatus 966 DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 967 uint64_t Address, const void *Decoder) { 968 if (RegNo > 15) 969 return MCDisassembler::Fail; 970 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 971 } 972 973 static const unsigned QPRDecoderTable[] = { 974 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 975 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 976 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 977 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 978 }; 979 980 981 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 982 uint64_t Address, const void *Decoder) { 983 if (RegNo > 31) 984 return MCDisassembler::Fail; 985 RegNo >>= 1; 986 987 unsigned Register = QPRDecoderTable[RegNo]; 988 Inst.addOperand(MCOperand::CreateReg(Register)); 989 return MCDisassembler::Success; 990 } 991 992 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 993 uint64_t Address, const void *Decoder) { 994 if (Val == 0xF) return MCDisassembler::Fail; 995 // AL predicate is not allowed on Thumb1 branches. 996 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 997 return MCDisassembler::Fail; 998 Inst.addOperand(MCOperand::CreateImm(Val)); 999 if (Val == ARMCC::AL) { 1000 Inst.addOperand(MCOperand::CreateReg(0)); 1001 } else 1002 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1003 return MCDisassembler::Success; 1004 } 1005 1006 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 1007 uint64_t Address, const void *Decoder) { 1008 if (Val) 1009 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1010 else 1011 Inst.addOperand(MCOperand::CreateReg(0)); 1012 return MCDisassembler::Success; 1013 } 1014 1015 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 1016 uint64_t Address, const void *Decoder) { 1017 uint32_t imm = Val & 0xFF; 1018 uint32_t rot = (Val & 0xF00) >> 7; 1019 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 1020 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 1021 return MCDisassembler::Success; 1022 } 1023 1024 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 1025 uint64_t Address, const void *Decoder) { 1026 DecodeStatus S = MCDisassembler::Success; 1027 1028 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1029 unsigned type = fieldFromInstruction32(Val, 5, 2); 1030 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1031 1032 // Register-immediate 1033 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1034 return MCDisassembler::Fail; 1035 1036 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1037 switch (type) { 1038 case 0: 1039 Shift = ARM_AM::lsl; 1040 break; 1041 case 1: 1042 Shift = ARM_AM::lsr; 1043 break; 1044 case 2: 1045 Shift = ARM_AM::asr; 1046 break; 1047 case 3: 1048 Shift = ARM_AM::ror; 1049 break; 1050 } 1051 1052 if (Shift == ARM_AM::ror && imm == 0) 1053 Shift = ARM_AM::rrx; 1054 1055 unsigned Op = Shift | (imm << 3); 1056 Inst.addOperand(MCOperand::CreateImm(Op)); 1057 1058 return S; 1059 } 1060 1061 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 1062 uint64_t Address, const void *Decoder) { 1063 DecodeStatus S = MCDisassembler::Success; 1064 1065 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1066 unsigned type = fieldFromInstruction32(Val, 5, 2); 1067 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 1068 1069 // Register-register 1070 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1071 return MCDisassembler::Fail; 1072 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1073 return MCDisassembler::Fail; 1074 1075 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1076 switch (type) { 1077 case 0: 1078 Shift = ARM_AM::lsl; 1079 break; 1080 case 1: 1081 Shift = ARM_AM::lsr; 1082 break; 1083 case 2: 1084 Shift = ARM_AM::asr; 1085 break; 1086 case 3: 1087 Shift = ARM_AM::ror; 1088 break; 1089 } 1090 1091 Inst.addOperand(MCOperand::CreateImm(Shift)); 1092 1093 return S; 1094 } 1095 1096 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 1097 uint64_t Address, const void *Decoder) { 1098 DecodeStatus S = MCDisassembler::Success; 1099 1100 bool writebackLoad = false; 1101 unsigned writebackReg = 0; 1102 switch (Inst.getOpcode()) { 1103 default: 1104 break; 1105 case ARM::LDMIA_UPD: 1106 case ARM::LDMDB_UPD: 1107 case ARM::LDMIB_UPD: 1108 case ARM::LDMDA_UPD: 1109 case ARM::t2LDMIA_UPD: 1110 case ARM::t2LDMDB_UPD: 1111 writebackLoad = true; 1112 writebackReg = Inst.getOperand(0).getReg(); 1113 break; 1114 } 1115 1116 // Empty register lists are not allowed. 1117 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail; 1118 for (unsigned i = 0; i < 16; ++i) { 1119 if (Val & (1 << i)) { 1120 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1121 return MCDisassembler::Fail; 1122 // Writeback not allowed if Rn is in the target list. 1123 if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) 1124 Check(S, MCDisassembler::SoftFail); 1125 } 1126 } 1127 1128 return S; 1129 } 1130 1131 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 1132 uint64_t Address, const void *Decoder) { 1133 DecodeStatus S = MCDisassembler::Success; 1134 1135 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 1136 unsigned regs = Val & 0xFF; 1137 1138 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1139 return MCDisassembler::Fail; 1140 for (unsigned i = 0; i < (regs - 1); ++i) { 1141 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1142 return MCDisassembler::Fail; 1143 } 1144 1145 return S; 1146 } 1147 1148 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 1149 uint64_t Address, const void *Decoder) { 1150 DecodeStatus S = MCDisassembler::Success; 1151 1152 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 1153 unsigned regs = (Val & 0xFF) / 2; 1154 1155 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1156 return MCDisassembler::Fail; 1157 for (unsigned i = 0; i < (regs - 1); ++i) { 1158 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1159 return MCDisassembler::Fail; 1160 } 1161 1162 return S; 1163 } 1164 1165 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 1166 uint64_t Address, const void *Decoder) { 1167 // This operand encodes a mask of contiguous zeros between a specified MSB 1168 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1169 // the mask of all bits LSB-and-lower, and then xor them to create 1170 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1171 // create the final mask. 1172 unsigned msb = fieldFromInstruction32(Val, 5, 5); 1173 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 1174 1175 DecodeStatus S = MCDisassembler::Success; 1176 if (lsb > msb) Check(S, MCDisassembler::SoftFail); 1177 1178 uint32_t msb_mask = 0xFFFFFFFF; 1179 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1180 uint32_t lsb_mask = (1U << lsb) - 1; 1181 1182 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1183 return S; 1184 } 1185 1186 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 1187 uint64_t Address, const void *Decoder) { 1188 DecodeStatus S = MCDisassembler::Success; 1189 1190 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1191 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 1192 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 1193 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 1194 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1195 unsigned U = fieldFromInstruction32(Insn, 23, 1); 1196 1197 switch (Inst.getOpcode()) { 1198 case ARM::LDC_OFFSET: 1199 case ARM::LDC_PRE: 1200 case ARM::LDC_POST: 1201 case ARM::LDC_OPTION: 1202 case ARM::LDCL_OFFSET: 1203 case ARM::LDCL_PRE: 1204 case ARM::LDCL_POST: 1205 case ARM::LDCL_OPTION: 1206 case ARM::STC_OFFSET: 1207 case ARM::STC_PRE: 1208 case ARM::STC_POST: 1209 case ARM::STC_OPTION: 1210 case ARM::STCL_OFFSET: 1211 case ARM::STCL_PRE: 1212 case ARM::STCL_POST: 1213 case ARM::STCL_OPTION: 1214 case ARM::t2LDC_OFFSET: 1215 case ARM::t2LDC_PRE: 1216 case ARM::t2LDC_POST: 1217 case ARM::t2LDC_OPTION: 1218 case ARM::t2LDCL_OFFSET: 1219 case ARM::t2LDCL_PRE: 1220 case ARM::t2LDCL_POST: 1221 case ARM::t2LDCL_OPTION: 1222 case ARM::t2STC_OFFSET: 1223 case ARM::t2STC_PRE: 1224 case ARM::t2STC_POST: 1225 case ARM::t2STC_OPTION: 1226 case ARM::t2STCL_OFFSET: 1227 case ARM::t2STCL_PRE: 1228 case ARM::t2STCL_POST: 1229 case ARM::t2STCL_OPTION: 1230 if (coproc == 0xA || coproc == 0xB) 1231 return MCDisassembler::Fail; 1232 break; 1233 default: 1234 break; 1235 } 1236 1237 Inst.addOperand(MCOperand::CreateImm(coproc)); 1238 Inst.addOperand(MCOperand::CreateImm(CRd)); 1239 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1240 return MCDisassembler::Fail; 1241 1242 switch (Inst.getOpcode()) { 1243 case ARM::t2LDC2_OFFSET: 1244 case ARM::t2LDC2L_OFFSET: 1245 case ARM::t2LDC2_PRE: 1246 case ARM::t2LDC2L_PRE: 1247 case ARM::t2STC2_OFFSET: 1248 case ARM::t2STC2L_OFFSET: 1249 case ARM::t2STC2_PRE: 1250 case ARM::t2STC2L_PRE: 1251 case ARM::LDC2_OFFSET: 1252 case ARM::LDC2L_OFFSET: 1253 case ARM::LDC2_PRE: 1254 case ARM::LDC2L_PRE: 1255 case ARM::STC2_OFFSET: 1256 case ARM::STC2L_OFFSET: 1257 case ARM::STC2_PRE: 1258 case ARM::STC2L_PRE: 1259 case ARM::t2LDC_OFFSET: 1260 case ARM::t2LDCL_OFFSET: 1261 case ARM::t2LDC_PRE: 1262 case ARM::t2LDCL_PRE: 1263 case ARM::t2STC_OFFSET: 1264 case ARM::t2STCL_OFFSET: 1265 case ARM::t2STC_PRE: 1266 case ARM::t2STCL_PRE: 1267 case ARM::LDC_OFFSET: 1268 case ARM::LDCL_OFFSET: 1269 case ARM::LDC_PRE: 1270 case ARM::LDCL_PRE: 1271 case ARM::STC_OFFSET: 1272 case ARM::STCL_OFFSET: 1273 case ARM::STC_PRE: 1274 case ARM::STCL_PRE: 1275 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1276 Inst.addOperand(MCOperand::CreateImm(imm)); 1277 break; 1278 case ARM::t2LDC2_POST: 1279 case ARM::t2LDC2L_POST: 1280 case ARM::t2STC2_POST: 1281 case ARM::t2STC2L_POST: 1282 case ARM::LDC2_POST: 1283 case ARM::LDC2L_POST: 1284 case ARM::STC2_POST: 1285 case ARM::STC2L_POST: 1286 case ARM::t2LDC_POST: 1287 case ARM::t2LDCL_POST: 1288 case ARM::t2STC_POST: 1289 case ARM::t2STCL_POST: 1290 case ARM::LDC_POST: 1291 case ARM::LDCL_POST: 1292 case ARM::STC_POST: 1293 case ARM::STCL_POST: 1294 imm |= U << 8; 1295 // fall through. 1296 default: 1297 // The 'option' variant doesn't encode 'U' in the immediate since 1298 // the immediate is unsigned [0,255]. 1299 Inst.addOperand(MCOperand::CreateImm(imm)); 1300 break; 1301 } 1302 1303 switch (Inst.getOpcode()) { 1304 case ARM::LDC_OFFSET: 1305 case ARM::LDC_PRE: 1306 case ARM::LDC_POST: 1307 case ARM::LDC_OPTION: 1308 case ARM::LDCL_OFFSET: 1309 case ARM::LDCL_PRE: 1310 case ARM::LDCL_POST: 1311 case ARM::LDCL_OPTION: 1312 case ARM::STC_OFFSET: 1313 case ARM::STC_PRE: 1314 case ARM::STC_POST: 1315 case ARM::STC_OPTION: 1316 case ARM::STCL_OFFSET: 1317 case ARM::STCL_PRE: 1318 case ARM::STCL_POST: 1319 case ARM::STCL_OPTION: 1320 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1321 return MCDisassembler::Fail; 1322 break; 1323 default: 1324 break; 1325 } 1326 1327 return S; 1328 } 1329 1330 static DecodeStatus 1331 DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 1332 uint64_t Address, const void *Decoder) { 1333 DecodeStatus S = MCDisassembler::Success; 1334 1335 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1336 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1337 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1338 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 1339 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1340 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 1341 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1342 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1343 1344 // On stores, the writeback operand precedes Rt. 1345 switch (Inst.getOpcode()) { 1346 case ARM::STR_POST_IMM: 1347 case ARM::STR_POST_REG: 1348 case ARM::STRB_POST_IMM: 1349 case ARM::STRB_POST_REG: 1350 case ARM::STRT_POST_REG: 1351 case ARM::STRT_POST_IMM: 1352 case ARM::STRBT_POST_REG: 1353 case ARM::STRBT_POST_IMM: 1354 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1355 return MCDisassembler::Fail; 1356 break; 1357 default: 1358 break; 1359 } 1360 1361 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1362 return MCDisassembler::Fail; 1363 1364 // On loads, the writeback operand comes after Rt. 1365 switch (Inst.getOpcode()) { 1366 case ARM::LDR_POST_IMM: 1367 case ARM::LDR_POST_REG: 1368 case ARM::LDRB_POST_IMM: 1369 case ARM::LDRB_POST_REG: 1370 case ARM::LDRBT_POST_REG: 1371 case ARM::LDRBT_POST_IMM: 1372 case ARM::LDRT_POST_REG: 1373 case ARM::LDRT_POST_IMM: 1374 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1375 return MCDisassembler::Fail; 1376 break; 1377 default: 1378 break; 1379 } 1380 1381 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1382 return MCDisassembler::Fail; 1383 1384 ARM_AM::AddrOpc Op = ARM_AM::add; 1385 if (!fieldFromInstruction32(Insn, 23, 1)) 1386 Op = ARM_AM::sub; 1387 1388 bool writeback = (P == 0) || (W == 1); 1389 unsigned idx_mode = 0; 1390 if (P && writeback) 1391 idx_mode = ARMII::IndexModePre; 1392 else if (!P && writeback) 1393 idx_mode = ARMII::IndexModePost; 1394 1395 if (writeback && (Rn == 15 || Rn == Rt)) 1396 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1397 1398 if (reg) { 1399 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1400 return MCDisassembler::Fail; 1401 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1402 switch( fieldFromInstruction32(Insn, 5, 2)) { 1403 case 0: 1404 Opc = ARM_AM::lsl; 1405 break; 1406 case 1: 1407 Opc = ARM_AM::lsr; 1408 break; 1409 case 2: 1410 Opc = ARM_AM::asr; 1411 break; 1412 case 3: 1413 Opc = ARM_AM::ror; 1414 break; 1415 default: 1416 return MCDisassembler::Fail; 1417 } 1418 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1419 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1420 1421 Inst.addOperand(MCOperand::CreateImm(imm)); 1422 } else { 1423 Inst.addOperand(MCOperand::CreateReg(0)); 1424 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1425 Inst.addOperand(MCOperand::CreateImm(tmp)); 1426 } 1427 1428 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1429 return MCDisassembler::Fail; 1430 1431 return S; 1432 } 1433 1434 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1435 uint64_t Address, const void *Decoder) { 1436 DecodeStatus S = MCDisassembler::Success; 1437 1438 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1439 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1440 unsigned type = fieldFromInstruction32(Val, 5, 2); 1441 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1442 unsigned U = fieldFromInstruction32(Val, 12, 1); 1443 1444 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1445 switch (type) { 1446 case 0: 1447 ShOp = ARM_AM::lsl; 1448 break; 1449 case 1: 1450 ShOp = ARM_AM::lsr; 1451 break; 1452 case 2: 1453 ShOp = ARM_AM::asr; 1454 break; 1455 case 3: 1456 ShOp = ARM_AM::ror; 1457 break; 1458 } 1459 1460 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1461 return MCDisassembler::Fail; 1462 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1463 return MCDisassembler::Fail; 1464 unsigned shift; 1465 if (U) 1466 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1467 else 1468 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1469 Inst.addOperand(MCOperand::CreateImm(shift)); 1470 1471 return S; 1472 } 1473 1474 static DecodeStatus 1475 DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1476 uint64_t Address, const void *Decoder) { 1477 DecodeStatus S = MCDisassembler::Success; 1478 1479 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1480 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1481 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1482 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1483 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1484 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1485 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1486 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1487 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1488 1489 bool writeback = (W == 1) | (P == 0); 1490 1491 // For {LD,ST}RD, Rt must be even, else undefined. 1492 switch (Inst.getOpcode()) { 1493 case ARM::STRD: 1494 case ARM::STRD_PRE: 1495 case ARM::STRD_POST: 1496 case ARM::LDRD: 1497 case ARM::LDRD_PRE: 1498 case ARM::LDRD_POST: 1499 if (Rt & 0x1) return MCDisassembler::Fail; 1500 break; 1501 default: 1502 break; 1503 } 1504 1505 if (writeback) { // Writeback 1506 if (P) 1507 U |= ARMII::IndexModePre << 9; 1508 else 1509 U |= ARMII::IndexModePost << 9; 1510 1511 // On stores, the writeback operand precedes Rt. 1512 switch (Inst.getOpcode()) { 1513 case ARM::STRD: 1514 case ARM::STRD_PRE: 1515 case ARM::STRD_POST: 1516 case ARM::STRH: 1517 case ARM::STRH_PRE: 1518 case ARM::STRH_POST: 1519 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1520 return MCDisassembler::Fail; 1521 break; 1522 default: 1523 break; 1524 } 1525 } 1526 1527 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1528 return MCDisassembler::Fail; 1529 switch (Inst.getOpcode()) { 1530 case ARM::STRD: 1531 case ARM::STRD_PRE: 1532 case ARM::STRD_POST: 1533 case ARM::LDRD: 1534 case ARM::LDRD_PRE: 1535 case ARM::LDRD_POST: 1536 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1537 return MCDisassembler::Fail; 1538 break; 1539 default: 1540 break; 1541 } 1542 1543 if (writeback) { 1544 // On loads, the writeback operand comes after Rt. 1545 switch (Inst.getOpcode()) { 1546 case ARM::LDRD: 1547 case ARM::LDRD_PRE: 1548 case ARM::LDRD_POST: 1549 case ARM::LDRH: 1550 case ARM::LDRH_PRE: 1551 case ARM::LDRH_POST: 1552 case ARM::LDRSH: 1553 case ARM::LDRSH_PRE: 1554 case ARM::LDRSH_POST: 1555 case ARM::LDRSB: 1556 case ARM::LDRSB_PRE: 1557 case ARM::LDRSB_POST: 1558 case ARM::LDRHTr: 1559 case ARM::LDRSBTr: 1560 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1561 return MCDisassembler::Fail; 1562 break; 1563 default: 1564 break; 1565 } 1566 } 1567 1568 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1569 return MCDisassembler::Fail; 1570 1571 if (type) { 1572 Inst.addOperand(MCOperand::CreateReg(0)); 1573 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1574 } else { 1575 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1576 return MCDisassembler::Fail; 1577 Inst.addOperand(MCOperand::CreateImm(U)); 1578 } 1579 1580 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1581 return MCDisassembler::Fail; 1582 1583 return S; 1584 } 1585 1586 static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1587 uint64_t Address, const void *Decoder) { 1588 DecodeStatus S = MCDisassembler::Success; 1589 1590 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1591 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1592 1593 switch (mode) { 1594 case 0: 1595 mode = ARM_AM::da; 1596 break; 1597 case 1: 1598 mode = ARM_AM::ia; 1599 break; 1600 case 2: 1601 mode = ARM_AM::db; 1602 break; 1603 case 3: 1604 mode = ARM_AM::ib; 1605 break; 1606 } 1607 1608 Inst.addOperand(MCOperand::CreateImm(mode)); 1609 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1610 return MCDisassembler::Fail; 1611 1612 return S; 1613 } 1614 1615 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1616 unsigned Insn, 1617 uint64_t Address, const void *Decoder) { 1618 DecodeStatus S = MCDisassembler::Success; 1619 1620 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1621 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1622 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1623 1624 if (pred == 0xF) { 1625 switch (Inst.getOpcode()) { 1626 case ARM::LDMDA: 1627 Inst.setOpcode(ARM::RFEDA); 1628 break; 1629 case ARM::LDMDA_UPD: 1630 Inst.setOpcode(ARM::RFEDA_UPD); 1631 break; 1632 case ARM::LDMDB: 1633 Inst.setOpcode(ARM::RFEDB); 1634 break; 1635 case ARM::LDMDB_UPD: 1636 Inst.setOpcode(ARM::RFEDB_UPD); 1637 break; 1638 case ARM::LDMIA: 1639 Inst.setOpcode(ARM::RFEIA); 1640 break; 1641 case ARM::LDMIA_UPD: 1642 Inst.setOpcode(ARM::RFEIA_UPD); 1643 break; 1644 case ARM::LDMIB: 1645 Inst.setOpcode(ARM::RFEIB); 1646 break; 1647 case ARM::LDMIB_UPD: 1648 Inst.setOpcode(ARM::RFEIB_UPD); 1649 break; 1650 case ARM::STMDA: 1651 Inst.setOpcode(ARM::SRSDA); 1652 break; 1653 case ARM::STMDA_UPD: 1654 Inst.setOpcode(ARM::SRSDA_UPD); 1655 break; 1656 case ARM::STMDB: 1657 Inst.setOpcode(ARM::SRSDB); 1658 break; 1659 case ARM::STMDB_UPD: 1660 Inst.setOpcode(ARM::SRSDB_UPD); 1661 break; 1662 case ARM::STMIA: 1663 Inst.setOpcode(ARM::SRSIA); 1664 break; 1665 case ARM::STMIA_UPD: 1666 Inst.setOpcode(ARM::SRSIA_UPD); 1667 break; 1668 case ARM::STMIB: 1669 Inst.setOpcode(ARM::SRSIB); 1670 break; 1671 case ARM::STMIB_UPD: 1672 Inst.setOpcode(ARM::SRSIB_UPD); 1673 break; 1674 default: 1675 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail; 1676 } 1677 1678 // For stores (which become SRS's, the only operand is the mode. 1679 if (fieldFromInstruction32(Insn, 20, 1) == 0) { 1680 Inst.addOperand( 1681 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4))); 1682 return S; 1683 } 1684 1685 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1686 } 1687 1688 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1689 return MCDisassembler::Fail; 1690 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1691 return MCDisassembler::Fail; // Tied 1692 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1693 return MCDisassembler::Fail; 1694 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1695 return MCDisassembler::Fail; 1696 1697 return S; 1698 } 1699 1700 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1701 uint64_t Address, const void *Decoder) { 1702 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1703 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1704 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1705 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1706 1707 DecodeStatus S = MCDisassembler::Success; 1708 1709 // imod == '01' --> UNPREDICTABLE 1710 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1711 // return failure here. The '01' imod value is unprintable, so there's 1712 // nothing useful we could do even if we returned UNPREDICTABLE. 1713 1714 if (imod == 1) return MCDisassembler::Fail; 1715 1716 if (imod && M) { 1717 Inst.setOpcode(ARM::CPS3p); 1718 Inst.addOperand(MCOperand::CreateImm(imod)); 1719 Inst.addOperand(MCOperand::CreateImm(iflags)); 1720 Inst.addOperand(MCOperand::CreateImm(mode)); 1721 } else if (imod && !M) { 1722 Inst.setOpcode(ARM::CPS2p); 1723 Inst.addOperand(MCOperand::CreateImm(imod)); 1724 Inst.addOperand(MCOperand::CreateImm(iflags)); 1725 if (mode) S = MCDisassembler::SoftFail; 1726 } else if (!imod && M) { 1727 Inst.setOpcode(ARM::CPS1p); 1728 Inst.addOperand(MCOperand::CreateImm(mode)); 1729 if (iflags) S = MCDisassembler::SoftFail; 1730 } else { 1731 // imod == '00' && M == '0' --> UNPREDICTABLE 1732 Inst.setOpcode(ARM::CPS1p); 1733 Inst.addOperand(MCOperand::CreateImm(mode)); 1734 S = MCDisassembler::SoftFail; 1735 } 1736 1737 return S; 1738 } 1739 1740 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1741 uint64_t Address, const void *Decoder) { 1742 unsigned imod = fieldFromInstruction32(Insn, 9, 2); 1743 unsigned M = fieldFromInstruction32(Insn, 8, 1); 1744 unsigned iflags = fieldFromInstruction32(Insn, 5, 3); 1745 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1746 1747 DecodeStatus S = MCDisassembler::Success; 1748 1749 // imod == '01' --> UNPREDICTABLE 1750 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1751 // return failure here. The '01' imod value is unprintable, so there's 1752 // nothing useful we could do even if we returned UNPREDICTABLE. 1753 1754 if (imod == 1) return MCDisassembler::Fail; 1755 1756 if (imod && M) { 1757 Inst.setOpcode(ARM::t2CPS3p); 1758 Inst.addOperand(MCOperand::CreateImm(imod)); 1759 Inst.addOperand(MCOperand::CreateImm(iflags)); 1760 Inst.addOperand(MCOperand::CreateImm(mode)); 1761 } else if (imod && !M) { 1762 Inst.setOpcode(ARM::t2CPS2p); 1763 Inst.addOperand(MCOperand::CreateImm(imod)); 1764 Inst.addOperand(MCOperand::CreateImm(iflags)); 1765 if (mode) S = MCDisassembler::SoftFail; 1766 } else if (!imod && M) { 1767 Inst.setOpcode(ARM::t2CPS1p); 1768 Inst.addOperand(MCOperand::CreateImm(mode)); 1769 if (iflags) S = MCDisassembler::SoftFail; 1770 } else { 1771 // imod == '00' && M == '0' --> UNPREDICTABLE 1772 Inst.setOpcode(ARM::t2CPS1p); 1773 Inst.addOperand(MCOperand::CreateImm(mode)); 1774 S = MCDisassembler::SoftFail; 1775 } 1776 1777 return S; 1778 } 1779 1780 static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 1781 uint64_t Address, const void *Decoder) { 1782 DecodeStatus S = MCDisassembler::Success; 1783 1784 unsigned Rd = fieldFromInstruction32(Insn, 8, 4); 1785 unsigned imm = 0; 1786 1787 imm |= (fieldFromInstruction32(Insn, 0, 8) << 0); 1788 imm |= (fieldFromInstruction32(Insn, 12, 3) << 8); 1789 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12); 1790 imm |= (fieldFromInstruction32(Insn, 26, 1) << 11); 1791 1792 if (Inst.getOpcode() == ARM::t2MOVTi16) 1793 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1794 return MCDisassembler::Fail; 1795 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1796 return MCDisassembler::Fail; 1797 1798 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1799 Inst.addOperand(MCOperand::CreateImm(imm)); 1800 1801 return S; 1802 } 1803 1804 static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 1805 uint64_t Address, const void *Decoder) { 1806 DecodeStatus S = MCDisassembler::Success; 1807 1808 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1809 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1810 unsigned imm = 0; 1811 1812 imm |= (fieldFromInstruction32(Insn, 0, 12) << 0); 1813 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12); 1814 1815 if (Inst.getOpcode() == ARM::MOVTi16) 1816 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1817 return MCDisassembler::Fail; 1818 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1819 return MCDisassembler::Fail; 1820 1821 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1822 Inst.addOperand(MCOperand::CreateImm(imm)); 1823 1824 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1825 return MCDisassembler::Fail; 1826 1827 return S; 1828 } 1829 1830 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1831 uint64_t Address, const void *Decoder) { 1832 DecodeStatus S = MCDisassembler::Success; 1833 1834 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1835 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1836 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1837 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1838 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1839 1840 if (pred == 0xF) 1841 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1842 1843 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1844 return MCDisassembler::Fail; 1845 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1846 return MCDisassembler::Fail; 1847 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1848 return MCDisassembler::Fail; 1849 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 1850 return MCDisassembler::Fail; 1851 1852 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1853 return MCDisassembler::Fail; 1854 1855 return S; 1856 } 1857 1858 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1859 uint64_t Address, const void *Decoder) { 1860 DecodeStatus S = MCDisassembler::Success; 1861 1862 unsigned add = fieldFromInstruction32(Val, 12, 1); 1863 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1864 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1865 1866 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1867 return MCDisassembler::Fail; 1868 1869 if (!add) imm *= -1; 1870 if (imm == 0 && !add) imm = INT32_MIN; 1871 Inst.addOperand(MCOperand::CreateImm(imm)); 1872 if (Rn == 15) 1873 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 1874 1875 return S; 1876 } 1877 1878 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1879 uint64_t Address, const void *Decoder) { 1880 DecodeStatus S = MCDisassembler::Success; 1881 1882 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1883 unsigned U = fieldFromInstruction32(Val, 8, 1); 1884 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1885 1886 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1887 return MCDisassembler::Fail; 1888 1889 if (U) 1890 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1891 else 1892 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1893 1894 return S; 1895 } 1896 1897 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1898 uint64_t Address, const void *Decoder) { 1899 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1900 } 1901 1902 static DecodeStatus 1903 DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1904 uint64_t Address, const void *Decoder) { 1905 DecodeStatus S = MCDisassembler::Success; 1906 1907 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1908 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1909 1910 if (pred == 0xF) { 1911 Inst.setOpcode(ARM::BLXi); 1912 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1913 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1914 return S; 1915 } 1916 1917 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, true, 1918 4, Inst, Decoder)) 1919 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1920 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1921 return MCDisassembler::Fail; 1922 1923 return S; 1924 } 1925 1926 1927 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1928 uint64_t Address, const void *Decoder) { 1929 DecodeStatus S = MCDisassembler::Success; 1930 1931 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1932 unsigned align = fieldFromInstruction32(Val, 4, 2); 1933 1934 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1935 return MCDisassembler::Fail; 1936 if (!align) 1937 Inst.addOperand(MCOperand::CreateImm(0)); 1938 else 1939 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1940 1941 return S; 1942 } 1943 1944 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1945 uint64_t Address, const void *Decoder) { 1946 DecodeStatus S = MCDisassembler::Success; 1947 1948 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1949 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1950 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1951 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1952 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1953 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1954 1955 // First output register 1956 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 1957 return MCDisassembler::Fail; 1958 1959 // Second output register 1960 switch (Inst.getOpcode()) { 1961 case ARM::VLD3d8: 1962 case ARM::VLD3d16: 1963 case ARM::VLD3d32: 1964 case ARM::VLD3d8_UPD: 1965 case ARM::VLD3d16_UPD: 1966 case ARM::VLD3d32_UPD: 1967 case ARM::VLD4d8: 1968 case ARM::VLD4d16: 1969 case ARM::VLD4d32: 1970 case ARM::VLD4d8_UPD: 1971 case ARM::VLD4d16_UPD: 1972 case ARM::VLD4d32_UPD: 1973 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 1974 return MCDisassembler::Fail; 1975 break; 1976 case ARM::VLD3q8: 1977 case ARM::VLD3q16: 1978 case ARM::VLD3q32: 1979 case ARM::VLD3q8_UPD: 1980 case ARM::VLD3q16_UPD: 1981 case ARM::VLD3q32_UPD: 1982 case ARM::VLD4q8: 1983 case ARM::VLD4q16: 1984 case ARM::VLD4q32: 1985 case ARM::VLD4q8_UPD: 1986 case ARM::VLD4q16_UPD: 1987 case ARM::VLD4q32_UPD: 1988 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 1989 return MCDisassembler::Fail; 1990 default: 1991 break; 1992 } 1993 1994 // Third output register 1995 switch(Inst.getOpcode()) { 1996 case ARM::VLD3d8: 1997 case ARM::VLD3d16: 1998 case ARM::VLD3d32: 1999 case ARM::VLD3d8_UPD: 2000 case ARM::VLD3d16_UPD: 2001 case ARM::VLD3d32_UPD: 2002 case ARM::VLD4d8: 2003 case ARM::VLD4d16: 2004 case ARM::VLD4d32: 2005 case ARM::VLD4d8_UPD: 2006 case ARM::VLD4d16_UPD: 2007 case ARM::VLD4d32_UPD: 2008 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2009 return MCDisassembler::Fail; 2010 break; 2011 case ARM::VLD3q8: 2012 case ARM::VLD3q16: 2013 case ARM::VLD3q32: 2014 case ARM::VLD3q8_UPD: 2015 case ARM::VLD3q16_UPD: 2016 case ARM::VLD3q32_UPD: 2017 case ARM::VLD4q8: 2018 case ARM::VLD4q16: 2019 case ARM::VLD4q32: 2020 case ARM::VLD4q8_UPD: 2021 case ARM::VLD4q16_UPD: 2022 case ARM::VLD4q32_UPD: 2023 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2024 return MCDisassembler::Fail; 2025 break; 2026 default: 2027 break; 2028 } 2029 2030 // Fourth output register 2031 switch (Inst.getOpcode()) { 2032 case ARM::VLD4d8: 2033 case ARM::VLD4d16: 2034 case ARM::VLD4d32: 2035 case ARM::VLD4d8_UPD: 2036 case ARM::VLD4d16_UPD: 2037 case ARM::VLD4d32_UPD: 2038 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2039 return MCDisassembler::Fail; 2040 break; 2041 case ARM::VLD4q8: 2042 case ARM::VLD4q16: 2043 case ARM::VLD4q32: 2044 case ARM::VLD4q8_UPD: 2045 case ARM::VLD4q16_UPD: 2046 case ARM::VLD4q32_UPD: 2047 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2048 return MCDisassembler::Fail; 2049 break; 2050 default: 2051 break; 2052 } 2053 2054 // Writeback operand 2055 switch (Inst.getOpcode()) { 2056 case ARM::VLD1d8wb_fixed: 2057 case ARM::VLD1d16wb_fixed: 2058 case ARM::VLD1d32wb_fixed: 2059 case ARM::VLD1d64wb_fixed: 2060 case ARM::VLD1d8wb_register: 2061 case ARM::VLD1d16wb_register: 2062 case ARM::VLD1d32wb_register: 2063 case ARM::VLD1d64wb_register: 2064 case ARM::VLD1q8wb_fixed: 2065 case ARM::VLD1q16wb_fixed: 2066 case ARM::VLD1q32wb_fixed: 2067 case ARM::VLD1q64wb_fixed: 2068 case ARM::VLD1q8wb_register: 2069 case ARM::VLD1q16wb_register: 2070 case ARM::VLD1q32wb_register: 2071 case ARM::VLD1q64wb_register: 2072 case ARM::VLD1d8Twb_fixed: 2073 case ARM::VLD1d8Twb_register: 2074 case ARM::VLD1d16Twb_fixed: 2075 case ARM::VLD1d16Twb_register: 2076 case ARM::VLD1d32Twb_fixed: 2077 case ARM::VLD1d32Twb_register: 2078 case ARM::VLD1d64Twb_fixed: 2079 case ARM::VLD1d64Twb_register: 2080 case ARM::VLD1d8Qwb_fixed: 2081 case ARM::VLD1d8Qwb_register: 2082 case ARM::VLD1d16Qwb_fixed: 2083 case ARM::VLD1d16Qwb_register: 2084 case ARM::VLD1d32Qwb_fixed: 2085 case ARM::VLD1d32Qwb_register: 2086 case ARM::VLD1d64Qwb_fixed: 2087 case ARM::VLD1d64Qwb_register: 2088 case ARM::VLD2d8_UPD: 2089 case ARM::VLD2d16_UPD: 2090 case ARM::VLD2d32_UPD: 2091 case ARM::VLD2q8_UPD: 2092 case ARM::VLD2q16_UPD: 2093 case ARM::VLD2q32_UPD: 2094 case ARM::VLD2b8_UPD: 2095 case ARM::VLD2b16_UPD: 2096 case ARM::VLD2b32_UPD: 2097 case ARM::VLD3d8_UPD: 2098 case ARM::VLD3d16_UPD: 2099 case ARM::VLD3d32_UPD: 2100 case ARM::VLD3q8_UPD: 2101 case ARM::VLD3q16_UPD: 2102 case ARM::VLD3q32_UPD: 2103 case ARM::VLD4d8_UPD: 2104 case ARM::VLD4d16_UPD: 2105 case ARM::VLD4d32_UPD: 2106 case ARM::VLD4q8_UPD: 2107 case ARM::VLD4q16_UPD: 2108 case ARM::VLD4q32_UPD: 2109 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2110 return MCDisassembler::Fail; 2111 break; 2112 default: 2113 break; 2114 } 2115 2116 // AddrMode6 Base (register+alignment) 2117 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2118 return MCDisassembler::Fail; 2119 2120 // AddrMode6 Offset (register) 2121 switch (Inst.getOpcode()) { 2122 default: 2123 // The below have been updated to have explicit am6offset split 2124 // between fixed and register offset. For those instructions not 2125 // yet updated, we need to add an additional reg0 operand for the 2126 // fixed variant. 2127 // 2128 // The fixed offset encodes as Rm == 0xd, so we check for that. 2129 if (Rm == 0xd) { 2130 Inst.addOperand(MCOperand::CreateReg(0)); 2131 break; 2132 } 2133 // Fall through to handle the register offset variant. 2134 case ARM::VLD1d8wb_fixed: 2135 case ARM::VLD1d16wb_fixed: 2136 case ARM::VLD1d32wb_fixed: 2137 case ARM::VLD1d64wb_fixed: 2138 case ARM::VLD1d8Twb_fixed: 2139 case ARM::VLD1d16Twb_fixed: 2140 case ARM::VLD1d32Twb_fixed: 2141 case ARM::VLD1d64Twb_fixed: 2142 case ARM::VLD1d8Qwb_fixed: 2143 case ARM::VLD1d16Qwb_fixed: 2144 case ARM::VLD1d32Qwb_fixed: 2145 case ARM::VLD1d64Qwb_fixed: 2146 case ARM::VLD1d8wb_register: 2147 case ARM::VLD1d16wb_register: 2148 case ARM::VLD1d32wb_register: 2149 case ARM::VLD1d64wb_register: 2150 case ARM::VLD1q8wb_fixed: 2151 case ARM::VLD1q16wb_fixed: 2152 case ARM::VLD1q32wb_fixed: 2153 case ARM::VLD1q64wb_fixed: 2154 case ARM::VLD1q8wb_register: 2155 case ARM::VLD1q16wb_register: 2156 case ARM::VLD1q32wb_register: 2157 case ARM::VLD1q64wb_register: 2158 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2159 // variant encodes Rm == 0xf. Anything else is a register offset post- 2160 // increment and we need to add the register operand to the instruction. 2161 if (Rm != 0xD && Rm != 0xF && 2162 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2163 return MCDisassembler::Fail; 2164 break; 2165 } 2166 2167 return S; 2168 } 2169 2170 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 2171 uint64_t Address, const void *Decoder) { 2172 DecodeStatus S = MCDisassembler::Success; 2173 2174 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2175 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2176 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 2177 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2178 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 2179 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2180 2181 // Writeback Operand 2182 switch (Inst.getOpcode()) { 2183 case ARM::VST1d8wb_fixed: 2184 case ARM::VST1d16wb_fixed: 2185 case ARM::VST1d32wb_fixed: 2186 case ARM::VST1d64wb_fixed: 2187 case ARM::VST1d8wb_register: 2188 case ARM::VST1d16wb_register: 2189 case ARM::VST1d32wb_register: 2190 case ARM::VST1d64wb_register: 2191 case ARM::VST1q8wb_fixed: 2192 case ARM::VST1q16wb_fixed: 2193 case ARM::VST1q32wb_fixed: 2194 case ARM::VST1q64wb_fixed: 2195 case ARM::VST1q8wb_register: 2196 case ARM::VST1q16wb_register: 2197 case ARM::VST1q32wb_register: 2198 case ARM::VST1q64wb_register: 2199 case ARM::VST1d8T_UPD: 2200 case ARM::VST1d16T_UPD: 2201 case ARM::VST1d32T_UPD: 2202 case ARM::VST1d64T_UPD: 2203 case ARM::VST1d8Q_UPD: 2204 case ARM::VST1d16Q_UPD: 2205 case ARM::VST1d32Q_UPD: 2206 case ARM::VST1d64Q_UPD: 2207 case ARM::VST2d8_UPD: 2208 case ARM::VST2d16_UPD: 2209 case ARM::VST2d32_UPD: 2210 case ARM::VST2q8_UPD: 2211 case ARM::VST2q16_UPD: 2212 case ARM::VST2q32_UPD: 2213 case ARM::VST2b8_UPD: 2214 case ARM::VST2b16_UPD: 2215 case ARM::VST2b32_UPD: 2216 case ARM::VST3d8_UPD: 2217 case ARM::VST3d16_UPD: 2218 case ARM::VST3d32_UPD: 2219 case ARM::VST3q8_UPD: 2220 case ARM::VST3q16_UPD: 2221 case ARM::VST3q32_UPD: 2222 case ARM::VST4d8_UPD: 2223 case ARM::VST4d16_UPD: 2224 case ARM::VST4d32_UPD: 2225 case ARM::VST4q8_UPD: 2226 case ARM::VST4q16_UPD: 2227 case ARM::VST4q32_UPD: 2228 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2229 return MCDisassembler::Fail; 2230 break; 2231 default: 2232 break; 2233 } 2234 2235 // AddrMode6 Base (register+alignment) 2236 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2237 return MCDisassembler::Fail; 2238 2239 // AddrMode6 Offset (register) 2240 switch (Inst.getOpcode()) { 2241 default: 2242 if (Rm == 0xD) 2243 Inst.addOperand(MCOperand::CreateReg(0)); 2244 else if (Rm != 0xF) { 2245 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2246 return MCDisassembler::Fail; 2247 } 2248 break; 2249 case ARM::VST1d8wb_fixed: 2250 case ARM::VST1d16wb_fixed: 2251 case ARM::VST1d32wb_fixed: 2252 case ARM::VST1d64wb_fixed: 2253 case ARM::VST1q8wb_fixed: 2254 case ARM::VST1q16wb_fixed: 2255 case ARM::VST1q32wb_fixed: 2256 case ARM::VST1q64wb_fixed: 2257 break; 2258 } 2259 2260 2261 // First input register 2262 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2263 return MCDisassembler::Fail; 2264 2265 // Second input register 2266 switch (Inst.getOpcode()) { 2267 case ARM::VST1d8T: 2268 case ARM::VST1d16T: 2269 case ARM::VST1d32T: 2270 case ARM::VST1d64T: 2271 case ARM::VST1d8T_UPD: 2272 case ARM::VST1d16T_UPD: 2273 case ARM::VST1d32T_UPD: 2274 case ARM::VST1d64T_UPD: 2275 case ARM::VST1d8Q: 2276 case ARM::VST1d16Q: 2277 case ARM::VST1d32Q: 2278 case ARM::VST1d64Q: 2279 case ARM::VST1d8Q_UPD: 2280 case ARM::VST1d16Q_UPD: 2281 case ARM::VST1d32Q_UPD: 2282 case ARM::VST1d64Q_UPD: 2283 case ARM::VST2d8: 2284 case ARM::VST2d16: 2285 case ARM::VST2d32: 2286 case ARM::VST2d8_UPD: 2287 case ARM::VST2d16_UPD: 2288 case ARM::VST2d32_UPD: 2289 case ARM::VST2q8: 2290 case ARM::VST2q16: 2291 case ARM::VST2q32: 2292 case ARM::VST2q8_UPD: 2293 case ARM::VST2q16_UPD: 2294 case ARM::VST2q32_UPD: 2295 case ARM::VST3d8: 2296 case ARM::VST3d16: 2297 case ARM::VST3d32: 2298 case ARM::VST3d8_UPD: 2299 case ARM::VST3d16_UPD: 2300 case ARM::VST3d32_UPD: 2301 case ARM::VST4d8: 2302 case ARM::VST4d16: 2303 case ARM::VST4d32: 2304 case ARM::VST4d8_UPD: 2305 case ARM::VST4d16_UPD: 2306 case ARM::VST4d32_UPD: 2307 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2308 return MCDisassembler::Fail; 2309 break; 2310 case ARM::VST2b8: 2311 case ARM::VST2b16: 2312 case ARM::VST2b32: 2313 case ARM::VST2b8_UPD: 2314 case ARM::VST2b16_UPD: 2315 case ARM::VST2b32_UPD: 2316 case ARM::VST3q8: 2317 case ARM::VST3q16: 2318 case ARM::VST3q32: 2319 case ARM::VST3q8_UPD: 2320 case ARM::VST3q16_UPD: 2321 case ARM::VST3q32_UPD: 2322 case ARM::VST4q8: 2323 case ARM::VST4q16: 2324 case ARM::VST4q32: 2325 case ARM::VST4q8_UPD: 2326 case ARM::VST4q16_UPD: 2327 case ARM::VST4q32_UPD: 2328 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2329 return MCDisassembler::Fail; 2330 break; 2331 default: 2332 break; 2333 } 2334 2335 // Third input register 2336 switch (Inst.getOpcode()) { 2337 case ARM::VST1d8T: 2338 case ARM::VST1d16T: 2339 case ARM::VST1d32T: 2340 case ARM::VST1d64T: 2341 case ARM::VST1d8T_UPD: 2342 case ARM::VST1d16T_UPD: 2343 case ARM::VST1d32T_UPD: 2344 case ARM::VST1d64T_UPD: 2345 case ARM::VST1d8Q: 2346 case ARM::VST1d16Q: 2347 case ARM::VST1d32Q: 2348 case ARM::VST1d64Q: 2349 case ARM::VST1d8Q_UPD: 2350 case ARM::VST1d16Q_UPD: 2351 case ARM::VST1d32Q_UPD: 2352 case ARM::VST1d64Q_UPD: 2353 case ARM::VST2q8: 2354 case ARM::VST2q16: 2355 case ARM::VST2q32: 2356 case ARM::VST2q8_UPD: 2357 case ARM::VST2q16_UPD: 2358 case ARM::VST2q32_UPD: 2359 case ARM::VST3d8: 2360 case ARM::VST3d16: 2361 case ARM::VST3d32: 2362 case ARM::VST3d8_UPD: 2363 case ARM::VST3d16_UPD: 2364 case ARM::VST3d32_UPD: 2365 case ARM::VST4d8: 2366 case ARM::VST4d16: 2367 case ARM::VST4d32: 2368 case ARM::VST4d8_UPD: 2369 case ARM::VST4d16_UPD: 2370 case ARM::VST4d32_UPD: 2371 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2372 return MCDisassembler::Fail; 2373 break; 2374 case ARM::VST3q8: 2375 case ARM::VST3q16: 2376 case ARM::VST3q32: 2377 case ARM::VST3q8_UPD: 2378 case ARM::VST3q16_UPD: 2379 case ARM::VST3q32_UPD: 2380 case ARM::VST4q8: 2381 case ARM::VST4q16: 2382 case ARM::VST4q32: 2383 case ARM::VST4q8_UPD: 2384 case ARM::VST4q16_UPD: 2385 case ARM::VST4q32_UPD: 2386 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2387 return MCDisassembler::Fail; 2388 break; 2389 default: 2390 break; 2391 } 2392 2393 // Fourth input register 2394 switch (Inst.getOpcode()) { 2395 case ARM::VST1d8Q: 2396 case ARM::VST1d16Q: 2397 case ARM::VST1d32Q: 2398 case ARM::VST1d64Q: 2399 case ARM::VST1d8Q_UPD: 2400 case ARM::VST1d16Q_UPD: 2401 case ARM::VST1d32Q_UPD: 2402 case ARM::VST1d64Q_UPD: 2403 case ARM::VST2q8: 2404 case ARM::VST2q16: 2405 case ARM::VST2q32: 2406 case ARM::VST2q8_UPD: 2407 case ARM::VST2q16_UPD: 2408 case ARM::VST2q32_UPD: 2409 case ARM::VST4d8: 2410 case ARM::VST4d16: 2411 case ARM::VST4d32: 2412 case ARM::VST4d8_UPD: 2413 case ARM::VST4d16_UPD: 2414 case ARM::VST4d32_UPD: 2415 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2416 return MCDisassembler::Fail; 2417 break; 2418 case ARM::VST4q8: 2419 case ARM::VST4q16: 2420 case ARM::VST4q32: 2421 case ARM::VST4q8_UPD: 2422 case ARM::VST4q16_UPD: 2423 case ARM::VST4q32_UPD: 2424 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2425 return MCDisassembler::Fail; 2426 break; 2427 default: 2428 break; 2429 } 2430 2431 return S; 2432 } 2433 2434 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2435 uint64_t Address, const void *Decoder) { 2436 DecodeStatus S = MCDisassembler::Success; 2437 2438 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2439 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2440 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2441 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2442 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2443 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2444 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1; 2445 2446 align *= (1 << size); 2447 2448 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2449 return MCDisassembler::Fail; 2450 if (regs == 2) { 2451 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2452 return MCDisassembler::Fail; 2453 } 2454 if (Rm != 0xF) { 2455 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2456 return MCDisassembler::Fail; 2457 } 2458 2459 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2460 return MCDisassembler::Fail; 2461 Inst.addOperand(MCOperand::CreateImm(align)); 2462 2463 if (Rm == 0xD) 2464 Inst.addOperand(MCOperand::CreateReg(0)); 2465 else if (Rm != 0xF) { 2466 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2467 return MCDisassembler::Fail; 2468 } 2469 2470 return S; 2471 } 2472 2473 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2474 uint64_t Address, const void *Decoder) { 2475 DecodeStatus S = MCDisassembler::Success; 2476 2477 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2478 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2479 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2480 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2481 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2482 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 2483 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2484 align *= 2*size; 2485 2486 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2487 return MCDisassembler::Fail; 2488 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2489 return MCDisassembler::Fail; 2490 if (Rm != 0xF) { 2491 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2492 return MCDisassembler::Fail; 2493 } 2494 2495 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2496 return MCDisassembler::Fail; 2497 Inst.addOperand(MCOperand::CreateImm(align)); 2498 2499 if (Rm == 0xD) 2500 Inst.addOperand(MCOperand::CreateReg(0)); 2501 else if (Rm != 0xF) { 2502 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2503 return MCDisassembler::Fail; 2504 } 2505 2506 return S; 2507 } 2508 2509 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2510 uint64_t Address, const void *Decoder) { 2511 DecodeStatus S = MCDisassembler::Success; 2512 2513 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2514 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2515 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2516 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2517 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2518 2519 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2520 return MCDisassembler::Fail; 2521 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2522 return MCDisassembler::Fail; 2523 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2524 return MCDisassembler::Fail; 2525 if (Rm != 0xF) { 2526 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2527 return MCDisassembler::Fail; 2528 } 2529 2530 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2531 return MCDisassembler::Fail; 2532 Inst.addOperand(MCOperand::CreateImm(0)); 2533 2534 if (Rm == 0xD) 2535 Inst.addOperand(MCOperand::CreateReg(0)); 2536 else if (Rm != 0xF) { 2537 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2538 return MCDisassembler::Fail; 2539 } 2540 2541 return S; 2542 } 2543 2544 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2545 uint64_t Address, const void *Decoder) { 2546 DecodeStatus S = MCDisassembler::Success; 2547 2548 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2549 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2550 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2551 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2552 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2553 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2554 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2555 2556 if (size == 0x3) { 2557 size = 4; 2558 align = 16; 2559 } else { 2560 if (size == 2) { 2561 size = 1 << size; 2562 align *= 8; 2563 } else { 2564 size = 1 << size; 2565 align *= 4*size; 2566 } 2567 } 2568 2569 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2570 return MCDisassembler::Fail; 2571 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2572 return MCDisassembler::Fail; 2573 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2574 return MCDisassembler::Fail; 2575 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2576 return MCDisassembler::Fail; 2577 if (Rm != 0xF) { 2578 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2579 return MCDisassembler::Fail; 2580 } 2581 2582 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2583 return MCDisassembler::Fail; 2584 Inst.addOperand(MCOperand::CreateImm(align)); 2585 2586 if (Rm == 0xD) 2587 Inst.addOperand(MCOperand::CreateReg(0)); 2588 else if (Rm != 0xF) { 2589 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2590 return MCDisassembler::Fail; 2591 } 2592 2593 return S; 2594 } 2595 2596 static DecodeStatus 2597 DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 2598 uint64_t Address, const void *Decoder) { 2599 DecodeStatus S = MCDisassembler::Success; 2600 2601 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2602 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2603 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2604 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 2605 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 2606 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 2607 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 2608 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 2609 2610 if (Q) { 2611 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2612 return MCDisassembler::Fail; 2613 } else { 2614 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2615 return MCDisassembler::Fail; 2616 } 2617 2618 Inst.addOperand(MCOperand::CreateImm(imm)); 2619 2620 switch (Inst.getOpcode()) { 2621 case ARM::VORRiv4i16: 2622 case ARM::VORRiv2i32: 2623 case ARM::VBICiv4i16: 2624 case ARM::VBICiv2i32: 2625 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2626 return MCDisassembler::Fail; 2627 break; 2628 case ARM::VORRiv8i16: 2629 case ARM::VORRiv4i32: 2630 case ARM::VBICiv8i16: 2631 case ARM::VBICiv4i32: 2632 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2633 return MCDisassembler::Fail; 2634 break; 2635 default: 2636 break; 2637 } 2638 2639 return S; 2640 } 2641 2642 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 2643 uint64_t Address, const void *Decoder) { 2644 DecodeStatus S = MCDisassembler::Success; 2645 2646 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2647 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2648 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2649 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2650 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2651 2652 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2653 return MCDisassembler::Fail; 2654 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2655 return MCDisassembler::Fail; 2656 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2657 2658 return S; 2659 } 2660 2661 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 2662 uint64_t Address, const void *Decoder) { 2663 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2664 return MCDisassembler::Success; 2665 } 2666 2667 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2668 uint64_t Address, const void *Decoder) { 2669 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2670 return MCDisassembler::Success; 2671 } 2672 2673 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2674 uint64_t Address, const void *Decoder) { 2675 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2676 return MCDisassembler::Success; 2677 } 2678 2679 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2680 uint64_t Address, const void *Decoder) { 2681 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2682 return MCDisassembler::Success; 2683 } 2684 2685 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2686 uint64_t Address, const void *Decoder) { 2687 DecodeStatus S = MCDisassembler::Success; 2688 2689 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2690 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2691 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2692 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2693 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2694 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2695 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2696 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; 2697 2698 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2699 return MCDisassembler::Fail; 2700 if (op) { 2701 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2702 return MCDisassembler::Fail; // Writeback 2703 } 2704 2705 for (unsigned i = 0; i < length; ++i) { 2706 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder))) 2707 return MCDisassembler::Fail; 2708 } 2709 2710 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2711 return MCDisassembler::Fail; 2712 2713 return S; 2714 } 2715 2716 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2717 uint64_t Address, const void *Decoder) { 2718 DecodeStatus S = MCDisassembler::Success; 2719 2720 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2721 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2722 2723 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 2724 return MCDisassembler::Fail; 2725 2726 switch(Inst.getOpcode()) { 2727 default: 2728 return MCDisassembler::Fail; 2729 case ARM::tADR: 2730 break; // tADR does not explicitly represent the PC as an operand. 2731 case ARM::tADDrSPi: 2732 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2733 break; 2734 } 2735 2736 Inst.addOperand(MCOperand::CreateImm(imm)); 2737 return S; 2738 } 2739 2740 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2741 uint64_t Address, const void *Decoder) { 2742 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2743 return MCDisassembler::Success; 2744 } 2745 2746 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2747 uint64_t Address, const void *Decoder) { 2748 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2749 return MCDisassembler::Success; 2750 } 2751 2752 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2753 uint64_t Address, const void *Decoder) { 2754 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2755 return MCDisassembler::Success; 2756 } 2757 2758 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2759 uint64_t Address, const void *Decoder) { 2760 DecodeStatus S = MCDisassembler::Success; 2761 2762 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2763 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2764 2765 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2766 return MCDisassembler::Fail; 2767 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 2768 return MCDisassembler::Fail; 2769 2770 return S; 2771 } 2772 2773 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2774 uint64_t Address, const void *Decoder) { 2775 DecodeStatus S = MCDisassembler::Success; 2776 2777 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2778 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2779 2780 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2781 return MCDisassembler::Fail; 2782 Inst.addOperand(MCOperand::CreateImm(imm)); 2783 2784 return S; 2785 } 2786 2787 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2788 uint64_t Address, const void *Decoder) { 2789 unsigned imm = Val << 2; 2790 2791 Inst.addOperand(MCOperand::CreateImm(imm)); 2792 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 2793 2794 return MCDisassembler::Success; 2795 } 2796 2797 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2798 uint64_t Address, const void *Decoder) { 2799 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2800 Inst.addOperand(MCOperand::CreateImm(Val)); 2801 2802 return MCDisassembler::Success; 2803 } 2804 2805 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2806 uint64_t Address, const void *Decoder) { 2807 DecodeStatus S = MCDisassembler::Success; 2808 2809 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2810 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2811 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2812 2813 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2814 return MCDisassembler::Fail; 2815 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 2816 return MCDisassembler::Fail; 2817 Inst.addOperand(MCOperand::CreateImm(imm)); 2818 2819 return S; 2820 } 2821 2822 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2823 uint64_t Address, const void *Decoder) { 2824 DecodeStatus S = MCDisassembler::Success; 2825 2826 switch (Inst.getOpcode()) { 2827 case ARM::t2PLDs: 2828 case ARM::t2PLDWs: 2829 case ARM::t2PLIs: 2830 break; 2831 default: { 2832 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2833 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 2834 return MCDisassembler::Fail; 2835 } 2836 } 2837 2838 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2839 if (Rn == 0xF) { 2840 switch (Inst.getOpcode()) { 2841 case ARM::t2LDRBs: 2842 Inst.setOpcode(ARM::t2LDRBpci); 2843 break; 2844 case ARM::t2LDRHs: 2845 Inst.setOpcode(ARM::t2LDRHpci); 2846 break; 2847 case ARM::t2LDRSHs: 2848 Inst.setOpcode(ARM::t2LDRSHpci); 2849 break; 2850 case ARM::t2LDRSBs: 2851 Inst.setOpcode(ARM::t2LDRSBpci); 2852 break; 2853 case ARM::t2PLDs: 2854 Inst.setOpcode(ARM::t2PLDi12); 2855 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2856 break; 2857 default: 2858 return MCDisassembler::Fail; 2859 } 2860 2861 int imm = fieldFromInstruction32(Insn, 0, 12); 2862 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2863 Inst.addOperand(MCOperand::CreateImm(imm)); 2864 2865 return S; 2866 } 2867 2868 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2869 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2870 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2871 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 2872 return MCDisassembler::Fail; 2873 2874 return S; 2875 } 2876 2877 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2878 uint64_t Address, const void *Decoder) { 2879 int imm = Val & 0xFF; 2880 if (!(Val & 0x100)) imm *= -1; 2881 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2882 2883 return MCDisassembler::Success; 2884 } 2885 2886 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2887 uint64_t Address, const void *Decoder) { 2888 DecodeStatus S = MCDisassembler::Success; 2889 2890 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2891 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2892 2893 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2894 return MCDisassembler::Fail; 2895 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 2896 return MCDisassembler::Fail; 2897 2898 return S; 2899 } 2900 2901 static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val, 2902 uint64_t Address, const void *Decoder) { 2903 DecodeStatus S = MCDisassembler::Success; 2904 2905 unsigned Rn = fieldFromInstruction32(Val, 8, 4); 2906 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2907 2908 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2909 return MCDisassembler::Fail; 2910 2911 Inst.addOperand(MCOperand::CreateImm(imm)); 2912 2913 return S; 2914 } 2915 2916 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2917 uint64_t Address, const void *Decoder) { 2918 int imm = Val & 0xFF; 2919 if (Val == 0) 2920 imm = INT32_MIN; 2921 else if (!(Val & 0x100)) 2922 imm *= -1; 2923 Inst.addOperand(MCOperand::CreateImm(imm)); 2924 2925 return MCDisassembler::Success; 2926 } 2927 2928 2929 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 2930 uint64_t Address, const void *Decoder) { 2931 DecodeStatus S = MCDisassembler::Success; 2932 2933 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2934 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2935 2936 // Some instructions always use an additive offset. 2937 switch (Inst.getOpcode()) { 2938 case ARM::t2LDRT: 2939 case ARM::t2LDRBT: 2940 case ARM::t2LDRHT: 2941 case ARM::t2LDRSBT: 2942 case ARM::t2LDRSHT: 2943 case ARM::t2STRT: 2944 case ARM::t2STRBT: 2945 case ARM::t2STRHT: 2946 imm |= 0x100; 2947 break; 2948 default: 2949 break; 2950 } 2951 2952 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2953 return MCDisassembler::Fail; 2954 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 2955 return MCDisassembler::Fail; 2956 2957 return S; 2958 } 2959 2960 static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn, 2961 uint64_t Address, const void *Decoder) { 2962 DecodeStatus S = MCDisassembler::Success; 2963 2964 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2965 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2966 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 2967 addr |= fieldFromInstruction32(Insn, 9, 1) << 8; 2968 addr |= Rn << 9; 2969 unsigned load = fieldFromInstruction32(Insn, 20, 1); 2970 2971 if (!load) { 2972 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2973 return MCDisassembler::Fail; 2974 } 2975 2976 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 2977 return MCDisassembler::Fail; 2978 2979 if (load) { 2980 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2981 return MCDisassembler::Fail; 2982 } 2983 2984 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 2985 return MCDisassembler::Fail; 2986 2987 return S; 2988 } 2989 2990 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 2991 uint64_t Address, const void *Decoder) { 2992 DecodeStatus S = MCDisassembler::Success; 2993 2994 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2995 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2996 2997 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2998 return MCDisassembler::Fail; 2999 Inst.addOperand(MCOperand::CreateImm(imm)); 3000 3001 return S; 3002 } 3003 3004 3005 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 3006 uint64_t Address, const void *Decoder) { 3007 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 3008 3009 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3010 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3011 Inst.addOperand(MCOperand::CreateImm(imm)); 3012 3013 return MCDisassembler::Success; 3014 } 3015 3016 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 3017 uint64_t Address, const void *Decoder) { 3018 DecodeStatus S = MCDisassembler::Success; 3019 3020 if (Inst.getOpcode() == ARM::tADDrSP) { 3021 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 3022 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 3023 3024 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3025 return MCDisassembler::Fail; 3026 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3027 return MCDisassembler::Fail; 3028 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3029 } else if (Inst.getOpcode() == ARM::tADDspr) { 3030 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 3031 3032 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3033 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3034 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3035 return MCDisassembler::Fail; 3036 } 3037 3038 return S; 3039 } 3040 3041 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 3042 uint64_t Address, const void *Decoder) { 3043 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 3044 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 3045 3046 Inst.addOperand(MCOperand::CreateImm(imod)); 3047 Inst.addOperand(MCOperand::CreateImm(flags)); 3048 3049 return MCDisassembler::Success; 3050 } 3051 3052 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 3053 uint64_t Address, const void *Decoder) { 3054 DecodeStatus S = MCDisassembler::Success; 3055 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3056 unsigned add = fieldFromInstruction32(Insn, 4, 1); 3057 3058 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3059 return MCDisassembler::Fail; 3060 Inst.addOperand(MCOperand::CreateImm(add)); 3061 3062 return S; 3063 } 3064 3065 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 3066 uint64_t Address, const void *Decoder) { 3067 if (!tryAddingSymbolicOperand(Address, 3068 (Address & ~2u) + SignExtend32<22>(Val << 1) + 4, 3069 true, 4, Inst, Decoder)) 3070 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 3071 return MCDisassembler::Success; 3072 } 3073 3074 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 3075 uint64_t Address, const void *Decoder) { 3076 if (Val == 0xA || Val == 0xB) 3077 return MCDisassembler::Fail; 3078 3079 Inst.addOperand(MCOperand::CreateImm(Val)); 3080 return MCDisassembler::Success; 3081 } 3082 3083 static DecodeStatus 3084 DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Insn, 3085 uint64_t Address, const void *Decoder) { 3086 DecodeStatus S = MCDisassembler::Success; 3087 3088 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3089 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3090 3091 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3092 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3093 return MCDisassembler::Fail; 3094 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3095 return MCDisassembler::Fail; 3096 return S; 3097 } 3098 3099 static DecodeStatus 3100 DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 3101 uint64_t Address, const void *Decoder) { 3102 DecodeStatus S = MCDisassembler::Success; 3103 3104 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 3105 if (pred == 0xE || pred == 0xF) { 3106 unsigned opc = fieldFromInstruction32(Insn, 4, 28); 3107 switch (opc) { 3108 default: 3109 return MCDisassembler::Fail; 3110 case 0xf3bf8f4: 3111 Inst.setOpcode(ARM::t2DSB); 3112 break; 3113 case 0xf3bf8f5: 3114 Inst.setOpcode(ARM::t2DMB); 3115 break; 3116 case 0xf3bf8f6: 3117 Inst.setOpcode(ARM::t2ISB); 3118 break; 3119 } 3120 3121 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 3122 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3123 } 3124 3125 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 3126 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 3127 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 3128 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 3129 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 3130 3131 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3132 return MCDisassembler::Fail; 3133 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3134 return MCDisassembler::Fail; 3135 3136 return S; 3137 } 3138 3139 // Decode a shifted immediate operand. These basically consist 3140 // of an 8-bit value, and a 4-bit directive that specifies either 3141 // a splat operation or a rotation. 3142 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 3143 uint64_t Address, const void *Decoder) { 3144 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 3145 if (ctrl == 0) { 3146 unsigned byte = fieldFromInstruction32(Val, 8, 2); 3147 unsigned imm = fieldFromInstruction32(Val, 0, 8); 3148 switch (byte) { 3149 case 0: 3150 Inst.addOperand(MCOperand::CreateImm(imm)); 3151 break; 3152 case 1: 3153 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 3154 break; 3155 case 2: 3156 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 3157 break; 3158 case 3: 3159 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 3160 (imm << 8) | imm)); 3161 break; 3162 } 3163 } else { 3164 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 3165 unsigned rot = fieldFromInstruction32(Val, 7, 5); 3166 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3167 Inst.addOperand(MCOperand::CreateImm(imm)); 3168 } 3169 3170 return MCDisassembler::Success; 3171 } 3172 3173 static DecodeStatus 3174 DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 3175 uint64_t Address, const void *Decoder){ 3176 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 3177 return MCDisassembler::Success; 3178 } 3179 3180 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 3181 uint64_t Address, const void *Decoder){ 3182 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 3183 return MCDisassembler::Success; 3184 } 3185 3186 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 3187 uint64_t Address, const void *Decoder) { 3188 switch (Val) { 3189 default: 3190 return MCDisassembler::Fail; 3191 case 0xF: // SY 3192 case 0xE: // ST 3193 case 0xB: // ISH 3194 case 0xA: // ISHST 3195 case 0x7: // NSH 3196 case 0x6: // NSHST 3197 case 0x3: // OSH 3198 case 0x2: // OSHST 3199 break; 3200 } 3201 3202 Inst.addOperand(MCOperand::CreateImm(Val)); 3203 return MCDisassembler::Success; 3204 } 3205 3206 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, 3207 uint64_t Address, const void *Decoder) { 3208 if (!Val) return MCDisassembler::Fail; 3209 Inst.addOperand(MCOperand::CreateImm(Val)); 3210 return MCDisassembler::Success; 3211 } 3212 3213 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 3214 uint64_t Address, const void *Decoder) { 3215 DecodeStatus S = MCDisassembler::Success; 3216 3217 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3218 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3219 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3220 3221 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3222 3223 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3224 return MCDisassembler::Fail; 3225 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3226 return MCDisassembler::Fail; 3227 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3228 return MCDisassembler::Fail; 3229 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3230 return MCDisassembler::Fail; 3231 3232 return S; 3233 } 3234 3235 3236 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 3237 uint64_t Address, const void *Decoder){ 3238 DecodeStatus S = MCDisassembler::Success; 3239 3240 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3241 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 3242 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3243 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3244 3245 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 3246 return MCDisassembler::Fail; 3247 3248 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3249 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail; 3250 3251 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3252 return MCDisassembler::Fail; 3253 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3254 return MCDisassembler::Fail; 3255 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3256 return MCDisassembler::Fail; 3257 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3258 return MCDisassembler::Fail; 3259 3260 return S; 3261 } 3262 3263 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 3264 uint64_t Address, const void *Decoder) { 3265 DecodeStatus S = MCDisassembler::Success; 3266 3267 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3268 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3269 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3270 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3271 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3272 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3273 3274 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3275 3276 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3277 return MCDisassembler::Fail; 3278 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3279 return MCDisassembler::Fail; 3280 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3281 return MCDisassembler::Fail; 3282 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3283 return MCDisassembler::Fail; 3284 3285 return S; 3286 } 3287 3288 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 3289 uint64_t Address, const void *Decoder) { 3290 DecodeStatus S = MCDisassembler::Success; 3291 3292 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3293 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3294 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3295 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3296 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3297 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3298 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3299 3300 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3301 if (Rm == 0xF) S = MCDisassembler::SoftFail; 3302 3303 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3304 return MCDisassembler::Fail; 3305 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3306 return MCDisassembler::Fail; 3307 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3308 return MCDisassembler::Fail; 3309 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3310 return MCDisassembler::Fail; 3311 3312 return S; 3313 } 3314 3315 3316 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 3317 uint64_t Address, const void *Decoder) { 3318 DecodeStatus S = MCDisassembler::Success; 3319 3320 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3321 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3322 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3323 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3324 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3325 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3326 3327 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3328 3329 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3330 return MCDisassembler::Fail; 3331 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3332 return MCDisassembler::Fail; 3333 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3334 return MCDisassembler::Fail; 3335 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3336 return MCDisassembler::Fail; 3337 3338 return S; 3339 } 3340 3341 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 3342 uint64_t Address, const void *Decoder) { 3343 DecodeStatus S = MCDisassembler::Success; 3344 3345 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3346 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3347 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3348 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3349 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3350 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3351 3352 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3353 3354 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3355 return MCDisassembler::Fail; 3356 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3357 return MCDisassembler::Fail; 3358 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3359 return MCDisassembler::Fail; 3360 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3361 return MCDisassembler::Fail; 3362 3363 return S; 3364 } 3365 3366 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 3367 uint64_t Address, const void *Decoder) { 3368 DecodeStatus S = MCDisassembler::Success; 3369 3370 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3371 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3372 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3373 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3374 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3375 3376 unsigned align = 0; 3377 unsigned index = 0; 3378 switch (size) { 3379 default: 3380 return MCDisassembler::Fail; 3381 case 0: 3382 if (fieldFromInstruction32(Insn, 4, 1)) 3383 return MCDisassembler::Fail; // UNDEFINED 3384 index = fieldFromInstruction32(Insn, 5, 3); 3385 break; 3386 case 1: 3387 if (fieldFromInstruction32(Insn, 5, 1)) 3388 return MCDisassembler::Fail; // UNDEFINED 3389 index = fieldFromInstruction32(Insn, 6, 2); 3390 if (fieldFromInstruction32(Insn, 4, 1)) 3391 align = 2; 3392 break; 3393 case 2: 3394 if (fieldFromInstruction32(Insn, 6, 1)) 3395 return MCDisassembler::Fail; // UNDEFINED 3396 index = fieldFromInstruction32(Insn, 7, 1); 3397 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3398 align = 4; 3399 } 3400 3401 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3402 return MCDisassembler::Fail; 3403 if (Rm != 0xF) { // Writeback 3404 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3405 return MCDisassembler::Fail; 3406 } 3407 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3408 return MCDisassembler::Fail; 3409 Inst.addOperand(MCOperand::CreateImm(align)); 3410 if (Rm != 0xF) { 3411 if (Rm != 0xD) { 3412 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3413 return MCDisassembler::Fail; 3414 } else 3415 Inst.addOperand(MCOperand::CreateReg(0)); 3416 } 3417 3418 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3419 return MCDisassembler::Fail; 3420 Inst.addOperand(MCOperand::CreateImm(index)); 3421 3422 return S; 3423 } 3424 3425 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 3426 uint64_t Address, const void *Decoder) { 3427 DecodeStatus S = MCDisassembler::Success; 3428 3429 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3430 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3431 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3432 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3433 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3434 3435 unsigned align = 0; 3436 unsigned index = 0; 3437 switch (size) { 3438 default: 3439 return MCDisassembler::Fail; 3440 case 0: 3441 if (fieldFromInstruction32(Insn, 4, 1)) 3442 return MCDisassembler::Fail; // UNDEFINED 3443 index = fieldFromInstruction32(Insn, 5, 3); 3444 break; 3445 case 1: 3446 if (fieldFromInstruction32(Insn, 5, 1)) 3447 return MCDisassembler::Fail; // UNDEFINED 3448 index = fieldFromInstruction32(Insn, 6, 2); 3449 if (fieldFromInstruction32(Insn, 4, 1)) 3450 align = 2; 3451 break; 3452 case 2: 3453 if (fieldFromInstruction32(Insn, 6, 1)) 3454 return MCDisassembler::Fail; // UNDEFINED 3455 index = fieldFromInstruction32(Insn, 7, 1); 3456 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3457 align = 4; 3458 } 3459 3460 if (Rm != 0xF) { // Writeback 3461 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3462 return MCDisassembler::Fail; 3463 } 3464 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3465 return MCDisassembler::Fail; 3466 Inst.addOperand(MCOperand::CreateImm(align)); 3467 if (Rm != 0xF) { 3468 if (Rm != 0xD) { 3469 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3470 return MCDisassembler::Fail; 3471 } else 3472 Inst.addOperand(MCOperand::CreateReg(0)); 3473 } 3474 3475 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3476 return MCDisassembler::Fail; 3477 Inst.addOperand(MCOperand::CreateImm(index)); 3478 3479 return S; 3480 } 3481 3482 3483 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 3484 uint64_t Address, const void *Decoder) { 3485 DecodeStatus S = MCDisassembler::Success; 3486 3487 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3488 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3489 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3490 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3491 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3492 3493 unsigned align = 0; 3494 unsigned index = 0; 3495 unsigned inc = 1; 3496 switch (size) { 3497 default: 3498 return MCDisassembler::Fail; 3499 case 0: 3500 index = fieldFromInstruction32(Insn, 5, 3); 3501 if (fieldFromInstruction32(Insn, 4, 1)) 3502 align = 2; 3503 break; 3504 case 1: 3505 index = fieldFromInstruction32(Insn, 6, 2); 3506 if (fieldFromInstruction32(Insn, 4, 1)) 3507 align = 4; 3508 if (fieldFromInstruction32(Insn, 5, 1)) 3509 inc = 2; 3510 break; 3511 case 2: 3512 if (fieldFromInstruction32(Insn, 5, 1)) 3513 return MCDisassembler::Fail; // UNDEFINED 3514 index = fieldFromInstruction32(Insn, 7, 1); 3515 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3516 align = 8; 3517 if (fieldFromInstruction32(Insn, 6, 1)) 3518 inc = 2; 3519 break; 3520 } 3521 3522 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3523 return MCDisassembler::Fail; 3524 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3525 return MCDisassembler::Fail; 3526 if (Rm != 0xF) { // Writeback 3527 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3528 return MCDisassembler::Fail; 3529 } 3530 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3531 return MCDisassembler::Fail; 3532 Inst.addOperand(MCOperand::CreateImm(align)); 3533 if (Rm != 0xF) { 3534 if (Rm != 0xD) { 3535 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3536 return MCDisassembler::Fail; 3537 } else 3538 Inst.addOperand(MCOperand::CreateReg(0)); 3539 } 3540 3541 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3542 return MCDisassembler::Fail; 3543 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3544 return MCDisassembler::Fail; 3545 Inst.addOperand(MCOperand::CreateImm(index)); 3546 3547 return S; 3548 } 3549 3550 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 3551 uint64_t Address, const void *Decoder) { 3552 DecodeStatus S = MCDisassembler::Success; 3553 3554 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3555 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3556 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3557 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3558 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3559 3560 unsigned align = 0; 3561 unsigned index = 0; 3562 unsigned inc = 1; 3563 switch (size) { 3564 default: 3565 return MCDisassembler::Fail; 3566 case 0: 3567 index = fieldFromInstruction32(Insn, 5, 3); 3568 if (fieldFromInstruction32(Insn, 4, 1)) 3569 align = 2; 3570 break; 3571 case 1: 3572 index = fieldFromInstruction32(Insn, 6, 2); 3573 if (fieldFromInstruction32(Insn, 4, 1)) 3574 align = 4; 3575 if (fieldFromInstruction32(Insn, 5, 1)) 3576 inc = 2; 3577 break; 3578 case 2: 3579 if (fieldFromInstruction32(Insn, 5, 1)) 3580 return MCDisassembler::Fail; // UNDEFINED 3581 index = fieldFromInstruction32(Insn, 7, 1); 3582 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3583 align = 8; 3584 if (fieldFromInstruction32(Insn, 6, 1)) 3585 inc = 2; 3586 break; 3587 } 3588 3589 if (Rm != 0xF) { // Writeback 3590 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3591 return MCDisassembler::Fail; 3592 } 3593 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3594 return MCDisassembler::Fail; 3595 Inst.addOperand(MCOperand::CreateImm(align)); 3596 if (Rm != 0xF) { 3597 if (Rm != 0xD) { 3598 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3599 return MCDisassembler::Fail; 3600 } else 3601 Inst.addOperand(MCOperand::CreateReg(0)); 3602 } 3603 3604 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3605 return MCDisassembler::Fail; 3606 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3607 return MCDisassembler::Fail; 3608 Inst.addOperand(MCOperand::CreateImm(index)); 3609 3610 return S; 3611 } 3612 3613 3614 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 3615 uint64_t Address, const void *Decoder) { 3616 DecodeStatus S = MCDisassembler::Success; 3617 3618 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3619 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3620 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3621 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3622 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3623 3624 unsigned align = 0; 3625 unsigned index = 0; 3626 unsigned inc = 1; 3627 switch (size) { 3628 default: 3629 return MCDisassembler::Fail; 3630 case 0: 3631 if (fieldFromInstruction32(Insn, 4, 1)) 3632 return MCDisassembler::Fail; // UNDEFINED 3633 index = fieldFromInstruction32(Insn, 5, 3); 3634 break; 3635 case 1: 3636 if (fieldFromInstruction32(Insn, 4, 1)) 3637 return MCDisassembler::Fail; // UNDEFINED 3638 index = fieldFromInstruction32(Insn, 6, 2); 3639 if (fieldFromInstruction32(Insn, 5, 1)) 3640 inc = 2; 3641 break; 3642 case 2: 3643 if (fieldFromInstruction32(Insn, 4, 2)) 3644 return MCDisassembler::Fail; // UNDEFINED 3645 index = fieldFromInstruction32(Insn, 7, 1); 3646 if (fieldFromInstruction32(Insn, 6, 1)) 3647 inc = 2; 3648 break; 3649 } 3650 3651 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3652 return MCDisassembler::Fail; 3653 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3654 return MCDisassembler::Fail; 3655 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3656 return MCDisassembler::Fail; 3657 3658 if (Rm != 0xF) { // Writeback 3659 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3660 return MCDisassembler::Fail; 3661 } 3662 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3663 return MCDisassembler::Fail; 3664 Inst.addOperand(MCOperand::CreateImm(align)); 3665 if (Rm != 0xF) { 3666 if (Rm != 0xD) { 3667 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3668 return MCDisassembler::Fail; 3669 } else 3670 Inst.addOperand(MCOperand::CreateReg(0)); 3671 } 3672 3673 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3674 return MCDisassembler::Fail; 3675 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3676 return MCDisassembler::Fail; 3677 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3678 return MCDisassembler::Fail; 3679 Inst.addOperand(MCOperand::CreateImm(index)); 3680 3681 return S; 3682 } 3683 3684 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 3685 uint64_t Address, const void *Decoder) { 3686 DecodeStatus S = MCDisassembler::Success; 3687 3688 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3689 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3690 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3691 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3692 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3693 3694 unsigned align = 0; 3695 unsigned index = 0; 3696 unsigned inc = 1; 3697 switch (size) { 3698 default: 3699 return MCDisassembler::Fail; 3700 case 0: 3701 if (fieldFromInstruction32(Insn, 4, 1)) 3702 return MCDisassembler::Fail; // UNDEFINED 3703 index = fieldFromInstruction32(Insn, 5, 3); 3704 break; 3705 case 1: 3706 if (fieldFromInstruction32(Insn, 4, 1)) 3707 return MCDisassembler::Fail; // UNDEFINED 3708 index = fieldFromInstruction32(Insn, 6, 2); 3709 if (fieldFromInstruction32(Insn, 5, 1)) 3710 inc = 2; 3711 break; 3712 case 2: 3713 if (fieldFromInstruction32(Insn, 4, 2)) 3714 return MCDisassembler::Fail; // UNDEFINED 3715 index = fieldFromInstruction32(Insn, 7, 1); 3716 if (fieldFromInstruction32(Insn, 6, 1)) 3717 inc = 2; 3718 break; 3719 } 3720 3721 if (Rm != 0xF) { // Writeback 3722 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3723 return MCDisassembler::Fail; 3724 } 3725 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3726 return MCDisassembler::Fail; 3727 Inst.addOperand(MCOperand::CreateImm(align)); 3728 if (Rm != 0xF) { 3729 if (Rm != 0xD) { 3730 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3731 return MCDisassembler::Fail; 3732 } else 3733 Inst.addOperand(MCOperand::CreateReg(0)); 3734 } 3735 3736 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3737 return MCDisassembler::Fail; 3738 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3739 return MCDisassembler::Fail; 3740 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3741 return MCDisassembler::Fail; 3742 Inst.addOperand(MCOperand::CreateImm(index)); 3743 3744 return S; 3745 } 3746 3747 3748 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 3749 uint64_t Address, const void *Decoder) { 3750 DecodeStatus S = MCDisassembler::Success; 3751 3752 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3753 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3754 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3755 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3756 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3757 3758 unsigned align = 0; 3759 unsigned index = 0; 3760 unsigned inc = 1; 3761 switch (size) { 3762 default: 3763 return MCDisassembler::Fail; 3764 case 0: 3765 if (fieldFromInstruction32(Insn, 4, 1)) 3766 align = 4; 3767 index = fieldFromInstruction32(Insn, 5, 3); 3768 break; 3769 case 1: 3770 if (fieldFromInstruction32(Insn, 4, 1)) 3771 align = 8; 3772 index = fieldFromInstruction32(Insn, 6, 2); 3773 if (fieldFromInstruction32(Insn, 5, 1)) 3774 inc = 2; 3775 break; 3776 case 2: 3777 if (fieldFromInstruction32(Insn, 4, 2)) 3778 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3779 index = fieldFromInstruction32(Insn, 7, 1); 3780 if (fieldFromInstruction32(Insn, 6, 1)) 3781 inc = 2; 3782 break; 3783 } 3784 3785 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3786 return MCDisassembler::Fail; 3787 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3788 return MCDisassembler::Fail; 3789 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3790 return MCDisassembler::Fail; 3791 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3792 return MCDisassembler::Fail; 3793 3794 if (Rm != 0xF) { // Writeback 3795 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3796 return MCDisassembler::Fail; 3797 } 3798 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3799 return MCDisassembler::Fail; 3800 Inst.addOperand(MCOperand::CreateImm(align)); 3801 if (Rm != 0xF) { 3802 if (Rm != 0xD) { 3803 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3804 return MCDisassembler::Fail; 3805 } else 3806 Inst.addOperand(MCOperand::CreateReg(0)); 3807 } 3808 3809 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3810 return MCDisassembler::Fail; 3811 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3812 return MCDisassembler::Fail; 3813 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3814 return MCDisassembler::Fail; 3815 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3816 return MCDisassembler::Fail; 3817 Inst.addOperand(MCOperand::CreateImm(index)); 3818 3819 return S; 3820 } 3821 3822 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 3823 uint64_t Address, const void *Decoder) { 3824 DecodeStatus S = MCDisassembler::Success; 3825 3826 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3827 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3828 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3829 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3830 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3831 3832 unsigned align = 0; 3833 unsigned index = 0; 3834 unsigned inc = 1; 3835 switch (size) { 3836 default: 3837 return MCDisassembler::Fail; 3838 case 0: 3839 if (fieldFromInstruction32(Insn, 4, 1)) 3840 align = 4; 3841 index = fieldFromInstruction32(Insn, 5, 3); 3842 break; 3843 case 1: 3844 if (fieldFromInstruction32(Insn, 4, 1)) 3845 align = 8; 3846 index = fieldFromInstruction32(Insn, 6, 2); 3847 if (fieldFromInstruction32(Insn, 5, 1)) 3848 inc = 2; 3849 break; 3850 case 2: 3851 if (fieldFromInstruction32(Insn, 4, 2)) 3852 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3853 index = fieldFromInstruction32(Insn, 7, 1); 3854 if (fieldFromInstruction32(Insn, 6, 1)) 3855 inc = 2; 3856 break; 3857 } 3858 3859 if (Rm != 0xF) { // Writeback 3860 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3861 return MCDisassembler::Fail; 3862 } 3863 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3864 return MCDisassembler::Fail; 3865 Inst.addOperand(MCOperand::CreateImm(align)); 3866 if (Rm != 0xF) { 3867 if (Rm != 0xD) { 3868 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3869 return MCDisassembler::Fail; 3870 } else 3871 Inst.addOperand(MCOperand::CreateReg(0)); 3872 } 3873 3874 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3875 return MCDisassembler::Fail; 3876 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3877 return MCDisassembler::Fail; 3878 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3879 return MCDisassembler::Fail; 3880 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3881 return MCDisassembler::Fail; 3882 Inst.addOperand(MCOperand::CreateImm(index)); 3883 3884 return S; 3885 } 3886 3887 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 3888 uint64_t Address, const void *Decoder) { 3889 DecodeStatus S = MCDisassembler::Success; 3890 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3891 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3892 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3893 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3894 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3895 3896 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3897 S = MCDisassembler::SoftFail; 3898 3899 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 3900 return MCDisassembler::Fail; 3901 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 3902 return MCDisassembler::Fail; 3903 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 3904 return MCDisassembler::Fail; 3905 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 3906 return MCDisassembler::Fail; 3907 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3908 return MCDisassembler::Fail; 3909 3910 return S; 3911 } 3912 3913 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 3914 uint64_t Address, const void *Decoder) { 3915 DecodeStatus S = MCDisassembler::Success; 3916 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3917 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3918 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3919 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3920 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3921 3922 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3923 S = MCDisassembler::SoftFail; 3924 3925 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 3926 return MCDisassembler::Fail; 3927 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 3928 return MCDisassembler::Fail; 3929 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 3930 return MCDisassembler::Fail; 3931 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 3932 return MCDisassembler::Fail; 3933 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3934 return MCDisassembler::Fail; 3935 3936 return S; 3937 } 3938 3939 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn, 3940 uint64_t Address, const void *Decoder) { 3941 DecodeStatus S = MCDisassembler::Success; 3942 unsigned pred = fieldFromInstruction16(Insn, 4, 4); 3943 // The InstPrinter needs to have the low bit of the predicate in 3944 // the mask operand to be able to print it properly. 3945 unsigned mask = fieldFromInstruction16(Insn, 0, 5); 3946 3947 if (pred == 0xF) { 3948 pred = 0xE; 3949 S = MCDisassembler::SoftFail; 3950 } 3951 3952 if ((mask & 0xF) == 0) { 3953 // Preserve the high bit of the mask, which is the low bit of 3954 // the predicate. 3955 mask &= 0x10; 3956 mask |= 0x8; 3957 S = MCDisassembler::SoftFail; 3958 } 3959 3960 Inst.addOperand(MCOperand::CreateImm(pred)); 3961 Inst.addOperand(MCOperand::CreateImm(mask)); 3962 return S; 3963 } 3964 3965 static DecodeStatus 3966 DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, 3967 uint64_t Address, const void *Decoder) { 3968 DecodeStatus S = MCDisassembler::Success; 3969 3970 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3971 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 3972 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3973 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 3974 unsigned W = fieldFromInstruction32(Insn, 21, 1); 3975 unsigned U = fieldFromInstruction32(Insn, 23, 1); 3976 unsigned P = fieldFromInstruction32(Insn, 24, 1); 3977 bool writeback = (W == 1) | (P == 0); 3978 3979 addr |= (U << 8) | (Rn << 9); 3980 3981 if (writeback && (Rn == Rt || Rn == Rt2)) 3982 Check(S, MCDisassembler::SoftFail); 3983 if (Rt == Rt2) 3984 Check(S, MCDisassembler::SoftFail); 3985 3986 // Rt 3987 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3988 return MCDisassembler::Fail; 3989 // Rt2 3990 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 3991 return MCDisassembler::Fail; 3992 // Writeback operand 3993 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 3994 return MCDisassembler::Fail; 3995 // addr 3996 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 3997 return MCDisassembler::Fail; 3998 3999 return S; 4000 } 4001 4002 static DecodeStatus 4003 DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, 4004 uint64_t Address, const void *Decoder) { 4005 DecodeStatus S = MCDisassembler::Success; 4006 4007 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4008 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 4009 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4010 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 4011 unsigned W = fieldFromInstruction32(Insn, 21, 1); 4012 unsigned U = fieldFromInstruction32(Insn, 23, 1); 4013 unsigned P = fieldFromInstruction32(Insn, 24, 1); 4014 bool writeback = (W == 1) | (P == 0); 4015 4016 addr |= (U << 8) | (Rn << 9); 4017 4018 if (writeback && (Rn == Rt || Rn == Rt2)) 4019 Check(S, MCDisassembler::SoftFail); 4020 4021 // Writeback operand 4022 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4023 return MCDisassembler::Fail; 4024 // Rt 4025 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4026 return MCDisassembler::Fail; 4027 // Rt2 4028 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4029 return MCDisassembler::Fail; 4030 // addr 4031 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4032 return MCDisassembler::Fail; 4033 4034 return S; 4035 } 4036 4037 static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn, 4038 uint64_t Address, const void *Decoder) { 4039 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1); 4040 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1); 4041 if (sign1 != sign2) return MCDisassembler::Fail; 4042 4043 unsigned Val = fieldFromInstruction32(Insn, 0, 8); 4044 Val |= fieldFromInstruction32(Insn, 12, 3) << 8; 4045 Val |= fieldFromInstruction32(Insn, 26, 1) << 11; 4046 Val |= sign1 << 12; 4047 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 4048 4049 return MCDisassembler::Success; 4050 } 4051 4052 static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, uint32_t Val, 4053 uint64_t Address, 4054 const void *Decoder) { 4055 DecodeStatus S = MCDisassembler::Success; 4056 4057 // Shift of "asr #32" is not allowed in Thumb2 mode. 4058 if (Val == 0x20) S = MCDisassembler::SoftFail; 4059 Inst.addOperand(MCOperand::CreateImm(Val)); 4060 return S; 4061 } 4062 4063 static DecodeStatus DecodeSwap(llvm::MCInst &Inst, unsigned Insn, 4064 uint64_t Address, const void *Decoder) { 4065 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4066 unsigned Rt2 = fieldFromInstruction32(Insn, 0, 4); 4067 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4068 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 4069 4070 if (pred == 0xF) 4071 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 4072 4073 DecodeStatus S = MCDisassembler::Success; 4074 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4075 return MCDisassembler::Fail; 4076 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4077 return MCDisassembler::Fail; 4078 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4079 return MCDisassembler::Fail; 4080 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4081 return MCDisassembler::Fail; 4082 4083 return S; 4084 } 4085 4086 static DecodeStatus DecodeVCVTD(llvm::MCInst &Inst, unsigned Insn, 4087 uint64_t Address, const void *Decoder) { 4088 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0); 4089 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4); 4090 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0); 4091 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4); 4092 unsigned imm = fieldFromInstruction32(Insn, 16, 6); 4093 unsigned cmode = fieldFromInstruction32(Insn, 8, 4); 4094 4095 DecodeStatus S = MCDisassembler::Success; 4096 4097 // VMOVv2f32 is ambiguous with these decodings. 4098 if (!(imm & 0x38 && cmode == 0xF)) { 4099 Inst.setOpcode(ARM::VMOVv2f32); 4100 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4101 } 4102 4103 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4104 4105 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 4106 return MCDisassembler::Fail; 4107 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 4108 return MCDisassembler::Fail; 4109 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4110 4111 return S; 4112 } 4113 4114 static DecodeStatus DecodeVCVTQ(llvm::MCInst &Inst, unsigned Insn, 4115 uint64_t Address, const void *Decoder) { 4116 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0); 4117 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4); 4118 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0); 4119 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4); 4120 unsigned imm = fieldFromInstruction32(Insn, 16, 6); 4121 unsigned cmode = fieldFromInstruction32(Insn, 8, 4); 4122 4123 DecodeStatus S = MCDisassembler::Success; 4124 4125 // VMOVv4f32 is ambiguous with these decodings. 4126 if (!(imm & 0x38) && cmode == 0xF) { 4127 Inst.setOpcode(ARM::VMOVv4f32); 4128 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4129 } 4130 4131 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4132 4133 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 4134 return MCDisassembler::Fail; 4135 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 4136 return MCDisassembler::Fail; 4137 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4138 4139 return S; 4140 } 4141 4142