1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "llvm/MC/MCDisassembler.h" 13 #include "MCTargetDesc/ARMAddressingModes.h" 14 #include "MCTargetDesc/ARMBaseInfo.h" 15 #include "MCTargetDesc/ARMMCExpr.h" 16 #include "llvm/MC/MCContext.h" 17 #include "llvm/MC/MCExpr.h" 18 #include "llvm/MC/MCFixedLenDisassembler.h" 19 #include "llvm/MC/MCInst.h" 20 #include "llvm/MC/MCInstrDesc.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/LEB128.h" 25 #include "llvm/Support/MemoryObject.h" 26 #include "llvm/Support/TargetRegistry.h" 27 #include "llvm/Support/raw_ostream.h" 28 #include <vector> 29 30 using namespace llvm; 31 32 typedef MCDisassembler::DecodeStatus DecodeStatus; 33 34 namespace { 35 // Handles the condition code status of instructions in IT blocks 36 class ITStatus 37 { 38 public: 39 // Returns the condition code for instruction in IT block 40 unsigned getITCC() { 41 unsigned CC = ARMCC::AL; 42 if (instrInITBlock()) 43 CC = ITStates.back(); 44 return CC; 45 } 46 47 // Advances the IT block state to the next T or E 48 void advanceITState() { 49 ITStates.pop_back(); 50 } 51 52 // Returns true if the current instruction is in an IT block 53 bool instrInITBlock() { 54 return !ITStates.empty(); 55 } 56 57 // Returns true if current instruction is the last instruction in an IT block 58 bool instrLastInITBlock() { 59 return ITStates.size() == 1; 60 } 61 62 // Called when decoding an IT instruction. Sets the IT state for the following 63 // instructions that for the IT block. Firstcond and Mask correspond to the 64 // fields in the IT instruction encoding. 65 void setITState(char Firstcond, char Mask) { 66 // (3 - the number of trailing zeros) is the number of then / else. 67 unsigned CondBit0 = Firstcond & 1; 68 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 69 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 70 assert(NumTZ <= 3 && "Invalid IT mask!"); 71 // push condition codes onto the stack the correct order for the pops 72 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 73 bool T = ((Mask >> Pos) & 1) == CondBit0; 74 if (T) 75 ITStates.push_back(CCBits); 76 else 77 ITStates.push_back(CCBits ^ 1); 78 } 79 ITStates.push_back(CCBits); 80 } 81 82 private: 83 std::vector<unsigned char> ITStates; 84 }; 85 } 86 87 namespace { 88 /// ARMDisassembler - ARM disassembler for all ARM platforms. 89 class ARMDisassembler : public MCDisassembler { 90 public: 91 /// Constructor - Initializes the disassembler. 92 /// 93 ARMDisassembler(const MCSubtargetInfo &STI) : 94 MCDisassembler(STI) { 95 } 96 97 ~ARMDisassembler() { 98 } 99 100 /// getInstruction - See MCDisassembler. 101 DecodeStatus getInstruction(MCInst &instr, 102 uint64_t &size, 103 const MemoryObject ®ion, 104 uint64_t address, 105 raw_ostream &vStream, 106 raw_ostream &cStream) const; 107 }; 108 109 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 110 class ThumbDisassembler : public MCDisassembler { 111 public: 112 /// Constructor - Initializes the disassembler. 113 /// 114 ThumbDisassembler(const MCSubtargetInfo &STI) : 115 MCDisassembler(STI) { 116 } 117 118 ~ThumbDisassembler() { 119 } 120 121 /// getInstruction - See MCDisassembler. 122 DecodeStatus getInstruction(MCInst &instr, 123 uint64_t &size, 124 const MemoryObject ®ion, 125 uint64_t address, 126 raw_ostream &vStream, 127 raw_ostream &cStream) const; 128 129 private: 130 mutable ITStatus ITBlock; 131 DecodeStatus AddThumbPredicate(MCInst&) const; 132 void UpdateThumbVFPPredicate(MCInst&) const; 133 }; 134 } 135 136 static bool Check(DecodeStatus &Out, DecodeStatus In) { 137 switch (In) { 138 case MCDisassembler::Success: 139 // Out stays the same. 140 return true; 141 case MCDisassembler::SoftFail: 142 Out = In; 143 return true; 144 case MCDisassembler::Fail: 145 Out = In; 146 return false; 147 } 148 llvm_unreachable("Invalid DecodeStatus!"); 149 } 150 151 152 // Forward declare these because the autogenerated code will reference them. 153 // Definitions are further down. 154 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 155 uint64_t Address, const void *Decoder); 156 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 157 unsigned RegNo, uint64_t Address, 158 const void *Decoder); 159 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 160 unsigned RegNo, uint64_t Address, 161 const void *Decoder); 162 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 163 uint64_t Address, const void *Decoder); 164 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 165 uint64_t Address, const void *Decoder); 166 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 167 uint64_t Address, const void *Decoder); 168 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 169 uint64_t Address, const void *Decoder); 170 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 171 uint64_t Address, const void *Decoder); 172 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 173 uint64_t Address, const void *Decoder); 174 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 175 uint64_t Address, const void *Decoder); 176 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 177 unsigned RegNo, 178 uint64_t Address, 179 const void *Decoder); 180 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 181 uint64_t Address, const void *Decoder); 182 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 183 uint64_t Address, const void *Decoder); 184 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 185 unsigned RegNo, uint64_t Address, 186 const void *Decoder); 187 188 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 193 uint64_t Address, const void *Decoder); 194 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 195 uint64_t Address, const void *Decoder); 196 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 197 uint64_t Address, const void *Decoder); 198 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 199 uint64_t Address, const void *Decoder); 200 201 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 204 uint64_t Address, const void *Decoder); 205 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 206 unsigned Insn, 207 uint64_t Address, 208 const void *Decoder); 209 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 214 uint64_t Address, const void *Decoder); 215 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 216 uint64_t Address, const void *Decoder); 217 218 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 219 unsigned Insn, 220 uint64_t Adddress, 221 const void *Decoder); 222 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 223 uint64_t Address, const void *Decoder); 224 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 225 uint64_t Address, const void *Decoder); 226 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 227 uint64_t Address, const void *Decoder); 228 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 229 uint64_t Address, const void *Decoder); 230 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 231 uint64_t Address, const void *Decoder); 232 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 233 uint64_t Address, const void *Decoder); 234 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 235 uint64_t Address, const void *Decoder); 236 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 237 uint64_t Address, const void *Decoder); 238 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 239 uint64_t Address, const void *Decoder); 240 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 241 uint64_t Address, const void *Decoder); 242 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 243 uint64_t Address, const void *Decoder); 244 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 245 uint64_t Address, const void *Decoder); 246 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 247 uint64_t Address, const void *Decoder); 248 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 255 uint64_t Address, const void *Decoder); 256 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 257 uint64_t Address, const void *Decoder); 258 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 259 uint64_t Address, const void *Decoder); 260 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 261 uint64_t Address, const void *Decoder); 262 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 263 uint64_t Address, const void *Decoder); 264 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 265 uint64_t Address, const void *Decoder); 266 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 269 uint64_t Address, const void *Decoder); 270 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 309 uint64_t Address, const void *Decoder); 310 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 311 uint64_t Address, const void *Decoder); 312 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 313 uint64_t Address, const void *Decoder); 314 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 315 uint64_t Address, const void *Decoder); 316 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 317 uint64_t Address, const void *Decoder); 318 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 319 uint64_t Address, const void *Decoder); 320 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 321 uint64_t Address, const void *Decoder); 322 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 323 uint64_t Address, const void *Decoder); 324 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 325 uint64_t Address, const void *Decoder); 326 327 328 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 329 uint64_t Address, const void *Decoder); 330 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 331 uint64_t Address, const void *Decoder); 332 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 333 uint64_t Address, const void *Decoder); 334 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 335 uint64_t Address, const void *Decoder); 336 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 337 uint64_t Address, const void *Decoder); 338 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 339 uint64_t Address, const void *Decoder); 340 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 341 uint64_t Address, const void *Decoder); 342 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 343 uint64_t Address, const void *Decoder); 344 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 345 uint64_t Address, const void *Decoder); 346 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 347 uint64_t Address, const void *Decoder); 348 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 349 uint64_t Address, const void* Decoder); 350 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 351 uint64_t Address, const void* Decoder); 352 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 353 uint64_t Address, const void* Decoder); 354 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 355 uint64_t Address, const void* Decoder); 356 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 357 uint64_t Address, const void *Decoder); 358 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 359 uint64_t Address, const void *Decoder); 360 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 361 uint64_t Address, const void *Decoder); 362 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 363 uint64_t Address, const void *Decoder); 364 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 365 uint64_t Address, const void *Decoder); 366 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 367 uint64_t Address, const void *Decoder); 368 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 369 uint64_t Address, const void *Decoder); 370 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 371 uint64_t Address, const void *Decoder); 372 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 373 uint64_t Address, const void *Decoder); 374 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 375 uint64_t Address, const void *Decoder); 376 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 377 uint64_t Address, const void *Decoder); 378 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 379 uint64_t Address, const void *Decoder); 380 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 381 uint64_t Address, const void *Decoder); 382 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 383 uint64_t Address, const void *Decoder); 384 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 385 uint64_t Address, const void *Decoder); 386 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 387 uint64_t Address, const void *Decoder); 388 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 389 uint64_t Address, const void *Decoder); 390 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 391 uint64_t Address, const void *Decoder); 392 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 393 uint64_t Address, const void *Decoder); 394 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 395 uint64_t Address, const void *Decoder); 396 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 397 uint64_t Address, const void *Decoder); 398 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 399 uint64_t Address, const void *Decoder); 400 401 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 402 uint64_t Address, const void *Decoder); 403 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 404 uint64_t Address, const void *Decoder); 405 #include "ARMGenDisassemblerTables.inc" 406 407 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 408 return new ARMDisassembler(STI); 409 } 410 411 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 412 return new ThumbDisassembler(STI); 413 } 414 415 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 416 const MemoryObject &Region, 417 uint64_t Address, 418 raw_ostream &os, 419 raw_ostream &cs) const { 420 CommentStream = &cs; 421 422 uint8_t bytes[4]; 423 424 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 425 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 426 427 // We want to read exactly 4 bytes of data. 428 if (Region.readBytes(Address, 4, bytes) == -1) { 429 Size = 0; 430 return MCDisassembler::Fail; 431 } 432 433 // Encoded as a small-endian 32-bit word in the stream. 434 uint32_t insn = (bytes[3] << 24) | 435 (bytes[2] << 16) | 436 (bytes[1] << 8) | 437 (bytes[0] << 0); 438 439 // Calling the auto-generated decoder function. 440 DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn, 441 Address, this, STI); 442 if (result != MCDisassembler::Fail) { 443 Size = 4; 444 return result; 445 } 446 447 // VFP and NEON instructions, similarly, are shared between ARM 448 // and Thumb modes. 449 MI.clear(); 450 result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI); 451 if (result != MCDisassembler::Fail) { 452 Size = 4; 453 return result; 454 } 455 456 MI.clear(); 457 result = decodeInstruction(DecoderTableVFPV832, MI, insn, Address, this, STI); 458 if (result != MCDisassembler::Fail) { 459 Size = 4; 460 return result; 461 } 462 463 MI.clear(); 464 result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address, 465 this, STI); 466 if (result != MCDisassembler::Fail) { 467 Size = 4; 468 // Add a fake predicate operand, because we share these instruction 469 // definitions with Thumb2 where these instructions are predicable. 470 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 471 return MCDisassembler::Fail; 472 return result; 473 } 474 475 MI.clear(); 476 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address, 477 this, STI); 478 if (result != MCDisassembler::Fail) { 479 Size = 4; 480 // Add a fake predicate operand, because we share these instruction 481 // definitions with Thumb2 where these instructions are predicable. 482 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 483 return MCDisassembler::Fail; 484 return result; 485 } 486 487 MI.clear(); 488 result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address, 489 this, STI); 490 if (result != MCDisassembler::Fail) { 491 Size = 4; 492 // Add a fake predicate operand, because we share these instruction 493 // definitions with Thumb2 where these instructions are predicable. 494 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 495 return MCDisassembler::Fail; 496 return result; 497 } 498 499 MI.clear(); 500 result = decodeInstruction(DecoderTablev8NEON32, MI, insn, Address, 501 this, STI); 502 if (result != MCDisassembler::Fail) { 503 Size = 4; 504 return result; 505 } 506 507 MI.clear(); 508 result = decodeInstruction(DecoderTablev8Crypto32, MI, insn, Address, 509 this, STI); 510 if (result != MCDisassembler::Fail) { 511 Size = 4; 512 return result; 513 } 514 515 MI.clear(); 516 Size = 0; 517 return MCDisassembler::Fail; 518 } 519 520 namespace llvm { 521 extern const MCInstrDesc ARMInsts[]; 522 } 523 524 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 525 /// immediate Value in the MCInst. The immediate Value has had any PC 526 /// adjustment made by the caller. If the instruction is a branch instruction 527 /// then isBranch is true, else false. If the getOpInfo() function was set as 528 /// part of the setupForSymbolicDisassembly() call then that function is called 529 /// to get any symbolic information at the Address for this instruction. If 530 /// that returns non-zero then the symbolic information it returns is used to 531 /// create an MCExpr and that is added as an operand to the MCInst. If 532 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 533 /// Value is done and if a symbol is found an MCExpr is created with that, else 534 /// an MCExpr with Value is created. This function returns true if it adds an 535 /// operand to the MCInst and false otherwise. 536 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 537 bool isBranch, uint64_t InstSize, 538 MCInst &MI, const void *Decoder) { 539 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 540 // FIXME: Does it make sense for value to be negative? 541 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 542 /* Offset */ 0, InstSize); 543 } 544 545 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 546 /// referenced by a load instruction with the base register that is the Pc. 547 /// These can often be values in a literal pool near the Address of the 548 /// instruction. The Address of the instruction and its immediate Value are 549 /// used as a possible literal pool entry. The SymbolLookUp call back will 550 /// return the name of a symbol referenced by the literal pool's entry if 551 /// the referenced address is that of a symbol. Or it will return a pointer to 552 /// a literal 'C' string if the referenced address of the literal pool's entry 553 /// is an address into a section with 'C' string literals. 554 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 555 const void *Decoder) { 556 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 557 Dis->tryAddingPcLoadReferenceComment(Value, Address); 558 } 559 560 // Thumb1 instructions don't have explicit S bits. Rather, they 561 // implicitly set CPSR. Since it's not represented in the encoding, the 562 // auto-generated decoder won't inject the CPSR operand. We need to fix 563 // that as a post-pass. 564 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 565 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 566 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 567 MCInst::iterator I = MI.begin(); 568 for (unsigned i = 0; i < NumOps; ++i, ++I) { 569 if (I == MI.end()) break; 570 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 571 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 572 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 573 return; 574 } 575 } 576 577 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 578 } 579 580 // Most Thumb instructions don't have explicit predicates in the 581 // encoding, but rather get their predicates from IT context. We need 582 // to fix up the predicate operands using this context information as a 583 // post-pass. 584 MCDisassembler::DecodeStatus 585 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 586 MCDisassembler::DecodeStatus S = Success; 587 588 // A few instructions actually have predicates encoded in them. Don't 589 // try to overwrite it if we're seeing one of those. 590 switch (MI.getOpcode()) { 591 case ARM::tBcc: 592 case ARM::t2Bcc: 593 case ARM::tCBZ: 594 case ARM::tCBNZ: 595 case ARM::tCPS: 596 case ARM::t2CPS3p: 597 case ARM::t2CPS2p: 598 case ARM::t2CPS1p: 599 case ARM::tMOVSr: 600 case ARM::tSETEND: 601 // Some instructions (mostly conditional branches) are not 602 // allowed in IT blocks. 603 if (ITBlock.instrInITBlock()) 604 S = SoftFail; 605 else 606 return Success; 607 break; 608 case ARM::tB: 609 case ARM::t2B: 610 case ARM::t2TBB: 611 case ARM::t2TBH: 612 // Some instructions (mostly unconditional branches) can 613 // only appears at the end of, or outside of, an IT. 614 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 615 S = SoftFail; 616 break; 617 default: 618 break; 619 } 620 621 // If we're in an IT block, base the predicate on that. Otherwise, 622 // assume a predicate of AL. 623 unsigned CC; 624 CC = ITBlock.getITCC(); 625 if (CC == 0xF) 626 CC = ARMCC::AL; 627 if (ITBlock.instrInITBlock()) 628 ITBlock.advanceITState(); 629 630 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 631 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 632 MCInst::iterator I = MI.begin(); 633 for (unsigned i = 0; i < NumOps; ++i, ++I) { 634 if (I == MI.end()) break; 635 if (OpInfo[i].isPredicate()) { 636 I = MI.insert(I, MCOperand::CreateImm(CC)); 637 ++I; 638 if (CC == ARMCC::AL) 639 MI.insert(I, MCOperand::CreateReg(0)); 640 else 641 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 642 return S; 643 } 644 } 645 646 I = MI.insert(I, MCOperand::CreateImm(CC)); 647 ++I; 648 if (CC == ARMCC::AL) 649 MI.insert(I, MCOperand::CreateReg(0)); 650 else 651 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 652 653 return S; 654 } 655 656 // Thumb VFP instructions are a special case. Because we share their 657 // encodings between ARM and Thumb modes, and they are predicable in ARM 658 // mode, the auto-generated decoder will give them an (incorrect) 659 // predicate operand. We need to rewrite these operands based on the IT 660 // context as a post-pass. 661 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 662 unsigned CC; 663 CC = ITBlock.getITCC(); 664 if (ITBlock.instrInITBlock()) 665 ITBlock.advanceITState(); 666 667 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 668 MCInst::iterator I = MI.begin(); 669 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 670 for (unsigned i = 0; i < NumOps; ++i, ++I) { 671 if (OpInfo[i].isPredicate() ) { 672 I->setImm(CC); 673 ++I; 674 if (CC == ARMCC::AL) 675 I->setReg(0); 676 else 677 I->setReg(ARM::CPSR); 678 return; 679 } 680 } 681 } 682 683 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 684 const MemoryObject &Region, 685 uint64_t Address, 686 raw_ostream &os, 687 raw_ostream &cs) const { 688 CommentStream = &cs; 689 690 uint8_t bytes[4]; 691 692 assert((STI.getFeatureBits() & ARM::ModeThumb) && 693 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 694 695 // We want to read exactly 2 bytes of data. 696 if (Region.readBytes(Address, 2, bytes) == -1) { 697 Size = 0; 698 return MCDisassembler::Fail; 699 } 700 701 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 702 DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16, 703 Address, this, STI); 704 if (result != MCDisassembler::Fail) { 705 Size = 2; 706 Check(result, AddThumbPredicate(MI)); 707 return result; 708 } 709 710 MI.clear(); 711 result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16, 712 Address, this, STI); 713 if (result) { 714 Size = 2; 715 bool InITBlock = ITBlock.instrInITBlock(); 716 Check(result, AddThumbPredicate(MI)); 717 AddThumb1SBit(MI, InITBlock); 718 return result; 719 } 720 721 MI.clear(); 722 result = decodeInstruction(DecoderTableThumb216, MI, insn16, 723 Address, this, STI); 724 if (result != MCDisassembler::Fail) { 725 Size = 2; 726 727 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 728 // the Thumb predicate. 729 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 730 result = MCDisassembler::SoftFail; 731 732 Check(result, AddThumbPredicate(MI)); 733 734 // If we find an IT instruction, we need to parse its condition 735 // code and mask operands so that we can apply them correctly 736 // to the subsequent instructions. 737 if (MI.getOpcode() == ARM::t2IT) { 738 739 unsigned Firstcond = MI.getOperand(0).getImm(); 740 unsigned Mask = MI.getOperand(1).getImm(); 741 ITBlock.setITState(Firstcond, Mask); 742 } 743 744 return result; 745 } 746 747 // We want to read exactly 4 bytes of data. 748 if (Region.readBytes(Address, 4, bytes) == -1) { 749 Size = 0; 750 return MCDisassembler::Fail; 751 } 752 753 uint32_t insn32 = (bytes[3] << 8) | 754 (bytes[2] << 0) | 755 (bytes[1] << 24) | 756 (bytes[0] << 16); 757 MI.clear(); 758 result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address, 759 this, STI); 760 if (result != MCDisassembler::Fail) { 761 Size = 4; 762 bool InITBlock = ITBlock.instrInITBlock(); 763 Check(result, AddThumbPredicate(MI)); 764 AddThumb1SBit(MI, InITBlock); 765 return result; 766 } 767 768 MI.clear(); 769 result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address, 770 this, STI); 771 if (result != MCDisassembler::Fail) { 772 Size = 4; 773 Check(result, AddThumbPredicate(MI)); 774 return result; 775 } 776 777 if (fieldFromInstruction(insn32, 28, 4) == 0xE) { 778 MI.clear(); 779 result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI); 780 if (result != MCDisassembler::Fail) { 781 Size = 4; 782 UpdateThumbVFPPredicate(MI); 783 return result; 784 } 785 } 786 787 MI.clear(); 788 result = decodeInstruction(DecoderTableVFPV832, MI, insn32, Address, this, STI); 789 if (result != MCDisassembler::Fail) { 790 Size = 4; 791 return result; 792 } 793 794 if (fieldFromInstruction(insn32, 28, 4) == 0xE) { 795 MI.clear(); 796 result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address, 797 this, STI); 798 if (result != MCDisassembler::Fail) { 799 Size = 4; 800 Check(result, AddThumbPredicate(MI)); 801 return result; 802 } 803 } 804 805 if (fieldFromInstruction(insn32, 24, 8) == 0xF9) { 806 MI.clear(); 807 uint32_t NEONLdStInsn = insn32; 808 NEONLdStInsn &= 0xF0FFFFFF; 809 NEONLdStInsn |= 0x04000000; 810 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 811 Address, this, STI); 812 if (result != MCDisassembler::Fail) { 813 Size = 4; 814 Check(result, AddThumbPredicate(MI)); 815 return result; 816 } 817 } 818 819 if (fieldFromInstruction(insn32, 24, 4) == 0xF) { 820 MI.clear(); 821 uint32_t NEONDataInsn = insn32; 822 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 823 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 824 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 825 result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 826 Address, this, STI); 827 if (result != MCDisassembler::Fail) { 828 Size = 4; 829 Check(result, AddThumbPredicate(MI)); 830 return result; 831 } 832 } 833 834 MI.clear(); 835 uint32_t NEONCryptoInsn = insn32; 836 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 837 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 838 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 839 result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 840 Address, this, STI); 841 if (result != MCDisassembler::Fail) { 842 Size = 4; 843 return result; 844 } 845 846 MI.clear(); 847 uint32_t NEONv8Insn = insn32; 848 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 849 result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 850 this, STI); 851 if (result != MCDisassembler::Fail) { 852 Size = 4; 853 return result; 854 } 855 856 MI.clear(); 857 Size = 0; 858 return MCDisassembler::Fail; 859 } 860 861 862 extern "C" void LLVMInitializeARMDisassembler() { 863 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 864 createARMDisassembler); 865 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 866 createThumbDisassembler); 867 } 868 869 static const uint16_t GPRDecoderTable[] = { 870 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 871 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 872 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 873 ARM::R12, ARM::SP, ARM::LR, ARM::PC 874 }; 875 876 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 877 uint64_t Address, const void *Decoder) { 878 if (RegNo > 15) 879 return MCDisassembler::Fail; 880 881 unsigned Register = GPRDecoderTable[RegNo]; 882 Inst.addOperand(MCOperand::CreateReg(Register)); 883 return MCDisassembler::Success; 884 } 885 886 static DecodeStatus 887 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 888 uint64_t Address, const void *Decoder) { 889 DecodeStatus S = MCDisassembler::Success; 890 891 if (RegNo == 15) 892 S = MCDisassembler::SoftFail; 893 894 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 895 896 return S; 897 } 898 899 static DecodeStatus 900 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 901 uint64_t Address, const void *Decoder) { 902 DecodeStatus S = MCDisassembler::Success; 903 904 if (RegNo == 15) 905 { 906 Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV)); 907 return MCDisassembler::Success; 908 } 909 910 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 911 return S; 912 } 913 914 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 915 uint64_t Address, const void *Decoder) { 916 if (RegNo > 7) 917 return MCDisassembler::Fail; 918 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 919 } 920 921 static const uint16_t GPRPairDecoderTable[] = { 922 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 923 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 924 }; 925 926 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 927 uint64_t Address, const void *Decoder) { 928 DecodeStatus S = MCDisassembler::Success; 929 930 if (RegNo > 13) 931 return MCDisassembler::Fail; 932 933 if ((RegNo & 1) || RegNo == 0xe) 934 S = MCDisassembler::SoftFail; 935 936 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 937 Inst.addOperand(MCOperand::CreateReg(RegisterPair)); 938 return S; 939 } 940 941 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 942 uint64_t Address, const void *Decoder) { 943 unsigned Register = 0; 944 switch (RegNo) { 945 case 0: 946 Register = ARM::R0; 947 break; 948 case 1: 949 Register = ARM::R1; 950 break; 951 case 2: 952 Register = ARM::R2; 953 break; 954 case 3: 955 Register = ARM::R3; 956 break; 957 case 9: 958 Register = ARM::R9; 959 break; 960 case 12: 961 Register = ARM::R12; 962 break; 963 default: 964 return MCDisassembler::Fail; 965 } 966 967 Inst.addOperand(MCOperand::CreateReg(Register)); 968 return MCDisassembler::Success; 969 } 970 971 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 972 uint64_t Address, const void *Decoder) { 973 DecodeStatus S = MCDisassembler::Success; 974 if (RegNo == 13 || RegNo == 15) 975 S = MCDisassembler::SoftFail; 976 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 977 return S; 978 } 979 980 static const uint16_t SPRDecoderTable[] = { 981 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 982 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 983 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 984 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 985 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 986 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 987 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 988 ARM::S28, ARM::S29, ARM::S30, ARM::S31 989 }; 990 991 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 992 uint64_t Address, const void *Decoder) { 993 if (RegNo > 31) 994 return MCDisassembler::Fail; 995 996 unsigned Register = SPRDecoderTable[RegNo]; 997 Inst.addOperand(MCOperand::CreateReg(Register)); 998 return MCDisassembler::Success; 999 } 1000 1001 static const uint16_t DPRDecoderTable[] = { 1002 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1003 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1004 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1005 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1006 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1007 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1008 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1009 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1010 }; 1011 1012 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1013 uint64_t Address, const void *Decoder) { 1014 if (RegNo > 31) 1015 return MCDisassembler::Fail; 1016 1017 unsigned Register = DPRDecoderTable[RegNo]; 1018 Inst.addOperand(MCOperand::CreateReg(Register)); 1019 return MCDisassembler::Success; 1020 } 1021 1022 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1023 uint64_t Address, const void *Decoder) { 1024 if (RegNo > 7) 1025 return MCDisassembler::Fail; 1026 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1027 } 1028 1029 static DecodeStatus 1030 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1031 uint64_t Address, const void *Decoder) { 1032 if (RegNo > 15) 1033 return MCDisassembler::Fail; 1034 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1035 } 1036 1037 static const uint16_t QPRDecoderTable[] = { 1038 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1039 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1040 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1041 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1042 }; 1043 1044 1045 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1046 uint64_t Address, const void *Decoder) { 1047 if (RegNo > 31 || (RegNo & 1) != 0) 1048 return MCDisassembler::Fail; 1049 RegNo >>= 1; 1050 1051 unsigned Register = QPRDecoderTable[RegNo]; 1052 Inst.addOperand(MCOperand::CreateReg(Register)); 1053 return MCDisassembler::Success; 1054 } 1055 1056 static const uint16_t DPairDecoderTable[] = { 1057 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1058 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1059 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1060 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1061 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1062 ARM::Q15 1063 }; 1064 1065 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1066 uint64_t Address, const void *Decoder) { 1067 if (RegNo > 30) 1068 return MCDisassembler::Fail; 1069 1070 unsigned Register = DPairDecoderTable[RegNo]; 1071 Inst.addOperand(MCOperand::CreateReg(Register)); 1072 return MCDisassembler::Success; 1073 } 1074 1075 static const uint16_t DPairSpacedDecoderTable[] = { 1076 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1077 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1078 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1079 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1080 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1081 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1082 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1083 ARM::D28_D30, ARM::D29_D31 1084 }; 1085 1086 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1087 unsigned RegNo, 1088 uint64_t Address, 1089 const void *Decoder) { 1090 if (RegNo > 29) 1091 return MCDisassembler::Fail; 1092 1093 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1094 Inst.addOperand(MCOperand::CreateReg(Register)); 1095 return MCDisassembler::Success; 1096 } 1097 1098 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1099 uint64_t Address, const void *Decoder) { 1100 if (Val == 0xF) return MCDisassembler::Fail; 1101 // AL predicate is not allowed on Thumb1 branches. 1102 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1103 return MCDisassembler::Fail; 1104 Inst.addOperand(MCOperand::CreateImm(Val)); 1105 if (Val == ARMCC::AL) { 1106 Inst.addOperand(MCOperand::CreateReg(0)); 1107 } else 1108 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1109 return MCDisassembler::Success; 1110 } 1111 1112 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1113 uint64_t Address, const void *Decoder) { 1114 if (Val) 1115 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1116 else 1117 Inst.addOperand(MCOperand::CreateReg(0)); 1118 return MCDisassembler::Success; 1119 } 1120 1121 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 1122 uint64_t Address, const void *Decoder) { 1123 uint32_t imm = Val & 0xFF; 1124 uint32_t rot = (Val & 0xF00) >> 7; 1125 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 1126 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 1127 return MCDisassembler::Success; 1128 } 1129 1130 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1131 uint64_t Address, const void *Decoder) { 1132 DecodeStatus S = MCDisassembler::Success; 1133 1134 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1135 unsigned type = fieldFromInstruction(Val, 5, 2); 1136 unsigned imm = fieldFromInstruction(Val, 7, 5); 1137 1138 // Register-immediate 1139 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1140 return MCDisassembler::Fail; 1141 1142 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1143 switch (type) { 1144 case 0: 1145 Shift = ARM_AM::lsl; 1146 break; 1147 case 1: 1148 Shift = ARM_AM::lsr; 1149 break; 1150 case 2: 1151 Shift = ARM_AM::asr; 1152 break; 1153 case 3: 1154 Shift = ARM_AM::ror; 1155 break; 1156 } 1157 1158 if (Shift == ARM_AM::ror && imm == 0) 1159 Shift = ARM_AM::rrx; 1160 1161 unsigned Op = Shift | (imm << 3); 1162 Inst.addOperand(MCOperand::CreateImm(Op)); 1163 1164 return S; 1165 } 1166 1167 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1168 uint64_t Address, const void *Decoder) { 1169 DecodeStatus S = MCDisassembler::Success; 1170 1171 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1172 unsigned type = fieldFromInstruction(Val, 5, 2); 1173 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1174 1175 // Register-register 1176 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1177 return MCDisassembler::Fail; 1178 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1179 return MCDisassembler::Fail; 1180 1181 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1182 switch (type) { 1183 case 0: 1184 Shift = ARM_AM::lsl; 1185 break; 1186 case 1: 1187 Shift = ARM_AM::lsr; 1188 break; 1189 case 2: 1190 Shift = ARM_AM::asr; 1191 break; 1192 case 3: 1193 Shift = ARM_AM::ror; 1194 break; 1195 } 1196 1197 Inst.addOperand(MCOperand::CreateImm(Shift)); 1198 1199 return S; 1200 } 1201 1202 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1203 uint64_t Address, const void *Decoder) { 1204 DecodeStatus S = MCDisassembler::Success; 1205 1206 bool NeedDisjointWriteback = false; 1207 unsigned WritebackReg = 0; 1208 switch (Inst.getOpcode()) { 1209 default: 1210 break; 1211 case ARM::LDMIA_UPD: 1212 case ARM::LDMDB_UPD: 1213 case ARM::LDMIB_UPD: 1214 case ARM::LDMDA_UPD: 1215 case ARM::t2LDMIA_UPD: 1216 case ARM::t2LDMDB_UPD: 1217 case ARM::t2STMIA_UPD: 1218 case ARM::t2STMDB_UPD: 1219 NeedDisjointWriteback = true; 1220 WritebackReg = Inst.getOperand(0).getReg(); 1221 break; 1222 } 1223 1224 // Empty register lists are not allowed. 1225 if (Val == 0) return MCDisassembler::Fail; 1226 for (unsigned i = 0; i < 16; ++i) { 1227 if (Val & (1 << i)) { 1228 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1229 return MCDisassembler::Fail; 1230 // Writeback not allowed if Rn is in the target list. 1231 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1232 Check(S, MCDisassembler::SoftFail); 1233 } 1234 } 1235 1236 return S; 1237 } 1238 1239 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1240 uint64_t Address, const void *Decoder) { 1241 DecodeStatus S = MCDisassembler::Success; 1242 1243 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1244 unsigned regs = fieldFromInstruction(Val, 0, 8); 1245 1246 // In case of unpredictable encoding, tweak the operands. 1247 if (regs == 0 || (Vd + regs) > 32) { 1248 regs = Vd + regs > 32 ? 32 - Vd : regs; 1249 regs = std::max( 1u, regs); 1250 S = MCDisassembler::SoftFail; 1251 } 1252 1253 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1254 return MCDisassembler::Fail; 1255 for (unsigned i = 0; i < (regs - 1); ++i) { 1256 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1257 return MCDisassembler::Fail; 1258 } 1259 1260 return S; 1261 } 1262 1263 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1264 uint64_t Address, const void *Decoder) { 1265 DecodeStatus S = MCDisassembler::Success; 1266 1267 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1268 unsigned regs = fieldFromInstruction(Val, 1, 7); 1269 1270 // In case of unpredictable encoding, tweak the operands. 1271 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1272 regs = Vd + regs > 32 ? 32 - Vd : regs; 1273 regs = std::max( 1u, regs); 1274 regs = std::min(16u, regs); 1275 S = MCDisassembler::SoftFail; 1276 } 1277 1278 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1279 return MCDisassembler::Fail; 1280 for (unsigned i = 0; i < (regs - 1); ++i) { 1281 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1282 return MCDisassembler::Fail; 1283 } 1284 1285 return S; 1286 } 1287 1288 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1289 uint64_t Address, const void *Decoder) { 1290 // This operand encodes a mask of contiguous zeros between a specified MSB 1291 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1292 // the mask of all bits LSB-and-lower, and then xor them to create 1293 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1294 // create the final mask. 1295 unsigned msb = fieldFromInstruction(Val, 5, 5); 1296 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1297 1298 DecodeStatus S = MCDisassembler::Success; 1299 if (lsb > msb) { 1300 Check(S, MCDisassembler::SoftFail); 1301 // The check above will cause the warning for the "potentially undefined 1302 // instruction encoding" but we can't build a bad MCOperand value here 1303 // with a lsb > msb or else printing the MCInst will cause a crash. 1304 lsb = msb; 1305 } 1306 1307 uint32_t msb_mask = 0xFFFFFFFF; 1308 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1309 uint32_t lsb_mask = (1U << lsb) - 1; 1310 1311 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1312 return S; 1313 } 1314 1315 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1316 uint64_t Address, const void *Decoder) { 1317 DecodeStatus S = MCDisassembler::Success; 1318 1319 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1320 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1321 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1322 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1323 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1324 unsigned U = fieldFromInstruction(Insn, 23, 1); 1325 1326 switch (Inst.getOpcode()) { 1327 case ARM::LDC_OFFSET: 1328 case ARM::LDC_PRE: 1329 case ARM::LDC_POST: 1330 case ARM::LDC_OPTION: 1331 case ARM::LDCL_OFFSET: 1332 case ARM::LDCL_PRE: 1333 case ARM::LDCL_POST: 1334 case ARM::LDCL_OPTION: 1335 case ARM::STC_OFFSET: 1336 case ARM::STC_PRE: 1337 case ARM::STC_POST: 1338 case ARM::STC_OPTION: 1339 case ARM::STCL_OFFSET: 1340 case ARM::STCL_PRE: 1341 case ARM::STCL_POST: 1342 case ARM::STCL_OPTION: 1343 case ARM::t2LDC_OFFSET: 1344 case ARM::t2LDC_PRE: 1345 case ARM::t2LDC_POST: 1346 case ARM::t2LDC_OPTION: 1347 case ARM::t2LDCL_OFFSET: 1348 case ARM::t2LDCL_PRE: 1349 case ARM::t2LDCL_POST: 1350 case ARM::t2LDCL_OPTION: 1351 case ARM::t2STC_OFFSET: 1352 case ARM::t2STC_PRE: 1353 case ARM::t2STC_POST: 1354 case ARM::t2STC_OPTION: 1355 case ARM::t2STCL_OFFSET: 1356 case ARM::t2STCL_PRE: 1357 case ARM::t2STCL_POST: 1358 case ARM::t2STCL_OPTION: 1359 if (coproc == 0xA || coproc == 0xB) 1360 return MCDisassembler::Fail; 1361 break; 1362 default: 1363 break; 1364 } 1365 1366 Inst.addOperand(MCOperand::CreateImm(coproc)); 1367 Inst.addOperand(MCOperand::CreateImm(CRd)); 1368 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1369 return MCDisassembler::Fail; 1370 1371 switch (Inst.getOpcode()) { 1372 case ARM::t2LDC2_OFFSET: 1373 case ARM::t2LDC2L_OFFSET: 1374 case ARM::t2LDC2_PRE: 1375 case ARM::t2LDC2L_PRE: 1376 case ARM::t2STC2_OFFSET: 1377 case ARM::t2STC2L_OFFSET: 1378 case ARM::t2STC2_PRE: 1379 case ARM::t2STC2L_PRE: 1380 case ARM::LDC2_OFFSET: 1381 case ARM::LDC2L_OFFSET: 1382 case ARM::LDC2_PRE: 1383 case ARM::LDC2L_PRE: 1384 case ARM::STC2_OFFSET: 1385 case ARM::STC2L_OFFSET: 1386 case ARM::STC2_PRE: 1387 case ARM::STC2L_PRE: 1388 case ARM::t2LDC_OFFSET: 1389 case ARM::t2LDCL_OFFSET: 1390 case ARM::t2LDC_PRE: 1391 case ARM::t2LDCL_PRE: 1392 case ARM::t2STC_OFFSET: 1393 case ARM::t2STCL_OFFSET: 1394 case ARM::t2STC_PRE: 1395 case ARM::t2STCL_PRE: 1396 case ARM::LDC_OFFSET: 1397 case ARM::LDCL_OFFSET: 1398 case ARM::LDC_PRE: 1399 case ARM::LDCL_PRE: 1400 case ARM::STC_OFFSET: 1401 case ARM::STCL_OFFSET: 1402 case ARM::STC_PRE: 1403 case ARM::STCL_PRE: 1404 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1405 Inst.addOperand(MCOperand::CreateImm(imm)); 1406 break; 1407 case ARM::t2LDC2_POST: 1408 case ARM::t2LDC2L_POST: 1409 case ARM::t2STC2_POST: 1410 case ARM::t2STC2L_POST: 1411 case ARM::LDC2_POST: 1412 case ARM::LDC2L_POST: 1413 case ARM::STC2_POST: 1414 case ARM::STC2L_POST: 1415 case ARM::t2LDC_POST: 1416 case ARM::t2LDCL_POST: 1417 case ARM::t2STC_POST: 1418 case ARM::t2STCL_POST: 1419 case ARM::LDC_POST: 1420 case ARM::LDCL_POST: 1421 case ARM::STC_POST: 1422 case ARM::STCL_POST: 1423 imm |= U << 8; 1424 // fall through. 1425 default: 1426 // The 'option' variant doesn't encode 'U' in the immediate since 1427 // the immediate is unsigned [0,255]. 1428 Inst.addOperand(MCOperand::CreateImm(imm)); 1429 break; 1430 } 1431 1432 switch (Inst.getOpcode()) { 1433 case ARM::LDC_OFFSET: 1434 case ARM::LDC_PRE: 1435 case ARM::LDC_POST: 1436 case ARM::LDC_OPTION: 1437 case ARM::LDCL_OFFSET: 1438 case ARM::LDCL_PRE: 1439 case ARM::LDCL_POST: 1440 case ARM::LDCL_OPTION: 1441 case ARM::STC_OFFSET: 1442 case ARM::STC_PRE: 1443 case ARM::STC_POST: 1444 case ARM::STC_OPTION: 1445 case ARM::STCL_OFFSET: 1446 case ARM::STCL_PRE: 1447 case ARM::STCL_POST: 1448 case ARM::STCL_OPTION: 1449 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1450 return MCDisassembler::Fail; 1451 break; 1452 default: 1453 break; 1454 } 1455 1456 return S; 1457 } 1458 1459 static DecodeStatus 1460 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1461 uint64_t Address, const void *Decoder) { 1462 DecodeStatus S = MCDisassembler::Success; 1463 1464 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1465 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1466 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1467 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1468 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1469 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1470 unsigned P = fieldFromInstruction(Insn, 24, 1); 1471 unsigned W = fieldFromInstruction(Insn, 21, 1); 1472 1473 // On stores, the writeback operand precedes Rt. 1474 switch (Inst.getOpcode()) { 1475 case ARM::STR_POST_IMM: 1476 case ARM::STR_POST_REG: 1477 case ARM::STRB_POST_IMM: 1478 case ARM::STRB_POST_REG: 1479 case ARM::STRT_POST_REG: 1480 case ARM::STRT_POST_IMM: 1481 case ARM::STRBT_POST_REG: 1482 case ARM::STRBT_POST_IMM: 1483 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1484 return MCDisassembler::Fail; 1485 break; 1486 default: 1487 break; 1488 } 1489 1490 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1491 return MCDisassembler::Fail; 1492 1493 // On loads, the writeback operand comes after Rt. 1494 switch (Inst.getOpcode()) { 1495 case ARM::LDR_POST_IMM: 1496 case ARM::LDR_POST_REG: 1497 case ARM::LDRB_POST_IMM: 1498 case ARM::LDRB_POST_REG: 1499 case ARM::LDRBT_POST_REG: 1500 case ARM::LDRBT_POST_IMM: 1501 case ARM::LDRT_POST_REG: 1502 case ARM::LDRT_POST_IMM: 1503 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1504 return MCDisassembler::Fail; 1505 break; 1506 default: 1507 break; 1508 } 1509 1510 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1511 return MCDisassembler::Fail; 1512 1513 ARM_AM::AddrOpc Op = ARM_AM::add; 1514 if (!fieldFromInstruction(Insn, 23, 1)) 1515 Op = ARM_AM::sub; 1516 1517 bool writeback = (P == 0) || (W == 1); 1518 unsigned idx_mode = 0; 1519 if (P && writeback) 1520 idx_mode = ARMII::IndexModePre; 1521 else if (!P && writeback) 1522 idx_mode = ARMII::IndexModePost; 1523 1524 if (writeback && (Rn == 15 || Rn == Rt)) 1525 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1526 1527 if (reg) { 1528 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1529 return MCDisassembler::Fail; 1530 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1531 switch( fieldFromInstruction(Insn, 5, 2)) { 1532 case 0: 1533 Opc = ARM_AM::lsl; 1534 break; 1535 case 1: 1536 Opc = ARM_AM::lsr; 1537 break; 1538 case 2: 1539 Opc = ARM_AM::asr; 1540 break; 1541 case 3: 1542 Opc = ARM_AM::ror; 1543 break; 1544 default: 1545 return MCDisassembler::Fail; 1546 } 1547 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1548 if (Opc == ARM_AM::ror && amt == 0) 1549 Opc = ARM_AM::rrx; 1550 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1551 1552 Inst.addOperand(MCOperand::CreateImm(imm)); 1553 } else { 1554 Inst.addOperand(MCOperand::CreateReg(0)); 1555 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1556 Inst.addOperand(MCOperand::CreateImm(tmp)); 1557 } 1558 1559 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1560 return MCDisassembler::Fail; 1561 1562 return S; 1563 } 1564 1565 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1566 uint64_t Address, const void *Decoder) { 1567 DecodeStatus S = MCDisassembler::Success; 1568 1569 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1570 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1571 unsigned type = fieldFromInstruction(Val, 5, 2); 1572 unsigned imm = fieldFromInstruction(Val, 7, 5); 1573 unsigned U = fieldFromInstruction(Val, 12, 1); 1574 1575 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1576 switch (type) { 1577 case 0: 1578 ShOp = ARM_AM::lsl; 1579 break; 1580 case 1: 1581 ShOp = ARM_AM::lsr; 1582 break; 1583 case 2: 1584 ShOp = ARM_AM::asr; 1585 break; 1586 case 3: 1587 ShOp = ARM_AM::ror; 1588 break; 1589 } 1590 1591 if (ShOp == ARM_AM::ror && imm == 0) 1592 ShOp = ARM_AM::rrx; 1593 1594 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1595 return MCDisassembler::Fail; 1596 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1597 return MCDisassembler::Fail; 1598 unsigned shift; 1599 if (U) 1600 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1601 else 1602 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1603 Inst.addOperand(MCOperand::CreateImm(shift)); 1604 1605 return S; 1606 } 1607 1608 static DecodeStatus 1609 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1610 uint64_t Address, const void *Decoder) { 1611 DecodeStatus S = MCDisassembler::Success; 1612 1613 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1614 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1615 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1616 unsigned type = fieldFromInstruction(Insn, 22, 1); 1617 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1618 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1619 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1620 unsigned W = fieldFromInstruction(Insn, 21, 1); 1621 unsigned P = fieldFromInstruction(Insn, 24, 1); 1622 unsigned Rt2 = Rt + 1; 1623 1624 bool writeback = (W == 1) | (P == 0); 1625 1626 // For {LD,ST}RD, Rt must be even, else undefined. 1627 switch (Inst.getOpcode()) { 1628 case ARM::STRD: 1629 case ARM::STRD_PRE: 1630 case ARM::STRD_POST: 1631 case ARM::LDRD: 1632 case ARM::LDRD_PRE: 1633 case ARM::LDRD_POST: 1634 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1635 break; 1636 default: 1637 break; 1638 } 1639 switch (Inst.getOpcode()) { 1640 case ARM::STRD: 1641 case ARM::STRD_PRE: 1642 case ARM::STRD_POST: 1643 if (P == 0 && W == 1) 1644 S = MCDisassembler::SoftFail; 1645 1646 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1647 S = MCDisassembler::SoftFail; 1648 if (type && Rm == 15) 1649 S = MCDisassembler::SoftFail; 1650 if (Rt2 == 15) 1651 S = MCDisassembler::SoftFail; 1652 if (!type && fieldFromInstruction(Insn, 8, 4)) 1653 S = MCDisassembler::SoftFail; 1654 break; 1655 case ARM::STRH: 1656 case ARM::STRH_PRE: 1657 case ARM::STRH_POST: 1658 if (Rt == 15) 1659 S = MCDisassembler::SoftFail; 1660 if (writeback && (Rn == 15 || Rn == Rt)) 1661 S = MCDisassembler::SoftFail; 1662 if (!type && Rm == 15) 1663 S = MCDisassembler::SoftFail; 1664 break; 1665 case ARM::LDRD: 1666 case ARM::LDRD_PRE: 1667 case ARM::LDRD_POST: 1668 if (type && Rn == 15){ 1669 if (Rt2 == 15) 1670 S = MCDisassembler::SoftFail; 1671 break; 1672 } 1673 if (P == 0 && W == 1) 1674 S = MCDisassembler::SoftFail; 1675 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1676 S = MCDisassembler::SoftFail; 1677 if (!type && writeback && Rn == 15) 1678 S = MCDisassembler::SoftFail; 1679 if (writeback && (Rn == Rt || Rn == Rt2)) 1680 S = MCDisassembler::SoftFail; 1681 break; 1682 case ARM::LDRH: 1683 case ARM::LDRH_PRE: 1684 case ARM::LDRH_POST: 1685 if (type && Rn == 15){ 1686 if (Rt == 15) 1687 S = MCDisassembler::SoftFail; 1688 break; 1689 } 1690 if (Rt == 15) 1691 S = MCDisassembler::SoftFail; 1692 if (!type && Rm == 15) 1693 S = MCDisassembler::SoftFail; 1694 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1695 S = MCDisassembler::SoftFail; 1696 break; 1697 case ARM::LDRSH: 1698 case ARM::LDRSH_PRE: 1699 case ARM::LDRSH_POST: 1700 case ARM::LDRSB: 1701 case ARM::LDRSB_PRE: 1702 case ARM::LDRSB_POST: 1703 if (type && Rn == 15){ 1704 if (Rt == 15) 1705 S = MCDisassembler::SoftFail; 1706 break; 1707 } 1708 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1709 S = MCDisassembler::SoftFail; 1710 if (!type && (Rt == 15 || Rm == 15)) 1711 S = MCDisassembler::SoftFail; 1712 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1713 S = MCDisassembler::SoftFail; 1714 break; 1715 default: 1716 break; 1717 } 1718 1719 if (writeback) { // Writeback 1720 if (P) 1721 U |= ARMII::IndexModePre << 9; 1722 else 1723 U |= ARMII::IndexModePost << 9; 1724 1725 // On stores, the writeback operand precedes Rt. 1726 switch (Inst.getOpcode()) { 1727 case ARM::STRD: 1728 case ARM::STRD_PRE: 1729 case ARM::STRD_POST: 1730 case ARM::STRH: 1731 case ARM::STRH_PRE: 1732 case ARM::STRH_POST: 1733 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1734 return MCDisassembler::Fail; 1735 break; 1736 default: 1737 break; 1738 } 1739 } 1740 1741 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1742 return MCDisassembler::Fail; 1743 switch (Inst.getOpcode()) { 1744 case ARM::STRD: 1745 case ARM::STRD_PRE: 1746 case ARM::STRD_POST: 1747 case ARM::LDRD: 1748 case ARM::LDRD_PRE: 1749 case ARM::LDRD_POST: 1750 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1751 return MCDisassembler::Fail; 1752 break; 1753 default: 1754 break; 1755 } 1756 1757 if (writeback) { 1758 // On loads, the writeback operand comes after Rt. 1759 switch (Inst.getOpcode()) { 1760 case ARM::LDRD: 1761 case ARM::LDRD_PRE: 1762 case ARM::LDRD_POST: 1763 case ARM::LDRH: 1764 case ARM::LDRH_PRE: 1765 case ARM::LDRH_POST: 1766 case ARM::LDRSH: 1767 case ARM::LDRSH_PRE: 1768 case ARM::LDRSH_POST: 1769 case ARM::LDRSB: 1770 case ARM::LDRSB_PRE: 1771 case ARM::LDRSB_POST: 1772 case ARM::LDRHTr: 1773 case ARM::LDRSBTr: 1774 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1775 return MCDisassembler::Fail; 1776 break; 1777 default: 1778 break; 1779 } 1780 } 1781 1782 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1783 return MCDisassembler::Fail; 1784 1785 if (type) { 1786 Inst.addOperand(MCOperand::CreateReg(0)); 1787 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1788 } else { 1789 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1790 return MCDisassembler::Fail; 1791 Inst.addOperand(MCOperand::CreateImm(U)); 1792 } 1793 1794 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1795 return MCDisassembler::Fail; 1796 1797 return S; 1798 } 1799 1800 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1801 uint64_t Address, const void *Decoder) { 1802 DecodeStatus S = MCDisassembler::Success; 1803 1804 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1805 unsigned mode = fieldFromInstruction(Insn, 23, 2); 1806 1807 switch (mode) { 1808 case 0: 1809 mode = ARM_AM::da; 1810 break; 1811 case 1: 1812 mode = ARM_AM::ia; 1813 break; 1814 case 2: 1815 mode = ARM_AM::db; 1816 break; 1817 case 3: 1818 mode = ARM_AM::ib; 1819 break; 1820 } 1821 1822 Inst.addOperand(MCOperand::CreateImm(mode)); 1823 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1824 return MCDisassembler::Fail; 1825 1826 return S; 1827 } 1828 1829 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 1830 uint64_t Address, const void *Decoder) { 1831 DecodeStatus S = MCDisassembler::Success; 1832 1833 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 1834 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1835 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1836 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1837 1838 if (pred == 0xF) 1839 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1840 1841 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1842 return MCDisassembler::Fail; 1843 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1844 return MCDisassembler::Fail; 1845 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1846 return MCDisassembler::Fail; 1847 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1848 return MCDisassembler::Fail; 1849 return S; 1850 } 1851 1852 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 1853 unsigned Insn, 1854 uint64_t Address, const void *Decoder) { 1855 DecodeStatus S = MCDisassembler::Success; 1856 1857 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1858 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1859 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 1860 1861 if (pred == 0xF) { 1862 // Ambiguous with RFE and SRS 1863 switch (Inst.getOpcode()) { 1864 case ARM::LDMDA: 1865 Inst.setOpcode(ARM::RFEDA); 1866 break; 1867 case ARM::LDMDA_UPD: 1868 Inst.setOpcode(ARM::RFEDA_UPD); 1869 break; 1870 case ARM::LDMDB: 1871 Inst.setOpcode(ARM::RFEDB); 1872 break; 1873 case ARM::LDMDB_UPD: 1874 Inst.setOpcode(ARM::RFEDB_UPD); 1875 break; 1876 case ARM::LDMIA: 1877 Inst.setOpcode(ARM::RFEIA); 1878 break; 1879 case ARM::LDMIA_UPD: 1880 Inst.setOpcode(ARM::RFEIA_UPD); 1881 break; 1882 case ARM::LDMIB: 1883 Inst.setOpcode(ARM::RFEIB); 1884 break; 1885 case ARM::LDMIB_UPD: 1886 Inst.setOpcode(ARM::RFEIB_UPD); 1887 break; 1888 case ARM::STMDA: 1889 Inst.setOpcode(ARM::SRSDA); 1890 break; 1891 case ARM::STMDA_UPD: 1892 Inst.setOpcode(ARM::SRSDA_UPD); 1893 break; 1894 case ARM::STMDB: 1895 Inst.setOpcode(ARM::SRSDB); 1896 break; 1897 case ARM::STMDB_UPD: 1898 Inst.setOpcode(ARM::SRSDB_UPD); 1899 break; 1900 case ARM::STMIA: 1901 Inst.setOpcode(ARM::SRSIA); 1902 break; 1903 case ARM::STMIA_UPD: 1904 Inst.setOpcode(ARM::SRSIA_UPD); 1905 break; 1906 case ARM::STMIB: 1907 Inst.setOpcode(ARM::SRSIB); 1908 break; 1909 case ARM::STMIB_UPD: 1910 Inst.setOpcode(ARM::SRSIB_UPD); 1911 break; 1912 default: 1913 return MCDisassembler::Fail; 1914 } 1915 1916 // For stores (which become SRS's, the only operand is the mode. 1917 if (fieldFromInstruction(Insn, 20, 1) == 0) { 1918 // Check SRS encoding constraints 1919 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 1920 fieldFromInstruction(Insn, 20, 1) == 0)) 1921 return MCDisassembler::Fail; 1922 1923 Inst.addOperand( 1924 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4))); 1925 return S; 1926 } 1927 1928 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1929 } 1930 1931 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1932 return MCDisassembler::Fail; 1933 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1934 return MCDisassembler::Fail; // Tied 1935 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1936 return MCDisassembler::Fail; 1937 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1938 return MCDisassembler::Fail; 1939 1940 return S; 1941 } 1942 1943 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 1944 uint64_t Address, const void *Decoder) { 1945 unsigned imod = fieldFromInstruction(Insn, 18, 2); 1946 unsigned M = fieldFromInstruction(Insn, 17, 1); 1947 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 1948 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1949 1950 DecodeStatus S = MCDisassembler::Success; 1951 1952 // This decoder is called from multiple location that do not check 1953 // the full encoding is valid before they do. 1954 if (fieldFromInstruction(Insn, 5, 1) != 0 || 1955 fieldFromInstruction(Insn, 16, 1) != 0 || 1956 fieldFromInstruction(Insn, 20, 8) != 0x10) 1957 return MCDisassembler::Fail; 1958 1959 // imod == '01' --> UNPREDICTABLE 1960 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1961 // return failure here. The '01' imod value is unprintable, so there's 1962 // nothing useful we could do even if we returned UNPREDICTABLE. 1963 1964 if (imod == 1) return MCDisassembler::Fail; 1965 1966 if (imod && M) { 1967 Inst.setOpcode(ARM::CPS3p); 1968 Inst.addOperand(MCOperand::CreateImm(imod)); 1969 Inst.addOperand(MCOperand::CreateImm(iflags)); 1970 Inst.addOperand(MCOperand::CreateImm(mode)); 1971 } else if (imod && !M) { 1972 Inst.setOpcode(ARM::CPS2p); 1973 Inst.addOperand(MCOperand::CreateImm(imod)); 1974 Inst.addOperand(MCOperand::CreateImm(iflags)); 1975 if (mode) S = MCDisassembler::SoftFail; 1976 } else if (!imod && M) { 1977 Inst.setOpcode(ARM::CPS1p); 1978 Inst.addOperand(MCOperand::CreateImm(mode)); 1979 if (iflags) S = MCDisassembler::SoftFail; 1980 } else { 1981 // imod == '00' && M == '0' --> UNPREDICTABLE 1982 Inst.setOpcode(ARM::CPS1p); 1983 Inst.addOperand(MCOperand::CreateImm(mode)); 1984 S = MCDisassembler::SoftFail; 1985 } 1986 1987 return S; 1988 } 1989 1990 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 1991 uint64_t Address, const void *Decoder) { 1992 unsigned imod = fieldFromInstruction(Insn, 9, 2); 1993 unsigned M = fieldFromInstruction(Insn, 8, 1); 1994 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 1995 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1996 1997 DecodeStatus S = MCDisassembler::Success; 1998 1999 // imod == '01' --> UNPREDICTABLE 2000 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2001 // return failure here. The '01' imod value is unprintable, so there's 2002 // nothing useful we could do even if we returned UNPREDICTABLE. 2003 2004 if (imod == 1) return MCDisassembler::Fail; 2005 2006 if (imod && M) { 2007 Inst.setOpcode(ARM::t2CPS3p); 2008 Inst.addOperand(MCOperand::CreateImm(imod)); 2009 Inst.addOperand(MCOperand::CreateImm(iflags)); 2010 Inst.addOperand(MCOperand::CreateImm(mode)); 2011 } else if (imod && !M) { 2012 Inst.setOpcode(ARM::t2CPS2p); 2013 Inst.addOperand(MCOperand::CreateImm(imod)); 2014 Inst.addOperand(MCOperand::CreateImm(iflags)); 2015 if (mode) S = MCDisassembler::SoftFail; 2016 } else if (!imod && M) { 2017 Inst.setOpcode(ARM::t2CPS1p); 2018 Inst.addOperand(MCOperand::CreateImm(mode)); 2019 if (iflags) S = MCDisassembler::SoftFail; 2020 } else { 2021 // imod == '00' && M == '0' --> this is a HINT instruction 2022 int imm = fieldFromInstruction(Insn, 0, 8); 2023 // HINT are defined only for immediate in [0..4] 2024 if(imm > 4) return MCDisassembler::Fail; 2025 Inst.setOpcode(ARM::t2HINT); 2026 Inst.addOperand(MCOperand::CreateImm(imm)); 2027 } 2028 2029 return S; 2030 } 2031 2032 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2033 uint64_t Address, const void *Decoder) { 2034 DecodeStatus S = MCDisassembler::Success; 2035 2036 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2037 unsigned imm = 0; 2038 2039 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2040 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2041 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2042 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2043 2044 if (Inst.getOpcode() == ARM::t2MOVTi16) 2045 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2046 return MCDisassembler::Fail; 2047 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2048 return MCDisassembler::Fail; 2049 2050 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2051 Inst.addOperand(MCOperand::CreateImm(imm)); 2052 2053 return S; 2054 } 2055 2056 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2057 uint64_t Address, const void *Decoder) { 2058 DecodeStatus S = MCDisassembler::Success; 2059 2060 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2061 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2062 unsigned imm = 0; 2063 2064 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2065 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2066 2067 if (Inst.getOpcode() == ARM::MOVTi16) 2068 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2069 return MCDisassembler::Fail; 2070 2071 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2072 return MCDisassembler::Fail; 2073 2074 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2075 Inst.addOperand(MCOperand::CreateImm(imm)); 2076 2077 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2078 return MCDisassembler::Fail; 2079 2080 return S; 2081 } 2082 2083 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2084 uint64_t Address, const void *Decoder) { 2085 DecodeStatus S = MCDisassembler::Success; 2086 2087 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2088 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2089 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2090 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2091 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2092 2093 if (pred == 0xF) 2094 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2095 2096 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2097 return MCDisassembler::Fail; 2098 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2099 return MCDisassembler::Fail; 2100 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2101 return MCDisassembler::Fail; 2102 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2103 return MCDisassembler::Fail; 2104 2105 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2106 return MCDisassembler::Fail; 2107 2108 return S; 2109 } 2110 2111 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2112 uint64_t Address, const void *Decoder) { 2113 DecodeStatus S = MCDisassembler::Success; 2114 2115 unsigned add = fieldFromInstruction(Val, 12, 1); 2116 unsigned imm = fieldFromInstruction(Val, 0, 12); 2117 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2118 2119 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2120 return MCDisassembler::Fail; 2121 2122 if (!add) imm *= -1; 2123 if (imm == 0 && !add) imm = INT32_MIN; 2124 Inst.addOperand(MCOperand::CreateImm(imm)); 2125 if (Rn == 15) 2126 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2127 2128 return S; 2129 } 2130 2131 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2132 uint64_t Address, const void *Decoder) { 2133 DecodeStatus S = MCDisassembler::Success; 2134 2135 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2136 unsigned U = fieldFromInstruction(Val, 8, 1); 2137 unsigned imm = fieldFromInstruction(Val, 0, 8); 2138 2139 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2140 return MCDisassembler::Fail; 2141 2142 if (U) 2143 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2144 else 2145 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2146 2147 return S; 2148 } 2149 2150 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2151 uint64_t Address, const void *Decoder) { 2152 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2153 } 2154 2155 static DecodeStatus 2156 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2157 uint64_t Address, const void *Decoder) { 2158 DecodeStatus Status = MCDisassembler::Success; 2159 2160 // Note the J1 and J2 values are from the encoded instruction. So here 2161 // change them to I1 and I2 values via as documented: 2162 // I1 = NOT(J1 EOR S); 2163 // I2 = NOT(J2 EOR S); 2164 // and build the imm32 with one trailing zero as documented: 2165 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2166 unsigned S = fieldFromInstruction(Insn, 26, 1); 2167 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2168 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2169 unsigned I1 = !(J1 ^ S); 2170 unsigned I2 = !(J2 ^ S); 2171 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2172 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2173 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2174 int imm32 = SignExtend32<25>(tmp << 1); 2175 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2176 true, 4, Inst, Decoder)) 2177 Inst.addOperand(MCOperand::CreateImm(imm32)); 2178 2179 return Status; 2180 } 2181 2182 static DecodeStatus 2183 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2184 uint64_t Address, const void *Decoder) { 2185 DecodeStatus S = MCDisassembler::Success; 2186 2187 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2188 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2189 2190 if (pred == 0xF) { 2191 Inst.setOpcode(ARM::BLXi); 2192 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2193 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2194 true, 4, Inst, Decoder)) 2195 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2196 return S; 2197 } 2198 2199 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2200 true, 4, Inst, Decoder)) 2201 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2202 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2203 return MCDisassembler::Fail; 2204 2205 return S; 2206 } 2207 2208 2209 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2210 uint64_t Address, const void *Decoder) { 2211 DecodeStatus S = MCDisassembler::Success; 2212 2213 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2214 unsigned align = fieldFromInstruction(Val, 4, 2); 2215 2216 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2217 return MCDisassembler::Fail; 2218 if (!align) 2219 Inst.addOperand(MCOperand::CreateImm(0)); 2220 else 2221 Inst.addOperand(MCOperand::CreateImm(4 << align)); 2222 2223 return S; 2224 } 2225 2226 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2227 uint64_t Address, const void *Decoder) { 2228 DecodeStatus S = MCDisassembler::Success; 2229 2230 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2231 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2232 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2233 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2234 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2235 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2236 2237 // First output register 2238 switch (Inst.getOpcode()) { 2239 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2240 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2241 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2242 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2243 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2244 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2245 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2246 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2247 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2248 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2249 return MCDisassembler::Fail; 2250 break; 2251 case ARM::VLD2b16: 2252 case ARM::VLD2b32: 2253 case ARM::VLD2b8: 2254 case ARM::VLD2b16wb_fixed: 2255 case ARM::VLD2b16wb_register: 2256 case ARM::VLD2b32wb_fixed: 2257 case ARM::VLD2b32wb_register: 2258 case ARM::VLD2b8wb_fixed: 2259 case ARM::VLD2b8wb_register: 2260 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2261 return MCDisassembler::Fail; 2262 break; 2263 default: 2264 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2265 return MCDisassembler::Fail; 2266 } 2267 2268 // Second output register 2269 switch (Inst.getOpcode()) { 2270 case ARM::VLD3d8: 2271 case ARM::VLD3d16: 2272 case ARM::VLD3d32: 2273 case ARM::VLD3d8_UPD: 2274 case ARM::VLD3d16_UPD: 2275 case ARM::VLD3d32_UPD: 2276 case ARM::VLD4d8: 2277 case ARM::VLD4d16: 2278 case ARM::VLD4d32: 2279 case ARM::VLD4d8_UPD: 2280 case ARM::VLD4d16_UPD: 2281 case ARM::VLD4d32_UPD: 2282 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2283 return MCDisassembler::Fail; 2284 break; 2285 case ARM::VLD3q8: 2286 case ARM::VLD3q16: 2287 case ARM::VLD3q32: 2288 case ARM::VLD3q8_UPD: 2289 case ARM::VLD3q16_UPD: 2290 case ARM::VLD3q32_UPD: 2291 case ARM::VLD4q8: 2292 case ARM::VLD4q16: 2293 case ARM::VLD4q32: 2294 case ARM::VLD4q8_UPD: 2295 case ARM::VLD4q16_UPD: 2296 case ARM::VLD4q32_UPD: 2297 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2298 return MCDisassembler::Fail; 2299 default: 2300 break; 2301 } 2302 2303 // Third output register 2304 switch(Inst.getOpcode()) { 2305 case ARM::VLD3d8: 2306 case ARM::VLD3d16: 2307 case ARM::VLD3d32: 2308 case ARM::VLD3d8_UPD: 2309 case ARM::VLD3d16_UPD: 2310 case ARM::VLD3d32_UPD: 2311 case ARM::VLD4d8: 2312 case ARM::VLD4d16: 2313 case ARM::VLD4d32: 2314 case ARM::VLD4d8_UPD: 2315 case ARM::VLD4d16_UPD: 2316 case ARM::VLD4d32_UPD: 2317 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2318 return MCDisassembler::Fail; 2319 break; 2320 case ARM::VLD3q8: 2321 case ARM::VLD3q16: 2322 case ARM::VLD3q32: 2323 case ARM::VLD3q8_UPD: 2324 case ARM::VLD3q16_UPD: 2325 case ARM::VLD3q32_UPD: 2326 case ARM::VLD4q8: 2327 case ARM::VLD4q16: 2328 case ARM::VLD4q32: 2329 case ARM::VLD4q8_UPD: 2330 case ARM::VLD4q16_UPD: 2331 case ARM::VLD4q32_UPD: 2332 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2333 return MCDisassembler::Fail; 2334 break; 2335 default: 2336 break; 2337 } 2338 2339 // Fourth output register 2340 switch (Inst.getOpcode()) { 2341 case ARM::VLD4d8: 2342 case ARM::VLD4d16: 2343 case ARM::VLD4d32: 2344 case ARM::VLD4d8_UPD: 2345 case ARM::VLD4d16_UPD: 2346 case ARM::VLD4d32_UPD: 2347 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2348 return MCDisassembler::Fail; 2349 break; 2350 case ARM::VLD4q8: 2351 case ARM::VLD4q16: 2352 case ARM::VLD4q32: 2353 case ARM::VLD4q8_UPD: 2354 case ARM::VLD4q16_UPD: 2355 case ARM::VLD4q32_UPD: 2356 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2357 return MCDisassembler::Fail; 2358 break; 2359 default: 2360 break; 2361 } 2362 2363 // Writeback operand 2364 switch (Inst.getOpcode()) { 2365 case ARM::VLD1d8wb_fixed: 2366 case ARM::VLD1d16wb_fixed: 2367 case ARM::VLD1d32wb_fixed: 2368 case ARM::VLD1d64wb_fixed: 2369 case ARM::VLD1d8wb_register: 2370 case ARM::VLD1d16wb_register: 2371 case ARM::VLD1d32wb_register: 2372 case ARM::VLD1d64wb_register: 2373 case ARM::VLD1q8wb_fixed: 2374 case ARM::VLD1q16wb_fixed: 2375 case ARM::VLD1q32wb_fixed: 2376 case ARM::VLD1q64wb_fixed: 2377 case ARM::VLD1q8wb_register: 2378 case ARM::VLD1q16wb_register: 2379 case ARM::VLD1q32wb_register: 2380 case ARM::VLD1q64wb_register: 2381 case ARM::VLD1d8Twb_fixed: 2382 case ARM::VLD1d8Twb_register: 2383 case ARM::VLD1d16Twb_fixed: 2384 case ARM::VLD1d16Twb_register: 2385 case ARM::VLD1d32Twb_fixed: 2386 case ARM::VLD1d32Twb_register: 2387 case ARM::VLD1d64Twb_fixed: 2388 case ARM::VLD1d64Twb_register: 2389 case ARM::VLD1d8Qwb_fixed: 2390 case ARM::VLD1d8Qwb_register: 2391 case ARM::VLD1d16Qwb_fixed: 2392 case ARM::VLD1d16Qwb_register: 2393 case ARM::VLD1d32Qwb_fixed: 2394 case ARM::VLD1d32Qwb_register: 2395 case ARM::VLD1d64Qwb_fixed: 2396 case ARM::VLD1d64Qwb_register: 2397 case ARM::VLD2d8wb_fixed: 2398 case ARM::VLD2d16wb_fixed: 2399 case ARM::VLD2d32wb_fixed: 2400 case ARM::VLD2q8wb_fixed: 2401 case ARM::VLD2q16wb_fixed: 2402 case ARM::VLD2q32wb_fixed: 2403 case ARM::VLD2d8wb_register: 2404 case ARM::VLD2d16wb_register: 2405 case ARM::VLD2d32wb_register: 2406 case ARM::VLD2q8wb_register: 2407 case ARM::VLD2q16wb_register: 2408 case ARM::VLD2q32wb_register: 2409 case ARM::VLD2b8wb_fixed: 2410 case ARM::VLD2b16wb_fixed: 2411 case ARM::VLD2b32wb_fixed: 2412 case ARM::VLD2b8wb_register: 2413 case ARM::VLD2b16wb_register: 2414 case ARM::VLD2b32wb_register: 2415 Inst.addOperand(MCOperand::CreateImm(0)); 2416 break; 2417 case ARM::VLD3d8_UPD: 2418 case ARM::VLD3d16_UPD: 2419 case ARM::VLD3d32_UPD: 2420 case ARM::VLD3q8_UPD: 2421 case ARM::VLD3q16_UPD: 2422 case ARM::VLD3q32_UPD: 2423 case ARM::VLD4d8_UPD: 2424 case ARM::VLD4d16_UPD: 2425 case ARM::VLD4d32_UPD: 2426 case ARM::VLD4q8_UPD: 2427 case ARM::VLD4q16_UPD: 2428 case ARM::VLD4q32_UPD: 2429 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2430 return MCDisassembler::Fail; 2431 break; 2432 default: 2433 break; 2434 } 2435 2436 // AddrMode6 Base (register+alignment) 2437 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2438 return MCDisassembler::Fail; 2439 2440 // AddrMode6 Offset (register) 2441 switch (Inst.getOpcode()) { 2442 default: 2443 // The below have been updated to have explicit am6offset split 2444 // between fixed and register offset. For those instructions not 2445 // yet updated, we need to add an additional reg0 operand for the 2446 // fixed variant. 2447 // 2448 // The fixed offset encodes as Rm == 0xd, so we check for that. 2449 if (Rm == 0xd) { 2450 Inst.addOperand(MCOperand::CreateReg(0)); 2451 break; 2452 } 2453 // Fall through to handle the register offset variant. 2454 case ARM::VLD1d8wb_fixed: 2455 case ARM::VLD1d16wb_fixed: 2456 case ARM::VLD1d32wb_fixed: 2457 case ARM::VLD1d64wb_fixed: 2458 case ARM::VLD1d8Twb_fixed: 2459 case ARM::VLD1d16Twb_fixed: 2460 case ARM::VLD1d32Twb_fixed: 2461 case ARM::VLD1d64Twb_fixed: 2462 case ARM::VLD1d8Qwb_fixed: 2463 case ARM::VLD1d16Qwb_fixed: 2464 case ARM::VLD1d32Qwb_fixed: 2465 case ARM::VLD1d64Qwb_fixed: 2466 case ARM::VLD1d8wb_register: 2467 case ARM::VLD1d16wb_register: 2468 case ARM::VLD1d32wb_register: 2469 case ARM::VLD1d64wb_register: 2470 case ARM::VLD1q8wb_fixed: 2471 case ARM::VLD1q16wb_fixed: 2472 case ARM::VLD1q32wb_fixed: 2473 case ARM::VLD1q64wb_fixed: 2474 case ARM::VLD1q8wb_register: 2475 case ARM::VLD1q16wb_register: 2476 case ARM::VLD1q32wb_register: 2477 case ARM::VLD1q64wb_register: 2478 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2479 // variant encodes Rm == 0xf. Anything else is a register offset post- 2480 // increment and we need to add the register operand to the instruction. 2481 if (Rm != 0xD && Rm != 0xF && 2482 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2483 return MCDisassembler::Fail; 2484 break; 2485 case ARM::VLD2d8wb_fixed: 2486 case ARM::VLD2d16wb_fixed: 2487 case ARM::VLD2d32wb_fixed: 2488 case ARM::VLD2b8wb_fixed: 2489 case ARM::VLD2b16wb_fixed: 2490 case ARM::VLD2b32wb_fixed: 2491 case ARM::VLD2q8wb_fixed: 2492 case ARM::VLD2q16wb_fixed: 2493 case ARM::VLD2q32wb_fixed: 2494 break; 2495 } 2496 2497 return S; 2498 } 2499 2500 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2501 uint64_t Address, const void *Decoder) { 2502 unsigned type = fieldFromInstruction(Insn, 8, 4); 2503 unsigned align = fieldFromInstruction(Insn, 4, 2); 2504 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2505 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2506 if (type == 10 && align == 3) return MCDisassembler::Fail; 2507 2508 unsigned load = fieldFromInstruction(Insn, 21, 1); 2509 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2510 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2511 } 2512 2513 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2514 uint64_t Address, const void *Decoder) { 2515 unsigned size = fieldFromInstruction(Insn, 6, 2); 2516 if (size == 3) return MCDisassembler::Fail; 2517 2518 unsigned type = fieldFromInstruction(Insn, 8, 4); 2519 unsigned align = fieldFromInstruction(Insn, 4, 2); 2520 if (type == 8 && align == 3) return MCDisassembler::Fail; 2521 if (type == 9 && align == 3) return MCDisassembler::Fail; 2522 2523 unsigned load = fieldFromInstruction(Insn, 21, 1); 2524 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2525 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2526 } 2527 2528 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 2529 uint64_t Address, const void *Decoder) { 2530 unsigned size = fieldFromInstruction(Insn, 6, 2); 2531 if (size == 3) return MCDisassembler::Fail; 2532 2533 unsigned align = fieldFromInstruction(Insn, 4, 2); 2534 if (align & 2) return MCDisassembler::Fail; 2535 2536 unsigned load = fieldFromInstruction(Insn, 21, 1); 2537 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2538 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2539 } 2540 2541 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 2542 uint64_t Address, const void *Decoder) { 2543 unsigned size = fieldFromInstruction(Insn, 6, 2); 2544 if (size == 3) return MCDisassembler::Fail; 2545 2546 unsigned load = fieldFromInstruction(Insn, 21, 1); 2547 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2548 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2549 } 2550 2551 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2552 uint64_t Address, const void *Decoder) { 2553 DecodeStatus S = MCDisassembler::Success; 2554 2555 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2556 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2557 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2558 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2559 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2560 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2561 2562 // Writeback Operand 2563 switch (Inst.getOpcode()) { 2564 case ARM::VST1d8wb_fixed: 2565 case ARM::VST1d16wb_fixed: 2566 case ARM::VST1d32wb_fixed: 2567 case ARM::VST1d64wb_fixed: 2568 case ARM::VST1d8wb_register: 2569 case ARM::VST1d16wb_register: 2570 case ARM::VST1d32wb_register: 2571 case ARM::VST1d64wb_register: 2572 case ARM::VST1q8wb_fixed: 2573 case ARM::VST1q16wb_fixed: 2574 case ARM::VST1q32wb_fixed: 2575 case ARM::VST1q64wb_fixed: 2576 case ARM::VST1q8wb_register: 2577 case ARM::VST1q16wb_register: 2578 case ARM::VST1q32wb_register: 2579 case ARM::VST1q64wb_register: 2580 case ARM::VST1d8Twb_fixed: 2581 case ARM::VST1d16Twb_fixed: 2582 case ARM::VST1d32Twb_fixed: 2583 case ARM::VST1d64Twb_fixed: 2584 case ARM::VST1d8Twb_register: 2585 case ARM::VST1d16Twb_register: 2586 case ARM::VST1d32Twb_register: 2587 case ARM::VST1d64Twb_register: 2588 case ARM::VST1d8Qwb_fixed: 2589 case ARM::VST1d16Qwb_fixed: 2590 case ARM::VST1d32Qwb_fixed: 2591 case ARM::VST1d64Qwb_fixed: 2592 case ARM::VST1d8Qwb_register: 2593 case ARM::VST1d16Qwb_register: 2594 case ARM::VST1d32Qwb_register: 2595 case ARM::VST1d64Qwb_register: 2596 case ARM::VST2d8wb_fixed: 2597 case ARM::VST2d16wb_fixed: 2598 case ARM::VST2d32wb_fixed: 2599 case ARM::VST2d8wb_register: 2600 case ARM::VST2d16wb_register: 2601 case ARM::VST2d32wb_register: 2602 case ARM::VST2q8wb_fixed: 2603 case ARM::VST2q16wb_fixed: 2604 case ARM::VST2q32wb_fixed: 2605 case ARM::VST2q8wb_register: 2606 case ARM::VST2q16wb_register: 2607 case ARM::VST2q32wb_register: 2608 case ARM::VST2b8wb_fixed: 2609 case ARM::VST2b16wb_fixed: 2610 case ARM::VST2b32wb_fixed: 2611 case ARM::VST2b8wb_register: 2612 case ARM::VST2b16wb_register: 2613 case ARM::VST2b32wb_register: 2614 if (Rm == 0xF) 2615 return MCDisassembler::Fail; 2616 Inst.addOperand(MCOperand::CreateImm(0)); 2617 break; 2618 case ARM::VST3d8_UPD: 2619 case ARM::VST3d16_UPD: 2620 case ARM::VST3d32_UPD: 2621 case ARM::VST3q8_UPD: 2622 case ARM::VST3q16_UPD: 2623 case ARM::VST3q32_UPD: 2624 case ARM::VST4d8_UPD: 2625 case ARM::VST4d16_UPD: 2626 case ARM::VST4d32_UPD: 2627 case ARM::VST4q8_UPD: 2628 case ARM::VST4q16_UPD: 2629 case ARM::VST4q32_UPD: 2630 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2631 return MCDisassembler::Fail; 2632 break; 2633 default: 2634 break; 2635 } 2636 2637 // AddrMode6 Base (register+alignment) 2638 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2639 return MCDisassembler::Fail; 2640 2641 // AddrMode6 Offset (register) 2642 switch (Inst.getOpcode()) { 2643 default: 2644 if (Rm == 0xD) 2645 Inst.addOperand(MCOperand::CreateReg(0)); 2646 else if (Rm != 0xF) { 2647 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2648 return MCDisassembler::Fail; 2649 } 2650 break; 2651 case ARM::VST1d8wb_fixed: 2652 case ARM::VST1d16wb_fixed: 2653 case ARM::VST1d32wb_fixed: 2654 case ARM::VST1d64wb_fixed: 2655 case ARM::VST1q8wb_fixed: 2656 case ARM::VST1q16wb_fixed: 2657 case ARM::VST1q32wb_fixed: 2658 case ARM::VST1q64wb_fixed: 2659 case ARM::VST1d8Twb_fixed: 2660 case ARM::VST1d16Twb_fixed: 2661 case ARM::VST1d32Twb_fixed: 2662 case ARM::VST1d64Twb_fixed: 2663 case ARM::VST1d8Qwb_fixed: 2664 case ARM::VST1d16Qwb_fixed: 2665 case ARM::VST1d32Qwb_fixed: 2666 case ARM::VST1d64Qwb_fixed: 2667 case ARM::VST2d8wb_fixed: 2668 case ARM::VST2d16wb_fixed: 2669 case ARM::VST2d32wb_fixed: 2670 case ARM::VST2q8wb_fixed: 2671 case ARM::VST2q16wb_fixed: 2672 case ARM::VST2q32wb_fixed: 2673 case ARM::VST2b8wb_fixed: 2674 case ARM::VST2b16wb_fixed: 2675 case ARM::VST2b32wb_fixed: 2676 break; 2677 } 2678 2679 2680 // First input register 2681 switch (Inst.getOpcode()) { 2682 case ARM::VST1q16: 2683 case ARM::VST1q32: 2684 case ARM::VST1q64: 2685 case ARM::VST1q8: 2686 case ARM::VST1q16wb_fixed: 2687 case ARM::VST1q16wb_register: 2688 case ARM::VST1q32wb_fixed: 2689 case ARM::VST1q32wb_register: 2690 case ARM::VST1q64wb_fixed: 2691 case ARM::VST1q64wb_register: 2692 case ARM::VST1q8wb_fixed: 2693 case ARM::VST1q8wb_register: 2694 case ARM::VST2d16: 2695 case ARM::VST2d32: 2696 case ARM::VST2d8: 2697 case ARM::VST2d16wb_fixed: 2698 case ARM::VST2d16wb_register: 2699 case ARM::VST2d32wb_fixed: 2700 case ARM::VST2d32wb_register: 2701 case ARM::VST2d8wb_fixed: 2702 case ARM::VST2d8wb_register: 2703 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2704 return MCDisassembler::Fail; 2705 break; 2706 case ARM::VST2b16: 2707 case ARM::VST2b32: 2708 case ARM::VST2b8: 2709 case ARM::VST2b16wb_fixed: 2710 case ARM::VST2b16wb_register: 2711 case ARM::VST2b32wb_fixed: 2712 case ARM::VST2b32wb_register: 2713 case ARM::VST2b8wb_fixed: 2714 case ARM::VST2b8wb_register: 2715 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2716 return MCDisassembler::Fail; 2717 break; 2718 default: 2719 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2720 return MCDisassembler::Fail; 2721 } 2722 2723 // Second input register 2724 switch (Inst.getOpcode()) { 2725 case ARM::VST3d8: 2726 case ARM::VST3d16: 2727 case ARM::VST3d32: 2728 case ARM::VST3d8_UPD: 2729 case ARM::VST3d16_UPD: 2730 case ARM::VST3d32_UPD: 2731 case ARM::VST4d8: 2732 case ARM::VST4d16: 2733 case ARM::VST4d32: 2734 case ARM::VST4d8_UPD: 2735 case ARM::VST4d16_UPD: 2736 case ARM::VST4d32_UPD: 2737 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2738 return MCDisassembler::Fail; 2739 break; 2740 case ARM::VST3q8: 2741 case ARM::VST3q16: 2742 case ARM::VST3q32: 2743 case ARM::VST3q8_UPD: 2744 case ARM::VST3q16_UPD: 2745 case ARM::VST3q32_UPD: 2746 case ARM::VST4q8: 2747 case ARM::VST4q16: 2748 case ARM::VST4q32: 2749 case ARM::VST4q8_UPD: 2750 case ARM::VST4q16_UPD: 2751 case ARM::VST4q32_UPD: 2752 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2753 return MCDisassembler::Fail; 2754 break; 2755 default: 2756 break; 2757 } 2758 2759 // Third input register 2760 switch (Inst.getOpcode()) { 2761 case ARM::VST3d8: 2762 case ARM::VST3d16: 2763 case ARM::VST3d32: 2764 case ARM::VST3d8_UPD: 2765 case ARM::VST3d16_UPD: 2766 case ARM::VST3d32_UPD: 2767 case ARM::VST4d8: 2768 case ARM::VST4d16: 2769 case ARM::VST4d32: 2770 case ARM::VST4d8_UPD: 2771 case ARM::VST4d16_UPD: 2772 case ARM::VST4d32_UPD: 2773 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2774 return MCDisassembler::Fail; 2775 break; 2776 case ARM::VST3q8: 2777 case ARM::VST3q16: 2778 case ARM::VST3q32: 2779 case ARM::VST3q8_UPD: 2780 case ARM::VST3q16_UPD: 2781 case ARM::VST3q32_UPD: 2782 case ARM::VST4q8: 2783 case ARM::VST4q16: 2784 case ARM::VST4q32: 2785 case ARM::VST4q8_UPD: 2786 case ARM::VST4q16_UPD: 2787 case ARM::VST4q32_UPD: 2788 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2789 return MCDisassembler::Fail; 2790 break; 2791 default: 2792 break; 2793 } 2794 2795 // Fourth input register 2796 switch (Inst.getOpcode()) { 2797 case ARM::VST4d8: 2798 case ARM::VST4d16: 2799 case ARM::VST4d32: 2800 case ARM::VST4d8_UPD: 2801 case ARM::VST4d16_UPD: 2802 case ARM::VST4d32_UPD: 2803 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2804 return MCDisassembler::Fail; 2805 break; 2806 case ARM::VST4q8: 2807 case ARM::VST4q16: 2808 case ARM::VST4q32: 2809 case ARM::VST4q8_UPD: 2810 case ARM::VST4q16_UPD: 2811 case ARM::VST4q32_UPD: 2812 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2813 return MCDisassembler::Fail; 2814 break; 2815 default: 2816 break; 2817 } 2818 2819 return S; 2820 } 2821 2822 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 2823 uint64_t Address, const void *Decoder) { 2824 DecodeStatus S = MCDisassembler::Success; 2825 2826 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2827 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2828 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2829 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2830 unsigned align = fieldFromInstruction(Insn, 4, 1); 2831 unsigned size = fieldFromInstruction(Insn, 6, 2); 2832 2833 if (size == 0 && align == 1) 2834 return MCDisassembler::Fail; 2835 align *= (1 << size); 2836 2837 switch (Inst.getOpcode()) { 2838 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2839 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2840 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2841 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2842 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2843 return MCDisassembler::Fail; 2844 break; 2845 default: 2846 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2847 return MCDisassembler::Fail; 2848 break; 2849 } 2850 if (Rm != 0xF) { 2851 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2852 return MCDisassembler::Fail; 2853 } 2854 2855 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2856 return MCDisassembler::Fail; 2857 Inst.addOperand(MCOperand::CreateImm(align)); 2858 2859 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2860 // variant encodes Rm == 0xf. Anything else is a register offset post- 2861 // increment and we need to add the register operand to the instruction. 2862 if (Rm != 0xD && Rm != 0xF && 2863 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2864 return MCDisassembler::Fail; 2865 2866 return S; 2867 } 2868 2869 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 2870 uint64_t Address, const void *Decoder) { 2871 DecodeStatus S = MCDisassembler::Success; 2872 2873 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2874 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2875 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2876 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2877 unsigned align = fieldFromInstruction(Insn, 4, 1); 2878 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 2879 align *= 2*size; 2880 2881 switch (Inst.getOpcode()) { 2882 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2883 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2884 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2885 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2886 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2887 return MCDisassembler::Fail; 2888 break; 2889 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 2890 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 2891 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 2892 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 2893 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2894 return MCDisassembler::Fail; 2895 break; 2896 default: 2897 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2898 return MCDisassembler::Fail; 2899 break; 2900 } 2901 2902 if (Rm != 0xF) 2903 Inst.addOperand(MCOperand::CreateImm(0)); 2904 2905 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2906 return MCDisassembler::Fail; 2907 Inst.addOperand(MCOperand::CreateImm(align)); 2908 2909 if (Rm != 0xD && Rm != 0xF) { 2910 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2911 return MCDisassembler::Fail; 2912 } 2913 2914 return S; 2915 } 2916 2917 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 2918 uint64_t Address, const void *Decoder) { 2919 DecodeStatus S = MCDisassembler::Success; 2920 2921 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2922 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2923 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2924 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2925 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2926 2927 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2928 return MCDisassembler::Fail; 2929 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2930 return MCDisassembler::Fail; 2931 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2932 return MCDisassembler::Fail; 2933 if (Rm != 0xF) { 2934 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2935 return MCDisassembler::Fail; 2936 } 2937 2938 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2939 return MCDisassembler::Fail; 2940 Inst.addOperand(MCOperand::CreateImm(0)); 2941 2942 if (Rm == 0xD) 2943 Inst.addOperand(MCOperand::CreateReg(0)); 2944 else if (Rm != 0xF) { 2945 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2946 return MCDisassembler::Fail; 2947 } 2948 2949 return S; 2950 } 2951 2952 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 2953 uint64_t Address, const void *Decoder) { 2954 DecodeStatus S = MCDisassembler::Success; 2955 2956 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2957 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2958 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2959 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2960 unsigned size = fieldFromInstruction(Insn, 6, 2); 2961 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2962 unsigned align = fieldFromInstruction(Insn, 4, 1); 2963 2964 if (size == 0x3) { 2965 if (align == 0) 2966 return MCDisassembler::Fail; 2967 size = 4; 2968 align = 16; 2969 } else { 2970 if (size == 2) { 2971 size = 1 << size; 2972 align *= 8; 2973 } else { 2974 size = 1 << size; 2975 align *= 4*size; 2976 } 2977 } 2978 2979 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2980 return MCDisassembler::Fail; 2981 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2982 return MCDisassembler::Fail; 2983 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2984 return MCDisassembler::Fail; 2985 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2986 return MCDisassembler::Fail; 2987 if (Rm != 0xF) { 2988 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2989 return MCDisassembler::Fail; 2990 } 2991 2992 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2993 return MCDisassembler::Fail; 2994 Inst.addOperand(MCOperand::CreateImm(align)); 2995 2996 if (Rm == 0xD) 2997 Inst.addOperand(MCOperand::CreateReg(0)); 2998 else if (Rm != 0xF) { 2999 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3000 return MCDisassembler::Fail; 3001 } 3002 3003 return S; 3004 } 3005 3006 static DecodeStatus 3007 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 3008 uint64_t Address, const void *Decoder) { 3009 DecodeStatus S = MCDisassembler::Success; 3010 3011 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3012 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3013 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3014 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3015 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3016 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3017 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3018 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3019 3020 if (Q) { 3021 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3022 return MCDisassembler::Fail; 3023 } else { 3024 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3025 return MCDisassembler::Fail; 3026 } 3027 3028 Inst.addOperand(MCOperand::CreateImm(imm)); 3029 3030 switch (Inst.getOpcode()) { 3031 case ARM::VORRiv4i16: 3032 case ARM::VORRiv2i32: 3033 case ARM::VBICiv4i16: 3034 case ARM::VBICiv2i32: 3035 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3036 return MCDisassembler::Fail; 3037 break; 3038 case ARM::VORRiv8i16: 3039 case ARM::VORRiv4i32: 3040 case ARM::VBICiv8i16: 3041 case ARM::VBICiv4i32: 3042 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3043 return MCDisassembler::Fail; 3044 break; 3045 default: 3046 break; 3047 } 3048 3049 return S; 3050 } 3051 3052 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3053 uint64_t Address, const void *Decoder) { 3054 DecodeStatus S = MCDisassembler::Success; 3055 3056 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3057 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3058 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3059 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3060 unsigned size = fieldFromInstruction(Insn, 18, 2); 3061 3062 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3063 return MCDisassembler::Fail; 3064 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3065 return MCDisassembler::Fail; 3066 Inst.addOperand(MCOperand::CreateImm(8 << size)); 3067 3068 return S; 3069 } 3070 3071 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3072 uint64_t Address, const void *Decoder) { 3073 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 3074 return MCDisassembler::Success; 3075 } 3076 3077 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3078 uint64_t Address, const void *Decoder) { 3079 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 3080 return MCDisassembler::Success; 3081 } 3082 3083 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3084 uint64_t Address, const void *Decoder) { 3085 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 3086 return MCDisassembler::Success; 3087 } 3088 3089 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3090 uint64_t Address, const void *Decoder) { 3091 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 3092 return MCDisassembler::Success; 3093 } 3094 3095 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3096 uint64_t Address, const void *Decoder) { 3097 DecodeStatus S = MCDisassembler::Success; 3098 3099 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3100 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3101 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3102 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3103 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3104 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3105 unsigned op = fieldFromInstruction(Insn, 6, 1); 3106 3107 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3108 return MCDisassembler::Fail; 3109 if (op) { 3110 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3111 return MCDisassembler::Fail; // Writeback 3112 } 3113 3114 switch (Inst.getOpcode()) { 3115 case ARM::VTBL2: 3116 case ARM::VTBX2: 3117 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3118 return MCDisassembler::Fail; 3119 break; 3120 default: 3121 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3122 return MCDisassembler::Fail; 3123 } 3124 3125 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3126 return MCDisassembler::Fail; 3127 3128 return S; 3129 } 3130 3131 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3132 uint64_t Address, const void *Decoder) { 3133 DecodeStatus S = MCDisassembler::Success; 3134 3135 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3136 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3137 3138 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3139 return MCDisassembler::Fail; 3140 3141 switch(Inst.getOpcode()) { 3142 default: 3143 return MCDisassembler::Fail; 3144 case ARM::tADR: 3145 break; // tADR does not explicitly represent the PC as an operand. 3146 case ARM::tADDrSPi: 3147 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3148 break; 3149 } 3150 3151 Inst.addOperand(MCOperand::CreateImm(imm)); 3152 return S; 3153 } 3154 3155 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3156 uint64_t Address, const void *Decoder) { 3157 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3158 true, 2, Inst, Decoder)) 3159 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 3160 return MCDisassembler::Success; 3161 } 3162 3163 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3164 uint64_t Address, const void *Decoder) { 3165 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3166 true, 4, Inst, Decoder)) 3167 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 3168 return MCDisassembler::Success; 3169 } 3170 3171 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3172 uint64_t Address, const void *Decoder) { 3173 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3174 true, 2, Inst, Decoder)) 3175 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 3176 return MCDisassembler::Success; 3177 } 3178 3179 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3180 uint64_t Address, const void *Decoder) { 3181 DecodeStatus S = MCDisassembler::Success; 3182 3183 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3184 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3185 3186 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3187 return MCDisassembler::Fail; 3188 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3189 return MCDisassembler::Fail; 3190 3191 return S; 3192 } 3193 3194 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3195 uint64_t Address, const void *Decoder) { 3196 DecodeStatus S = MCDisassembler::Success; 3197 3198 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3199 unsigned imm = fieldFromInstruction(Val, 3, 5); 3200 3201 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3202 return MCDisassembler::Fail; 3203 Inst.addOperand(MCOperand::CreateImm(imm)); 3204 3205 return S; 3206 } 3207 3208 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3209 uint64_t Address, const void *Decoder) { 3210 unsigned imm = Val << 2; 3211 3212 Inst.addOperand(MCOperand::CreateImm(imm)); 3213 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3214 3215 return MCDisassembler::Success; 3216 } 3217 3218 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3219 uint64_t Address, const void *Decoder) { 3220 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3221 Inst.addOperand(MCOperand::CreateImm(Val)); 3222 3223 return MCDisassembler::Success; 3224 } 3225 3226 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3227 uint64_t Address, const void *Decoder) { 3228 DecodeStatus S = MCDisassembler::Success; 3229 3230 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3231 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3232 unsigned imm = fieldFromInstruction(Val, 0, 2); 3233 3234 // Thumb stores cannot use PC as dest register. 3235 switch (Inst.getOpcode()) { 3236 case ARM::t2STRHs: 3237 case ARM::t2STRBs: 3238 case ARM::t2STRs: 3239 if (Rn == 15) 3240 return MCDisassembler::Fail; 3241 default: 3242 break; 3243 } 3244 3245 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3246 return MCDisassembler::Fail; 3247 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3248 return MCDisassembler::Fail; 3249 Inst.addOperand(MCOperand::CreateImm(imm)); 3250 3251 return S; 3252 } 3253 3254 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3255 uint64_t Address, const void *Decoder) { 3256 DecodeStatus S = MCDisassembler::Success; 3257 3258 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3259 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3260 3261 if (Rn == 15) { 3262 switch (Inst.getOpcode()) { 3263 case ARM::t2LDRBs: 3264 Inst.setOpcode(ARM::t2LDRBpci); 3265 break; 3266 case ARM::t2LDRHs: 3267 Inst.setOpcode(ARM::t2LDRHpci); 3268 break; 3269 case ARM::t2LDRSHs: 3270 Inst.setOpcode(ARM::t2LDRSHpci); 3271 break; 3272 case ARM::t2LDRSBs: 3273 Inst.setOpcode(ARM::t2LDRSBpci); 3274 break; 3275 case ARM::t2LDRs: 3276 Inst.setOpcode(ARM::t2LDRpci); 3277 break; 3278 case ARM::t2PLDs: 3279 Inst.setOpcode(ARM::t2PLDpci); 3280 break; 3281 case ARM::t2PLIs: 3282 Inst.setOpcode(ARM::t2PLIpci); 3283 break; 3284 default: 3285 return MCDisassembler::Fail; 3286 } 3287 3288 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3289 } 3290 3291 if (Rt == 15) { 3292 switch (Inst.getOpcode()) { 3293 case ARM::t2LDRSHs: 3294 return MCDisassembler::Fail; 3295 case ARM::t2LDRHs: 3296 // FIXME: this instruction is only available with MP extensions, 3297 // this should be checked first but we don't have access to the 3298 // feature bits here. 3299 Inst.setOpcode(ARM::t2PLDWs); 3300 break; 3301 default: 3302 break; 3303 } 3304 } 3305 3306 switch (Inst.getOpcode()) { 3307 case ARM::t2PLDs: 3308 case ARM::t2PLDWs: 3309 case ARM::t2PLIs: 3310 break; 3311 default: 3312 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3313 return MCDisassembler::Fail; 3314 } 3315 3316 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3317 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3318 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3319 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3320 return MCDisassembler::Fail; 3321 3322 return S; 3323 } 3324 3325 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3326 uint64_t Address, const void* Decoder) { 3327 DecodeStatus S = MCDisassembler::Success; 3328 3329 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3330 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3331 unsigned U = fieldFromInstruction(Insn, 9, 1); 3332 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3333 imm |= (U << 8); 3334 imm |= (Rn << 9); 3335 3336 if (Rn == 15) { 3337 switch (Inst.getOpcode()) { 3338 case ARM::t2LDRi8: 3339 Inst.setOpcode(ARM::t2LDRpci); 3340 break; 3341 case ARM::t2LDRBi8: 3342 Inst.setOpcode(ARM::t2LDRBpci); 3343 break; 3344 case ARM::t2LDRSBi8: 3345 Inst.setOpcode(ARM::t2LDRSBpci); 3346 break; 3347 case ARM::t2LDRHi8: 3348 Inst.setOpcode(ARM::t2LDRHpci); 3349 break; 3350 case ARM::t2LDRSHi8: 3351 Inst.setOpcode(ARM::t2LDRSHpci); 3352 break; 3353 case ARM::t2PLDi8: 3354 Inst.setOpcode(ARM::t2PLDpci); 3355 break; 3356 case ARM::t2PLIi8: 3357 Inst.setOpcode(ARM::t2PLIpci); 3358 break; 3359 default: 3360 return MCDisassembler::Fail; 3361 } 3362 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3363 } 3364 3365 if (Rt == 15) { 3366 switch (Inst.getOpcode()) { 3367 case ARM::t2LDRSHi8: 3368 return MCDisassembler::Fail; 3369 default: 3370 break; 3371 } 3372 } 3373 3374 switch (Inst.getOpcode()) { 3375 case ARM::t2PLDi8: 3376 case ARM::t2PLIi8: 3377 case ARM::t2PLDWi8: 3378 break; 3379 default: 3380 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3381 return MCDisassembler::Fail; 3382 } 3383 3384 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3385 return MCDisassembler::Fail; 3386 return S; 3387 } 3388 3389 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3390 uint64_t Address, const void* Decoder) { 3391 DecodeStatus S = MCDisassembler::Success; 3392 3393 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3394 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3395 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3396 imm |= (Rn << 13); 3397 3398 if (Rn == 15) { 3399 switch (Inst.getOpcode()) { 3400 case ARM::t2LDRi12: 3401 Inst.setOpcode(ARM::t2LDRpci); 3402 break; 3403 case ARM::t2LDRHi12: 3404 Inst.setOpcode(ARM::t2LDRHpci); 3405 break; 3406 case ARM::t2LDRSHi12: 3407 Inst.setOpcode(ARM::t2LDRSHpci); 3408 break; 3409 case ARM::t2LDRBi12: 3410 Inst.setOpcode(ARM::t2LDRBpci); 3411 break; 3412 case ARM::t2LDRSBi12: 3413 Inst.setOpcode(ARM::t2LDRSBpci); 3414 break; 3415 case ARM::t2PLDi12: 3416 Inst.setOpcode(ARM::t2PLDpci); 3417 break; 3418 case ARM::t2PLIi12: 3419 Inst.setOpcode(ARM::t2PLIpci); 3420 break; 3421 default: 3422 return MCDisassembler::Fail; 3423 } 3424 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3425 } 3426 3427 if (Rt == 15) { 3428 switch (Inst.getOpcode()) { 3429 case ARM::t2LDRSHi12: 3430 return MCDisassembler::Fail; 3431 case ARM::t2LDRHi12: 3432 Inst.setOpcode(ARM::t2PLDi12); 3433 break; 3434 default: 3435 break; 3436 } 3437 } 3438 3439 switch (Inst.getOpcode()) { 3440 case ARM::t2PLDi12: 3441 case ARM::t2PLDWi12: 3442 case ARM::t2PLIi12: 3443 break; 3444 default: 3445 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3446 return MCDisassembler::Fail; 3447 } 3448 3449 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 3450 return MCDisassembler::Fail; 3451 return S; 3452 } 3453 3454 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 3455 uint64_t Address, const void* Decoder) { 3456 DecodeStatus S = MCDisassembler::Success; 3457 3458 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3459 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3460 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3461 imm |= (Rn << 9); 3462 3463 if (Rn == 15) { 3464 switch (Inst.getOpcode()) { 3465 case ARM::t2LDRT: 3466 Inst.setOpcode(ARM::t2LDRpci); 3467 break; 3468 case ARM::t2LDRBT: 3469 Inst.setOpcode(ARM::t2LDRBpci); 3470 break; 3471 case ARM::t2LDRHT: 3472 Inst.setOpcode(ARM::t2LDRHpci); 3473 break; 3474 case ARM::t2LDRSBT: 3475 Inst.setOpcode(ARM::t2LDRSBpci); 3476 break; 3477 case ARM::t2LDRSHT: 3478 Inst.setOpcode(ARM::t2LDRSHpci); 3479 break; 3480 default: 3481 return MCDisassembler::Fail; 3482 } 3483 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3484 } 3485 3486 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3487 return MCDisassembler::Fail; 3488 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3489 return MCDisassembler::Fail; 3490 return S; 3491 } 3492 3493 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 3494 uint64_t Address, const void* Decoder) { 3495 DecodeStatus S = MCDisassembler::Success; 3496 3497 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3498 unsigned U = fieldFromInstruction(Insn, 23, 1); 3499 int imm = fieldFromInstruction(Insn, 0, 12); 3500 3501 if (Rt == 15) { 3502 switch (Inst.getOpcode()) { 3503 case ARM::t2LDRBpci: 3504 case ARM::t2LDRHpci: 3505 Inst.setOpcode(ARM::t2PLDpci); 3506 break; 3507 case ARM::t2LDRSBpci: 3508 Inst.setOpcode(ARM::t2PLIpci); 3509 break; 3510 case ARM::t2LDRSHpci: 3511 return MCDisassembler::Fail; 3512 default: 3513 break; 3514 } 3515 } 3516 3517 switch(Inst.getOpcode()) { 3518 case ARM::t2PLDpci: 3519 case ARM::t2PLIpci: 3520 break; 3521 default: 3522 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3523 return MCDisassembler::Fail; 3524 } 3525 3526 if (!U) { 3527 // Special case for #-0. 3528 if (imm == 0) 3529 imm = INT32_MIN; 3530 else 3531 imm = -imm; 3532 } 3533 Inst.addOperand(MCOperand::CreateImm(imm)); 3534 3535 return S; 3536 } 3537 3538 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3539 uint64_t Address, const void *Decoder) { 3540 if (Val == 0) 3541 Inst.addOperand(MCOperand::CreateImm(INT32_MIN)); 3542 else { 3543 int imm = Val & 0xFF; 3544 3545 if (!(Val & 0x100)) imm *= -1; 3546 Inst.addOperand(MCOperand::CreateImm(imm * 4)); 3547 } 3548 3549 return MCDisassembler::Success; 3550 } 3551 3552 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3553 uint64_t Address, const void *Decoder) { 3554 DecodeStatus S = MCDisassembler::Success; 3555 3556 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3557 unsigned imm = fieldFromInstruction(Val, 0, 9); 3558 3559 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3560 return MCDisassembler::Fail; 3561 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3562 return MCDisassembler::Fail; 3563 3564 return S; 3565 } 3566 3567 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3568 uint64_t Address, const void *Decoder) { 3569 DecodeStatus S = MCDisassembler::Success; 3570 3571 unsigned Rn = fieldFromInstruction(Val, 8, 4); 3572 unsigned imm = fieldFromInstruction(Val, 0, 8); 3573 3574 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3575 return MCDisassembler::Fail; 3576 3577 Inst.addOperand(MCOperand::CreateImm(imm)); 3578 3579 return S; 3580 } 3581 3582 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3583 uint64_t Address, const void *Decoder) { 3584 int imm = Val & 0xFF; 3585 if (Val == 0) 3586 imm = INT32_MIN; 3587 else if (!(Val & 0x100)) 3588 imm *= -1; 3589 Inst.addOperand(MCOperand::CreateImm(imm)); 3590 3591 return MCDisassembler::Success; 3592 } 3593 3594 3595 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3596 uint64_t Address, const void *Decoder) { 3597 DecodeStatus S = MCDisassembler::Success; 3598 3599 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3600 unsigned imm = fieldFromInstruction(Val, 0, 9); 3601 3602 // Thumb stores cannot use PC as dest register. 3603 switch (Inst.getOpcode()) { 3604 case ARM::t2STRT: 3605 case ARM::t2STRBT: 3606 case ARM::t2STRHT: 3607 case ARM::t2STRi8: 3608 case ARM::t2STRHi8: 3609 case ARM::t2STRBi8: 3610 if (Rn == 15) 3611 return MCDisassembler::Fail; 3612 break; 3613 default: 3614 break; 3615 } 3616 3617 // Some instructions always use an additive offset. 3618 switch (Inst.getOpcode()) { 3619 case ARM::t2LDRT: 3620 case ARM::t2LDRBT: 3621 case ARM::t2LDRHT: 3622 case ARM::t2LDRSBT: 3623 case ARM::t2LDRSHT: 3624 case ARM::t2STRT: 3625 case ARM::t2STRBT: 3626 case ARM::t2STRHT: 3627 imm |= 0x100; 3628 break; 3629 default: 3630 break; 3631 } 3632 3633 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3634 return MCDisassembler::Fail; 3635 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3636 return MCDisassembler::Fail; 3637 3638 return S; 3639 } 3640 3641 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3642 uint64_t Address, const void *Decoder) { 3643 DecodeStatus S = MCDisassembler::Success; 3644 3645 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3646 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3647 unsigned addr = fieldFromInstruction(Insn, 0, 8); 3648 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 3649 addr |= Rn << 9; 3650 unsigned load = fieldFromInstruction(Insn, 20, 1); 3651 3652 if (Rn == 15) { 3653 switch (Inst.getOpcode()) { 3654 case ARM::t2LDR_PRE: 3655 case ARM::t2LDR_POST: 3656 Inst.setOpcode(ARM::t2LDRpci); 3657 break; 3658 case ARM::t2LDRB_PRE: 3659 case ARM::t2LDRB_POST: 3660 Inst.setOpcode(ARM::t2LDRBpci); 3661 break; 3662 case ARM::t2LDRH_PRE: 3663 case ARM::t2LDRH_POST: 3664 Inst.setOpcode(ARM::t2LDRHpci); 3665 break; 3666 case ARM::t2LDRSB_PRE: 3667 case ARM::t2LDRSB_POST: 3668 if (Rt == 15) 3669 Inst.setOpcode(ARM::t2PLIpci); 3670 else 3671 Inst.setOpcode(ARM::t2LDRSBpci); 3672 break; 3673 case ARM::t2LDRSH_PRE: 3674 case ARM::t2LDRSH_POST: 3675 Inst.setOpcode(ARM::t2LDRSHpci); 3676 break; 3677 default: 3678 return MCDisassembler::Fail; 3679 } 3680 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3681 } 3682 3683 if (!load) { 3684 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3685 return MCDisassembler::Fail; 3686 } 3687 3688 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3689 return MCDisassembler::Fail; 3690 3691 if (load) { 3692 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3693 return MCDisassembler::Fail; 3694 } 3695 3696 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3697 return MCDisassembler::Fail; 3698 3699 return S; 3700 } 3701 3702 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 3703 uint64_t Address, const void *Decoder) { 3704 DecodeStatus S = MCDisassembler::Success; 3705 3706 unsigned Rn = fieldFromInstruction(Val, 13, 4); 3707 unsigned imm = fieldFromInstruction(Val, 0, 12); 3708 3709 // Thumb stores cannot use PC as dest register. 3710 switch (Inst.getOpcode()) { 3711 case ARM::t2STRi12: 3712 case ARM::t2STRBi12: 3713 case ARM::t2STRHi12: 3714 if (Rn == 15) 3715 return MCDisassembler::Fail; 3716 default: 3717 break; 3718 } 3719 3720 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3721 return MCDisassembler::Fail; 3722 Inst.addOperand(MCOperand::CreateImm(imm)); 3723 3724 return S; 3725 } 3726 3727 3728 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 3729 uint64_t Address, const void *Decoder) { 3730 unsigned imm = fieldFromInstruction(Insn, 0, 7); 3731 3732 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3733 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3734 Inst.addOperand(MCOperand::CreateImm(imm)); 3735 3736 return MCDisassembler::Success; 3737 } 3738 3739 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 3740 uint64_t Address, const void *Decoder) { 3741 DecodeStatus S = MCDisassembler::Success; 3742 3743 if (Inst.getOpcode() == ARM::tADDrSP) { 3744 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 3745 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 3746 3747 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3748 return MCDisassembler::Fail; 3749 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3750 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3751 return MCDisassembler::Fail; 3752 } else if (Inst.getOpcode() == ARM::tADDspr) { 3753 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 3754 3755 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3756 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3757 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3758 return MCDisassembler::Fail; 3759 } 3760 3761 return S; 3762 } 3763 3764 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 3765 uint64_t Address, const void *Decoder) { 3766 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 3767 unsigned flags = fieldFromInstruction(Insn, 0, 3); 3768 3769 Inst.addOperand(MCOperand::CreateImm(imod)); 3770 Inst.addOperand(MCOperand::CreateImm(flags)); 3771 3772 return MCDisassembler::Success; 3773 } 3774 3775 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 3776 uint64_t Address, const void *Decoder) { 3777 DecodeStatus S = MCDisassembler::Success; 3778 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3779 unsigned add = fieldFromInstruction(Insn, 4, 1); 3780 3781 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3782 return MCDisassembler::Fail; 3783 Inst.addOperand(MCOperand::CreateImm(add)); 3784 3785 return S; 3786 } 3787 3788 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 3789 uint64_t Address, const void *Decoder) { 3790 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 3791 // Note only one trailing zero not two. Also the J1 and J2 values are from 3792 // the encoded instruction. So here change to I1 and I2 values via: 3793 // I1 = NOT(J1 EOR S); 3794 // I2 = NOT(J2 EOR S); 3795 // and build the imm32 with two trailing zeros as documented: 3796 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 3797 unsigned S = (Val >> 23) & 1; 3798 unsigned J1 = (Val >> 22) & 1; 3799 unsigned J2 = (Val >> 21) & 1; 3800 unsigned I1 = !(J1 ^ S); 3801 unsigned I2 = !(J2 ^ S); 3802 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3803 int imm32 = SignExtend32<25>(tmp << 1); 3804 3805 if (!tryAddingSymbolicOperand(Address, 3806 (Address & ~2u) + imm32 + 4, 3807 true, 4, Inst, Decoder)) 3808 Inst.addOperand(MCOperand::CreateImm(imm32)); 3809 return MCDisassembler::Success; 3810 } 3811 3812 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 3813 uint64_t Address, const void *Decoder) { 3814 if (Val == 0xA || Val == 0xB) 3815 return MCDisassembler::Fail; 3816 3817 Inst.addOperand(MCOperand::CreateImm(Val)); 3818 return MCDisassembler::Success; 3819 } 3820 3821 static DecodeStatus 3822 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 3823 uint64_t Address, const void *Decoder) { 3824 DecodeStatus S = MCDisassembler::Success; 3825 3826 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3827 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3828 3829 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3830 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3831 return MCDisassembler::Fail; 3832 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3833 return MCDisassembler::Fail; 3834 return S; 3835 } 3836 3837 static DecodeStatus 3838 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 3839 uint64_t Address, const void *Decoder) { 3840 DecodeStatus S = MCDisassembler::Success; 3841 3842 unsigned pred = fieldFromInstruction(Insn, 22, 4); 3843 if (pred == 0xE || pred == 0xF) { 3844 unsigned opc = fieldFromInstruction(Insn, 4, 28); 3845 switch (opc) { 3846 default: 3847 return MCDisassembler::Fail; 3848 case 0xf3bf8f4: 3849 Inst.setOpcode(ARM::t2DSB); 3850 break; 3851 case 0xf3bf8f5: 3852 Inst.setOpcode(ARM::t2DMB); 3853 break; 3854 case 0xf3bf8f6: 3855 Inst.setOpcode(ARM::t2ISB); 3856 break; 3857 } 3858 3859 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3860 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3861 } 3862 3863 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 3864 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 3865 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 3866 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 3867 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 3868 3869 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3870 return MCDisassembler::Fail; 3871 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3872 return MCDisassembler::Fail; 3873 3874 return S; 3875 } 3876 3877 // Decode a shifted immediate operand. These basically consist 3878 // of an 8-bit value, and a 4-bit directive that specifies either 3879 // a splat operation or a rotation. 3880 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 3881 uint64_t Address, const void *Decoder) { 3882 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 3883 if (ctrl == 0) { 3884 unsigned byte = fieldFromInstruction(Val, 8, 2); 3885 unsigned imm = fieldFromInstruction(Val, 0, 8); 3886 switch (byte) { 3887 case 0: 3888 Inst.addOperand(MCOperand::CreateImm(imm)); 3889 break; 3890 case 1: 3891 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 3892 break; 3893 case 2: 3894 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 3895 break; 3896 case 3: 3897 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 3898 (imm << 8) | imm)); 3899 break; 3900 } 3901 } else { 3902 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 3903 unsigned rot = fieldFromInstruction(Val, 7, 5); 3904 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3905 Inst.addOperand(MCOperand::CreateImm(imm)); 3906 } 3907 3908 return MCDisassembler::Success; 3909 } 3910 3911 static DecodeStatus 3912 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 3913 uint64_t Address, const void *Decoder){ 3914 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 3915 true, 2, Inst, Decoder)) 3916 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1))); 3917 return MCDisassembler::Success; 3918 } 3919 3920 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 3921 uint64_t Address, const void *Decoder){ 3922 // Val is passed in as S:J1:J2:imm10:imm11 3923 // Note no trailing zero after imm11. Also the J1 and J2 values are from 3924 // the encoded instruction. So here change to I1 and I2 values via: 3925 // I1 = NOT(J1 EOR S); 3926 // I2 = NOT(J2 EOR S); 3927 // and build the imm32 with one trailing zero as documented: 3928 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 3929 unsigned S = (Val >> 23) & 1; 3930 unsigned J1 = (Val >> 22) & 1; 3931 unsigned J2 = (Val >> 21) & 1; 3932 unsigned I1 = !(J1 ^ S); 3933 unsigned I2 = !(J2 ^ S); 3934 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3935 int imm32 = SignExtend32<25>(tmp << 1); 3936 3937 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 3938 true, 4, Inst, Decoder)) 3939 Inst.addOperand(MCOperand::CreateImm(imm32)); 3940 return MCDisassembler::Success; 3941 } 3942 3943 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 3944 uint64_t Address, const void *Decoder) { 3945 if (Val & ~0xf) 3946 return MCDisassembler::Fail; 3947 3948 Inst.addOperand(MCOperand::CreateImm(Val)); 3949 return MCDisassembler::Success; 3950 } 3951 3952 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 3953 uint64_t Address, const void *Decoder) { 3954 if (Val & ~0xf) 3955 return MCDisassembler::Fail; 3956 3957 Inst.addOperand(MCOperand::CreateImm(Val)); 3958 return MCDisassembler::Success; 3959 } 3960 3961 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 3962 uint64_t Address, const void *Decoder) { 3963 if (!Val) return MCDisassembler::Fail; 3964 Inst.addOperand(MCOperand::CreateImm(Val)); 3965 return MCDisassembler::Success; 3966 } 3967 3968 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 3969 uint64_t Address, const void *Decoder) { 3970 DecodeStatus S = MCDisassembler::Success; 3971 3972 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3973 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3974 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3975 3976 if (Rn == 0xF) 3977 S = MCDisassembler::SoftFail; 3978 3979 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 3980 return MCDisassembler::Fail; 3981 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3982 return MCDisassembler::Fail; 3983 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3984 return MCDisassembler::Fail; 3985 3986 return S; 3987 } 3988 3989 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 3990 uint64_t Address, const void *Decoder){ 3991 DecodeStatus S = MCDisassembler::Success; 3992 3993 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3994 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 3995 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3996 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3997 3998 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 3999 return MCDisassembler::Fail; 4000 4001 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 4002 S = MCDisassembler::SoftFail; 4003 4004 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4005 return MCDisassembler::Fail; 4006 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4007 return MCDisassembler::Fail; 4008 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4009 return MCDisassembler::Fail; 4010 4011 return S; 4012 } 4013 4014 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 4015 uint64_t Address, const void *Decoder) { 4016 DecodeStatus S = MCDisassembler::Success; 4017 4018 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4019 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4020 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4021 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4022 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4023 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4024 4025 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4026 4027 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4028 return MCDisassembler::Fail; 4029 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4030 return MCDisassembler::Fail; 4031 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4032 return MCDisassembler::Fail; 4033 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4034 return MCDisassembler::Fail; 4035 4036 return S; 4037 } 4038 4039 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 4040 uint64_t Address, const void *Decoder) { 4041 DecodeStatus S = MCDisassembler::Success; 4042 4043 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4044 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4045 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4046 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4047 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4048 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4049 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4050 4051 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4052 if (Rm == 0xF) S = MCDisassembler::SoftFail; 4053 4054 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4055 return MCDisassembler::Fail; 4056 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4057 return MCDisassembler::Fail; 4058 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4059 return MCDisassembler::Fail; 4060 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4061 return MCDisassembler::Fail; 4062 4063 return S; 4064 } 4065 4066 4067 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4068 uint64_t Address, const void *Decoder) { 4069 DecodeStatus S = MCDisassembler::Success; 4070 4071 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4072 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4073 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4074 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4075 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4076 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4077 4078 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4079 4080 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4081 return MCDisassembler::Fail; 4082 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4083 return MCDisassembler::Fail; 4084 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4085 return MCDisassembler::Fail; 4086 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4087 return MCDisassembler::Fail; 4088 4089 return S; 4090 } 4091 4092 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4093 uint64_t Address, const void *Decoder) { 4094 DecodeStatus S = MCDisassembler::Success; 4095 4096 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4097 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4098 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4099 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4100 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4101 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4102 4103 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4104 4105 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4106 return MCDisassembler::Fail; 4107 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4108 return MCDisassembler::Fail; 4109 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4110 return MCDisassembler::Fail; 4111 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4112 return MCDisassembler::Fail; 4113 4114 return S; 4115 } 4116 4117 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4118 uint64_t Address, const void *Decoder) { 4119 DecodeStatus S = MCDisassembler::Success; 4120 4121 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4122 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4123 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4124 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4125 unsigned size = fieldFromInstruction(Insn, 10, 2); 4126 4127 unsigned align = 0; 4128 unsigned index = 0; 4129 switch (size) { 4130 default: 4131 return MCDisassembler::Fail; 4132 case 0: 4133 if (fieldFromInstruction(Insn, 4, 1)) 4134 return MCDisassembler::Fail; // UNDEFINED 4135 index = fieldFromInstruction(Insn, 5, 3); 4136 break; 4137 case 1: 4138 if (fieldFromInstruction(Insn, 5, 1)) 4139 return MCDisassembler::Fail; // UNDEFINED 4140 index = fieldFromInstruction(Insn, 6, 2); 4141 if (fieldFromInstruction(Insn, 4, 1)) 4142 align = 2; 4143 break; 4144 case 2: 4145 if (fieldFromInstruction(Insn, 6, 1)) 4146 return MCDisassembler::Fail; // UNDEFINED 4147 index = fieldFromInstruction(Insn, 7, 1); 4148 4149 switch (fieldFromInstruction(Insn, 4, 2)) { 4150 case 0 : 4151 align = 0; break; 4152 case 3: 4153 align = 4; break; 4154 default: 4155 return MCDisassembler::Fail; 4156 } 4157 break; 4158 } 4159 4160 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4161 return MCDisassembler::Fail; 4162 if (Rm != 0xF) { // Writeback 4163 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4164 return MCDisassembler::Fail; 4165 } 4166 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4167 return MCDisassembler::Fail; 4168 Inst.addOperand(MCOperand::CreateImm(align)); 4169 if (Rm != 0xF) { 4170 if (Rm != 0xD) { 4171 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4172 return MCDisassembler::Fail; 4173 } else 4174 Inst.addOperand(MCOperand::CreateReg(0)); 4175 } 4176 4177 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4178 return MCDisassembler::Fail; 4179 Inst.addOperand(MCOperand::CreateImm(index)); 4180 4181 return S; 4182 } 4183 4184 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4185 uint64_t Address, const void *Decoder) { 4186 DecodeStatus S = MCDisassembler::Success; 4187 4188 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4189 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4190 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4191 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4192 unsigned size = fieldFromInstruction(Insn, 10, 2); 4193 4194 unsigned align = 0; 4195 unsigned index = 0; 4196 switch (size) { 4197 default: 4198 return MCDisassembler::Fail; 4199 case 0: 4200 if (fieldFromInstruction(Insn, 4, 1)) 4201 return MCDisassembler::Fail; // UNDEFINED 4202 index = fieldFromInstruction(Insn, 5, 3); 4203 break; 4204 case 1: 4205 if (fieldFromInstruction(Insn, 5, 1)) 4206 return MCDisassembler::Fail; // UNDEFINED 4207 index = fieldFromInstruction(Insn, 6, 2); 4208 if (fieldFromInstruction(Insn, 4, 1)) 4209 align = 2; 4210 break; 4211 case 2: 4212 if (fieldFromInstruction(Insn, 6, 1)) 4213 return MCDisassembler::Fail; // UNDEFINED 4214 index = fieldFromInstruction(Insn, 7, 1); 4215 4216 switch (fieldFromInstruction(Insn, 4, 2)) { 4217 case 0: 4218 align = 0; break; 4219 case 3: 4220 align = 4; break; 4221 default: 4222 return MCDisassembler::Fail; 4223 } 4224 break; 4225 } 4226 4227 if (Rm != 0xF) { // Writeback 4228 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4229 return MCDisassembler::Fail; 4230 } 4231 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4232 return MCDisassembler::Fail; 4233 Inst.addOperand(MCOperand::CreateImm(align)); 4234 if (Rm != 0xF) { 4235 if (Rm != 0xD) { 4236 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4237 return MCDisassembler::Fail; 4238 } else 4239 Inst.addOperand(MCOperand::CreateReg(0)); 4240 } 4241 4242 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4243 return MCDisassembler::Fail; 4244 Inst.addOperand(MCOperand::CreateImm(index)); 4245 4246 return S; 4247 } 4248 4249 4250 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 4251 uint64_t Address, const void *Decoder) { 4252 DecodeStatus S = MCDisassembler::Success; 4253 4254 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4255 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4256 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4257 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4258 unsigned size = fieldFromInstruction(Insn, 10, 2); 4259 4260 unsigned align = 0; 4261 unsigned index = 0; 4262 unsigned inc = 1; 4263 switch (size) { 4264 default: 4265 return MCDisassembler::Fail; 4266 case 0: 4267 index = fieldFromInstruction(Insn, 5, 3); 4268 if (fieldFromInstruction(Insn, 4, 1)) 4269 align = 2; 4270 break; 4271 case 1: 4272 index = fieldFromInstruction(Insn, 6, 2); 4273 if (fieldFromInstruction(Insn, 4, 1)) 4274 align = 4; 4275 if (fieldFromInstruction(Insn, 5, 1)) 4276 inc = 2; 4277 break; 4278 case 2: 4279 if (fieldFromInstruction(Insn, 5, 1)) 4280 return MCDisassembler::Fail; // UNDEFINED 4281 index = fieldFromInstruction(Insn, 7, 1); 4282 if (fieldFromInstruction(Insn, 4, 1) != 0) 4283 align = 8; 4284 if (fieldFromInstruction(Insn, 6, 1)) 4285 inc = 2; 4286 break; 4287 } 4288 4289 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4290 return MCDisassembler::Fail; 4291 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4292 return MCDisassembler::Fail; 4293 if (Rm != 0xF) { // Writeback 4294 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4295 return MCDisassembler::Fail; 4296 } 4297 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4298 return MCDisassembler::Fail; 4299 Inst.addOperand(MCOperand::CreateImm(align)); 4300 if (Rm != 0xF) { 4301 if (Rm != 0xD) { 4302 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4303 return MCDisassembler::Fail; 4304 } else 4305 Inst.addOperand(MCOperand::CreateReg(0)); 4306 } 4307 4308 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4309 return MCDisassembler::Fail; 4310 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4311 return MCDisassembler::Fail; 4312 Inst.addOperand(MCOperand::CreateImm(index)); 4313 4314 return S; 4315 } 4316 4317 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 4318 uint64_t Address, const void *Decoder) { 4319 DecodeStatus S = MCDisassembler::Success; 4320 4321 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4322 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4323 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4324 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4325 unsigned size = fieldFromInstruction(Insn, 10, 2); 4326 4327 unsigned align = 0; 4328 unsigned index = 0; 4329 unsigned inc = 1; 4330 switch (size) { 4331 default: 4332 return MCDisassembler::Fail; 4333 case 0: 4334 index = fieldFromInstruction(Insn, 5, 3); 4335 if (fieldFromInstruction(Insn, 4, 1)) 4336 align = 2; 4337 break; 4338 case 1: 4339 index = fieldFromInstruction(Insn, 6, 2); 4340 if (fieldFromInstruction(Insn, 4, 1)) 4341 align = 4; 4342 if (fieldFromInstruction(Insn, 5, 1)) 4343 inc = 2; 4344 break; 4345 case 2: 4346 if (fieldFromInstruction(Insn, 5, 1)) 4347 return MCDisassembler::Fail; // UNDEFINED 4348 index = fieldFromInstruction(Insn, 7, 1); 4349 if (fieldFromInstruction(Insn, 4, 1) != 0) 4350 align = 8; 4351 if (fieldFromInstruction(Insn, 6, 1)) 4352 inc = 2; 4353 break; 4354 } 4355 4356 if (Rm != 0xF) { // Writeback 4357 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4358 return MCDisassembler::Fail; 4359 } 4360 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4361 return MCDisassembler::Fail; 4362 Inst.addOperand(MCOperand::CreateImm(align)); 4363 if (Rm != 0xF) { 4364 if (Rm != 0xD) { 4365 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4366 return MCDisassembler::Fail; 4367 } else 4368 Inst.addOperand(MCOperand::CreateReg(0)); 4369 } 4370 4371 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4372 return MCDisassembler::Fail; 4373 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4374 return MCDisassembler::Fail; 4375 Inst.addOperand(MCOperand::CreateImm(index)); 4376 4377 return S; 4378 } 4379 4380 4381 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 4382 uint64_t Address, const void *Decoder) { 4383 DecodeStatus S = MCDisassembler::Success; 4384 4385 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4386 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4387 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4388 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4389 unsigned size = fieldFromInstruction(Insn, 10, 2); 4390 4391 unsigned align = 0; 4392 unsigned index = 0; 4393 unsigned inc = 1; 4394 switch (size) { 4395 default: 4396 return MCDisassembler::Fail; 4397 case 0: 4398 if (fieldFromInstruction(Insn, 4, 1)) 4399 return MCDisassembler::Fail; // UNDEFINED 4400 index = fieldFromInstruction(Insn, 5, 3); 4401 break; 4402 case 1: 4403 if (fieldFromInstruction(Insn, 4, 1)) 4404 return MCDisassembler::Fail; // UNDEFINED 4405 index = fieldFromInstruction(Insn, 6, 2); 4406 if (fieldFromInstruction(Insn, 5, 1)) 4407 inc = 2; 4408 break; 4409 case 2: 4410 if (fieldFromInstruction(Insn, 4, 2)) 4411 return MCDisassembler::Fail; // UNDEFINED 4412 index = fieldFromInstruction(Insn, 7, 1); 4413 if (fieldFromInstruction(Insn, 6, 1)) 4414 inc = 2; 4415 break; 4416 } 4417 4418 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4419 return MCDisassembler::Fail; 4420 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4421 return MCDisassembler::Fail; 4422 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4423 return MCDisassembler::Fail; 4424 4425 if (Rm != 0xF) { // Writeback 4426 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4427 return MCDisassembler::Fail; 4428 } 4429 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4430 return MCDisassembler::Fail; 4431 Inst.addOperand(MCOperand::CreateImm(align)); 4432 if (Rm != 0xF) { 4433 if (Rm != 0xD) { 4434 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4435 return MCDisassembler::Fail; 4436 } else 4437 Inst.addOperand(MCOperand::CreateReg(0)); 4438 } 4439 4440 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4441 return MCDisassembler::Fail; 4442 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4443 return MCDisassembler::Fail; 4444 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4445 return MCDisassembler::Fail; 4446 Inst.addOperand(MCOperand::CreateImm(index)); 4447 4448 return S; 4449 } 4450 4451 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 4452 uint64_t Address, const void *Decoder) { 4453 DecodeStatus S = MCDisassembler::Success; 4454 4455 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4456 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4457 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4458 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4459 unsigned size = fieldFromInstruction(Insn, 10, 2); 4460 4461 unsigned align = 0; 4462 unsigned index = 0; 4463 unsigned inc = 1; 4464 switch (size) { 4465 default: 4466 return MCDisassembler::Fail; 4467 case 0: 4468 if (fieldFromInstruction(Insn, 4, 1)) 4469 return MCDisassembler::Fail; // UNDEFINED 4470 index = fieldFromInstruction(Insn, 5, 3); 4471 break; 4472 case 1: 4473 if (fieldFromInstruction(Insn, 4, 1)) 4474 return MCDisassembler::Fail; // UNDEFINED 4475 index = fieldFromInstruction(Insn, 6, 2); 4476 if (fieldFromInstruction(Insn, 5, 1)) 4477 inc = 2; 4478 break; 4479 case 2: 4480 if (fieldFromInstruction(Insn, 4, 2)) 4481 return MCDisassembler::Fail; // UNDEFINED 4482 index = fieldFromInstruction(Insn, 7, 1); 4483 if (fieldFromInstruction(Insn, 6, 1)) 4484 inc = 2; 4485 break; 4486 } 4487 4488 if (Rm != 0xF) { // Writeback 4489 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4490 return MCDisassembler::Fail; 4491 } 4492 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4493 return MCDisassembler::Fail; 4494 Inst.addOperand(MCOperand::CreateImm(align)); 4495 if (Rm != 0xF) { 4496 if (Rm != 0xD) { 4497 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4498 return MCDisassembler::Fail; 4499 } else 4500 Inst.addOperand(MCOperand::CreateReg(0)); 4501 } 4502 4503 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4504 return MCDisassembler::Fail; 4505 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4506 return MCDisassembler::Fail; 4507 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4508 return MCDisassembler::Fail; 4509 Inst.addOperand(MCOperand::CreateImm(index)); 4510 4511 return S; 4512 } 4513 4514 4515 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 4516 uint64_t Address, const void *Decoder) { 4517 DecodeStatus S = MCDisassembler::Success; 4518 4519 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4520 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4521 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4522 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4523 unsigned size = fieldFromInstruction(Insn, 10, 2); 4524 4525 unsigned align = 0; 4526 unsigned index = 0; 4527 unsigned inc = 1; 4528 switch (size) { 4529 default: 4530 return MCDisassembler::Fail; 4531 case 0: 4532 if (fieldFromInstruction(Insn, 4, 1)) 4533 align = 4; 4534 index = fieldFromInstruction(Insn, 5, 3); 4535 break; 4536 case 1: 4537 if (fieldFromInstruction(Insn, 4, 1)) 4538 align = 8; 4539 index = fieldFromInstruction(Insn, 6, 2); 4540 if (fieldFromInstruction(Insn, 5, 1)) 4541 inc = 2; 4542 break; 4543 case 2: 4544 switch (fieldFromInstruction(Insn, 4, 2)) { 4545 case 0: 4546 align = 0; break; 4547 case 3: 4548 return MCDisassembler::Fail; 4549 default: 4550 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4551 } 4552 4553 index = fieldFromInstruction(Insn, 7, 1); 4554 if (fieldFromInstruction(Insn, 6, 1)) 4555 inc = 2; 4556 break; 4557 } 4558 4559 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4560 return MCDisassembler::Fail; 4561 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4562 return MCDisassembler::Fail; 4563 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4564 return MCDisassembler::Fail; 4565 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4566 return MCDisassembler::Fail; 4567 4568 if (Rm != 0xF) { // Writeback 4569 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4570 return MCDisassembler::Fail; 4571 } 4572 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4573 return MCDisassembler::Fail; 4574 Inst.addOperand(MCOperand::CreateImm(align)); 4575 if (Rm != 0xF) { 4576 if (Rm != 0xD) { 4577 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4578 return MCDisassembler::Fail; 4579 } else 4580 Inst.addOperand(MCOperand::CreateReg(0)); 4581 } 4582 4583 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4584 return MCDisassembler::Fail; 4585 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4586 return MCDisassembler::Fail; 4587 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4588 return MCDisassembler::Fail; 4589 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4590 return MCDisassembler::Fail; 4591 Inst.addOperand(MCOperand::CreateImm(index)); 4592 4593 return S; 4594 } 4595 4596 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 4597 uint64_t Address, const void *Decoder) { 4598 DecodeStatus S = MCDisassembler::Success; 4599 4600 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4601 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4602 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4603 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4604 unsigned size = fieldFromInstruction(Insn, 10, 2); 4605 4606 unsigned align = 0; 4607 unsigned index = 0; 4608 unsigned inc = 1; 4609 switch (size) { 4610 default: 4611 return MCDisassembler::Fail; 4612 case 0: 4613 if (fieldFromInstruction(Insn, 4, 1)) 4614 align = 4; 4615 index = fieldFromInstruction(Insn, 5, 3); 4616 break; 4617 case 1: 4618 if (fieldFromInstruction(Insn, 4, 1)) 4619 align = 8; 4620 index = fieldFromInstruction(Insn, 6, 2); 4621 if (fieldFromInstruction(Insn, 5, 1)) 4622 inc = 2; 4623 break; 4624 case 2: 4625 switch (fieldFromInstruction(Insn, 4, 2)) { 4626 case 0: 4627 align = 0; break; 4628 case 3: 4629 return MCDisassembler::Fail; 4630 default: 4631 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4632 } 4633 4634 index = fieldFromInstruction(Insn, 7, 1); 4635 if (fieldFromInstruction(Insn, 6, 1)) 4636 inc = 2; 4637 break; 4638 } 4639 4640 if (Rm != 0xF) { // Writeback 4641 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4642 return MCDisassembler::Fail; 4643 } 4644 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4645 return MCDisassembler::Fail; 4646 Inst.addOperand(MCOperand::CreateImm(align)); 4647 if (Rm != 0xF) { 4648 if (Rm != 0xD) { 4649 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4650 return MCDisassembler::Fail; 4651 } else 4652 Inst.addOperand(MCOperand::CreateReg(0)); 4653 } 4654 4655 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4656 return MCDisassembler::Fail; 4657 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4658 return MCDisassembler::Fail; 4659 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4660 return MCDisassembler::Fail; 4661 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4662 return MCDisassembler::Fail; 4663 Inst.addOperand(MCOperand::CreateImm(index)); 4664 4665 return S; 4666 } 4667 4668 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 4669 uint64_t Address, const void *Decoder) { 4670 DecodeStatus S = MCDisassembler::Success; 4671 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4672 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4673 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4674 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4675 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4676 4677 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4678 S = MCDisassembler::SoftFail; 4679 4680 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4681 return MCDisassembler::Fail; 4682 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4683 return MCDisassembler::Fail; 4684 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4685 return MCDisassembler::Fail; 4686 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4687 return MCDisassembler::Fail; 4688 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4689 return MCDisassembler::Fail; 4690 4691 return S; 4692 } 4693 4694 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 4695 uint64_t Address, const void *Decoder) { 4696 DecodeStatus S = MCDisassembler::Success; 4697 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4698 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4699 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4700 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4701 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4702 4703 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4704 S = MCDisassembler::SoftFail; 4705 4706 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4707 return MCDisassembler::Fail; 4708 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4709 return MCDisassembler::Fail; 4710 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4711 return MCDisassembler::Fail; 4712 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4713 return MCDisassembler::Fail; 4714 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4715 return MCDisassembler::Fail; 4716 4717 return S; 4718 } 4719 4720 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 4721 uint64_t Address, const void *Decoder) { 4722 DecodeStatus S = MCDisassembler::Success; 4723 unsigned pred = fieldFromInstruction(Insn, 4, 4); 4724 unsigned mask = fieldFromInstruction(Insn, 0, 4); 4725 4726 if (pred == 0xF) { 4727 pred = 0xE; 4728 S = MCDisassembler::SoftFail; 4729 } 4730 4731 if (mask == 0x0) 4732 return MCDisassembler::Fail; 4733 4734 Inst.addOperand(MCOperand::CreateImm(pred)); 4735 Inst.addOperand(MCOperand::CreateImm(mask)); 4736 return S; 4737 } 4738 4739 static DecodeStatus 4740 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 4741 uint64_t Address, const void *Decoder) { 4742 DecodeStatus S = MCDisassembler::Success; 4743 4744 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4745 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4746 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4747 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4748 unsigned W = fieldFromInstruction(Insn, 21, 1); 4749 unsigned U = fieldFromInstruction(Insn, 23, 1); 4750 unsigned P = fieldFromInstruction(Insn, 24, 1); 4751 bool writeback = (W == 1) | (P == 0); 4752 4753 addr |= (U << 8) | (Rn << 9); 4754 4755 if (writeback && (Rn == Rt || Rn == Rt2)) 4756 Check(S, MCDisassembler::SoftFail); 4757 if (Rt == Rt2) 4758 Check(S, MCDisassembler::SoftFail); 4759 4760 // Rt 4761 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4762 return MCDisassembler::Fail; 4763 // Rt2 4764 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4765 return MCDisassembler::Fail; 4766 // Writeback operand 4767 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4768 return MCDisassembler::Fail; 4769 // addr 4770 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4771 return MCDisassembler::Fail; 4772 4773 return S; 4774 } 4775 4776 static DecodeStatus 4777 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 4778 uint64_t Address, const void *Decoder) { 4779 DecodeStatus S = MCDisassembler::Success; 4780 4781 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4782 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4783 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4784 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4785 unsigned W = fieldFromInstruction(Insn, 21, 1); 4786 unsigned U = fieldFromInstruction(Insn, 23, 1); 4787 unsigned P = fieldFromInstruction(Insn, 24, 1); 4788 bool writeback = (W == 1) | (P == 0); 4789 4790 addr |= (U << 8) | (Rn << 9); 4791 4792 if (writeback && (Rn == Rt || Rn == Rt2)) 4793 Check(S, MCDisassembler::SoftFail); 4794 4795 // Writeback operand 4796 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4797 return MCDisassembler::Fail; 4798 // Rt 4799 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4800 return MCDisassembler::Fail; 4801 // Rt2 4802 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4803 return MCDisassembler::Fail; 4804 // addr 4805 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4806 return MCDisassembler::Fail; 4807 4808 return S; 4809 } 4810 4811 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 4812 uint64_t Address, const void *Decoder) { 4813 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 4814 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 4815 if (sign1 != sign2) return MCDisassembler::Fail; 4816 4817 unsigned Val = fieldFromInstruction(Insn, 0, 8); 4818 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 4819 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 4820 Val |= sign1 << 12; 4821 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 4822 4823 return MCDisassembler::Success; 4824 } 4825 4826 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 4827 uint64_t Address, 4828 const void *Decoder) { 4829 DecodeStatus S = MCDisassembler::Success; 4830 4831 // Shift of "asr #32" is not allowed in Thumb2 mode. 4832 if (Val == 0x20) S = MCDisassembler::SoftFail; 4833 Inst.addOperand(MCOperand::CreateImm(Val)); 4834 return S; 4835 } 4836 4837 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 4838 uint64_t Address, const void *Decoder) { 4839 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4840 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 4841 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4842 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4843 4844 if (pred == 0xF) 4845 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 4846 4847 DecodeStatus S = MCDisassembler::Success; 4848 4849 if (Rt == Rn || Rn == Rt2) 4850 S = MCDisassembler::SoftFail; 4851 4852 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4853 return MCDisassembler::Fail; 4854 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4855 return MCDisassembler::Fail; 4856 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4857 return MCDisassembler::Fail; 4858 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4859 return MCDisassembler::Fail; 4860 4861 return S; 4862 } 4863 4864 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 4865 uint64_t Address, const void *Decoder) { 4866 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 4867 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 4868 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 4869 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 4870 unsigned imm = fieldFromInstruction(Insn, 16, 6); 4871 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 4872 unsigned op = fieldFromInstruction(Insn, 5, 1); 4873 4874 DecodeStatus S = MCDisassembler::Success; 4875 4876 // VMOVv2f32 is ambiguous with these decodings. 4877 if (!(imm & 0x38) && cmode == 0xF) { 4878 if (op == 1) return MCDisassembler::Fail; 4879 Inst.setOpcode(ARM::VMOVv2f32); 4880 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4881 } 4882 4883 if (!(imm & 0x20)) return MCDisassembler::Fail; 4884 4885 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 4886 return MCDisassembler::Fail; 4887 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 4888 return MCDisassembler::Fail; 4889 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4890 4891 return S; 4892 } 4893 4894 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 4895 uint64_t Address, const void *Decoder) { 4896 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 4897 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 4898 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 4899 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 4900 unsigned imm = fieldFromInstruction(Insn, 16, 6); 4901 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 4902 unsigned op = fieldFromInstruction(Insn, 5, 1); 4903 4904 DecodeStatus S = MCDisassembler::Success; 4905 4906 // VMOVv4f32 is ambiguous with these decodings. 4907 if (!(imm & 0x38) && cmode == 0xF) { 4908 if (op == 1) return MCDisassembler::Fail; 4909 Inst.setOpcode(ARM::VMOVv4f32); 4910 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4911 } 4912 4913 if (!(imm & 0x20)) return MCDisassembler::Fail; 4914 4915 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 4916 return MCDisassembler::Fail; 4917 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 4918 return MCDisassembler::Fail; 4919 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4920 4921 return S; 4922 } 4923 4924 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 4925 uint64_t Address, const void *Decoder) { 4926 DecodeStatus S = MCDisassembler::Success; 4927 4928 unsigned Rn = fieldFromInstruction(Val, 16, 4); 4929 unsigned Rt = fieldFromInstruction(Val, 12, 4); 4930 unsigned Rm = fieldFromInstruction(Val, 0, 4); 4931 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 4932 unsigned Cond = fieldFromInstruction(Val, 28, 4); 4933 4934 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 4935 S = MCDisassembler::SoftFail; 4936 4937 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4938 return MCDisassembler::Fail; 4939 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4940 return MCDisassembler::Fail; 4941 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 4942 return MCDisassembler::Fail; 4943 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 4944 return MCDisassembler::Fail; 4945 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 4946 return MCDisassembler::Fail; 4947 4948 return S; 4949 } 4950 4951 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 4952 uint64_t Address, const void *Decoder) { 4953 4954 DecodeStatus S = MCDisassembler::Success; 4955 4956 unsigned CRm = fieldFromInstruction(Val, 0, 4); 4957 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 4958 unsigned cop = fieldFromInstruction(Val, 8, 4); 4959 unsigned Rt = fieldFromInstruction(Val, 12, 4); 4960 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 4961 4962 if ((cop & ~0x1) == 0xa) 4963 return MCDisassembler::Fail; 4964 4965 if (Rt == Rt2) 4966 S = MCDisassembler::SoftFail; 4967 4968 Inst.addOperand(MCOperand::CreateImm(cop)); 4969 Inst.addOperand(MCOperand::CreateImm(opc1)); 4970 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4971 return MCDisassembler::Fail; 4972 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4973 return MCDisassembler::Fail; 4974 Inst.addOperand(MCOperand::CreateImm(CRm)); 4975 4976 return S; 4977 } 4978 4979