1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "MCTargetDesc/ARMAddressingModes.h" 11 #include "MCTargetDesc/ARMBaseInfo.h" 12 #include "MCTargetDesc/ARMMCTargetDesc.h" 13 #include "Utils/ARMBaseInfo.h" 14 #include "llvm/MC/MCContext.h" 15 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 16 #include "llvm/MC/MCFixedLenDisassembler.h" 17 #include "llvm/MC/MCInst.h" 18 #include "llvm/MC/MCInstrDesc.h" 19 #include "llvm/MC/MCSubtargetInfo.h" 20 #include "llvm/MC/SubtargetFeature.h" 21 #include "llvm/Support/Compiler.h" 22 #include "llvm/Support/ErrorHandling.h" 23 #include "llvm/Support/MathExtras.h" 24 #include "llvm/Support/TargetRegistry.h" 25 #include "llvm/Support/raw_ostream.h" 26 #include <algorithm> 27 #include <cassert> 28 #include <cstdint> 29 #include <vector> 30 31 using namespace llvm; 32 33 #define DEBUG_TYPE "arm-disassembler" 34 35 using DecodeStatus = MCDisassembler::DecodeStatus; 36 37 namespace { 38 39 // Handles the condition code status of instructions in IT blocks 40 class ITStatus 41 { 42 public: 43 // Returns the condition code for instruction in IT block 44 unsigned getITCC() { 45 unsigned CC = ARMCC::AL; 46 if (instrInITBlock()) 47 CC = ITStates.back(); 48 return CC; 49 } 50 51 // Advances the IT block state to the next T or E 52 void advanceITState() { 53 ITStates.pop_back(); 54 } 55 56 // Returns true if the current instruction is in an IT block 57 bool instrInITBlock() { 58 return !ITStates.empty(); 59 } 60 61 // Returns true if current instruction is the last instruction in an IT block 62 bool instrLastInITBlock() { 63 return ITStates.size() == 1; 64 } 65 66 // Called when decoding an IT instruction. Sets the IT state for the following 67 // instructions that for the IT block. Firstcond and Mask correspond to the 68 // fields in the IT instruction encoding. 69 void setITState(char Firstcond, char Mask) { 70 // (3 - the number of trailing zeros) is the number of then / else. 71 unsigned CondBit0 = Firstcond & 1; 72 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 73 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 74 assert(NumTZ <= 3 && "Invalid IT mask!"); 75 // push condition codes onto the stack the correct order for the pops 76 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 77 bool T = ((Mask >> Pos) & 1) == CondBit0; 78 if (T) 79 ITStates.push_back(CCBits); 80 else 81 ITStates.push_back(CCBits ^ 1); 82 } 83 ITStates.push_back(CCBits); 84 } 85 86 private: 87 std::vector<unsigned char> ITStates; 88 }; 89 90 /// ARM disassembler for all ARM platforms. 91 class ARMDisassembler : public MCDisassembler { 92 public: 93 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 94 MCDisassembler(STI, Ctx) { 95 } 96 97 ~ARMDisassembler() override = default; 98 99 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 100 ArrayRef<uint8_t> Bytes, uint64_t Address, 101 raw_ostream &VStream, 102 raw_ostream &CStream) const override; 103 }; 104 105 /// Thumb disassembler for all Thumb platforms. 106 class ThumbDisassembler : public MCDisassembler { 107 public: 108 ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 109 MCDisassembler(STI, Ctx) { 110 } 111 112 ~ThumbDisassembler() override = default; 113 114 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 115 ArrayRef<uint8_t> Bytes, uint64_t Address, 116 raw_ostream &VStream, 117 raw_ostream &CStream) const override; 118 119 private: 120 mutable ITStatus ITBlock; 121 122 DecodeStatus AddThumbPredicate(MCInst&) const; 123 void UpdateThumbVFPPredicate(MCInst&) const; 124 }; 125 126 } // end anonymous namespace 127 128 static bool Check(DecodeStatus &Out, DecodeStatus In) { 129 switch (In) { 130 case MCDisassembler::Success: 131 // Out stays the same. 132 return true; 133 case MCDisassembler::SoftFail: 134 Out = In; 135 return true; 136 case MCDisassembler::Fail: 137 Out = In; 138 return false; 139 } 140 llvm_unreachable("Invalid DecodeStatus!"); 141 } 142 143 // Forward declare these because the autogenerated code will reference them. 144 // Definitions are further down. 145 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 146 uint64_t Address, const void *Decoder); 147 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 148 unsigned RegNo, uint64_t Address, 149 const void *Decoder); 150 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 151 unsigned RegNo, uint64_t Address, 152 const void *Decoder); 153 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 154 uint64_t Address, const void *Decoder); 155 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 156 uint64_t Address, const void *Decoder); 157 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 158 uint64_t Address, const void *Decoder); 159 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 160 uint64_t Address, const void *Decoder); 161 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 162 uint64_t Address, const void *Decoder); 163 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 164 uint64_t Address, const void *Decoder); 165 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 166 uint64_t Address, const void *Decoder); 167 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 168 unsigned RegNo, 169 uint64_t Address, 170 const void *Decoder); 171 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 172 uint64_t Address, const void *Decoder); 173 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 174 uint64_t Address, const void *Decoder); 175 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 176 unsigned RegNo, uint64_t Address, 177 const void *Decoder); 178 179 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 180 uint64_t Address, const void *Decoder); 181 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 182 uint64_t Address, const void *Decoder); 183 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 184 uint64_t Address, const void *Decoder); 185 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 186 uint64_t Address, const void *Decoder); 187 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 188 uint64_t Address, const void *Decoder); 189 190 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 191 uint64_t Address, const void *Decoder); 192 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 193 uint64_t Address, const void *Decoder); 194 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 195 unsigned Insn, 196 uint64_t Address, 197 const void *Decoder); 198 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 199 uint64_t Address, const void *Decoder); 200 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 201 uint64_t Address, const void *Decoder); 202 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 203 uint64_t Address, const void *Decoder); 204 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 205 uint64_t Address, const void *Decoder); 206 207 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 208 unsigned Insn, 209 uint64_t Adddress, 210 const void *Decoder); 211 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 214 uint64_t Address, const void *Decoder); 215 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 216 uint64_t Address, const void *Decoder); 217 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 218 uint64_t Address, const void *Decoder); 219 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 220 uint64_t Address, const void *Decoder); 221 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 222 uint64_t Address, const void *Decoder); 223 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 224 uint64_t Address, const void *Decoder); 225 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 226 uint64_t Address, const void *Decoder); 227 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 228 uint64_t Address, const void *Decoder); 229 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 230 uint64_t Address, const void *Decoder); 231 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 232 uint64_t Address, const void *Decoder); 233 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 234 uint64_t Address, const void *Decoder); 235 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 236 uint64_t Address, const void *Decoder); 237 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 238 uint64_t Address, const void *Decoder); 239 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 240 uint64_t Address, const void *Decoder); 241 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 242 uint64_t Address, const void *Decoder); 243 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 244 uint64_t Address, const void *Decoder); 245 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 246 uint64_t Address, const void *Decoder); 247 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 248 uint64_t Address, const void *Decoder); 249 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 250 uint64_t Address, const void *Decoder); 251 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 252 uint64_t Address, const void *Decoder); 253 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 254 uint64_t Address, const void *Decoder); 255 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 256 uint64_t Address, const void *Decoder); 257 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 258 uint64_t Address, const void *Decoder); 259 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 260 uint64_t Address, const void *Decoder); 261 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 262 uint64_t Address, const void *Decoder); 263 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 264 uint64_t Address, const void *Decoder); 265 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 266 uint64_t Address, const void *Decoder); 267 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 268 uint64_t Address, const void *Decoder); 269 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 270 uint64_t Address, const void *Decoder); 271 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 272 uint64_t Address, const void *Decoder); 273 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 274 uint64_t Address, const void *Decoder); 275 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 276 uint64_t Address, const void *Decoder); 277 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 278 uint64_t Address, const void *Decoder); 279 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 280 uint64_t Address, const void *Decoder); 281 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 282 uint64_t Address, const void *Decoder); 283 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 284 uint64_t Address, const void *Decoder); 285 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 286 uint64_t Address, const void *Decoder); 287 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 288 uint64_t Address, const void *Decoder); 289 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 290 uint64_t Address, const void *Decoder); 291 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 292 uint64_t Address, const void *Decoder); 293 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 294 uint64_t Address, const void *Decoder); 295 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 296 uint64_t Address, const void *Decoder); 297 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 298 uint64_t Address, const void *Decoder); 299 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 300 uint64_t Address, const void *Decoder); 301 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 302 uint64_t Address, const void *Decoder); 303 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 304 uint64_t Address, const void *Decoder); 305 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 306 uint64_t Address, const void *Decoder); 307 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 308 uint64_t Address, const void *Decoder); 309 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 310 uint64_t Address, const void *Decoder); 311 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 312 uint64_t Address, const void *Decoder); 313 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 314 uint64_t Address, const void *Decoder); 315 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 316 uint64_t Address, const void *Decoder); 317 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 318 uint64_t Address, const void *Decoder); 319 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 320 uint64_t Address, const void *Decoder); 321 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 322 uint64_t Address, const void *Decoder); 323 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 324 uint64_t Address, const void *Decoder); 325 326 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 327 uint64_t Address, const void *Decoder); 328 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 329 uint64_t Address, const void *Decoder); 330 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 331 uint64_t Address, const void *Decoder); 332 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 333 uint64_t Address, const void *Decoder); 334 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 335 uint64_t Address, const void *Decoder); 336 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 337 uint64_t Address, const void *Decoder); 338 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 339 uint64_t Address, const void *Decoder); 340 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 341 uint64_t Address, const void *Decoder); 342 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 343 uint64_t Address, const void *Decoder); 344 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 345 uint64_t Address, const void *Decoder); 346 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 347 uint64_t Address, const void* Decoder); 348 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 349 uint64_t Address, const void* Decoder); 350 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 351 uint64_t Address, const void* Decoder); 352 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 353 uint64_t Address, const void* Decoder); 354 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 355 uint64_t Address, const void *Decoder); 356 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 357 uint64_t Address, const void *Decoder); 358 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 359 uint64_t Address, const void *Decoder); 360 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 361 uint64_t Address, const void *Decoder); 362 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 363 uint64_t Address, const void *Decoder); 364 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 365 uint64_t Address, const void *Decoder); 366 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 367 uint64_t Address, const void *Decoder); 368 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 369 uint64_t Address, const void *Decoder); 370 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 371 uint64_t Address, const void *Decoder); 372 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 373 uint64_t Address, const void *Decoder); 374 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 375 uint64_t Address, const void *Decoder); 376 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 377 uint64_t Address, const void *Decoder); 378 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 379 uint64_t Address, const void *Decoder); 380 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 381 uint64_t Address, const void *Decoder); 382 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 383 uint64_t Address, const void *Decoder); 384 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 385 uint64_t Address, const void *Decoder); 386 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 387 uint64_t Address, const void *Decoder); 388 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 389 uint64_t Address, const void *Decoder); 390 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 391 uint64_t Address, const void *Decoder); 392 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 393 uint64_t Address, const void *Decoder); 394 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 395 uint64_t Address, const void *Decoder); 396 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 397 uint64_t Address, const void *Decoder); 398 399 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 400 uint64_t Address, const void *Decoder); 401 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 402 uint64_t Address, const void *Decoder); 403 404 #include "ARMGenDisassemblerTables.inc" 405 406 static MCDisassembler *createARMDisassembler(const Target &T, 407 const MCSubtargetInfo &STI, 408 MCContext &Ctx) { 409 return new ARMDisassembler(STI, Ctx); 410 } 411 412 static MCDisassembler *createThumbDisassembler(const Target &T, 413 const MCSubtargetInfo &STI, 414 MCContext &Ctx) { 415 return new ThumbDisassembler(STI, Ctx); 416 } 417 418 // Post-decoding checks 419 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 420 uint64_t Address, raw_ostream &OS, 421 raw_ostream &CS, 422 uint32_t Insn, 423 DecodeStatus Result) { 424 switch (MI.getOpcode()) { 425 case ARM::HVC: { 426 // HVC is undefined if condition = 0xf otherwise upredictable 427 // if condition != 0xe 428 uint32_t Cond = (Insn >> 28) & 0xF; 429 if (Cond == 0xF) 430 return MCDisassembler::Fail; 431 if (Cond != 0xE) 432 return MCDisassembler::SoftFail; 433 return Result; 434 } 435 default: return Result; 436 } 437 } 438 439 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 440 ArrayRef<uint8_t> Bytes, 441 uint64_t Address, raw_ostream &OS, 442 raw_ostream &CS) const { 443 CommentStream = &CS; 444 445 assert(!STI.getFeatureBits()[ARM::ModeThumb] && 446 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 447 "mode!"); 448 449 // We want to read exactly 4 bytes of data. 450 if (Bytes.size() < 4) { 451 Size = 0; 452 return MCDisassembler::Fail; 453 } 454 455 // Encoded as a small-endian 32-bit word in the stream. 456 uint32_t Insn = 457 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 458 459 // Calling the auto-generated decoder function. 460 DecodeStatus Result = 461 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 462 if (Result != MCDisassembler::Fail) { 463 Size = 4; 464 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 465 } 466 467 struct DecodeTable { 468 const uint8_t *P; 469 bool DecodePred; 470 }; 471 472 const DecodeTable Tables[] = { 473 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false}, 474 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true}, 475 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false}, 476 {DecoderTablev8Crypto32, false}, 477 }; 478 479 for (auto Table : Tables) { 480 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI); 481 if (Result != MCDisassembler::Fail) { 482 Size = 4; 483 // Add a fake predicate operand, because we share these instruction 484 // definitions with Thumb2 where these instructions are predicable. 485 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this)) 486 return MCDisassembler::Fail; 487 return Result; 488 } 489 } 490 491 Result = 492 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI); 493 if (Result != MCDisassembler::Fail) { 494 Size = 4; 495 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 496 } 497 498 Size = 4; 499 return MCDisassembler::Fail; 500 } 501 502 namespace llvm { 503 504 extern const MCInstrDesc ARMInsts[]; 505 506 } // end namespace llvm 507 508 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 509 /// immediate Value in the MCInst. The immediate Value has had any PC 510 /// adjustment made by the caller. If the instruction is a branch instruction 511 /// then isBranch is true, else false. If the getOpInfo() function was set as 512 /// part of the setupForSymbolicDisassembly() call then that function is called 513 /// to get any symbolic information at the Address for this instruction. If 514 /// that returns non-zero then the symbolic information it returns is used to 515 /// create an MCExpr and that is added as an operand to the MCInst. If 516 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 517 /// Value is done and if a symbol is found an MCExpr is created with that, else 518 /// an MCExpr with Value is created. This function returns true if it adds an 519 /// operand to the MCInst and false otherwise. 520 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 521 bool isBranch, uint64_t InstSize, 522 MCInst &MI, const void *Decoder) { 523 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 524 // FIXME: Does it make sense for value to be negative? 525 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 526 /* Offset */ 0, InstSize); 527 } 528 529 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 530 /// referenced by a load instruction with the base register that is the Pc. 531 /// These can often be values in a literal pool near the Address of the 532 /// instruction. The Address of the instruction and its immediate Value are 533 /// used as a possible literal pool entry. The SymbolLookUp call back will 534 /// return the name of a symbol referenced by the literal pool's entry if 535 /// the referenced address is that of a symbol. Or it will return a pointer to 536 /// a literal 'C' string if the referenced address of the literal pool's entry 537 /// is an address into a section with 'C' string literals. 538 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 539 const void *Decoder) { 540 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 541 Dis->tryAddingPcLoadReferenceComment(Value, Address); 542 } 543 544 // Thumb1 instructions don't have explicit S bits. Rather, they 545 // implicitly set CPSR. Since it's not represented in the encoding, the 546 // auto-generated decoder won't inject the CPSR operand. We need to fix 547 // that as a post-pass. 548 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 549 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 550 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 551 MCInst::iterator I = MI.begin(); 552 for (unsigned i = 0; i < NumOps; ++i, ++I) { 553 if (I == MI.end()) break; 554 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 555 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 556 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 557 return; 558 } 559 } 560 561 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 562 } 563 564 // Most Thumb instructions don't have explicit predicates in the 565 // encoding, but rather get their predicates from IT context. We need 566 // to fix up the predicate operands using this context information as a 567 // post-pass. 568 MCDisassembler::DecodeStatus 569 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 570 MCDisassembler::DecodeStatus S = Success; 571 572 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); 573 574 // A few instructions actually have predicates encoded in them. Don't 575 // try to overwrite it if we're seeing one of those. 576 switch (MI.getOpcode()) { 577 case ARM::tBcc: 578 case ARM::t2Bcc: 579 case ARM::tCBZ: 580 case ARM::tCBNZ: 581 case ARM::tCPS: 582 case ARM::t2CPS3p: 583 case ARM::t2CPS2p: 584 case ARM::t2CPS1p: 585 case ARM::tMOVSr: 586 case ARM::tSETEND: 587 // Some instructions (mostly conditional branches) are not 588 // allowed in IT blocks. 589 if (ITBlock.instrInITBlock()) 590 S = SoftFail; 591 else 592 return Success; 593 break; 594 case ARM::t2HINT: 595 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) 596 S = SoftFail; 597 break; 598 case ARM::tB: 599 case ARM::t2B: 600 case ARM::t2TBB: 601 case ARM::t2TBH: 602 // Some instructions (mostly unconditional branches) can 603 // only appears at the end of, or outside of, an IT. 604 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 605 S = SoftFail; 606 break; 607 default: 608 break; 609 } 610 611 // If we're in an IT block, base the predicate on that. Otherwise, 612 // assume a predicate of AL. 613 unsigned CC; 614 CC = ITBlock.getITCC(); 615 if (CC == 0xF) 616 CC = ARMCC::AL; 617 if (ITBlock.instrInITBlock()) 618 ITBlock.advanceITState(); 619 620 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 621 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 622 MCInst::iterator I = MI.begin(); 623 for (unsigned i = 0; i < NumOps; ++i, ++I) { 624 if (I == MI.end()) break; 625 if (OpInfo[i].isPredicate()) { 626 I = MI.insert(I, MCOperand::createImm(CC)); 627 ++I; 628 if (CC == ARMCC::AL) 629 MI.insert(I, MCOperand::createReg(0)); 630 else 631 MI.insert(I, MCOperand::createReg(ARM::CPSR)); 632 return S; 633 } 634 } 635 636 I = MI.insert(I, MCOperand::createImm(CC)); 637 ++I; 638 if (CC == ARMCC::AL) 639 MI.insert(I, MCOperand::createReg(0)); 640 else 641 MI.insert(I, MCOperand::createReg(ARM::CPSR)); 642 643 return S; 644 } 645 646 // Thumb VFP instructions are a special case. Because we share their 647 // encodings between ARM and Thumb modes, and they are predicable in ARM 648 // mode, the auto-generated decoder will give them an (incorrect) 649 // predicate operand. We need to rewrite these operands based on the IT 650 // context as a post-pass. 651 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 652 unsigned CC; 653 CC = ITBlock.getITCC(); 654 if (ITBlock.instrInITBlock()) 655 ITBlock.advanceITState(); 656 657 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 658 MCInst::iterator I = MI.begin(); 659 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 660 for (unsigned i = 0; i < NumOps; ++i, ++I) { 661 if (OpInfo[i].isPredicate() ) { 662 I->setImm(CC); 663 ++I; 664 if (CC == ARMCC::AL) 665 I->setReg(0); 666 else 667 I->setReg(ARM::CPSR); 668 return; 669 } 670 } 671 } 672 673 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 674 ArrayRef<uint8_t> Bytes, 675 uint64_t Address, 676 raw_ostream &OS, 677 raw_ostream &CS) const { 678 CommentStream = &CS; 679 680 assert(STI.getFeatureBits()[ARM::ModeThumb] && 681 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 682 683 // We want to read exactly 2 bytes of data. 684 if (Bytes.size() < 2) { 685 Size = 0; 686 return MCDisassembler::Fail; 687 } 688 689 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0]; 690 DecodeStatus Result = 691 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 692 if (Result != MCDisassembler::Fail) { 693 Size = 2; 694 Check(Result, AddThumbPredicate(MI)); 695 return Result; 696 } 697 698 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 699 STI); 700 if (Result) { 701 Size = 2; 702 bool InITBlock = ITBlock.instrInITBlock(); 703 Check(Result, AddThumbPredicate(MI)); 704 AddThumb1SBit(MI, InITBlock); 705 return Result; 706 } 707 708 Result = 709 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 710 if (Result != MCDisassembler::Fail) { 711 Size = 2; 712 713 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 714 // the Thumb predicate. 715 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 716 Result = MCDisassembler::SoftFail; 717 718 Check(Result, AddThumbPredicate(MI)); 719 720 // If we find an IT instruction, we need to parse its condition 721 // code and mask operands so that we can apply them correctly 722 // to the subsequent instructions. 723 if (MI.getOpcode() == ARM::t2IT) { 724 725 unsigned Firstcond = MI.getOperand(0).getImm(); 726 unsigned Mask = MI.getOperand(1).getImm(); 727 ITBlock.setITState(Firstcond, Mask); 728 } 729 730 return Result; 731 } 732 733 // We want to read exactly 4 bytes of data. 734 if (Bytes.size() < 4) { 735 Size = 0; 736 return MCDisassembler::Fail; 737 } 738 739 uint32_t Insn32 = 740 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16); 741 Result = 742 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 743 if (Result != MCDisassembler::Fail) { 744 Size = 4; 745 bool InITBlock = ITBlock.instrInITBlock(); 746 Check(Result, AddThumbPredicate(MI)); 747 AddThumb1SBit(MI, InITBlock); 748 return Result; 749 } 750 751 Result = 752 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 753 if (Result != MCDisassembler::Fail) { 754 Size = 4; 755 Check(Result, AddThumbPredicate(MI)); 756 return Result; 757 } 758 759 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 760 Result = 761 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 762 if (Result != MCDisassembler::Fail) { 763 Size = 4; 764 UpdateThumbVFPPredicate(MI); 765 return Result; 766 } 767 } 768 769 Result = 770 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 771 if (Result != MCDisassembler::Fail) { 772 Size = 4; 773 return Result; 774 } 775 776 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 777 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 778 STI); 779 if (Result != MCDisassembler::Fail) { 780 Size = 4; 781 Check(Result, AddThumbPredicate(MI)); 782 return Result; 783 } 784 } 785 786 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 787 uint32_t NEONLdStInsn = Insn32; 788 NEONLdStInsn &= 0xF0FFFFFF; 789 NEONLdStInsn |= 0x04000000; 790 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 791 Address, this, STI); 792 if (Result != MCDisassembler::Fail) { 793 Size = 4; 794 Check(Result, AddThumbPredicate(MI)); 795 return Result; 796 } 797 } 798 799 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 800 uint32_t NEONDataInsn = Insn32; 801 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 802 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 803 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 804 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 805 Address, this, STI); 806 if (Result != MCDisassembler::Fail) { 807 Size = 4; 808 Check(Result, AddThumbPredicate(MI)); 809 return Result; 810 } 811 812 uint32_t NEONCryptoInsn = Insn32; 813 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 814 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 815 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 816 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 817 Address, this, STI); 818 if (Result != MCDisassembler::Fail) { 819 Size = 4; 820 return Result; 821 } 822 823 uint32_t NEONv8Insn = Insn32; 824 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 825 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 826 this, STI); 827 if (Result != MCDisassembler::Fail) { 828 Size = 4; 829 return Result; 830 } 831 } 832 833 Result = 834 decodeInstruction(DecoderTableThumb2CoProc32, MI, Insn32, Address, this, STI); 835 if (Result != MCDisassembler::Fail) { 836 Size = 4; 837 Check(Result, AddThumbPredicate(MI)); 838 return Result; 839 } 840 841 Size = 0; 842 return MCDisassembler::Fail; 843 } 844 845 extern "C" void LLVMInitializeARMDisassembler() { 846 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(), 847 createARMDisassembler); 848 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(), 849 createARMDisassembler); 850 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(), 851 createThumbDisassembler); 852 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(), 853 createThumbDisassembler); 854 } 855 856 static const uint16_t GPRDecoderTable[] = { 857 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 858 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 859 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 860 ARM::R12, ARM::SP, ARM::LR, ARM::PC 861 }; 862 863 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 864 uint64_t Address, const void *Decoder) { 865 if (RegNo > 15) 866 return MCDisassembler::Fail; 867 868 unsigned Register = GPRDecoderTable[RegNo]; 869 Inst.addOperand(MCOperand::createReg(Register)); 870 return MCDisassembler::Success; 871 } 872 873 static DecodeStatus 874 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 875 uint64_t Address, const void *Decoder) { 876 DecodeStatus S = MCDisassembler::Success; 877 878 if (RegNo == 15) 879 S = MCDisassembler::SoftFail; 880 881 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 882 883 return S; 884 } 885 886 static DecodeStatus 887 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 888 uint64_t Address, const void *Decoder) { 889 DecodeStatus S = MCDisassembler::Success; 890 891 if (RegNo == 15) 892 { 893 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 894 return MCDisassembler::Success; 895 } 896 897 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 898 return S; 899 } 900 901 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 902 uint64_t Address, const void *Decoder) { 903 if (RegNo > 7) 904 return MCDisassembler::Fail; 905 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 906 } 907 908 static const uint16_t GPRPairDecoderTable[] = { 909 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 910 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 911 }; 912 913 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 914 uint64_t Address, const void *Decoder) { 915 DecodeStatus S = MCDisassembler::Success; 916 917 if (RegNo > 13) 918 return MCDisassembler::Fail; 919 920 if ((RegNo & 1) || RegNo == 0xe) 921 S = MCDisassembler::SoftFail; 922 923 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 924 Inst.addOperand(MCOperand::createReg(RegisterPair)); 925 return S; 926 } 927 928 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 929 uint64_t Address, const void *Decoder) { 930 unsigned Register = 0; 931 switch (RegNo) { 932 case 0: 933 Register = ARM::R0; 934 break; 935 case 1: 936 Register = ARM::R1; 937 break; 938 case 2: 939 Register = ARM::R2; 940 break; 941 case 3: 942 Register = ARM::R3; 943 break; 944 case 9: 945 Register = ARM::R9; 946 break; 947 case 12: 948 Register = ARM::R12; 949 break; 950 default: 951 return MCDisassembler::Fail; 952 } 953 954 Inst.addOperand(MCOperand::createReg(Register)); 955 return MCDisassembler::Success; 956 } 957 958 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 959 uint64_t Address, const void *Decoder) { 960 DecodeStatus S = MCDisassembler::Success; 961 962 const FeatureBitset &featureBits = 963 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 964 965 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) 966 S = MCDisassembler::SoftFail; 967 968 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 969 return S; 970 } 971 972 static const uint16_t SPRDecoderTable[] = { 973 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 974 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 975 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 976 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 977 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 978 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 979 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 980 ARM::S28, ARM::S29, ARM::S30, ARM::S31 981 }; 982 983 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 984 uint64_t Address, const void *Decoder) { 985 if (RegNo > 31) 986 return MCDisassembler::Fail; 987 988 unsigned Register = SPRDecoderTable[RegNo]; 989 Inst.addOperand(MCOperand::createReg(Register)); 990 return MCDisassembler::Success; 991 } 992 993 static const uint16_t DPRDecoderTable[] = { 994 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 995 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 996 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 997 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 998 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 999 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1000 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1001 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1002 }; 1003 1004 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1005 uint64_t Address, const void *Decoder) { 1006 const FeatureBitset &featureBits = 1007 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1008 1009 bool hasD16 = featureBits[ARM::FeatureD16]; 1010 1011 if (RegNo > 31 || (hasD16 && RegNo > 15)) 1012 return MCDisassembler::Fail; 1013 1014 unsigned Register = DPRDecoderTable[RegNo]; 1015 Inst.addOperand(MCOperand::createReg(Register)); 1016 return MCDisassembler::Success; 1017 } 1018 1019 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1020 uint64_t Address, const void *Decoder) { 1021 if (RegNo > 7) 1022 return MCDisassembler::Fail; 1023 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1024 } 1025 1026 static DecodeStatus 1027 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1028 uint64_t Address, const void *Decoder) { 1029 if (RegNo > 15) 1030 return MCDisassembler::Fail; 1031 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1032 } 1033 1034 static const uint16_t QPRDecoderTable[] = { 1035 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1036 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1037 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1038 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1039 }; 1040 1041 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1042 uint64_t Address, const void *Decoder) { 1043 if (RegNo > 31 || (RegNo & 1) != 0) 1044 return MCDisassembler::Fail; 1045 RegNo >>= 1; 1046 1047 unsigned Register = QPRDecoderTable[RegNo]; 1048 Inst.addOperand(MCOperand::createReg(Register)); 1049 return MCDisassembler::Success; 1050 } 1051 1052 static const uint16_t DPairDecoderTable[] = { 1053 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1054 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1055 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1056 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1057 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1058 ARM::Q15 1059 }; 1060 1061 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1062 uint64_t Address, const void *Decoder) { 1063 if (RegNo > 30) 1064 return MCDisassembler::Fail; 1065 1066 unsigned Register = DPairDecoderTable[RegNo]; 1067 Inst.addOperand(MCOperand::createReg(Register)); 1068 return MCDisassembler::Success; 1069 } 1070 1071 static const uint16_t DPairSpacedDecoderTable[] = { 1072 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1073 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1074 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1075 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1076 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1077 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1078 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1079 ARM::D28_D30, ARM::D29_D31 1080 }; 1081 1082 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1083 unsigned RegNo, 1084 uint64_t Address, 1085 const void *Decoder) { 1086 if (RegNo > 29) 1087 return MCDisassembler::Fail; 1088 1089 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1090 Inst.addOperand(MCOperand::createReg(Register)); 1091 return MCDisassembler::Success; 1092 } 1093 1094 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1095 uint64_t Address, const void *Decoder) { 1096 if (Val == 0xF) return MCDisassembler::Fail; 1097 // AL predicate is not allowed on Thumb1 branches. 1098 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1099 return MCDisassembler::Fail; 1100 Inst.addOperand(MCOperand::createImm(Val)); 1101 if (Val == ARMCC::AL) { 1102 Inst.addOperand(MCOperand::createReg(0)); 1103 } else 1104 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1105 return MCDisassembler::Success; 1106 } 1107 1108 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1109 uint64_t Address, const void *Decoder) { 1110 if (Val) 1111 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1112 else 1113 Inst.addOperand(MCOperand::createReg(0)); 1114 return MCDisassembler::Success; 1115 } 1116 1117 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1118 uint64_t Address, const void *Decoder) { 1119 DecodeStatus S = MCDisassembler::Success; 1120 1121 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1122 unsigned type = fieldFromInstruction(Val, 5, 2); 1123 unsigned imm = fieldFromInstruction(Val, 7, 5); 1124 1125 // Register-immediate 1126 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 1127 return MCDisassembler::Fail; 1128 1129 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1130 switch (type) { 1131 case 0: 1132 Shift = ARM_AM::lsl; 1133 break; 1134 case 1: 1135 Shift = ARM_AM::lsr; 1136 break; 1137 case 2: 1138 Shift = ARM_AM::asr; 1139 break; 1140 case 3: 1141 Shift = ARM_AM::ror; 1142 break; 1143 } 1144 1145 if (Shift == ARM_AM::ror && imm == 0) 1146 Shift = ARM_AM::rrx; 1147 1148 unsigned Op = Shift | (imm << 3); 1149 Inst.addOperand(MCOperand::createImm(Op)); 1150 1151 return S; 1152 } 1153 1154 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1155 uint64_t Address, const void *Decoder) { 1156 DecodeStatus S = MCDisassembler::Success; 1157 1158 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1159 unsigned type = fieldFromInstruction(Val, 5, 2); 1160 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1161 1162 // Register-register 1163 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1164 return MCDisassembler::Fail; 1165 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1166 return MCDisassembler::Fail; 1167 1168 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1169 switch (type) { 1170 case 0: 1171 Shift = ARM_AM::lsl; 1172 break; 1173 case 1: 1174 Shift = ARM_AM::lsr; 1175 break; 1176 case 2: 1177 Shift = ARM_AM::asr; 1178 break; 1179 case 3: 1180 Shift = ARM_AM::ror; 1181 break; 1182 } 1183 1184 Inst.addOperand(MCOperand::createImm(Shift)); 1185 1186 return S; 1187 } 1188 1189 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1190 uint64_t Address, const void *Decoder) { 1191 DecodeStatus S = MCDisassembler::Success; 1192 1193 bool NeedDisjointWriteback = false; 1194 unsigned WritebackReg = 0; 1195 switch (Inst.getOpcode()) { 1196 default: 1197 break; 1198 case ARM::LDMIA_UPD: 1199 case ARM::LDMDB_UPD: 1200 case ARM::LDMIB_UPD: 1201 case ARM::LDMDA_UPD: 1202 case ARM::t2LDMIA_UPD: 1203 case ARM::t2LDMDB_UPD: 1204 case ARM::t2STMIA_UPD: 1205 case ARM::t2STMDB_UPD: 1206 NeedDisjointWriteback = true; 1207 WritebackReg = Inst.getOperand(0).getReg(); 1208 break; 1209 } 1210 1211 // Empty register lists are not allowed. 1212 if (Val == 0) return MCDisassembler::Fail; 1213 for (unsigned i = 0; i < 16; ++i) { 1214 if (Val & (1 << i)) { 1215 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1216 return MCDisassembler::Fail; 1217 // Writeback not allowed if Rn is in the target list. 1218 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1219 Check(S, MCDisassembler::SoftFail); 1220 } 1221 } 1222 1223 return S; 1224 } 1225 1226 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1227 uint64_t Address, const void *Decoder) { 1228 DecodeStatus S = MCDisassembler::Success; 1229 1230 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1231 unsigned regs = fieldFromInstruction(Val, 0, 8); 1232 1233 // In case of unpredictable encoding, tweak the operands. 1234 if (regs == 0 || (Vd + regs) > 32) { 1235 regs = Vd + regs > 32 ? 32 - Vd : regs; 1236 regs = std::max( 1u, regs); 1237 S = MCDisassembler::SoftFail; 1238 } 1239 1240 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1241 return MCDisassembler::Fail; 1242 for (unsigned i = 0; i < (regs - 1); ++i) { 1243 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1244 return MCDisassembler::Fail; 1245 } 1246 1247 return S; 1248 } 1249 1250 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1251 uint64_t Address, const void *Decoder) { 1252 DecodeStatus S = MCDisassembler::Success; 1253 1254 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1255 unsigned regs = fieldFromInstruction(Val, 1, 7); 1256 1257 // In case of unpredictable encoding, tweak the operands. 1258 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1259 regs = Vd + regs > 32 ? 32 - Vd : regs; 1260 regs = std::max( 1u, regs); 1261 regs = std::min(16u, regs); 1262 S = MCDisassembler::SoftFail; 1263 } 1264 1265 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1266 return MCDisassembler::Fail; 1267 for (unsigned i = 0; i < (regs - 1); ++i) { 1268 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1269 return MCDisassembler::Fail; 1270 } 1271 1272 return S; 1273 } 1274 1275 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1276 uint64_t Address, const void *Decoder) { 1277 // This operand encodes a mask of contiguous zeros between a specified MSB 1278 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1279 // the mask of all bits LSB-and-lower, and then xor them to create 1280 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1281 // create the final mask. 1282 unsigned msb = fieldFromInstruction(Val, 5, 5); 1283 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1284 1285 DecodeStatus S = MCDisassembler::Success; 1286 if (lsb > msb) { 1287 Check(S, MCDisassembler::SoftFail); 1288 // The check above will cause the warning for the "potentially undefined 1289 // instruction encoding" but we can't build a bad MCOperand value here 1290 // with a lsb > msb or else printing the MCInst will cause a crash. 1291 lsb = msb; 1292 } 1293 1294 uint32_t msb_mask = 0xFFFFFFFF; 1295 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1296 uint32_t lsb_mask = (1U << lsb) - 1; 1297 1298 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); 1299 return S; 1300 } 1301 1302 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1303 uint64_t Address, const void *Decoder) { 1304 DecodeStatus S = MCDisassembler::Success; 1305 1306 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1307 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1308 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1309 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1310 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1311 unsigned U = fieldFromInstruction(Insn, 23, 1); 1312 1313 switch (Inst.getOpcode()) { 1314 case ARM::LDC_OFFSET: 1315 case ARM::LDC_PRE: 1316 case ARM::LDC_POST: 1317 case ARM::LDC_OPTION: 1318 case ARM::LDCL_OFFSET: 1319 case ARM::LDCL_PRE: 1320 case ARM::LDCL_POST: 1321 case ARM::LDCL_OPTION: 1322 case ARM::STC_OFFSET: 1323 case ARM::STC_PRE: 1324 case ARM::STC_POST: 1325 case ARM::STC_OPTION: 1326 case ARM::STCL_OFFSET: 1327 case ARM::STCL_PRE: 1328 case ARM::STCL_POST: 1329 case ARM::STCL_OPTION: 1330 case ARM::t2LDC_OFFSET: 1331 case ARM::t2LDC_PRE: 1332 case ARM::t2LDC_POST: 1333 case ARM::t2LDC_OPTION: 1334 case ARM::t2LDCL_OFFSET: 1335 case ARM::t2LDCL_PRE: 1336 case ARM::t2LDCL_POST: 1337 case ARM::t2LDCL_OPTION: 1338 case ARM::t2STC_OFFSET: 1339 case ARM::t2STC_PRE: 1340 case ARM::t2STC_POST: 1341 case ARM::t2STC_OPTION: 1342 case ARM::t2STCL_OFFSET: 1343 case ARM::t2STCL_PRE: 1344 case ARM::t2STCL_POST: 1345 case ARM::t2STCL_OPTION: 1346 if (coproc == 0xA || coproc == 0xB) 1347 return MCDisassembler::Fail; 1348 break; 1349 default: 1350 break; 1351 } 1352 1353 const FeatureBitset &featureBits = 1354 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1355 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) 1356 return MCDisassembler::Fail; 1357 1358 Inst.addOperand(MCOperand::createImm(coproc)); 1359 Inst.addOperand(MCOperand::createImm(CRd)); 1360 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1361 return MCDisassembler::Fail; 1362 1363 switch (Inst.getOpcode()) { 1364 case ARM::t2LDC2_OFFSET: 1365 case ARM::t2LDC2L_OFFSET: 1366 case ARM::t2LDC2_PRE: 1367 case ARM::t2LDC2L_PRE: 1368 case ARM::t2STC2_OFFSET: 1369 case ARM::t2STC2L_OFFSET: 1370 case ARM::t2STC2_PRE: 1371 case ARM::t2STC2L_PRE: 1372 case ARM::LDC2_OFFSET: 1373 case ARM::LDC2L_OFFSET: 1374 case ARM::LDC2_PRE: 1375 case ARM::LDC2L_PRE: 1376 case ARM::STC2_OFFSET: 1377 case ARM::STC2L_OFFSET: 1378 case ARM::STC2_PRE: 1379 case ARM::STC2L_PRE: 1380 case ARM::t2LDC_OFFSET: 1381 case ARM::t2LDCL_OFFSET: 1382 case ARM::t2LDC_PRE: 1383 case ARM::t2LDCL_PRE: 1384 case ARM::t2STC_OFFSET: 1385 case ARM::t2STCL_OFFSET: 1386 case ARM::t2STC_PRE: 1387 case ARM::t2STCL_PRE: 1388 case ARM::LDC_OFFSET: 1389 case ARM::LDCL_OFFSET: 1390 case ARM::LDC_PRE: 1391 case ARM::LDCL_PRE: 1392 case ARM::STC_OFFSET: 1393 case ARM::STCL_OFFSET: 1394 case ARM::STC_PRE: 1395 case ARM::STCL_PRE: 1396 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1397 Inst.addOperand(MCOperand::createImm(imm)); 1398 break; 1399 case ARM::t2LDC2_POST: 1400 case ARM::t2LDC2L_POST: 1401 case ARM::t2STC2_POST: 1402 case ARM::t2STC2L_POST: 1403 case ARM::LDC2_POST: 1404 case ARM::LDC2L_POST: 1405 case ARM::STC2_POST: 1406 case ARM::STC2L_POST: 1407 case ARM::t2LDC_POST: 1408 case ARM::t2LDCL_POST: 1409 case ARM::t2STC_POST: 1410 case ARM::t2STCL_POST: 1411 case ARM::LDC_POST: 1412 case ARM::LDCL_POST: 1413 case ARM::STC_POST: 1414 case ARM::STCL_POST: 1415 imm |= U << 8; 1416 LLVM_FALLTHROUGH; 1417 default: 1418 // The 'option' variant doesn't encode 'U' in the immediate since 1419 // the immediate is unsigned [0,255]. 1420 Inst.addOperand(MCOperand::createImm(imm)); 1421 break; 1422 } 1423 1424 switch (Inst.getOpcode()) { 1425 case ARM::LDC_OFFSET: 1426 case ARM::LDC_PRE: 1427 case ARM::LDC_POST: 1428 case ARM::LDC_OPTION: 1429 case ARM::LDCL_OFFSET: 1430 case ARM::LDCL_PRE: 1431 case ARM::LDCL_POST: 1432 case ARM::LDCL_OPTION: 1433 case ARM::STC_OFFSET: 1434 case ARM::STC_PRE: 1435 case ARM::STC_POST: 1436 case ARM::STC_OPTION: 1437 case ARM::STCL_OFFSET: 1438 case ARM::STCL_PRE: 1439 case ARM::STCL_POST: 1440 case ARM::STCL_OPTION: 1441 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1442 return MCDisassembler::Fail; 1443 break; 1444 default: 1445 break; 1446 } 1447 1448 return S; 1449 } 1450 1451 static DecodeStatus 1452 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1453 uint64_t Address, const void *Decoder) { 1454 DecodeStatus S = MCDisassembler::Success; 1455 1456 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1457 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1458 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1459 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1460 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1461 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1462 unsigned P = fieldFromInstruction(Insn, 24, 1); 1463 unsigned W = fieldFromInstruction(Insn, 21, 1); 1464 1465 // On stores, the writeback operand precedes Rt. 1466 switch (Inst.getOpcode()) { 1467 case ARM::STR_POST_IMM: 1468 case ARM::STR_POST_REG: 1469 case ARM::STRB_POST_IMM: 1470 case ARM::STRB_POST_REG: 1471 case ARM::STRT_POST_REG: 1472 case ARM::STRT_POST_IMM: 1473 case ARM::STRBT_POST_REG: 1474 case ARM::STRBT_POST_IMM: 1475 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1476 return MCDisassembler::Fail; 1477 break; 1478 default: 1479 break; 1480 } 1481 1482 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1483 return MCDisassembler::Fail; 1484 1485 // On loads, the writeback operand comes after Rt. 1486 switch (Inst.getOpcode()) { 1487 case ARM::LDR_POST_IMM: 1488 case ARM::LDR_POST_REG: 1489 case ARM::LDRB_POST_IMM: 1490 case ARM::LDRB_POST_REG: 1491 case ARM::LDRBT_POST_REG: 1492 case ARM::LDRBT_POST_IMM: 1493 case ARM::LDRT_POST_REG: 1494 case ARM::LDRT_POST_IMM: 1495 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1496 return MCDisassembler::Fail; 1497 break; 1498 default: 1499 break; 1500 } 1501 1502 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1503 return MCDisassembler::Fail; 1504 1505 ARM_AM::AddrOpc Op = ARM_AM::add; 1506 if (!fieldFromInstruction(Insn, 23, 1)) 1507 Op = ARM_AM::sub; 1508 1509 bool writeback = (P == 0) || (W == 1); 1510 unsigned idx_mode = 0; 1511 if (P && writeback) 1512 idx_mode = ARMII::IndexModePre; 1513 else if (!P && writeback) 1514 idx_mode = ARMII::IndexModePost; 1515 1516 if (writeback && (Rn == 15 || Rn == Rt)) 1517 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1518 1519 if (reg) { 1520 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1521 return MCDisassembler::Fail; 1522 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1523 switch( fieldFromInstruction(Insn, 5, 2)) { 1524 case 0: 1525 Opc = ARM_AM::lsl; 1526 break; 1527 case 1: 1528 Opc = ARM_AM::lsr; 1529 break; 1530 case 2: 1531 Opc = ARM_AM::asr; 1532 break; 1533 case 3: 1534 Opc = ARM_AM::ror; 1535 break; 1536 default: 1537 return MCDisassembler::Fail; 1538 } 1539 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1540 if (Opc == ARM_AM::ror && amt == 0) 1541 Opc = ARM_AM::rrx; 1542 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1543 1544 Inst.addOperand(MCOperand::createImm(imm)); 1545 } else { 1546 Inst.addOperand(MCOperand::createReg(0)); 1547 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1548 Inst.addOperand(MCOperand::createImm(tmp)); 1549 } 1550 1551 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1552 return MCDisassembler::Fail; 1553 1554 return S; 1555 } 1556 1557 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1558 uint64_t Address, const void *Decoder) { 1559 DecodeStatus S = MCDisassembler::Success; 1560 1561 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1562 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1563 unsigned type = fieldFromInstruction(Val, 5, 2); 1564 unsigned imm = fieldFromInstruction(Val, 7, 5); 1565 unsigned U = fieldFromInstruction(Val, 12, 1); 1566 1567 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1568 switch (type) { 1569 case 0: 1570 ShOp = ARM_AM::lsl; 1571 break; 1572 case 1: 1573 ShOp = ARM_AM::lsr; 1574 break; 1575 case 2: 1576 ShOp = ARM_AM::asr; 1577 break; 1578 case 3: 1579 ShOp = ARM_AM::ror; 1580 break; 1581 } 1582 1583 if (ShOp == ARM_AM::ror && imm == 0) 1584 ShOp = ARM_AM::rrx; 1585 1586 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1587 return MCDisassembler::Fail; 1588 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1589 return MCDisassembler::Fail; 1590 unsigned shift; 1591 if (U) 1592 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1593 else 1594 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1595 Inst.addOperand(MCOperand::createImm(shift)); 1596 1597 return S; 1598 } 1599 1600 static DecodeStatus 1601 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1602 uint64_t Address, const void *Decoder) { 1603 DecodeStatus S = MCDisassembler::Success; 1604 1605 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1606 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1607 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1608 unsigned type = fieldFromInstruction(Insn, 22, 1); 1609 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1610 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1611 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1612 unsigned W = fieldFromInstruction(Insn, 21, 1); 1613 unsigned P = fieldFromInstruction(Insn, 24, 1); 1614 unsigned Rt2 = Rt + 1; 1615 1616 bool writeback = (W == 1) | (P == 0); 1617 1618 // For {LD,ST}RD, Rt must be even, else undefined. 1619 switch (Inst.getOpcode()) { 1620 case ARM::STRD: 1621 case ARM::STRD_PRE: 1622 case ARM::STRD_POST: 1623 case ARM::LDRD: 1624 case ARM::LDRD_PRE: 1625 case ARM::LDRD_POST: 1626 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1627 break; 1628 default: 1629 break; 1630 } 1631 switch (Inst.getOpcode()) { 1632 case ARM::STRD: 1633 case ARM::STRD_PRE: 1634 case ARM::STRD_POST: 1635 if (P == 0 && W == 1) 1636 S = MCDisassembler::SoftFail; 1637 1638 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1639 S = MCDisassembler::SoftFail; 1640 if (type && Rm == 15) 1641 S = MCDisassembler::SoftFail; 1642 if (Rt2 == 15) 1643 S = MCDisassembler::SoftFail; 1644 if (!type && fieldFromInstruction(Insn, 8, 4)) 1645 S = MCDisassembler::SoftFail; 1646 break; 1647 case ARM::STRH: 1648 case ARM::STRH_PRE: 1649 case ARM::STRH_POST: 1650 if (Rt == 15) 1651 S = MCDisassembler::SoftFail; 1652 if (writeback && (Rn == 15 || Rn == Rt)) 1653 S = MCDisassembler::SoftFail; 1654 if (!type && Rm == 15) 1655 S = MCDisassembler::SoftFail; 1656 break; 1657 case ARM::LDRD: 1658 case ARM::LDRD_PRE: 1659 case ARM::LDRD_POST: 1660 if (type && Rn == 15) { 1661 if (Rt2 == 15) 1662 S = MCDisassembler::SoftFail; 1663 break; 1664 } 1665 if (P == 0 && W == 1) 1666 S = MCDisassembler::SoftFail; 1667 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1668 S = MCDisassembler::SoftFail; 1669 if (!type && writeback && Rn == 15) 1670 S = MCDisassembler::SoftFail; 1671 if (writeback && (Rn == Rt || Rn == Rt2)) 1672 S = MCDisassembler::SoftFail; 1673 break; 1674 case ARM::LDRH: 1675 case ARM::LDRH_PRE: 1676 case ARM::LDRH_POST: 1677 if (type && Rn == 15) { 1678 if (Rt == 15) 1679 S = MCDisassembler::SoftFail; 1680 break; 1681 } 1682 if (Rt == 15) 1683 S = MCDisassembler::SoftFail; 1684 if (!type && Rm == 15) 1685 S = MCDisassembler::SoftFail; 1686 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1687 S = MCDisassembler::SoftFail; 1688 break; 1689 case ARM::LDRSH: 1690 case ARM::LDRSH_PRE: 1691 case ARM::LDRSH_POST: 1692 case ARM::LDRSB: 1693 case ARM::LDRSB_PRE: 1694 case ARM::LDRSB_POST: 1695 if (type && Rn == 15) { 1696 if (Rt == 15) 1697 S = MCDisassembler::SoftFail; 1698 break; 1699 } 1700 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1701 S = MCDisassembler::SoftFail; 1702 if (!type && (Rt == 15 || Rm == 15)) 1703 S = MCDisassembler::SoftFail; 1704 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1705 S = MCDisassembler::SoftFail; 1706 break; 1707 default: 1708 break; 1709 } 1710 1711 if (writeback) { // Writeback 1712 if (P) 1713 U |= ARMII::IndexModePre << 9; 1714 else 1715 U |= ARMII::IndexModePost << 9; 1716 1717 // On stores, the writeback operand precedes Rt. 1718 switch (Inst.getOpcode()) { 1719 case ARM::STRD: 1720 case ARM::STRD_PRE: 1721 case ARM::STRD_POST: 1722 case ARM::STRH: 1723 case ARM::STRH_PRE: 1724 case ARM::STRH_POST: 1725 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1726 return MCDisassembler::Fail; 1727 break; 1728 default: 1729 break; 1730 } 1731 } 1732 1733 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1734 return MCDisassembler::Fail; 1735 switch (Inst.getOpcode()) { 1736 case ARM::STRD: 1737 case ARM::STRD_PRE: 1738 case ARM::STRD_POST: 1739 case ARM::LDRD: 1740 case ARM::LDRD_PRE: 1741 case ARM::LDRD_POST: 1742 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1743 return MCDisassembler::Fail; 1744 break; 1745 default: 1746 break; 1747 } 1748 1749 if (writeback) { 1750 // On loads, the writeback operand comes after Rt. 1751 switch (Inst.getOpcode()) { 1752 case ARM::LDRD: 1753 case ARM::LDRD_PRE: 1754 case ARM::LDRD_POST: 1755 case ARM::LDRH: 1756 case ARM::LDRH_PRE: 1757 case ARM::LDRH_POST: 1758 case ARM::LDRSH: 1759 case ARM::LDRSH_PRE: 1760 case ARM::LDRSH_POST: 1761 case ARM::LDRSB: 1762 case ARM::LDRSB_PRE: 1763 case ARM::LDRSB_POST: 1764 case ARM::LDRHTr: 1765 case ARM::LDRSBTr: 1766 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1767 return MCDisassembler::Fail; 1768 break; 1769 default: 1770 break; 1771 } 1772 } 1773 1774 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1775 return MCDisassembler::Fail; 1776 1777 if (type) { 1778 Inst.addOperand(MCOperand::createReg(0)); 1779 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); 1780 } else { 1781 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1782 return MCDisassembler::Fail; 1783 Inst.addOperand(MCOperand::createImm(U)); 1784 } 1785 1786 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1787 return MCDisassembler::Fail; 1788 1789 return S; 1790 } 1791 1792 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1793 uint64_t Address, const void *Decoder) { 1794 DecodeStatus S = MCDisassembler::Success; 1795 1796 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1797 unsigned mode = fieldFromInstruction(Insn, 23, 2); 1798 1799 switch (mode) { 1800 case 0: 1801 mode = ARM_AM::da; 1802 break; 1803 case 1: 1804 mode = ARM_AM::ia; 1805 break; 1806 case 2: 1807 mode = ARM_AM::db; 1808 break; 1809 case 3: 1810 mode = ARM_AM::ib; 1811 break; 1812 } 1813 1814 Inst.addOperand(MCOperand::createImm(mode)); 1815 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1816 return MCDisassembler::Fail; 1817 1818 return S; 1819 } 1820 1821 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 1822 uint64_t Address, const void *Decoder) { 1823 DecodeStatus S = MCDisassembler::Success; 1824 1825 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 1826 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1827 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1828 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1829 1830 if (pred == 0xF) 1831 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1832 1833 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1834 return MCDisassembler::Fail; 1835 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1836 return MCDisassembler::Fail; 1837 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1838 return MCDisassembler::Fail; 1839 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1840 return MCDisassembler::Fail; 1841 return S; 1842 } 1843 1844 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 1845 unsigned Insn, 1846 uint64_t Address, const void *Decoder) { 1847 DecodeStatus S = MCDisassembler::Success; 1848 1849 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1850 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1851 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 1852 1853 if (pred == 0xF) { 1854 // Ambiguous with RFE and SRS 1855 switch (Inst.getOpcode()) { 1856 case ARM::LDMDA: 1857 Inst.setOpcode(ARM::RFEDA); 1858 break; 1859 case ARM::LDMDA_UPD: 1860 Inst.setOpcode(ARM::RFEDA_UPD); 1861 break; 1862 case ARM::LDMDB: 1863 Inst.setOpcode(ARM::RFEDB); 1864 break; 1865 case ARM::LDMDB_UPD: 1866 Inst.setOpcode(ARM::RFEDB_UPD); 1867 break; 1868 case ARM::LDMIA: 1869 Inst.setOpcode(ARM::RFEIA); 1870 break; 1871 case ARM::LDMIA_UPD: 1872 Inst.setOpcode(ARM::RFEIA_UPD); 1873 break; 1874 case ARM::LDMIB: 1875 Inst.setOpcode(ARM::RFEIB); 1876 break; 1877 case ARM::LDMIB_UPD: 1878 Inst.setOpcode(ARM::RFEIB_UPD); 1879 break; 1880 case ARM::STMDA: 1881 Inst.setOpcode(ARM::SRSDA); 1882 break; 1883 case ARM::STMDA_UPD: 1884 Inst.setOpcode(ARM::SRSDA_UPD); 1885 break; 1886 case ARM::STMDB: 1887 Inst.setOpcode(ARM::SRSDB); 1888 break; 1889 case ARM::STMDB_UPD: 1890 Inst.setOpcode(ARM::SRSDB_UPD); 1891 break; 1892 case ARM::STMIA: 1893 Inst.setOpcode(ARM::SRSIA); 1894 break; 1895 case ARM::STMIA_UPD: 1896 Inst.setOpcode(ARM::SRSIA_UPD); 1897 break; 1898 case ARM::STMIB: 1899 Inst.setOpcode(ARM::SRSIB); 1900 break; 1901 case ARM::STMIB_UPD: 1902 Inst.setOpcode(ARM::SRSIB_UPD); 1903 break; 1904 default: 1905 return MCDisassembler::Fail; 1906 } 1907 1908 // For stores (which become SRS's, the only operand is the mode. 1909 if (fieldFromInstruction(Insn, 20, 1) == 0) { 1910 // Check SRS encoding constraints 1911 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 1912 fieldFromInstruction(Insn, 20, 1) == 0)) 1913 return MCDisassembler::Fail; 1914 1915 Inst.addOperand( 1916 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); 1917 return S; 1918 } 1919 1920 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1921 } 1922 1923 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1924 return MCDisassembler::Fail; 1925 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1926 return MCDisassembler::Fail; // Tied 1927 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1928 return MCDisassembler::Fail; 1929 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1930 return MCDisassembler::Fail; 1931 1932 return S; 1933 } 1934 1935 // Check for UNPREDICTABLE predicated ESB instruction 1936 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 1937 uint64_t Address, const void *Decoder) { 1938 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1939 unsigned imm8 = fieldFromInstruction(Insn, 0, 8); 1940 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 1941 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 1942 1943 DecodeStatus S = MCDisassembler::Success; 1944 1945 Inst.addOperand(MCOperand::createImm(imm8)); 1946 1947 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1948 return MCDisassembler::Fail; 1949 1950 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, 1951 // so all predicates should be allowed. 1952 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) 1953 S = MCDisassembler::SoftFail; 1954 1955 return S; 1956 } 1957 1958 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 1959 uint64_t Address, const void *Decoder) { 1960 unsigned imod = fieldFromInstruction(Insn, 18, 2); 1961 unsigned M = fieldFromInstruction(Insn, 17, 1); 1962 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 1963 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1964 1965 DecodeStatus S = MCDisassembler::Success; 1966 1967 // This decoder is called from multiple location that do not check 1968 // the full encoding is valid before they do. 1969 if (fieldFromInstruction(Insn, 5, 1) != 0 || 1970 fieldFromInstruction(Insn, 16, 1) != 0 || 1971 fieldFromInstruction(Insn, 20, 8) != 0x10) 1972 return MCDisassembler::Fail; 1973 1974 // imod == '01' --> UNPREDICTABLE 1975 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1976 // return failure here. The '01' imod value is unprintable, so there's 1977 // nothing useful we could do even if we returned UNPREDICTABLE. 1978 1979 if (imod == 1) return MCDisassembler::Fail; 1980 1981 if (imod && M) { 1982 Inst.setOpcode(ARM::CPS3p); 1983 Inst.addOperand(MCOperand::createImm(imod)); 1984 Inst.addOperand(MCOperand::createImm(iflags)); 1985 Inst.addOperand(MCOperand::createImm(mode)); 1986 } else if (imod && !M) { 1987 Inst.setOpcode(ARM::CPS2p); 1988 Inst.addOperand(MCOperand::createImm(imod)); 1989 Inst.addOperand(MCOperand::createImm(iflags)); 1990 if (mode) S = MCDisassembler::SoftFail; 1991 } else if (!imod && M) { 1992 Inst.setOpcode(ARM::CPS1p); 1993 Inst.addOperand(MCOperand::createImm(mode)); 1994 if (iflags) S = MCDisassembler::SoftFail; 1995 } else { 1996 // imod == '00' && M == '0' --> UNPREDICTABLE 1997 Inst.setOpcode(ARM::CPS1p); 1998 Inst.addOperand(MCOperand::createImm(mode)); 1999 S = MCDisassembler::SoftFail; 2000 } 2001 2002 return S; 2003 } 2004 2005 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2006 uint64_t Address, const void *Decoder) { 2007 unsigned imod = fieldFromInstruction(Insn, 9, 2); 2008 unsigned M = fieldFromInstruction(Insn, 8, 1); 2009 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 2010 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2011 2012 DecodeStatus S = MCDisassembler::Success; 2013 2014 // imod == '01' --> UNPREDICTABLE 2015 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2016 // return failure here. The '01' imod value is unprintable, so there's 2017 // nothing useful we could do even if we returned UNPREDICTABLE. 2018 2019 if (imod == 1) return MCDisassembler::Fail; 2020 2021 if (imod && M) { 2022 Inst.setOpcode(ARM::t2CPS3p); 2023 Inst.addOperand(MCOperand::createImm(imod)); 2024 Inst.addOperand(MCOperand::createImm(iflags)); 2025 Inst.addOperand(MCOperand::createImm(mode)); 2026 } else if (imod && !M) { 2027 Inst.setOpcode(ARM::t2CPS2p); 2028 Inst.addOperand(MCOperand::createImm(imod)); 2029 Inst.addOperand(MCOperand::createImm(iflags)); 2030 if (mode) S = MCDisassembler::SoftFail; 2031 } else if (!imod && M) { 2032 Inst.setOpcode(ARM::t2CPS1p); 2033 Inst.addOperand(MCOperand::createImm(mode)); 2034 if (iflags) S = MCDisassembler::SoftFail; 2035 } else { 2036 // imod == '00' && M == '0' --> this is a HINT instruction 2037 int imm = fieldFromInstruction(Insn, 0, 8); 2038 // HINT are defined only for immediate in [0..4] 2039 if(imm > 4) return MCDisassembler::Fail; 2040 Inst.setOpcode(ARM::t2HINT); 2041 Inst.addOperand(MCOperand::createImm(imm)); 2042 } 2043 2044 return S; 2045 } 2046 2047 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2048 uint64_t Address, const void *Decoder) { 2049 DecodeStatus S = MCDisassembler::Success; 2050 2051 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2052 unsigned imm = 0; 2053 2054 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2055 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2056 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2057 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2058 2059 if (Inst.getOpcode() == ARM::t2MOVTi16) 2060 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2061 return MCDisassembler::Fail; 2062 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2063 return MCDisassembler::Fail; 2064 2065 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2066 Inst.addOperand(MCOperand::createImm(imm)); 2067 2068 return S; 2069 } 2070 2071 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2072 uint64_t Address, const void *Decoder) { 2073 DecodeStatus S = MCDisassembler::Success; 2074 2075 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2076 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2077 unsigned imm = 0; 2078 2079 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2080 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2081 2082 if (Inst.getOpcode() == ARM::MOVTi16) 2083 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2084 return MCDisassembler::Fail; 2085 2086 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2087 return MCDisassembler::Fail; 2088 2089 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2090 Inst.addOperand(MCOperand::createImm(imm)); 2091 2092 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2093 return MCDisassembler::Fail; 2094 2095 return S; 2096 } 2097 2098 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2099 uint64_t Address, const void *Decoder) { 2100 DecodeStatus S = MCDisassembler::Success; 2101 2102 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2103 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2104 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2105 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2106 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2107 2108 if (pred == 0xF) 2109 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2110 2111 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2112 return MCDisassembler::Fail; 2113 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2114 return MCDisassembler::Fail; 2115 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2116 return MCDisassembler::Fail; 2117 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2118 return MCDisassembler::Fail; 2119 2120 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2121 return MCDisassembler::Fail; 2122 2123 return S; 2124 } 2125 2126 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 2127 uint64_t Address, const void *Decoder) { 2128 DecodeStatus S = MCDisassembler::Success; 2129 2130 unsigned Pred = fieldFromInstruction(Insn, 28, 4); 2131 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2132 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2133 2134 if (Pred == 0xF) 2135 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); 2136 2137 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2138 return MCDisassembler::Fail; 2139 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2140 return MCDisassembler::Fail; 2141 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) 2142 return MCDisassembler::Fail; 2143 2144 return S; 2145 } 2146 2147 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 2148 uint64_t Address, const void *Decoder) { 2149 DecodeStatus S = MCDisassembler::Success; 2150 2151 unsigned Imm = fieldFromInstruction(Insn, 9, 1); 2152 2153 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2154 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2155 2156 if (!FeatureBits[ARM::HasV8_1aOps] || 2157 !FeatureBits[ARM::HasV8Ops]) 2158 return MCDisassembler::Fail; 2159 2160 // Decoder can be called from DecodeTST, which does not check the full 2161 // encoding is valid. 2162 if (fieldFromInstruction(Insn, 20,12) != 0xf11 || 2163 fieldFromInstruction(Insn, 4,4) != 0) 2164 return MCDisassembler::Fail; 2165 if (fieldFromInstruction(Insn, 10,10) != 0 || 2166 fieldFromInstruction(Insn, 0,4) != 0) 2167 S = MCDisassembler::SoftFail; 2168 2169 Inst.setOpcode(ARM::SETPAN); 2170 Inst.addOperand(MCOperand::createImm(Imm)); 2171 2172 return S; 2173 } 2174 2175 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2176 uint64_t Address, const void *Decoder) { 2177 DecodeStatus S = MCDisassembler::Success; 2178 2179 unsigned add = fieldFromInstruction(Val, 12, 1); 2180 unsigned imm = fieldFromInstruction(Val, 0, 12); 2181 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2182 2183 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2184 return MCDisassembler::Fail; 2185 2186 if (!add) imm *= -1; 2187 if (imm == 0 && !add) imm = INT32_MIN; 2188 Inst.addOperand(MCOperand::createImm(imm)); 2189 if (Rn == 15) 2190 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2191 2192 return S; 2193 } 2194 2195 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2196 uint64_t Address, const void *Decoder) { 2197 DecodeStatus S = MCDisassembler::Success; 2198 2199 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2200 // U == 1 to add imm, 0 to subtract it. 2201 unsigned U = fieldFromInstruction(Val, 8, 1); 2202 unsigned imm = fieldFromInstruction(Val, 0, 8); 2203 2204 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2205 return MCDisassembler::Fail; 2206 2207 if (U) 2208 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2209 else 2210 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2211 2212 return S; 2213 } 2214 2215 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 2216 uint64_t Address, const void *Decoder) { 2217 DecodeStatus S = MCDisassembler::Success; 2218 2219 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2220 // U == 1 to add imm, 0 to subtract it. 2221 unsigned U = fieldFromInstruction(Val, 8, 1); 2222 unsigned imm = fieldFromInstruction(Val, 0, 8); 2223 2224 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2225 return MCDisassembler::Fail; 2226 2227 if (U) 2228 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm))); 2229 else 2230 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); 2231 2232 return S; 2233 } 2234 2235 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2236 uint64_t Address, const void *Decoder) { 2237 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2238 } 2239 2240 static DecodeStatus 2241 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2242 uint64_t Address, const void *Decoder) { 2243 DecodeStatus Status = MCDisassembler::Success; 2244 2245 // Note the J1 and J2 values are from the encoded instruction. So here 2246 // change them to I1 and I2 values via as documented: 2247 // I1 = NOT(J1 EOR S); 2248 // I2 = NOT(J2 EOR S); 2249 // and build the imm32 with one trailing zero as documented: 2250 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2251 unsigned S = fieldFromInstruction(Insn, 26, 1); 2252 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2253 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2254 unsigned I1 = !(J1 ^ S); 2255 unsigned I2 = !(J2 ^ S); 2256 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2257 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2258 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2259 int imm32 = SignExtend32<25>(tmp << 1); 2260 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2261 true, 4, Inst, Decoder)) 2262 Inst.addOperand(MCOperand::createImm(imm32)); 2263 2264 return Status; 2265 } 2266 2267 static DecodeStatus 2268 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2269 uint64_t Address, const void *Decoder) { 2270 DecodeStatus S = MCDisassembler::Success; 2271 2272 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2273 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2274 2275 if (pred == 0xF) { 2276 Inst.setOpcode(ARM::BLXi); 2277 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2278 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2279 true, 4, Inst, Decoder)) 2280 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2281 return S; 2282 } 2283 2284 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2285 true, 4, Inst, Decoder)) 2286 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2287 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2288 return MCDisassembler::Fail; 2289 2290 return S; 2291 } 2292 2293 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2294 uint64_t Address, const void *Decoder) { 2295 DecodeStatus S = MCDisassembler::Success; 2296 2297 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2298 unsigned align = fieldFromInstruction(Val, 4, 2); 2299 2300 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2301 return MCDisassembler::Fail; 2302 if (!align) 2303 Inst.addOperand(MCOperand::createImm(0)); 2304 else 2305 Inst.addOperand(MCOperand::createImm(4 << align)); 2306 2307 return S; 2308 } 2309 2310 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2311 uint64_t Address, const void *Decoder) { 2312 DecodeStatus S = MCDisassembler::Success; 2313 2314 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2315 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2316 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2317 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2318 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2319 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2320 2321 // First output register 2322 switch (Inst.getOpcode()) { 2323 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2324 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2325 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2326 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2327 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2328 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2329 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2330 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2331 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2332 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2333 return MCDisassembler::Fail; 2334 break; 2335 case ARM::VLD2b16: 2336 case ARM::VLD2b32: 2337 case ARM::VLD2b8: 2338 case ARM::VLD2b16wb_fixed: 2339 case ARM::VLD2b16wb_register: 2340 case ARM::VLD2b32wb_fixed: 2341 case ARM::VLD2b32wb_register: 2342 case ARM::VLD2b8wb_fixed: 2343 case ARM::VLD2b8wb_register: 2344 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2345 return MCDisassembler::Fail; 2346 break; 2347 default: 2348 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2349 return MCDisassembler::Fail; 2350 } 2351 2352 // Second output register 2353 switch (Inst.getOpcode()) { 2354 case ARM::VLD3d8: 2355 case ARM::VLD3d16: 2356 case ARM::VLD3d32: 2357 case ARM::VLD3d8_UPD: 2358 case ARM::VLD3d16_UPD: 2359 case ARM::VLD3d32_UPD: 2360 case ARM::VLD4d8: 2361 case ARM::VLD4d16: 2362 case ARM::VLD4d32: 2363 case ARM::VLD4d8_UPD: 2364 case ARM::VLD4d16_UPD: 2365 case ARM::VLD4d32_UPD: 2366 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2367 return MCDisassembler::Fail; 2368 break; 2369 case ARM::VLD3q8: 2370 case ARM::VLD3q16: 2371 case ARM::VLD3q32: 2372 case ARM::VLD3q8_UPD: 2373 case ARM::VLD3q16_UPD: 2374 case ARM::VLD3q32_UPD: 2375 case ARM::VLD4q8: 2376 case ARM::VLD4q16: 2377 case ARM::VLD4q32: 2378 case ARM::VLD4q8_UPD: 2379 case ARM::VLD4q16_UPD: 2380 case ARM::VLD4q32_UPD: 2381 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2382 return MCDisassembler::Fail; 2383 default: 2384 break; 2385 } 2386 2387 // Third output register 2388 switch(Inst.getOpcode()) { 2389 case ARM::VLD3d8: 2390 case ARM::VLD3d16: 2391 case ARM::VLD3d32: 2392 case ARM::VLD3d8_UPD: 2393 case ARM::VLD3d16_UPD: 2394 case ARM::VLD3d32_UPD: 2395 case ARM::VLD4d8: 2396 case ARM::VLD4d16: 2397 case ARM::VLD4d32: 2398 case ARM::VLD4d8_UPD: 2399 case ARM::VLD4d16_UPD: 2400 case ARM::VLD4d32_UPD: 2401 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2402 return MCDisassembler::Fail; 2403 break; 2404 case ARM::VLD3q8: 2405 case ARM::VLD3q16: 2406 case ARM::VLD3q32: 2407 case ARM::VLD3q8_UPD: 2408 case ARM::VLD3q16_UPD: 2409 case ARM::VLD3q32_UPD: 2410 case ARM::VLD4q8: 2411 case ARM::VLD4q16: 2412 case ARM::VLD4q32: 2413 case ARM::VLD4q8_UPD: 2414 case ARM::VLD4q16_UPD: 2415 case ARM::VLD4q32_UPD: 2416 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2417 return MCDisassembler::Fail; 2418 break; 2419 default: 2420 break; 2421 } 2422 2423 // Fourth output register 2424 switch (Inst.getOpcode()) { 2425 case ARM::VLD4d8: 2426 case ARM::VLD4d16: 2427 case ARM::VLD4d32: 2428 case ARM::VLD4d8_UPD: 2429 case ARM::VLD4d16_UPD: 2430 case ARM::VLD4d32_UPD: 2431 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2432 return MCDisassembler::Fail; 2433 break; 2434 case ARM::VLD4q8: 2435 case ARM::VLD4q16: 2436 case ARM::VLD4q32: 2437 case ARM::VLD4q8_UPD: 2438 case ARM::VLD4q16_UPD: 2439 case ARM::VLD4q32_UPD: 2440 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2441 return MCDisassembler::Fail; 2442 break; 2443 default: 2444 break; 2445 } 2446 2447 // Writeback operand 2448 switch (Inst.getOpcode()) { 2449 case ARM::VLD1d8wb_fixed: 2450 case ARM::VLD1d16wb_fixed: 2451 case ARM::VLD1d32wb_fixed: 2452 case ARM::VLD1d64wb_fixed: 2453 case ARM::VLD1d8wb_register: 2454 case ARM::VLD1d16wb_register: 2455 case ARM::VLD1d32wb_register: 2456 case ARM::VLD1d64wb_register: 2457 case ARM::VLD1q8wb_fixed: 2458 case ARM::VLD1q16wb_fixed: 2459 case ARM::VLD1q32wb_fixed: 2460 case ARM::VLD1q64wb_fixed: 2461 case ARM::VLD1q8wb_register: 2462 case ARM::VLD1q16wb_register: 2463 case ARM::VLD1q32wb_register: 2464 case ARM::VLD1q64wb_register: 2465 case ARM::VLD1d8Twb_fixed: 2466 case ARM::VLD1d8Twb_register: 2467 case ARM::VLD1d16Twb_fixed: 2468 case ARM::VLD1d16Twb_register: 2469 case ARM::VLD1d32Twb_fixed: 2470 case ARM::VLD1d32Twb_register: 2471 case ARM::VLD1d64Twb_fixed: 2472 case ARM::VLD1d64Twb_register: 2473 case ARM::VLD1d8Qwb_fixed: 2474 case ARM::VLD1d8Qwb_register: 2475 case ARM::VLD1d16Qwb_fixed: 2476 case ARM::VLD1d16Qwb_register: 2477 case ARM::VLD1d32Qwb_fixed: 2478 case ARM::VLD1d32Qwb_register: 2479 case ARM::VLD1d64Qwb_fixed: 2480 case ARM::VLD1d64Qwb_register: 2481 case ARM::VLD2d8wb_fixed: 2482 case ARM::VLD2d16wb_fixed: 2483 case ARM::VLD2d32wb_fixed: 2484 case ARM::VLD2q8wb_fixed: 2485 case ARM::VLD2q16wb_fixed: 2486 case ARM::VLD2q32wb_fixed: 2487 case ARM::VLD2d8wb_register: 2488 case ARM::VLD2d16wb_register: 2489 case ARM::VLD2d32wb_register: 2490 case ARM::VLD2q8wb_register: 2491 case ARM::VLD2q16wb_register: 2492 case ARM::VLD2q32wb_register: 2493 case ARM::VLD2b8wb_fixed: 2494 case ARM::VLD2b16wb_fixed: 2495 case ARM::VLD2b32wb_fixed: 2496 case ARM::VLD2b8wb_register: 2497 case ARM::VLD2b16wb_register: 2498 case ARM::VLD2b32wb_register: 2499 Inst.addOperand(MCOperand::createImm(0)); 2500 break; 2501 case ARM::VLD3d8_UPD: 2502 case ARM::VLD3d16_UPD: 2503 case ARM::VLD3d32_UPD: 2504 case ARM::VLD3q8_UPD: 2505 case ARM::VLD3q16_UPD: 2506 case ARM::VLD3q32_UPD: 2507 case ARM::VLD4d8_UPD: 2508 case ARM::VLD4d16_UPD: 2509 case ARM::VLD4d32_UPD: 2510 case ARM::VLD4q8_UPD: 2511 case ARM::VLD4q16_UPD: 2512 case ARM::VLD4q32_UPD: 2513 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2514 return MCDisassembler::Fail; 2515 break; 2516 default: 2517 break; 2518 } 2519 2520 // AddrMode6 Base (register+alignment) 2521 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2522 return MCDisassembler::Fail; 2523 2524 // AddrMode6 Offset (register) 2525 switch (Inst.getOpcode()) { 2526 default: 2527 // The below have been updated to have explicit am6offset split 2528 // between fixed and register offset. For those instructions not 2529 // yet updated, we need to add an additional reg0 operand for the 2530 // fixed variant. 2531 // 2532 // The fixed offset encodes as Rm == 0xd, so we check for that. 2533 if (Rm == 0xd) { 2534 Inst.addOperand(MCOperand::createReg(0)); 2535 break; 2536 } 2537 // Fall through to handle the register offset variant. 2538 LLVM_FALLTHROUGH; 2539 case ARM::VLD1d8wb_fixed: 2540 case ARM::VLD1d16wb_fixed: 2541 case ARM::VLD1d32wb_fixed: 2542 case ARM::VLD1d64wb_fixed: 2543 case ARM::VLD1d8Twb_fixed: 2544 case ARM::VLD1d16Twb_fixed: 2545 case ARM::VLD1d32Twb_fixed: 2546 case ARM::VLD1d64Twb_fixed: 2547 case ARM::VLD1d8Qwb_fixed: 2548 case ARM::VLD1d16Qwb_fixed: 2549 case ARM::VLD1d32Qwb_fixed: 2550 case ARM::VLD1d64Qwb_fixed: 2551 case ARM::VLD1d8wb_register: 2552 case ARM::VLD1d16wb_register: 2553 case ARM::VLD1d32wb_register: 2554 case ARM::VLD1d64wb_register: 2555 case ARM::VLD1q8wb_fixed: 2556 case ARM::VLD1q16wb_fixed: 2557 case ARM::VLD1q32wb_fixed: 2558 case ARM::VLD1q64wb_fixed: 2559 case ARM::VLD1q8wb_register: 2560 case ARM::VLD1q16wb_register: 2561 case ARM::VLD1q32wb_register: 2562 case ARM::VLD1q64wb_register: 2563 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2564 // variant encodes Rm == 0xf. Anything else is a register offset post- 2565 // increment and we need to add the register operand to the instruction. 2566 if (Rm != 0xD && Rm != 0xF && 2567 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2568 return MCDisassembler::Fail; 2569 break; 2570 case ARM::VLD2d8wb_fixed: 2571 case ARM::VLD2d16wb_fixed: 2572 case ARM::VLD2d32wb_fixed: 2573 case ARM::VLD2b8wb_fixed: 2574 case ARM::VLD2b16wb_fixed: 2575 case ARM::VLD2b32wb_fixed: 2576 case ARM::VLD2q8wb_fixed: 2577 case ARM::VLD2q16wb_fixed: 2578 case ARM::VLD2q32wb_fixed: 2579 break; 2580 } 2581 2582 return S; 2583 } 2584 2585 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2586 uint64_t Address, const void *Decoder) { 2587 unsigned type = fieldFromInstruction(Insn, 8, 4); 2588 unsigned align = fieldFromInstruction(Insn, 4, 2); 2589 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2590 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2591 if (type == 10 && align == 3) return MCDisassembler::Fail; 2592 2593 unsigned load = fieldFromInstruction(Insn, 21, 1); 2594 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2595 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2596 } 2597 2598 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2599 uint64_t Address, const void *Decoder) { 2600 unsigned size = fieldFromInstruction(Insn, 6, 2); 2601 if (size == 3) return MCDisassembler::Fail; 2602 2603 unsigned type = fieldFromInstruction(Insn, 8, 4); 2604 unsigned align = fieldFromInstruction(Insn, 4, 2); 2605 if (type == 8 && align == 3) return MCDisassembler::Fail; 2606 if (type == 9 && align == 3) return MCDisassembler::Fail; 2607 2608 unsigned load = fieldFromInstruction(Insn, 21, 1); 2609 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2610 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2611 } 2612 2613 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 2614 uint64_t Address, const void *Decoder) { 2615 unsigned size = fieldFromInstruction(Insn, 6, 2); 2616 if (size == 3) return MCDisassembler::Fail; 2617 2618 unsigned align = fieldFromInstruction(Insn, 4, 2); 2619 if (align & 2) return MCDisassembler::Fail; 2620 2621 unsigned load = fieldFromInstruction(Insn, 21, 1); 2622 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2623 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2624 } 2625 2626 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 2627 uint64_t Address, const void *Decoder) { 2628 unsigned size = fieldFromInstruction(Insn, 6, 2); 2629 if (size == 3) return MCDisassembler::Fail; 2630 2631 unsigned load = fieldFromInstruction(Insn, 21, 1); 2632 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2633 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2634 } 2635 2636 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2637 uint64_t Address, const void *Decoder) { 2638 DecodeStatus S = MCDisassembler::Success; 2639 2640 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2641 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2642 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2643 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2644 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2645 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2646 2647 // Writeback Operand 2648 switch (Inst.getOpcode()) { 2649 case ARM::VST1d8wb_fixed: 2650 case ARM::VST1d16wb_fixed: 2651 case ARM::VST1d32wb_fixed: 2652 case ARM::VST1d64wb_fixed: 2653 case ARM::VST1d8wb_register: 2654 case ARM::VST1d16wb_register: 2655 case ARM::VST1d32wb_register: 2656 case ARM::VST1d64wb_register: 2657 case ARM::VST1q8wb_fixed: 2658 case ARM::VST1q16wb_fixed: 2659 case ARM::VST1q32wb_fixed: 2660 case ARM::VST1q64wb_fixed: 2661 case ARM::VST1q8wb_register: 2662 case ARM::VST1q16wb_register: 2663 case ARM::VST1q32wb_register: 2664 case ARM::VST1q64wb_register: 2665 case ARM::VST1d8Twb_fixed: 2666 case ARM::VST1d16Twb_fixed: 2667 case ARM::VST1d32Twb_fixed: 2668 case ARM::VST1d64Twb_fixed: 2669 case ARM::VST1d8Twb_register: 2670 case ARM::VST1d16Twb_register: 2671 case ARM::VST1d32Twb_register: 2672 case ARM::VST1d64Twb_register: 2673 case ARM::VST1d8Qwb_fixed: 2674 case ARM::VST1d16Qwb_fixed: 2675 case ARM::VST1d32Qwb_fixed: 2676 case ARM::VST1d64Qwb_fixed: 2677 case ARM::VST1d8Qwb_register: 2678 case ARM::VST1d16Qwb_register: 2679 case ARM::VST1d32Qwb_register: 2680 case ARM::VST1d64Qwb_register: 2681 case ARM::VST2d8wb_fixed: 2682 case ARM::VST2d16wb_fixed: 2683 case ARM::VST2d32wb_fixed: 2684 case ARM::VST2d8wb_register: 2685 case ARM::VST2d16wb_register: 2686 case ARM::VST2d32wb_register: 2687 case ARM::VST2q8wb_fixed: 2688 case ARM::VST2q16wb_fixed: 2689 case ARM::VST2q32wb_fixed: 2690 case ARM::VST2q8wb_register: 2691 case ARM::VST2q16wb_register: 2692 case ARM::VST2q32wb_register: 2693 case ARM::VST2b8wb_fixed: 2694 case ARM::VST2b16wb_fixed: 2695 case ARM::VST2b32wb_fixed: 2696 case ARM::VST2b8wb_register: 2697 case ARM::VST2b16wb_register: 2698 case ARM::VST2b32wb_register: 2699 if (Rm == 0xF) 2700 return MCDisassembler::Fail; 2701 Inst.addOperand(MCOperand::createImm(0)); 2702 break; 2703 case ARM::VST3d8_UPD: 2704 case ARM::VST3d16_UPD: 2705 case ARM::VST3d32_UPD: 2706 case ARM::VST3q8_UPD: 2707 case ARM::VST3q16_UPD: 2708 case ARM::VST3q32_UPD: 2709 case ARM::VST4d8_UPD: 2710 case ARM::VST4d16_UPD: 2711 case ARM::VST4d32_UPD: 2712 case ARM::VST4q8_UPD: 2713 case ARM::VST4q16_UPD: 2714 case ARM::VST4q32_UPD: 2715 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2716 return MCDisassembler::Fail; 2717 break; 2718 default: 2719 break; 2720 } 2721 2722 // AddrMode6 Base (register+alignment) 2723 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2724 return MCDisassembler::Fail; 2725 2726 // AddrMode6 Offset (register) 2727 switch (Inst.getOpcode()) { 2728 default: 2729 if (Rm == 0xD) 2730 Inst.addOperand(MCOperand::createReg(0)); 2731 else if (Rm != 0xF) { 2732 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2733 return MCDisassembler::Fail; 2734 } 2735 break; 2736 case ARM::VST1d8wb_fixed: 2737 case ARM::VST1d16wb_fixed: 2738 case ARM::VST1d32wb_fixed: 2739 case ARM::VST1d64wb_fixed: 2740 case ARM::VST1q8wb_fixed: 2741 case ARM::VST1q16wb_fixed: 2742 case ARM::VST1q32wb_fixed: 2743 case ARM::VST1q64wb_fixed: 2744 case ARM::VST1d8Twb_fixed: 2745 case ARM::VST1d16Twb_fixed: 2746 case ARM::VST1d32Twb_fixed: 2747 case ARM::VST1d64Twb_fixed: 2748 case ARM::VST1d8Qwb_fixed: 2749 case ARM::VST1d16Qwb_fixed: 2750 case ARM::VST1d32Qwb_fixed: 2751 case ARM::VST1d64Qwb_fixed: 2752 case ARM::VST2d8wb_fixed: 2753 case ARM::VST2d16wb_fixed: 2754 case ARM::VST2d32wb_fixed: 2755 case ARM::VST2q8wb_fixed: 2756 case ARM::VST2q16wb_fixed: 2757 case ARM::VST2q32wb_fixed: 2758 case ARM::VST2b8wb_fixed: 2759 case ARM::VST2b16wb_fixed: 2760 case ARM::VST2b32wb_fixed: 2761 break; 2762 } 2763 2764 // First input register 2765 switch (Inst.getOpcode()) { 2766 case ARM::VST1q16: 2767 case ARM::VST1q32: 2768 case ARM::VST1q64: 2769 case ARM::VST1q8: 2770 case ARM::VST1q16wb_fixed: 2771 case ARM::VST1q16wb_register: 2772 case ARM::VST1q32wb_fixed: 2773 case ARM::VST1q32wb_register: 2774 case ARM::VST1q64wb_fixed: 2775 case ARM::VST1q64wb_register: 2776 case ARM::VST1q8wb_fixed: 2777 case ARM::VST1q8wb_register: 2778 case ARM::VST2d16: 2779 case ARM::VST2d32: 2780 case ARM::VST2d8: 2781 case ARM::VST2d16wb_fixed: 2782 case ARM::VST2d16wb_register: 2783 case ARM::VST2d32wb_fixed: 2784 case ARM::VST2d32wb_register: 2785 case ARM::VST2d8wb_fixed: 2786 case ARM::VST2d8wb_register: 2787 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2788 return MCDisassembler::Fail; 2789 break; 2790 case ARM::VST2b16: 2791 case ARM::VST2b32: 2792 case ARM::VST2b8: 2793 case ARM::VST2b16wb_fixed: 2794 case ARM::VST2b16wb_register: 2795 case ARM::VST2b32wb_fixed: 2796 case ARM::VST2b32wb_register: 2797 case ARM::VST2b8wb_fixed: 2798 case ARM::VST2b8wb_register: 2799 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2800 return MCDisassembler::Fail; 2801 break; 2802 default: 2803 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2804 return MCDisassembler::Fail; 2805 } 2806 2807 // Second input register 2808 switch (Inst.getOpcode()) { 2809 case ARM::VST3d8: 2810 case ARM::VST3d16: 2811 case ARM::VST3d32: 2812 case ARM::VST3d8_UPD: 2813 case ARM::VST3d16_UPD: 2814 case ARM::VST3d32_UPD: 2815 case ARM::VST4d8: 2816 case ARM::VST4d16: 2817 case ARM::VST4d32: 2818 case ARM::VST4d8_UPD: 2819 case ARM::VST4d16_UPD: 2820 case ARM::VST4d32_UPD: 2821 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2822 return MCDisassembler::Fail; 2823 break; 2824 case ARM::VST3q8: 2825 case ARM::VST3q16: 2826 case ARM::VST3q32: 2827 case ARM::VST3q8_UPD: 2828 case ARM::VST3q16_UPD: 2829 case ARM::VST3q32_UPD: 2830 case ARM::VST4q8: 2831 case ARM::VST4q16: 2832 case ARM::VST4q32: 2833 case ARM::VST4q8_UPD: 2834 case ARM::VST4q16_UPD: 2835 case ARM::VST4q32_UPD: 2836 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2837 return MCDisassembler::Fail; 2838 break; 2839 default: 2840 break; 2841 } 2842 2843 // Third input register 2844 switch (Inst.getOpcode()) { 2845 case ARM::VST3d8: 2846 case ARM::VST3d16: 2847 case ARM::VST3d32: 2848 case ARM::VST3d8_UPD: 2849 case ARM::VST3d16_UPD: 2850 case ARM::VST3d32_UPD: 2851 case ARM::VST4d8: 2852 case ARM::VST4d16: 2853 case ARM::VST4d32: 2854 case ARM::VST4d8_UPD: 2855 case ARM::VST4d16_UPD: 2856 case ARM::VST4d32_UPD: 2857 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2858 return MCDisassembler::Fail; 2859 break; 2860 case ARM::VST3q8: 2861 case ARM::VST3q16: 2862 case ARM::VST3q32: 2863 case ARM::VST3q8_UPD: 2864 case ARM::VST3q16_UPD: 2865 case ARM::VST3q32_UPD: 2866 case ARM::VST4q8: 2867 case ARM::VST4q16: 2868 case ARM::VST4q32: 2869 case ARM::VST4q8_UPD: 2870 case ARM::VST4q16_UPD: 2871 case ARM::VST4q32_UPD: 2872 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2873 return MCDisassembler::Fail; 2874 break; 2875 default: 2876 break; 2877 } 2878 2879 // Fourth input register 2880 switch (Inst.getOpcode()) { 2881 case ARM::VST4d8: 2882 case ARM::VST4d16: 2883 case ARM::VST4d32: 2884 case ARM::VST4d8_UPD: 2885 case ARM::VST4d16_UPD: 2886 case ARM::VST4d32_UPD: 2887 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2888 return MCDisassembler::Fail; 2889 break; 2890 case ARM::VST4q8: 2891 case ARM::VST4q16: 2892 case ARM::VST4q32: 2893 case ARM::VST4q8_UPD: 2894 case ARM::VST4q16_UPD: 2895 case ARM::VST4q32_UPD: 2896 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2897 return MCDisassembler::Fail; 2898 break; 2899 default: 2900 break; 2901 } 2902 2903 return S; 2904 } 2905 2906 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 2907 uint64_t Address, const void *Decoder) { 2908 DecodeStatus S = MCDisassembler::Success; 2909 2910 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2911 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2912 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2913 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2914 unsigned align = fieldFromInstruction(Insn, 4, 1); 2915 unsigned size = fieldFromInstruction(Insn, 6, 2); 2916 2917 if (size == 0 && align == 1) 2918 return MCDisassembler::Fail; 2919 align *= (1 << size); 2920 2921 switch (Inst.getOpcode()) { 2922 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2923 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2924 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2925 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2926 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2927 return MCDisassembler::Fail; 2928 break; 2929 default: 2930 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2931 return MCDisassembler::Fail; 2932 break; 2933 } 2934 if (Rm != 0xF) { 2935 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2936 return MCDisassembler::Fail; 2937 } 2938 2939 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2940 return MCDisassembler::Fail; 2941 Inst.addOperand(MCOperand::createImm(align)); 2942 2943 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2944 // variant encodes Rm == 0xf. Anything else is a register offset post- 2945 // increment and we need to add the register operand to the instruction. 2946 if (Rm != 0xD && Rm != 0xF && 2947 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2948 return MCDisassembler::Fail; 2949 2950 return S; 2951 } 2952 2953 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 2954 uint64_t Address, const void *Decoder) { 2955 DecodeStatus S = MCDisassembler::Success; 2956 2957 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2958 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2959 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2960 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2961 unsigned align = fieldFromInstruction(Insn, 4, 1); 2962 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 2963 align *= 2*size; 2964 2965 switch (Inst.getOpcode()) { 2966 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2967 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2968 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2969 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2970 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2971 return MCDisassembler::Fail; 2972 break; 2973 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 2974 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 2975 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 2976 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 2977 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2978 return MCDisassembler::Fail; 2979 break; 2980 default: 2981 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2982 return MCDisassembler::Fail; 2983 break; 2984 } 2985 2986 if (Rm != 0xF) 2987 Inst.addOperand(MCOperand::createImm(0)); 2988 2989 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2990 return MCDisassembler::Fail; 2991 Inst.addOperand(MCOperand::createImm(align)); 2992 2993 if (Rm != 0xD && Rm != 0xF) { 2994 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2995 return MCDisassembler::Fail; 2996 } 2997 2998 return S; 2999 } 3000 3001 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 3002 uint64_t Address, const void *Decoder) { 3003 DecodeStatus S = MCDisassembler::Success; 3004 3005 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3006 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3007 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3008 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3009 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3010 3011 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3012 return MCDisassembler::Fail; 3013 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3014 return MCDisassembler::Fail; 3015 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3016 return MCDisassembler::Fail; 3017 if (Rm != 0xF) { 3018 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3019 return MCDisassembler::Fail; 3020 } 3021 3022 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3023 return MCDisassembler::Fail; 3024 Inst.addOperand(MCOperand::createImm(0)); 3025 3026 if (Rm == 0xD) 3027 Inst.addOperand(MCOperand::createReg(0)); 3028 else if (Rm != 0xF) { 3029 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3030 return MCDisassembler::Fail; 3031 } 3032 3033 return S; 3034 } 3035 3036 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 3037 uint64_t Address, const void *Decoder) { 3038 DecodeStatus S = MCDisassembler::Success; 3039 3040 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3041 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3042 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3043 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3044 unsigned size = fieldFromInstruction(Insn, 6, 2); 3045 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3046 unsigned align = fieldFromInstruction(Insn, 4, 1); 3047 3048 if (size == 0x3) { 3049 if (align == 0) 3050 return MCDisassembler::Fail; 3051 align = 16; 3052 } else { 3053 if (size == 2) { 3054 align *= 8; 3055 } else { 3056 size = 1 << size; 3057 align *= 4*size; 3058 } 3059 } 3060 3061 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3062 return MCDisassembler::Fail; 3063 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3064 return MCDisassembler::Fail; 3065 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3066 return MCDisassembler::Fail; 3067 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3068 return MCDisassembler::Fail; 3069 if (Rm != 0xF) { 3070 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3071 return MCDisassembler::Fail; 3072 } 3073 3074 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3075 return MCDisassembler::Fail; 3076 Inst.addOperand(MCOperand::createImm(align)); 3077 3078 if (Rm == 0xD) 3079 Inst.addOperand(MCOperand::createReg(0)); 3080 else if (Rm != 0xF) { 3081 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3082 return MCDisassembler::Fail; 3083 } 3084 3085 return S; 3086 } 3087 3088 static DecodeStatus 3089 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 3090 uint64_t Address, const void *Decoder) { 3091 DecodeStatus S = MCDisassembler::Success; 3092 3093 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3094 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3095 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3096 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3097 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3098 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3099 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3100 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3101 3102 if (Q) { 3103 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3104 return MCDisassembler::Fail; 3105 } else { 3106 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3107 return MCDisassembler::Fail; 3108 } 3109 3110 Inst.addOperand(MCOperand::createImm(imm)); 3111 3112 switch (Inst.getOpcode()) { 3113 case ARM::VORRiv4i16: 3114 case ARM::VORRiv2i32: 3115 case ARM::VBICiv4i16: 3116 case ARM::VBICiv2i32: 3117 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3118 return MCDisassembler::Fail; 3119 break; 3120 case ARM::VORRiv8i16: 3121 case ARM::VORRiv4i32: 3122 case ARM::VBICiv8i16: 3123 case ARM::VBICiv4i32: 3124 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3125 return MCDisassembler::Fail; 3126 break; 3127 default: 3128 break; 3129 } 3130 3131 return S; 3132 } 3133 3134 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3135 uint64_t Address, const void *Decoder) { 3136 DecodeStatus S = MCDisassembler::Success; 3137 3138 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3139 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3140 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3141 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3142 unsigned size = fieldFromInstruction(Insn, 18, 2); 3143 3144 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3145 return MCDisassembler::Fail; 3146 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3147 return MCDisassembler::Fail; 3148 Inst.addOperand(MCOperand::createImm(8 << size)); 3149 3150 return S; 3151 } 3152 3153 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3154 uint64_t Address, const void *Decoder) { 3155 Inst.addOperand(MCOperand::createImm(8 - Val)); 3156 return MCDisassembler::Success; 3157 } 3158 3159 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3160 uint64_t Address, const void *Decoder) { 3161 Inst.addOperand(MCOperand::createImm(16 - Val)); 3162 return MCDisassembler::Success; 3163 } 3164 3165 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3166 uint64_t Address, const void *Decoder) { 3167 Inst.addOperand(MCOperand::createImm(32 - Val)); 3168 return MCDisassembler::Success; 3169 } 3170 3171 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3172 uint64_t Address, const void *Decoder) { 3173 Inst.addOperand(MCOperand::createImm(64 - Val)); 3174 return MCDisassembler::Success; 3175 } 3176 3177 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3178 uint64_t Address, const void *Decoder) { 3179 DecodeStatus S = MCDisassembler::Success; 3180 3181 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3182 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3183 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3184 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3185 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3186 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3187 unsigned op = fieldFromInstruction(Insn, 6, 1); 3188 3189 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3190 return MCDisassembler::Fail; 3191 if (op) { 3192 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3193 return MCDisassembler::Fail; // Writeback 3194 } 3195 3196 switch (Inst.getOpcode()) { 3197 case ARM::VTBL2: 3198 case ARM::VTBX2: 3199 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3200 return MCDisassembler::Fail; 3201 break; 3202 default: 3203 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3204 return MCDisassembler::Fail; 3205 } 3206 3207 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3208 return MCDisassembler::Fail; 3209 3210 return S; 3211 } 3212 3213 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3214 uint64_t Address, const void *Decoder) { 3215 DecodeStatus S = MCDisassembler::Success; 3216 3217 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3218 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3219 3220 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3221 return MCDisassembler::Fail; 3222 3223 switch(Inst.getOpcode()) { 3224 default: 3225 return MCDisassembler::Fail; 3226 case ARM::tADR: 3227 break; // tADR does not explicitly represent the PC as an operand. 3228 case ARM::tADDrSPi: 3229 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3230 break; 3231 } 3232 3233 Inst.addOperand(MCOperand::createImm(imm)); 3234 return S; 3235 } 3236 3237 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3238 uint64_t Address, const void *Decoder) { 3239 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3240 true, 2, Inst, Decoder)) 3241 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); 3242 return MCDisassembler::Success; 3243 } 3244 3245 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3246 uint64_t Address, const void *Decoder) { 3247 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3248 true, 4, Inst, Decoder)) 3249 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); 3250 return MCDisassembler::Success; 3251 } 3252 3253 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3254 uint64_t Address, const void *Decoder) { 3255 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3256 true, 2, Inst, Decoder)) 3257 Inst.addOperand(MCOperand::createImm(Val << 1)); 3258 return MCDisassembler::Success; 3259 } 3260 3261 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3262 uint64_t Address, const void *Decoder) { 3263 DecodeStatus S = MCDisassembler::Success; 3264 3265 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3266 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3267 3268 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3269 return MCDisassembler::Fail; 3270 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3271 return MCDisassembler::Fail; 3272 3273 return S; 3274 } 3275 3276 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3277 uint64_t Address, const void *Decoder) { 3278 DecodeStatus S = MCDisassembler::Success; 3279 3280 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3281 unsigned imm = fieldFromInstruction(Val, 3, 5); 3282 3283 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3284 return MCDisassembler::Fail; 3285 Inst.addOperand(MCOperand::createImm(imm)); 3286 3287 return S; 3288 } 3289 3290 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3291 uint64_t Address, const void *Decoder) { 3292 unsigned imm = Val << 2; 3293 3294 Inst.addOperand(MCOperand::createImm(imm)); 3295 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3296 3297 return MCDisassembler::Success; 3298 } 3299 3300 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3301 uint64_t Address, const void *Decoder) { 3302 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3303 Inst.addOperand(MCOperand::createImm(Val)); 3304 3305 return MCDisassembler::Success; 3306 } 3307 3308 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3309 uint64_t Address, const void *Decoder) { 3310 DecodeStatus S = MCDisassembler::Success; 3311 3312 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3313 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3314 unsigned imm = fieldFromInstruction(Val, 0, 2); 3315 3316 // Thumb stores cannot use PC as dest register. 3317 switch (Inst.getOpcode()) { 3318 case ARM::t2STRHs: 3319 case ARM::t2STRBs: 3320 case ARM::t2STRs: 3321 if (Rn == 15) 3322 return MCDisassembler::Fail; 3323 default: 3324 break; 3325 } 3326 3327 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3328 return MCDisassembler::Fail; 3329 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3330 return MCDisassembler::Fail; 3331 Inst.addOperand(MCOperand::createImm(imm)); 3332 3333 return S; 3334 } 3335 3336 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3337 uint64_t Address, const void *Decoder) { 3338 DecodeStatus S = MCDisassembler::Success; 3339 3340 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3341 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3342 3343 const FeatureBitset &featureBits = 3344 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3345 3346 bool hasMP = featureBits[ARM::FeatureMP]; 3347 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3348 3349 if (Rn == 15) { 3350 switch (Inst.getOpcode()) { 3351 case ARM::t2LDRBs: 3352 Inst.setOpcode(ARM::t2LDRBpci); 3353 break; 3354 case ARM::t2LDRHs: 3355 Inst.setOpcode(ARM::t2LDRHpci); 3356 break; 3357 case ARM::t2LDRSHs: 3358 Inst.setOpcode(ARM::t2LDRSHpci); 3359 break; 3360 case ARM::t2LDRSBs: 3361 Inst.setOpcode(ARM::t2LDRSBpci); 3362 break; 3363 case ARM::t2LDRs: 3364 Inst.setOpcode(ARM::t2LDRpci); 3365 break; 3366 case ARM::t2PLDs: 3367 Inst.setOpcode(ARM::t2PLDpci); 3368 break; 3369 case ARM::t2PLIs: 3370 Inst.setOpcode(ARM::t2PLIpci); 3371 break; 3372 default: 3373 return MCDisassembler::Fail; 3374 } 3375 3376 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3377 } 3378 3379 if (Rt == 15) { 3380 switch (Inst.getOpcode()) { 3381 case ARM::t2LDRSHs: 3382 return MCDisassembler::Fail; 3383 case ARM::t2LDRHs: 3384 Inst.setOpcode(ARM::t2PLDWs); 3385 break; 3386 case ARM::t2LDRSBs: 3387 Inst.setOpcode(ARM::t2PLIs); 3388 default: 3389 break; 3390 } 3391 } 3392 3393 switch (Inst.getOpcode()) { 3394 case ARM::t2PLDs: 3395 break; 3396 case ARM::t2PLIs: 3397 if (!hasV7Ops) 3398 return MCDisassembler::Fail; 3399 break; 3400 case ARM::t2PLDWs: 3401 if (!hasV7Ops || !hasMP) 3402 return MCDisassembler::Fail; 3403 break; 3404 default: 3405 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3406 return MCDisassembler::Fail; 3407 } 3408 3409 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3410 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3411 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3412 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3413 return MCDisassembler::Fail; 3414 3415 return S; 3416 } 3417 3418 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3419 uint64_t Address, const void* Decoder) { 3420 DecodeStatus S = MCDisassembler::Success; 3421 3422 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3423 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3424 unsigned U = fieldFromInstruction(Insn, 9, 1); 3425 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3426 imm |= (U << 8); 3427 imm |= (Rn << 9); 3428 unsigned add = fieldFromInstruction(Insn, 9, 1); 3429 3430 const FeatureBitset &featureBits = 3431 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3432 3433 bool hasMP = featureBits[ARM::FeatureMP]; 3434 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3435 3436 if (Rn == 15) { 3437 switch (Inst.getOpcode()) { 3438 case ARM::t2LDRi8: 3439 Inst.setOpcode(ARM::t2LDRpci); 3440 break; 3441 case ARM::t2LDRBi8: 3442 Inst.setOpcode(ARM::t2LDRBpci); 3443 break; 3444 case ARM::t2LDRSBi8: 3445 Inst.setOpcode(ARM::t2LDRSBpci); 3446 break; 3447 case ARM::t2LDRHi8: 3448 Inst.setOpcode(ARM::t2LDRHpci); 3449 break; 3450 case ARM::t2LDRSHi8: 3451 Inst.setOpcode(ARM::t2LDRSHpci); 3452 break; 3453 case ARM::t2PLDi8: 3454 Inst.setOpcode(ARM::t2PLDpci); 3455 break; 3456 case ARM::t2PLIi8: 3457 Inst.setOpcode(ARM::t2PLIpci); 3458 break; 3459 default: 3460 return MCDisassembler::Fail; 3461 } 3462 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3463 } 3464 3465 if (Rt == 15) { 3466 switch (Inst.getOpcode()) { 3467 case ARM::t2LDRSHi8: 3468 return MCDisassembler::Fail; 3469 case ARM::t2LDRHi8: 3470 if (!add) 3471 Inst.setOpcode(ARM::t2PLDWi8); 3472 break; 3473 case ARM::t2LDRSBi8: 3474 Inst.setOpcode(ARM::t2PLIi8); 3475 break; 3476 default: 3477 break; 3478 } 3479 } 3480 3481 switch (Inst.getOpcode()) { 3482 case ARM::t2PLDi8: 3483 break; 3484 case ARM::t2PLIi8: 3485 if (!hasV7Ops) 3486 return MCDisassembler::Fail; 3487 break; 3488 case ARM::t2PLDWi8: 3489 if (!hasV7Ops || !hasMP) 3490 return MCDisassembler::Fail; 3491 break; 3492 default: 3493 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3494 return MCDisassembler::Fail; 3495 } 3496 3497 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3498 return MCDisassembler::Fail; 3499 return S; 3500 } 3501 3502 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3503 uint64_t Address, const void* Decoder) { 3504 DecodeStatus S = MCDisassembler::Success; 3505 3506 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3507 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3508 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3509 imm |= (Rn << 13); 3510 3511 const FeatureBitset &featureBits = 3512 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3513 3514 bool hasMP = featureBits[ARM::FeatureMP]; 3515 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3516 3517 if (Rn == 15) { 3518 switch (Inst.getOpcode()) { 3519 case ARM::t2LDRi12: 3520 Inst.setOpcode(ARM::t2LDRpci); 3521 break; 3522 case ARM::t2LDRHi12: 3523 Inst.setOpcode(ARM::t2LDRHpci); 3524 break; 3525 case ARM::t2LDRSHi12: 3526 Inst.setOpcode(ARM::t2LDRSHpci); 3527 break; 3528 case ARM::t2LDRBi12: 3529 Inst.setOpcode(ARM::t2LDRBpci); 3530 break; 3531 case ARM::t2LDRSBi12: 3532 Inst.setOpcode(ARM::t2LDRSBpci); 3533 break; 3534 case ARM::t2PLDi12: 3535 Inst.setOpcode(ARM::t2PLDpci); 3536 break; 3537 case ARM::t2PLIi12: 3538 Inst.setOpcode(ARM::t2PLIpci); 3539 break; 3540 default: 3541 return MCDisassembler::Fail; 3542 } 3543 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3544 } 3545 3546 if (Rt == 15) { 3547 switch (Inst.getOpcode()) { 3548 case ARM::t2LDRSHi12: 3549 return MCDisassembler::Fail; 3550 case ARM::t2LDRHi12: 3551 Inst.setOpcode(ARM::t2PLDWi12); 3552 break; 3553 case ARM::t2LDRSBi12: 3554 Inst.setOpcode(ARM::t2PLIi12); 3555 break; 3556 default: 3557 break; 3558 } 3559 } 3560 3561 switch (Inst.getOpcode()) { 3562 case ARM::t2PLDi12: 3563 break; 3564 case ARM::t2PLIi12: 3565 if (!hasV7Ops) 3566 return MCDisassembler::Fail; 3567 break; 3568 case ARM::t2PLDWi12: 3569 if (!hasV7Ops || !hasMP) 3570 return MCDisassembler::Fail; 3571 break; 3572 default: 3573 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3574 return MCDisassembler::Fail; 3575 } 3576 3577 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 3578 return MCDisassembler::Fail; 3579 return S; 3580 } 3581 3582 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 3583 uint64_t Address, const void* Decoder) { 3584 DecodeStatus S = MCDisassembler::Success; 3585 3586 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3587 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3588 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3589 imm |= (Rn << 9); 3590 3591 if (Rn == 15) { 3592 switch (Inst.getOpcode()) { 3593 case ARM::t2LDRT: 3594 Inst.setOpcode(ARM::t2LDRpci); 3595 break; 3596 case ARM::t2LDRBT: 3597 Inst.setOpcode(ARM::t2LDRBpci); 3598 break; 3599 case ARM::t2LDRHT: 3600 Inst.setOpcode(ARM::t2LDRHpci); 3601 break; 3602 case ARM::t2LDRSBT: 3603 Inst.setOpcode(ARM::t2LDRSBpci); 3604 break; 3605 case ARM::t2LDRSHT: 3606 Inst.setOpcode(ARM::t2LDRSHpci); 3607 break; 3608 default: 3609 return MCDisassembler::Fail; 3610 } 3611 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3612 } 3613 3614 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3615 return MCDisassembler::Fail; 3616 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3617 return MCDisassembler::Fail; 3618 return S; 3619 } 3620 3621 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 3622 uint64_t Address, const void* Decoder) { 3623 DecodeStatus S = MCDisassembler::Success; 3624 3625 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3626 unsigned U = fieldFromInstruction(Insn, 23, 1); 3627 int imm = fieldFromInstruction(Insn, 0, 12); 3628 3629 const FeatureBitset &featureBits = 3630 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3631 3632 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3633 3634 if (Rt == 15) { 3635 switch (Inst.getOpcode()) { 3636 case ARM::t2LDRBpci: 3637 case ARM::t2LDRHpci: 3638 Inst.setOpcode(ARM::t2PLDpci); 3639 break; 3640 case ARM::t2LDRSBpci: 3641 Inst.setOpcode(ARM::t2PLIpci); 3642 break; 3643 case ARM::t2LDRSHpci: 3644 return MCDisassembler::Fail; 3645 default: 3646 break; 3647 } 3648 } 3649 3650 switch(Inst.getOpcode()) { 3651 case ARM::t2PLDpci: 3652 break; 3653 case ARM::t2PLIpci: 3654 if (!hasV7Ops) 3655 return MCDisassembler::Fail; 3656 break; 3657 default: 3658 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3659 return MCDisassembler::Fail; 3660 } 3661 3662 if (!U) { 3663 // Special case for #-0. 3664 if (imm == 0) 3665 imm = INT32_MIN; 3666 else 3667 imm = -imm; 3668 } 3669 Inst.addOperand(MCOperand::createImm(imm)); 3670 3671 return S; 3672 } 3673 3674 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3675 uint64_t Address, const void *Decoder) { 3676 if (Val == 0) 3677 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 3678 else { 3679 int imm = Val & 0xFF; 3680 3681 if (!(Val & 0x100)) imm *= -1; 3682 Inst.addOperand(MCOperand::createImm(imm * 4)); 3683 } 3684 3685 return MCDisassembler::Success; 3686 } 3687 3688 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3689 uint64_t Address, const void *Decoder) { 3690 DecodeStatus S = MCDisassembler::Success; 3691 3692 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3693 unsigned imm = fieldFromInstruction(Val, 0, 9); 3694 3695 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3696 return MCDisassembler::Fail; 3697 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3698 return MCDisassembler::Fail; 3699 3700 return S; 3701 } 3702 3703 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3704 uint64_t Address, const void *Decoder) { 3705 DecodeStatus S = MCDisassembler::Success; 3706 3707 unsigned Rn = fieldFromInstruction(Val, 8, 4); 3708 unsigned imm = fieldFromInstruction(Val, 0, 8); 3709 3710 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3711 return MCDisassembler::Fail; 3712 3713 Inst.addOperand(MCOperand::createImm(imm)); 3714 3715 return S; 3716 } 3717 3718 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3719 uint64_t Address, const void *Decoder) { 3720 int imm = Val & 0xFF; 3721 if (Val == 0) 3722 imm = INT32_MIN; 3723 else if (!(Val & 0x100)) 3724 imm *= -1; 3725 Inst.addOperand(MCOperand::createImm(imm)); 3726 3727 return MCDisassembler::Success; 3728 } 3729 3730 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3731 uint64_t Address, const void *Decoder) { 3732 DecodeStatus S = MCDisassembler::Success; 3733 3734 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3735 unsigned imm = fieldFromInstruction(Val, 0, 9); 3736 3737 // Thumb stores cannot use PC as dest register. 3738 switch (Inst.getOpcode()) { 3739 case ARM::t2STRT: 3740 case ARM::t2STRBT: 3741 case ARM::t2STRHT: 3742 case ARM::t2STRi8: 3743 case ARM::t2STRHi8: 3744 case ARM::t2STRBi8: 3745 if (Rn == 15) 3746 return MCDisassembler::Fail; 3747 break; 3748 default: 3749 break; 3750 } 3751 3752 // Some instructions always use an additive offset. 3753 switch (Inst.getOpcode()) { 3754 case ARM::t2LDRT: 3755 case ARM::t2LDRBT: 3756 case ARM::t2LDRHT: 3757 case ARM::t2LDRSBT: 3758 case ARM::t2LDRSHT: 3759 case ARM::t2STRT: 3760 case ARM::t2STRBT: 3761 case ARM::t2STRHT: 3762 imm |= 0x100; 3763 break; 3764 default: 3765 break; 3766 } 3767 3768 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3769 return MCDisassembler::Fail; 3770 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3771 return MCDisassembler::Fail; 3772 3773 return S; 3774 } 3775 3776 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3777 uint64_t Address, const void *Decoder) { 3778 DecodeStatus S = MCDisassembler::Success; 3779 3780 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3781 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3782 unsigned addr = fieldFromInstruction(Insn, 0, 8); 3783 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 3784 addr |= Rn << 9; 3785 unsigned load = fieldFromInstruction(Insn, 20, 1); 3786 3787 if (Rn == 15) { 3788 switch (Inst.getOpcode()) { 3789 case ARM::t2LDR_PRE: 3790 case ARM::t2LDR_POST: 3791 Inst.setOpcode(ARM::t2LDRpci); 3792 break; 3793 case ARM::t2LDRB_PRE: 3794 case ARM::t2LDRB_POST: 3795 Inst.setOpcode(ARM::t2LDRBpci); 3796 break; 3797 case ARM::t2LDRH_PRE: 3798 case ARM::t2LDRH_POST: 3799 Inst.setOpcode(ARM::t2LDRHpci); 3800 break; 3801 case ARM::t2LDRSB_PRE: 3802 case ARM::t2LDRSB_POST: 3803 if (Rt == 15) 3804 Inst.setOpcode(ARM::t2PLIpci); 3805 else 3806 Inst.setOpcode(ARM::t2LDRSBpci); 3807 break; 3808 case ARM::t2LDRSH_PRE: 3809 case ARM::t2LDRSH_POST: 3810 Inst.setOpcode(ARM::t2LDRSHpci); 3811 break; 3812 default: 3813 return MCDisassembler::Fail; 3814 } 3815 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3816 } 3817 3818 if (!load) { 3819 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3820 return MCDisassembler::Fail; 3821 } 3822 3823 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3824 return MCDisassembler::Fail; 3825 3826 if (load) { 3827 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3828 return MCDisassembler::Fail; 3829 } 3830 3831 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3832 return MCDisassembler::Fail; 3833 3834 return S; 3835 } 3836 3837 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 3838 uint64_t Address, const void *Decoder) { 3839 DecodeStatus S = MCDisassembler::Success; 3840 3841 unsigned Rn = fieldFromInstruction(Val, 13, 4); 3842 unsigned imm = fieldFromInstruction(Val, 0, 12); 3843 3844 // Thumb stores cannot use PC as dest register. 3845 switch (Inst.getOpcode()) { 3846 case ARM::t2STRi12: 3847 case ARM::t2STRBi12: 3848 case ARM::t2STRHi12: 3849 if (Rn == 15) 3850 return MCDisassembler::Fail; 3851 default: 3852 break; 3853 } 3854 3855 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3856 return MCDisassembler::Fail; 3857 Inst.addOperand(MCOperand::createImm(imm)); 3858 3859 return S; 3860 } 3861 3862 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 3863 uint64_t Address, const void *Decoder) { 3864 unsigned imm = fieldFromInstruction(Insn, 0, 7); 3865 3866 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3867 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3868 Inst.addOperand(MCOperand::createImm(imm)); 3869 3870 return MCDisassembler::Success; 3871 } 3872 3873 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 3874 uint64_t Address, const void *Decoder) { 3875 DecodeStatus S = MCDisassembler::Success; 3876 3877 if (Inst.getOpcode() == ARM::tADDrSP) { 3878 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 3879 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 3880 3881 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3882 return MCDisassembler::Fail; 3883 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3884 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3885 return MCDisassembler::Fail; 3886 } else if (Inst.getOpcode() == ARM::tADDspr) { 3887 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 3888 3889 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3890 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3891 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3892 return MCDisassembler::Fail; 3893 } 3894 3895 return S; 3896 } 3897 3898 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 3899 uint64_t Address, const void *Decoder) { 3900 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 3901 unsigned flags = fieldFromInstruction(Insn, 0, 3); 3902 3903 Inst.addOperand(MCOperand::createImm(imod)); 3904 Inst.addOperand(MCOperand::createImm(flags)); 3905 3906 return MCDisassembler::Success; 3907 } 3908 3909 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 3910 uint64_t Address, const void *Decoder) { 3911 DecodeStatus S = MCDisassembler::Success; 3912 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3913 unsigned add = fieldFromInstruction(Insn, 4, 1); 3914 3915 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3916 return MCDisassembler::Fail; 3917 Inst.addOperand(MCOperand::createImm(add)); 3918 3919 return S; 3920 } 3921 3922 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 3923 uint64_t Address, const void *Decoder) { 3924 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 3925 // Note only one trailing zero not two. Also the J1 and J2 values are from 3926 // the encoded instruction. So here change to I1 and I2 values via: 3927 // I1 = NOT(J1 EOR S); 3928 // I2 = NOT(J2 EOR S); 3929 // and build the imm32 with two trailing zeros as documented: 3930 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 3931 unsigned S = (Val >> 23) & 1; 3932 unsigned J1 = (Val >> 22) & 1; 3933 unsigned J2 = (Val >> 21) & 1; 3934 unsigned I1 = !(J1 ^ S); 3935 unsigned I2 = !(J2 ^ S); 3936 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3937 int imm32 = SignExtend32<25>(tmp << 1); 3938 3939 if (!tryAddingSymbolicOperand(Address, 3940 (Address & ~2u) + imm32 + 4, 3941 true, 4, Inst, Decoder)) 3942 Inst.addOperand(MCOperand::createImm(imm32)); 3943 return MCDisassembler::Success; 3944 } 3945 3946 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 3947 uint64_t Address, const void *Decoder) { 3948 if (Val == 0xA || Val == 0xB) 3949 return MCDisassembler::Fail; 3950 3951 const FeatureBitset &featureBits = 3952 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3953 3954 if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15)) 3955 return MCDisassembler::Fail; 3956 3957 Inst.addOperand(MCOperand::createImm(Val)); 3958 return MCDisassembler::Success; 3959 } 3960 3961 static DecodeStatus 3962 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 3963 uint64_t Address, const void *Decoder) { 3964 DecodeStatus S = MCDisassembler::Success; 3965 3966 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3967 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3968 3969 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3970 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3971 return MCDisassembler::Fail; 3972 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3973 return MCDisassembler::Fail; 3974 return S; 3975 } 3976 3977 static DecodeStatus 3978 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 3979 uint64_t Address, const void *Decoder) { 3980 DecodeStatus S = MCDisassembler::Success; 3981 3982 unsigned pred = fieldFromInstruction(Insn, 22, 4); 3983 if (pred == 0xE || pred == 0xF) { 3984 unsigned opc = fieldFromInstruction(Insn, 4, 28); 3985 switch (opc) { 3986 default: 3987 return MCDisassembler::Fail; 3988 case 0xf3bf8f4: 3989 Inst.setOpcode(ARM::t2DSB); 3990 break; 3991 case 0xf3bf8f5: 3992 Inst.setOpcode(ARM::t2DMB); 3993 break; 3994 case 0xf3bf8f6: 3995 Inst.setOpcode(ARM::t2ISB); 3996 break; 3997 } 3998 3999 unsigned imm = fieldFromInstruction(Insn, 0, 4); 4000 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 4001 } 4002 4003 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 4004 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 4005 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 4006 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 4007 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 4008 4009 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 4010 return MCDisassembler::Fail; 4011 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4012 return MCDisassembler::Fail; 4013 4014 return S; 4015 } 4016 4017 // Decode a shifted immediate operand. These basically consist 4018 // of an 8-bit value, and a 4-bit directive that specifies either 4019 // a splat operation or a rotation. 4020 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 4021 uint64_t Address, const void *Decoder) { 4022 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 4023 if (ctrl == 0) { 4024 unsigned byte = fieldFromInstruction(Val, 8, 2); 4025 unsigned imm = fieldFromInstruction(Val, 0, 8); 4026 switch (byte) { 4027 case 0: 4028 Inst.addOperand(MCOperand::createImm(imm)); 4029 break; 4030 case 1: 4031 Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); 4032 break; 4033 case 2: 4034 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); 4035 break; 4036 case 3: 4037 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | 4038 (imm << 8) | imm)); 4039 break; 4040 } 4041 } else { 4042 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 4043 unsigned rot = fieldFromInstruction(Val, 7, 5); 4044 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 4045 Inst.addOperand(MCOperand::createImm(imm)); 4046 } 4047 4048 return MCDisassembler::Success; 4049 } 4050 4051 static DecodeStatus 4052 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 4053 uint64_t Address, const void *Decoder) { 4054 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 4055 true, 2, Inst, Decoder)) 4056 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); 4057 return MCDisassembler::Success; 4058 } 4059 4060 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 4061 uint64_t Address, 4062 const void *Decoder) { 4063 // Val is passed in as S:J1:J2:imm10:imm11 4064 // Note no trailing zero after imm11. Also the J1 and J2 values are from 4065 // the encoded instruction. So here change to I1 and I2 values via: 4066 // I1 = NOT(J1 EOR S); 4067 // I2 = NOT(J2 EOR S); 4068 // and build the imm32 with one trailing zero as documented: 4069 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4070 unsigned S = (Val >> 23) & 1; 4071 unsigned J1 = (Val >> 22) & 1; 4072 unsigned J2 = (Val >> 21) & 1; 4073 unsigned I1 = !(J1 ^ S); 4074 unsigned I2 = !(J2 ^ S); 4075 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4076 int imm32 = SignExtend32<25>(tmp << 1); 4077 4078 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4079 true, 4, Inst, Decoder)) 4080 Inst.addOperand(MCOperand::createImm(imm32)); 4081 return MCDisassembler::Success; 4082 } 4083 4084 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4085 uint64_t Address, const void *Decoder) { 4086 if (Val & ~0xf) 4087 return MCDisassembler::Fail; 4088 4089 Inst.addOperand(MCOperand::createImm(Val)); 4090 return MCDisassembler::Success; 4091 } 4092 4093 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4094 uint64_t Address, const void *Decoder) { 4095 if (Val & ~0xf) 4096 return MCDisassembler::Fail; 4097 4098 Inst.addOperand(MCOperand::createImm(Val)); 4099 return MCDisassembler::Success; 4100 } 4101 4102 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 4103 uint64_t Address, const void *Decoder) { 4104 DecodeStatus S = MCDisassembler::Success; 4105 const FeatureBitset &FeatureBits = 4106 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4107 4108 if (FeatureBits[ARM::FeatureMClass]) { 4109 unsigned ValLow = Val & 0xff; 4110 4111 // Validate the SYSm value first. 4112 switch (ValLow) { 4113 case 0: // apsr 4114 case 1: // iapsr 4115 case 2: // eapsr 4116 case 3: // xpsr 4117 case 5: // ipsr 4118 case 6: // epsr 4119 case 7: // iepsr 4120 case 8: // msp 4121 case 9: // psp 4122 case 16: // primask 4123 case 20: // control 4124 break; 4125 case 17: // basepri 4126 case 18: // basepri_max 4127 case 19: // faultmask 4128 if (!(FeatureBits[ARM::HasV7Ops])) 4129 // Values basepri, basepri_max and faultmask are only valid for v7m. 4130 return MCDisassembler::Fail; 4131 break; 4132 case 0x8a: // msplim_ns 4133 case 0x8b: // psplim_ns 4134 case 0x91: // basepri_ns 4135 case 0x92: // basepri_max_ns 4136 case 0x93: // faultmask_ns 4137 if (!(FeatureBits[ARM::HasV8MMainlineOps])) 4138 return MCDisassembler::Fail; 4139 LLVM_FALLTHROUGH; 4140 case 10: // msplim 4141 case 11: // psplim 4142 case 0x88: // msp_ns 4143 case 0x89: // psp_ns 4144 case 0x90: // primask_ns 4145 case 0x94: // control_ns 4146 case 0x98: // sp_ns 4147 if (!(FeatureBits[ARM::Feature8MSecExt])) 4148 return MCDisassembler::Fail; 4149 break; 4150 default: 4151 return MCDisassembler::Fail; 4152 } 4153 4154 if (Inst.getOpcode() == ARM::t2MSR_M) { 4155 unsigned Mask = fieldFromInstruction(Val, 10, 2); 4156 if (!(FeatureBits[ARM::HasV7Ops])) { 4157 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 4158 // unpredictable. 4159 if (Mask != 2) 4160 S = MCDisassembler::SoftFail; 4161 } 4162 else { 4163 // The ARMv7-M architecture stores an additional 2-bit mask value in 4164 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 4165 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 4166 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 4167 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 4168 // only if the processor includes the DSP extension. 4169 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 4170 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) 4171 S = MCDisassembler::SoftFail; 4172 } 4173 } 4174 } else { 4175 // A/R class 4176 if (Val == 0) 4177 return MCDisassembler::Fail; 4178 } 4179 Inst.addOperand(MCOperand::createImm(Val)); 4180 return S; 4181 } 4182 4183 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 4184 uint64_t Address, const void *Decoder) { 4185 unsigned R = fieldFromInstruction(Val, 5, 1); 4186 unsigned SysM = fieldFromInstruction(Val, 0, 5); 4187 4188 // The table of encodings for these banked registers comes from B9.2.3 of the 4189 // ARM ARM. There are patterns, but nothing regular enough to make this logic 4190 // neater. So by fiat, these values are UNPREDICTABLE: 4191 if (!R) { 4192 if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 || 4193 SysM == 0x1a || SysM == 0x1b) 4194 return MCDisassembler::SoftFail; 4195 } else { 4196 if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 && 4197 SysM != 0x16 && SysM != 0x1c && SysM != 0x1e) 4198 return MCDisassembler::SoftFail; 4199 } 4200 4201 Inst.addOperand(MCOperand::createImm(Val)); 4202 return MCDisassembler::Success; 4203 } 4204 4205 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 4206 uint64_t Address, const void *Decoder) { 4207 DecodeStatus S = MCDisassembler::Success; 4208 4209 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4210 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4211 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4212 4213 if (Rn == 0xF) 4214 S = MCDisassembler::SoftFail; 4215 4216 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4217 return MCDisassembler::Fail; 4218 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4219 return MCDisassembler::Fail; 4220 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4221 return MCDisassembler::Fail; 4222 4223 return S; 4224 } 4225 4226 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 4227 uint64_t Address, 4228 const void *Decoder) { 4229 DecodeStatus S = MCDisassembler::Success; 4230 4231 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4232 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 4233 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4234 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4235 4236 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 4237 return MCDisassembler::Fail; 4238 4239 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 4240 S = MCDisassembler::SoftFail; 4241 4242 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4243 return MCDisassembler::Fail; 4244 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4245 return MCDisassembler::Fail; 4246 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4247 return MCDisassembler::Fail; 4248 4249 return S; 4250 } 4251 4252 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 4253 uint64_t Address, const void *Decoder) { 4254 DecodeStatus S = MCDisassembler::Success; 4255 4256 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4257 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4258 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4259 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4260 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4261 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4262 4263 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4264 4265 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4266 return MCDisassembler::Fail; 4267 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4268 return MCDisassembler::Fail; 4269 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4270 return MCDisassembler::Fail; 4271 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4272 return MCDisassembler::Fail; 4273 4274 return S; 4275 } 4276 4277 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 4278 uint64_t Address, const void *Decoder) { 4279 DecodeStatus S = MCDisassembler::Success; 4280 4281 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4282 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4283 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4284 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4285 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4286 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4287 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4288 4289 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4290 if (Rm == 0xF) S = MCDisassembler::SoftFail; 4291 4292 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4293 return MCDisassembler::Fail; 4294 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4295 return MCDisassembler::Fail; 4296 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4297 return MCDisassembler::Fail; 4298 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4299 return MCDisassembler::Fail; 4300 4301 return S; 4302 } 4303 4304 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4305 uint64_t Address, const void *Decoder) { 4306 DecodeStatus S = MCDisassembler::Success; 4307 4308 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4309 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4310 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4311 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4312 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4313 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4314 4315 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4316 4317 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4318 return MCDisassembler::Fail; 4319 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4320 return MCDisassembler::Fail; 4321 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4322 return MCDisassembler::Fail; 4323 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4324 return MCDisassembler::Fail; 4325 4326 return S; 4327 } 4328 4329 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4330 uint64_t Address, const void *Decoder) { 4331 DecodeStatus S = MCDisassembler::Success; 4332 4333 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4334 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4335 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4336 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4337 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4338 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4339 4340 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4341 4342 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4343 return MCDisassembler::Fail; 4344 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4345 return MCDisassembler::Fail; 4346 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4347 return MCDisassembler::Fail; 4348 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4349 return MCDisassembler::Fail; 4350 4351 return S; 4352 } 4353 4354 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4355 uint64_t Address, const void *Decoder) { 4356 DecodeStatus S = MCDisassembler::Success; 4357 4358 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4359 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4360 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4361 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4362 unsigned size = fieldFromInstruction(Insn, 10, 2); 4363 4364 unsigned align = 0; 4365 unsigned index = 0; 4366 switch (size) { 4367 default: 4368 return MCDisassembler::Fail; 4369 case 0: 4370 if (fieldFromInstruction(Insn, 4, 1)) 4371 return MCDisassembler::Fail; // UNDEFINED 4372 index = fieldFromInstruction(Insn, 5, 3); 4373 break; 4374 case 1: 4375 if (fieldFromInstruction(Insn, 5, 1)) 4376 return MCDisassembler::Fail; // UNDEFINED 4377 index = fieldFromInstruction(Insn, 6, 2); 4378 if (fieldFromInstruction(Insn, 4, 1)) 4379 align = 2; 4380 break; 4381 case 2: 4382 if (fieldFromInstruction(Insn, 6, 1)) 4383 return MCDisassembler::Fail; // UNDEFINED 4384 index = fieldFromInstruction(Insn, 7, 1); 4385 4386 switch (fieldFromInstruction(Insn, 4, 2)) { 4387 case 0 : 4388 align = 0; break; 4389 case 3: 4390 align = 4; break; 4391 default: 4392 return MCDisassembler::Fail; 4393 } 4394 break; 4395 } 4396 4397 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4398 return MCDisassembler::Fail; 4399 if (Rm != 0xF) { // Writeback 4400 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4401 return MCDisassembler::Fail; 4402 } 4403 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4404 return MCDisassembler::Fail; 4405 Inst.addOperand(MCOperand::createImm(align)); 4406 if (Rm != 0xF) { 4407 if (Rm != 0xD) { 4408 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4409 return MCDisassembler::Fail; 4410 } else 4411 Inst.addOperand(MCOperand::createReg(0)); 4412 } 4413 4414 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4415 return MCDisassembler::Fail; 4416 Inst.addOperand(MCOperand::createImm(index)); 4417 4418 return S; 4419 } 4420 4421 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4422 uint64_t Address, const void *Decoder) { 4423 DecodeStatus S = MCDisassembler::Success; 4424 4425 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4426 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4427 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4428 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4429 unsigned size = fieldFromInstruction(Insn, 10, 2); 4430 4431 unsigned align = 0; 4432 unsigned index = 0; 4433 switch (size) { 4434 default: 4435 return MCDisassembler::Fail; 4436 case 0: 4437 if (fieldFromInstruction(Insn, 4, 1)) 4438 return MCDisassembler::Fail; // UNDEFINED 4439 index = fieldFromInstruction(Insn, 5, 3); 4440 break; 4441 case 1: 4442 if (fieldFromInstruction(Insn, 5, 1)) 4443 return MCDisassembler::Fail; // UNDEFINED 4444 index = fieldFromInstruction(Insn, 6, 2); 4445 if (fieldFromInstruction(Insn, 4, 1)) 4446 align = 2; 4447 break; 4448 case 2: 4449 if (fieldFromInstruction(Insn, 6, 1)) 4450 return MCDisassembler::Fail; // UNDEFINED 4451 index = fieldFromInstruction(Insn, 7, 1); 4452 4453 switch (fieldFromInstruction(Insn, 4, 2)) { 4454 case 0: 4455 align = 0; break; 4456 case 3: 4457 align = 4; break; 4458 default: 4459 return MCDisassembler::Fail; 4460 } 4461 break; 4462 } 4463 4464 if (Rm != 0xF) { // Writeback 4465 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4466 return MCDisassembler::Fail; 4467 } 4468 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4469 return MCDisassembler::Fail; 4470 Inst.addOperand(MCOperand::createImm(align)); 4471 if (Rm != 0xF) { 4472 if (Rm != 0xD) { 4473 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4474 return MCDisassembler::Fail; 4475 } else 4476 Inst.addOperand(MCOperand::createReg(0)); 4477 } 4478 4479 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4480 return MCDisassembler::Fail; 4481 Inst.addOperand(MCOperand::createImm(index)); 4482 4483 return S; 4484 } 4485 4486 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 4487 uint64_t Address, const void *Decoder) { 4488 DecodeStatus S = MCDisassembler::Success; 4489 4490 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4491 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4492 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4493 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4494 unsigned size = fieldFromInstruction(Insn, 10, 2); 4495 4496 unsigned align = 0; 4497 unsigned index = 0; 4498 unsigned inc = 1; 4499 switch (size) { 4500 default: 4501 return MCDisassembler::Fail; 4502 case 0: 4503 index = fieldFromInstruction(Insn, 5, 3); 4504 if (fieldFromInstruction(Insn, 4, 1)) 4505 align = 2; 4506 break; 4507 case 1: 4508 index = fieldFromInstruction(Insn, 6, 2); 4509 if (fieldFromInstruction(Insn, 4, 1)) 4510 align = 4; 4511 if (fieldFromInstruction(Insn, 5, 1)) 4512 inc = 2; 4513 break; 4514 case 2: 4515 if (fieldFromInstruction(Insn, 5, 1)) 4516 return MCDisassembler::Fail; // UNDEFINED 4517 index = fieldFromInstruction(Insn, 7, 1); 4518 if (fieldFromInstruction(Insn, 4, 1) != 0) 4519 align = 8; 4520 if (fieldFromInstruction(Insn, 6, 1)) 4521 inc = 2; 4522 break; 4523 } 4524 4525 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4526 return MCDisassembler::Fail; 4527 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4528 return MCDisassembler::Fail; 4529 if (Rm != 0xF) { // Writeback 4530 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4531 return MCDisassembler::Fail; 4532 } 4533 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4534 return MCDisassembler::Fail; 4535 Inst.addOperand(MCOperand::createImm(align)); 4536 if (Rm != 0xF) { 4537 if (Rm != 0xD) { 4538 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4539 return MCDisassembler::Fail; 4540 } else 4541 Inst.addOperand(MCOperand::createReg(0)); 4542 } 4543 4544 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4545 return MCDisassembler::Fail; 4546 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4547 return MCDisassembler::Fail; 4548 Inst.addOperand(MCOperand::createImm(index)); 4549 4550 return S; 4551 } 4552 4553 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 4554 uint64_t Address, const void *Decoder) { 4555 DecodeStatus S = MCDisassembler::Success; 4556 4557 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4558 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4559 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4560 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4561 unsigned size = fieldFromInstruction(Insn, 10, 2); 4562 4563 unsigned align = 0; 4564 unsigned index = 0; 4565 unsigned inc = 1; 4566 switch (size) { 4567 default: 4568 return MCDisassembler::Fail; 4569 case 0: 4570 index = fieldFromInstruction(Insn, 5, 3); 4571 if (fieldFromInstruction(Insn, 4, 1)) 4572 align = 2; 4573 break; 4574 case 1: 4575 index = fieldFromInstruction(Insn, 6, 2); 4576 if (fieldFromInstruction(Insn, 4, 1)) 4577 align = 4; 4578 if (fieldFromInstruction(Insn, 5, 1)) 4579 inc = 2; 4580 break; 4581 case 2: 4582 if (fieldFromInstruction(Insn, 5, 1)) 4583 return MCDisassembler::Fail; // UNDEFINED 4584 index = fieldFromInstruction(Insn, 7, 1); 4585 if (fieldFromInstruction(Insn, 4, 1) != 0) 4586 align = 8; 4587 if (fieldFromInstruction(Insn, 6, 1)) 4588 inc = 2; 4589 break; 4590 } 4591 4592 if (Rm != 0xF) { // Writeback 4593 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4594 return MCDisassembler::Fail; 4595 } 4596 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4597 return MCDisassembler::Fail; 4598 Inst.addOperand(MCOperand::createImm(align)); 4599 if (Rm != 0xF) { 4600 if (Rm != 0xD) { 4601 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4602 return MCDisassembler::Fail; 4603 } else 4604 Inst.addOperand(MCOperand::createReg(0)); 4605 } 4606 4607 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4608 return MCDisassembler::Fail; 4609 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4610 return MCDisassembler::Fail; 4611 Inst.addOperand(MCOperand::createImm(index)); 4612 4613 return S; 4614 } 4615 4616 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 4617 uint64_t Address, const void *Decoder) { 4618 DecodeStatus S = MCDisassembler::Success; 4619 4620 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4621 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4622 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4623 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4624 unsigned size = fieldFromInstruction(Insn, 10, 2); 4625 4626 unsigned align = 0; 4627 unsigned index = 0; 4628 unsigned inc = 1; 4629 switch (size) { 4630 default: 4631 return MCDisassembler::Fail; 4632 case 0: 4633 if (fieldFromInstruction(Insn, 4, 1)) 4634 return MCDisassembler::Fail; // UNDEFINED 4635 index = fieldFromInstruction(Insn, 5, 3); 4636 break; 4637 case 1: 4638 if (fieldFromInstruction(Insn, 4, 1)) 4639 return MCDisassembler::Fail; // UNDEFINED 4640 index = fieldFromInstruction(Insn, 6, 2); 4641 if (fieldFromInstruction(Insn, 5, 1)) 4642 inc = 2; 4643 break; 4644 case 2: 4645 if (fieldFromInstruction(Insn, 4, 2)) 4646 return MCDisassembler::Fail; // UNDEFINED 4647 index = fieldFromInstruction(Insn, 7, 1); 4648 if (fieldFromInstruction(Insn, 6, 1)) 4649 inc = 2; 4650 break; 4651 } 4652 4653 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4654 return MCDisassembler::Fail; 4655 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4656 return MCDisassembler::Fail; 4657 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4658 return MCDisassembler::Fail; 4659 4660 if (Rm != 0xF) { // Writeback 4661 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4662 return MCDisassembler::Fail; 4663 } 4664 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4665 return MCDisassembler::Fail; 4666 Inst.addOperand(MCOperand::createImm(align)); 4667 if (Rm != 0xF) { 4668 if (Rm != 0xD) { 4669 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4670 return MCDisassembler::Fail; 4671 } else 4672 Inst.addOperand(MCOperand::createReg(0)); 4673 } 4674 4675 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4676 return MCDisassembler::Fail; 4677 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4678 return MCDisassembler::Fail; 4679 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4680 return MCDisassembler::Fail; 4681 Inst.addOperand(MCOperand::createImm(index)); 4682 4683 return S; 4684 } 4685 4686 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 4687 uint64_t Address, const void *Decoder) { 4688 DecodeStatus S = MCDisassembler::Success; 4689 4690 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4691 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4692 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4693 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4694 unsigned size = fieldFromInstruction(Insn, 10, 2); 4695 4696 unsigned align = 0; 4697 unsigned index = 0; 4698 unsigned inc = 1; 4699 switch (size) { 4700 default: 4701 return MCDisassembler::Fail; 4702 case 0: 4703 if (fieldFromInstruction(Insn, 4, 1)) 4704 return MCDisassembler::Fail; // UNDEFINED 4705 index = fieldFromInstruction(Insn, 5, 3); 4706 break; 4707 case 1: 4708 if (fieldFromInstruction(Insn, 4, 1)) 4709 return MCDisassembler::Fail; // UNDEFINED 4710 index = fieldFromInstruction(Insn, 6, 2); 4711 if (fieldFromInstruction(Insn, 5, 1)) 4712 inc = 2; 4713 break; 4714 case 2: 4715 if (fieldFromInstruction(Insn, 4, 2)) 4716 return MCDisassembler::Fail; // UNDEFINED 4717 index = fieldFromInstruction(Insn, 7, 1); 4718 if (fieldFromInstruction(Insn, 6, 1)) 4719 inc = 2; 4720 break; 4721 } 4722 4723 if (Rm != 0xF) { // Writeback 4724 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4725 return MCDisassembler::Fail; 4726 } 4727 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4728 return MCDisassembler::Fail; 4729 Inst.addOperand(MCOperand::createImm(align)); 4730 if (Rm != 0xF) { 4731 if (Rm != 0xD) { 4732 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4733 return MCDisassembler::Fail; 4734 } else 4735 Inst.addOperand(MCOperand::createReg(0)); 4736 } 4737 4738 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4739 return MCDisassembler::Fail; 4740 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4741 return MCDisassembler::Fail; 4742 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4743 return MCDisassembler::Fail; 4744 Inst.addOperand(MCOperand::createImm(index)); 4745 4746 return S; 4747 } 4748 4749 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 4750 uint64_t Address, const void *Decoder) { 4751 DecodeStatus S = MCDisassembler::Success; 4752 4753 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4754 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4755 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4756 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4757 unsigned size = fieldFromInstruction(Insn, 10, 2); 4758 4759 unsigned align = 0; 4760 unsigned index = 0; 4761 unsigned inc = 1; 4762 switch (size) { 4763 default: 4764 return MCDisassembler::Fail; 4765 case 0: 4766 if (fieldFromInstruction(Insn, 4, 1)) 4767 align = 4; 4768 index = fieldFromInstruction(Insn, 5, 3); 4769 break; 4770 case 1: 4771 if (fieldFromInstruction(Insn, 4, 1)) 4772 align = 8; 4773 index = fieldFromInstruction(Insn, 6, 2); 4774 if (fieldFromInstruction(Insn, 5, 1)) 4775 inc = 2; 4776 break; 4777 case 2: 4778 switch (fieldFromInstruction(Insn, 4, 2)) { 4779 case 0: 4780 align = 0; break; 4781 case 3: 4782 return MCDisassembler::Fail; 4783 default: 4784 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4785 } 4786 4787 index = fieldFromInstruction(Insn, 7, 1); 4788 if (fieldFromInstruction(Insn, 6, 1)) 4789 inc = 2; 4790 break; 4791 } 4792 4793 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4794 return MCDisassembler::Fail; 4795 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4796 return MCDisassembler::Fail; 4797 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4798 return MCDisassembler::Fail; 4799 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4800 return MCDisassembler::Fail; 4801 4802 if (Rm != 0xF) { // Writeback 4803 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4804 return MCDisassembler::Fail; 4805 } 4806 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4807 return MCDisassembler::Fail; 4808 Inst.addOperand(MCOperand::createImm(align)); 4809 if (Rm != 0xF) { 4810 if (Rm != 0xD) { 4811 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4812 return MCDisassembler::Fail; 4813 } else 4814 Inst.addOperand(MCOperand::createReg(0)); 4815 } 4816 4817 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4818 return MCDisassembler::Fail; 4819 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4820 return MCDisassembler::Fail; 4821 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4822 return MCDisassembler::Fail; 4823 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4824 return MCDisassembler::Fail; 4825 Inst.addOperand(MCOperand::createImm(index)); 4826 4827 return S; 4828 } 4829 4830 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 4831 uint64_t Address, const void *Decoder) { 4832 DecodeStatus S = MCDisassembler::Success; 4833 4834 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4835 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4836 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4837 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4838 unsigned size = fieldFromInstruction(Insn, 10, 2); 4839 4840 unsigned align = 0; 4841 unsigned index = 0; 4842 unsigned inc = 1; 4843 switch (size) { 4844 default: 4845 return MCDisassembler::Fail; 4846 case 0: 4847 if (fieldFromInstruction(Insn, 4, 1)) 4848 align = 4; 4849 index = fieldFromInstruction(Insn, 5, 3); 4850 break; 4851 case 1: 4852 if (fieldFromInstruction(Insn, 4, 1)) 4853 align = 8; 4854 index = fieldFromInstruction(Insn, 6, 2); 4855 if (fieldFromInstruction(Insn, 5, 1)) 4856 inc = 2; 4857 break; 4858 case 2: 4859 switch (fieldFromInstruction(Insn, 4, 2)) { 4860 case 0: 4861 align = 0; break; 4862 case 3: 4863 return MCDisassembler::Fail; 4864 default: 4865 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4866 } 4867 4868 index = fieldFromInstruction(Insn, 7, 1); 4869 if (fieldFromInstruction(Insn, 6, 1)) 4870 inc = 2; 4871 break; 4872 } 4873 4874 if (Rm != 0xF) { // Writeback 4875 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4876 return MCDisassembler::Fail; 4877 } 4878 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4879 return MCDisassembler::Fail; 4880 Inst.addOperand(MCOperand::createImm(align)); 4881 if (Rm != 0xF) { 4882 if (Rm != 0xD) { 4883 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4884 return MCDisassembler::Fail; 4885 } else 4886 Inst.addOperand(MCOperand::createReg(0)); 4887 } 4888 4889 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4890 return MCDisassembler::Fail; 4891 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4892 return MCDisassembler::Fail; 4893 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4894 return MCDisassembler::Fail; 4895 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4896 return MCDisassembler::Fail; 4897 Inst.addOperand(MCOperand::createImm(index)); 4898 4899 return S; 4900 } 4901 4902 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 4903 uint64_t Address, const void *Decoder) { 4904 DecodeStatus S = MCDisassembler::Success; 4905 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4906 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4907 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4908 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4909 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4910 4911 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4912 S = MCDisassembler::SoftFail; 4913 4914 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4915 return MCDisassembler::Fail; 4916 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4917 return MCDisassembler::Fail; 4918 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4919 return MCDisassembler::Fail; 4920 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4921 return MCDisassembler::Fail; 4922 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4923 return MCDisassembler::Fail; 4924 4925 return S; 4926 } 4927 4928 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 4929 uint64_t Address, const void *Decoder) { 4930 DecodeStatus S = MCDisassembler::Success; 4931 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4932 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4933 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4934 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4935 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4936 4937 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4938 S = MCDisassembler::SoftFail; 4939 4940 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4941 return MCDisassembler::Fail; 4942 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4943 return MCDisassembler::Fail; 4944 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4945 return MCDisassembler::Fail; 4946 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4947 return MCDisassembler::Fail; 4948 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4949 return MCDisassembler::Fail; 4950 4951 return S; 4952 } 4953 4954 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 4955 uint64_t Address, const void *Decoder) { 4956 DecodeStatus S = MCDisassembler::Success; 4957 unsigned pred = fieldFromInstruction(Insn, 4, 4); 4958 unsigned mask = fieldFromInstruction(Insn, 0, 4); 4959 4960 if (pred == 0xF) { 4961 pred = 0xE; 4962 S = MCDisassembler::SoftFail; 4963 } 4964 4965 if (mask == 0x0) 4966 return MCDisassembler::Fail; 4967 4968 Inst.addOperand(MCOperand::createImm(pred)); 4969 Inst.addOperand(MCOperand::createImm(mask)); 4970 return S; 4971 } 4972 4973 static DecodeStatus 4974 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 4975 uint64_t Address, const void *Decoder) { 4976 DecodeStatus S = MCDisassembler::Success; 4977 4978 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4979 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4980 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4981 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4982 unsigned W = fieldFromInstruction(Insn, 21, 1); 4983 unsigned U = fieldFromInstruction(Insn, 23, 1); 4984 unsigned P = fieldFromInstruction(Insn, 24, 1); 4985 bool writeback = (W == 1) | (P == 0); 4986 4987 addr |= (U << 8) | (Rn << 9); 4988 4989 if (writeback && (Rn == Rt || Rn == Rt2)) 4990 Check(S, MCDisassembler::SoftFail); 4991 if (Rt == Rt2) 4992 Check(S, MCDisassembler::SoftFail); 4993 4994 // Rt 4995 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4996 return MCDisassembler::Fail; 4997 // Rt2 4998 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4999 return MCDisassembler::Fail; 5000 // Writeback operand 5001 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5002 return MCDisassembler::Fail; 5003 // addr 5004 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5005 return MCDisassembler::Fail; 5006 5007 return S; 5008 } 5009 5010 static DecodeStatus 5011 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 5012 uint64_t Address, const void *Decoder) { 5013 DecodeStatus S = MCDisassembler::Success; 5014 5015 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5016 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5017 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5018 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5019 unsigned W = fieldFromInstruction(Insn, 21, 1); 5020 unsigned U = fieldFromInstruction(Insn, 23, 1); 5021 unsigned P = fieldFromInstruction(Insn, 24, 1); 5022 bool writeback = (W == 1) | (P == 0); 5023 5024 addr |= (U << 8) | (Rn << 9); 5025 5026 if (writeback && (Rn == Rt || Rn == Rt2)) 5027 Check(S, MCDisassembler::SoftFail); 5028 5029 // Writeback operand 5030 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5031 return MCDisassembler::Fail; 5032 // Rt 5033 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5034 return MCDisassembler::Fail; 5035 // Rt2 5036 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5037 return MCDisassembler::Fail; 5038 // addr 5039 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5040 return MCDisassembler::Fail; 5041 5042 return S; 5043 } 5044 5045 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 5046 uint64_t Address, const void *Decoder) { 5047 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 5048 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 5049 if (sign1 != sign2) return MCDisassembler::Fail; 5050 5051 unsigned Val = fieldFromInstruction(Insn, 0, 8); 5052 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 5053 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 5054 Val |= sign1 << 12; 5055 Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val))); 5056 5057 return MCDisassembler::Success; 5058 } 5059 5060 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 5061 uint64_t Address, 5062 const void *Decoder) { 5063 DecodeStatus S = MCDisassembler::Success; 5064 5065 // Shift of "asr #32" is not allowed in Thumb2 mode. 5066 if (Val == 0x20) S = MCDisassembler::Fail; 5067 Inst.addOperand(MCOperand::createImm(Val)); 5068 return S; 5069 } 5070 5071 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 5072 uint64_t Address, const void *Decoder) { 5073 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5074 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 5075 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5076 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5077 5078 if (pred == 0xF) 5079 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 5080 5081 DecodeStatus S = MCDisassembler::Success; 5082 5083 if (Rt == Rn || Rn == Rt2) 5084 S = MCDisassembler::SoftFail; 5085 5086 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5087 return MCDisassembler::Fail; 5088 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5089 return MCDisassembler::Fail; 5090 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5091 return MCDisassembler::Fail; 5092 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5093 return MCDisassembler::Fail; 5094 5095 return S; 5096 } 5097 5098 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 5099 uint64_t Address, const void *Decoder) { 5100 const FeatureBitset &featureBits = 5101 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5102 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5103 5104 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5105 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5106 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5107 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5108 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5109 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5110 unsigned op = fieldFromInstruction(Insn, 5, 1); 5111 5112 DecodeStatus S = MCDisassembler::Success; 5113 5114 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5115 if (!(imm & 0x38)) { 5116 if (cmode == 0xF) { 5117 if (op == 1) return MCDisassembler::Fail; 5118 Inst.setOpcode(ARM::VMOVv2f32); 5119 } 5120 if (hasFullFP16) { 5121 if (cmode == 0xE) { 5122 if (op == 1) { 5123 Inst.setOpcode(ARM::VMOVv1i64); 5124 } else { 5125 Inst.setOpcode(ARM::VMOVv8i8); 5126 } 5127 } 5128 if (cmode == 0xD) { 5129 if (op == 1) { 5130 Inst.setOpcode(ARM::VMVNv2i32); 5131 } else { 5132 Inst.setOpcode(ARM::VMOVv2i32); 5133 } 5134 } 5135 if (cmode == 0xC) { 5136 if (op == 1) { 5137 Inst.setOpcode(ARM::VMVNv2i32); 5138 } else { 5139 Inst.setOpcode(ARM::VMOVv2i32); 5140 } 5141 } 5142 } 5143 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5144 } 5145 5146 if (!(imm & 0x20)) return MCDisassembler::Fail; 5147 5148 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 5149 return MCDisassembler::Fail; 5150 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5151 return MCDisassembler::Fail; 5152 Inst.addOperand(MCOperand::createImm(64 - imm)); 5153 5154 return S; 5155 } 5156 5157 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 5158 uint64_t Address, const void *Decoder) { 5159 const FeatureBitset &featureBits = 5160 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5161 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5162 5163 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5164 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5165 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5166 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5167 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5168 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5169 unsigned op = fieldFromInstruction(Insn, 5, 1); 5170 5171 DecodeStatus S = MCDisassembler::Success; 5172 5173 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5174 if (!(imm & 0x38)) { 5175 if (cmode == 0xF) { 5176 if (op == 1) return MCDisassembler::Fail; 5177 Inst.setOpcode(ARM::VMOVv4f32); 5178 } 5179 if (hasFullFP16) { 5180 if (cmode == 0xE) { 5181 if (op == 1) { 5182 Inst.setOpcode(ARM::VMOVv2i64); 5183 } else { 5184 Inst.setOpcode(ARM::VMOVv16i8); 5185 } 5186 } 5187 if (cmode == 0xD) { 5188 if (op == 1) { 5189 Inst.setOpcode(ARM::VMVNv4i32); 5190 } else { 5191 Inst.setOpcode(ARM::VMOVv4i32); 5192 } 5193 } 5194 if (cmode == 0xC) { 5195 if (op == 1) { 5196 Inst.setOpcode(ARM::VMVNv4i32); 5197 } else { 5198 Inst.setOpcode(ARM::VMOVv4i32); 5199 } 5200 } 5201 } 5202 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5203 } 5204 5205 if (!(imm & 0x20)) return MCDisassembler::Fail; 5206 5207 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 5208 return MCDisassembler::Fail; 5209 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 5210 return MCDisassembler::Fail; 5211 Inst.addOperand(MCOperand::createImm(64 - imm)); 5212 5213 return S; 5214 } 5215 5216 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 5217 uint64_t Address, const void *Decoder) { 5218 DecodeStatus S = MCDisassembler::Success; 5219 5220 unsigned Rn = fieldFromInstruction(Val, 16, 4); 5221 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5222 unsigned Rm = fieldFromInstruction(Val, 0, 4); 5223 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 5224 unsigned Cond = fieldFromInstruction(Val, 28, 4); 5225 5226 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 5227 S = MCDisassembler::SoftFail; 5228 5229 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5230 return MCDisassembler::Fail; 5231 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5232 return MCDisassembler::Fail; 5233 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 5234 return MCDisassembler::Fail; 5235 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 5236 return MCDisassembler::Fail; 5237 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 5238 return MCDisassembler::Fail; 5239 5240 return S; 5241 } 5242 5243 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 5244 uint64_t Address, const void *Decoder) { 5245 DecodeStatus S = MCDisassembler::Success; 5246 5247 unsigned CRm = fieldFromInstruction(Val, 0, 4); 5248 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 5249 unsigned cop = fieldFromInstruction(Val, 8, 4); 5250 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5251 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 5252 5253 if ((cop & ~0x1) == 0xa) 5254 return MCDisassembler::Fail; 5255 5256 if (Rt == Rt2) 5257 S = MCDisassembler::SoftFail; 5258 5259 // We have to check if the instruction is MRRC2 5260 // or MCRR2 when constructing the operands for 5261 // Inst. Reason is because MRRC2 stores to two 5262 // registers so it's tablegen desc has has two 5263 // outputs whereas MCRR doesn't store to any 5264 // registers so all of it's operands are listed 5265 // as inputs, therefore the operand order for 5266 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] 5267 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] 5268 5269 if (Inst.getOpcode() == ARM::MRRC2) { 5270 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5271 return MCDisassembler::Fail; 5272 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5273 return MCDisassembler::Fail; 5274 } 5275 Inst.addOperand(MCOperand::createImm(cop)); 5276 Inst.addOperand(MCOperand::createImm(opc1)); 5277 if (Inst.getOpcode() == ARM::MCRR2) { 5278 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5279 return MCDisassembler::Fail; 5280 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5281 return MCDisassembler::Fail; 5282 } 5283 Inst.addOperand(MCOperand::createImm(CRm)); 5284 5285 return S; 5286 } 5287