1 //===- ARMRegisterBankInfo.cpp -----------------------------------*- C++ -*-==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// \file 10 /// This file implements the targeting of the RegisterBankInfo class for ARM. 11 /// \todo This should be generated by TableGen. 12 //===----------------------------------------------------------------------===// 13 14 #include "ARMRegisterBankInfo.h" 15 #include "ARMInstrInfo.h" // For the register classes 16 #include "ARMSubtarget.h" 17 #include "llvm/CodeGen/GlobalISel/RegisterBank.h" 18 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h" 19 #include "llvm/CodeGen/MachineRegisterInfo.h" 20 #include "llvm/CodeGen/TargetRegisterInfo.h" 21 22 #define GET_TARGET_REGBANK_IMPL 23 #include "ARMGenRegisterBank.inc" 24 25 using namespace llvm; 26 27 // FIXME: TableGen this. 28 // If it grows too much and TableGen still isn't ready to do the job, extract it 29 // into an ARMGenRegisterBankInfo.def (similar to AArch64). 30 namespace llvm { 31 namespace ARM { 32 enum PartialMappingIdx { 33 PMI_GPR, 34 PMI_SPR, 35 PMI_DPR, 36 PMI_Min = PMI_GPR, 37 }; 38 39 RegisterBankInfo::PartialMapping PartMappings[]{ 40 // GPR Partial Mapping 41 {0, 32, GPRRegBank}, 42 // SPR Partial Mapping 43 {0, 32, FPRRegBank}, 44 // DPR Partial Mapping 45 {0, 64, FPRRegBank}, 46 }; 47 48 #ifndef NDEBUG 49 static bool checkPartMapping(const RegisterBankInfo::PartialMapping &PM, 50 unsigned Start, unsigned Length, 51 unsigned RegBankID) { 52 return PM.StartIdx == Start && PM.Length == Length && 53 PM.RegBank->getID() == RegBankID; 54 } 55 56 static void checkPartialMappings() { 57 assert( 58 checkPartMapping(PartMappings[PMI_GPR - PMI_Min], 0, 32, GPRRegBankID) && 59 "Wrong mapping for GPR"); 60 assert( 61 checkPartMapping(PartMappings[PMI_SPR - PMI_Min], 0, 32, FPRRegBankID) && 62 "Wrong mapping for SPR"); 63 assert( 64 checkPartMapping(PartMappings[PMI_DPR - PMI_Min], 0, 64, FPRRegBankID) && 65 "Wrong mapping for DPR"); 66 } 67 #endif 68 69 enum ValueMappingIdx { 70 InvalidIdx = 0, 71 GPR3OpsIdx = 1, 72 SPR3OpsIdx = 4, 73 DPR3OpsIdx = 7, 74 }; 75 76 RegisterBankInfo::ValueMapping ValueMappings[] = { 77 // invalid 78 {nullptr, 0}, 79 // 3 ops in GPRs 80 {&PartMappings[PMI_GPR - PMI_Min], 1}, 81 {&PartMappings[PMI_GPR - PMI_Min], 1}, 82 {&PartMappings[PMI_GPR - PMI_Min], 1}, 83 // 3 ops in SPRs 84 {&PartMappings[PMI_SPR - PMI_Min], 1}, 85 {&PartMappings[PMI_SPR - PMI_Min], 1}, 86 {&PartMappings[PMI_SPR - PMI_Min], 1}, 87 // 3 ops in DPRs 88 {&PartMappings[PMI_DPR - PMI_Min], 1}, 89 {&PartMappings[PMI_DPR - PMI_Min], 1}, 90 {&PartMappings[PMI_DPR - PMI_Min], 1}}; 91 92 #ifndef NDEBUG 93 static bool checkValueMapping(const RegisterBankInfo::ValueMapping &VM, 94 RegisterBankInfo::PartialMapping *BreakDown) { 95 return VM.NumBreakDowns == 1 && VM.BreakDown == BreakDown; 96 } 97 98 static void checkValueMappings() { 99 assert(checkValueMapping(ValueMappings[GPR3OpsIdx], 100 &PartMappings[PMI_GPR - PMI_Min]) && 101 "Wrong value mapping for 3 GPR ops instruction"); 102 assert(checkValueMapping(ValueMappings[GPR3OpsIdx + 1], 103 &PartMappings[PMI_GPR - PMI_Min]) && 104 "Wrong value mapping for 3 GPR ops instruction"); 105 assert(checkValueMapping(ValueMappings[GPR3OpsIdx + 2], 106 &PartMappings[PMI_GPR - PMI_Min]) && 107 "Wrong value mapping for 3 GPR ops instruction"); 108 109 assert(checkValueMapping(ValueMappings[SPR3OpsIdx], 110 &PartMappings[PMI_SPR - PMI_Min]) && 111 "Wrong value mapping for 3 SPR ops instruction"); 112 assert(checkValueMapping(ValueMappings[SPR3OpsIdx + 1], 113 &PartMappings[PMI_SPR - PMI_Min]) && 114 "Wrong value mapping for 3 SPR ops instruction"); 115 assert(checkValueMapping(ValueMappings[SPR3OpsIdx + 2], 116 &PartMappings[PMI_SPR - PMI_Min]) && 117 "Wrong value mapping for 3 SPR ops instruction"); 118 119 assert(checkValueMapping(ValueMappings[DPR3OpsIdx], 120 &PartMappings[PMI_DPR - PMI_Min]) && 121 "Wrong value mapping for 3 DPR ops instruction"); 122 assert(checkValueMapping(ValueMappings[DPR3OpsIdx + 1], 123 &PartMappings[PMI_DPR - PMI_Min]) && 124 "Wrong value mapping for 3 DPR ops instruction"); 125 assert(checkValueMapping(ValueMappings[DPR3OpsIdx + 2], 126 &PartMappings[PMI_DPR - PMI_Min]) && 127 "Wrong value mapping for 3 DPR ops instruction"); 128 } 129 #endif 130 } // end namespace arm 131 } // end namespace llvm 132 133 ARMRegisterBankInfo::ARMRegisterBankInfo(const TargetRegisterInfo &TRI) 134 : ARMGenRegisterBankInfo() { 135 static bool AlreadyInit = false; 136 // We have only one set of register banks, whatever the subtarget 137 // is. Therefore, the initialization of the RegBanks table should be 138 // done only once. Indeed the table of all register banks 139 // (ARM::RegBanks) is unique in the compiler. At some point, it 140 // will get tablegen'ed and the whole constructor becomes empty. 141 if (AlreadyInit) 142 return; 143 AlreadyInit = true; 144 145 const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID); 146 (void)RBGPR; 147 assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up"); 148 149 // Initialize the GPR bank. 150 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) && 151 "Subclass not added?"); 152 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) && 153 "Subclass not added?"); 154 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) && 155 "Subclass not added?"); 156 assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) && 157 "Subclass not added?"); 158 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) && 159 "Subclass not added?"); 160 assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) && 161 "Subclass not added?"); 162 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPR_and_tcGPRRegClassID)) && 163 "Subclass not added?"); 164 assert(RBGPR.getSize() == 32 && "GPRs should hold up to 32-bit"); 165 166 #ifndef NDEBUG 167 ARM::checkPartialMappings(); 168 ARM::checkValueMappings(); 169 #endif 170 } 171 172 const RegisterBank &ARMRegisterBankInfo::getRegBankFromRegClass( 173 const TargetRegisterClass &RC) const { 174 using namespace ARM; 175 176 switch (RC.getID()) { 177 case GPRRegClassID: 178 case GPRnopcRegClassID: 179 case GPRspRegClassID: 180 case tGPR_and_tcGPRRegClassID: 181 case tGPRRegClassID: 182 return getRegBank(ARM::GPRRegBankID); 183 case SPR_8RegClassID: 184 case SPRRegClassID: 185 case DPR_8RegClassID: 186 case DPRRegClassID: 187 return getRegBank(ARM::FPRRegBankID); 188 default: 189 llvm_unreachable("Unsupported register kind"); 190 } 191 192 llvm_unreachable("Switch should handle all register classes"); 193 } 194 195 const RegisterBankInfo::InstructionMapping & 196 ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { 197 auto Opc = MI.getOpcode(); 198 199 // Try the default logic for non-generic instructions that are either copies 200 // or already have some operands assigned to banks. 201 if (!isPreISelGenericOpcode(Opc) || Opc == TargetOpcode::G_PHI) { 202 const InstructionMapping &Mapping = getInstrMappingImpl(MI); 203 if (Mapping.isValid()) 204 return Mapping; 205 } 206 207 using namespace TargetOpcode; 208 209 const MachineFunction &MF = *MI.getParent()->getParent(); 210 const MachineRegisterInfo &MRI = MF.getRegInfo(); 211 unsigned NumOperands = MI.getNumOperands(); 212 const ValueMapping *OperandsMapping = &ARM::ValueMappings[ARM::GPR3OpsIdx]; 213 214 switch (Opc) { 215 case G_ADD: 216 case G_SUB: 217 case G_MUL: 218 case G_AND: 219 case G_OR: 220 case G_XOR: 221 case G_LSHR: 222 case G_ASHR: 223 case G_SHL: 224 case G_SDIV: 225 case G_UDIV: 226 case G_SEXT: 227 case G_ZEXT: 228 case G_ANYEXT: 229 case G_GEP: 230 case G_INTTOPTR: 231 case G_PTRTOINT: 232 // FIXME: We're abusing the fact that everything lives in a GPR for now; in 233 // the real world we would use different mappings. 234 OperandsMapping = &ARM::ValueMappings[ARM::GPR3OpsIdx]; 235 break; 236 case G_TRUNC: { 237 // In some cases we may end up with a G_TRUNC from a 64-bit value to a 238 // 32-bit value. This isn't a real floating point trunc (that would be a 239 // G_FPTRUNC). Instead it is an integer trunc in disguise, which can appear 240 // because the legalizer doesn't distinguish between integer and floating 241 // point values so it may leave some 64-bit integers un-narrowed. Until we 242 // have a more principled solution that doesn't let such things sneak all 243 // the way to this point, just map the source to a DPR and the destination 244 // to a GPR. 245 LLT LargeTy = MRI.getType(MI.getOperand(1).getReg()); 246 OperandsMapping = 247 LargeTy.getSizeInBits() <= 32 248 ? &ARM::ValueMappings[ARM::GPR3OpsIdx] 249 : getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], 250 &ARM::ValueMappings[ARM::DPR3OpsIdx]}); 251 break; 252 } 253 case G_LOAD: 254 case G_STORE: { 255 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 256 OperandsMapping = 257 Ty.getSizeInBits() == 64 258 ? getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx], 259 &ARM::ValueMappings[ARM::GPR3OpsIdx]}) 260 : &ARM::ValueMappings[ARM::GPR3OpsIdx]; 261 break; 262 } 263 case G_FADD: 264 case G_FSUB: 265 case G_FMUL: 266 case G_FDIV: 267 case G_FNEG: { 268 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 269 OperandsMapping =Ty.getSizeInBits() == 64 270 ? &ARM::ValueMappings[ARM::DPR3OpsIdx] 271 : &ARM::ValueMappings[ARM::SPR3OpsIdx]; 272 break; 273 } 274 case G_FMA: { 275 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 276 OperandsMapping = 277 Ty.getSizeInBits() == 64 278 ? getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx], 279 &ARM::ValueMappings[ARM::DPR3OpsIdx], 280 &ARM::ValueMappings[ARM::DPR3OpsIdx], 281 &ARM::ValueMappings[ARM::DPR3OpsIdx]}) 282 : getOperandsMapping({&ARM::ValueMappings[ARM::SPR3OpsIdx], 283 &ARM::ValueMappings[ARM::SPR3OpsIdx], 284 &ARM::ValueMappings[ARM::SPR3OpsIdx], 285 &ARM::ValueMappings[ARM::SPR3OpsIdx]}); 286 break; 287 } 288 case G_FPEXT: { 289 LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); 290 LLT FromTy = MRI.getType(MI.getOperand(1).getReg()); 291 if (ToTy.getSizeInBits() == 64 && FromTy.getSizeInBits() == 32) 292 OperandsMapping = 293 getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx], 294 &ARM::ValueMappings[ARM::SPR3OpsIdx]}); 295 break; 296 } 297 case G_FPTRUNC: { 298 LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); 299 LLT FromTy = MRI.getType(MI.getOperand(1).getReg()); 300 if (ToTy.getSizeInBits() == 32 && FromTy.getSizeInBits() == 64) 301 OperandsMapping = 302 getOperandsMapping({&ARM::ValueMappings[ARM::SPR3OpsIdx], 303 &ARM::ValueMappings[ARM::DPR3OpsIdx]}); 304 break; 305 } 306 case G_FPTOSI: 307 case G_FPTOUI: { 308 LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); 309 LLT FromTy = MRI.getType(MI.getOperand(1).getReg()); 310 if ((FromTy.getSizeInBits() == 32 || FromTy.getSizeInBits() == 64) && 311 ToTy.getSizeInBits() == 32) 312 OperandsMapping = 313 FromTy.getSizeInBits() == 64 314 ? getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], 315 &ARM::ValueMappings[ARM::DPR3OpsIdx]}) 316 : getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], 317 &ARM::ValueMappings[ARM::SPR3OpsIdx]}); 318 break; 319 } 320 case G_CONSTANT: 321 case G_FRAME_INDEX: 322 case G_GLOBAL_VALUE: 323 OperandsMapping = 324 getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr}); 325 break; 326 case G_SELECT: { 327 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 328 (void)Ty; 329 LLT Ty2 = MRI.getType(MI.getOperand(1).getReg()); 330 (void)Ty2; 331 assert(Ty.getSizeInBits() == 32 && "Unsupported size for G_SELECT"); 332 assert(Ty2.getSizeInBits() == 1 && "Unsupported size for G_SELECT"); 333 OperandsMapping = 334 getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], 335 &ARM::ValueMappings[ARM::GPR3OpsIdx], 336 &ARM::ValueMappings[ARM::GPR3OpsIdx], 337 &ARM::ValueMappings[ARM::GPR3OpsIdx]}); 338 break; 339 } 340 case G_ICMP: { 341 LLT Ty2 = MRI.getType(MI.getOperand(2).getReg()); 342 (void)Ty2; 343 assert(Ty2.getSizeInBits() == 32 && "Unsupported size for G_ICMP"); 344 OperandsMapping = 345 getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr, 346 &ARM::ValueMappings[ARM::GPR3OpsIdx], 347 &ARM::ValueMappings[ARM::GPR3OpsIdx]}); 348 break; 349 } 350 case G_FCMP: { 351 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 352 (void)Ty; 353 LLT Ty1 = MRI.getType(MI.getOperand(2).getReg()); 354 LLT Ty2 = MRI.getType(MI.getOperand(3).getReg()); 355 (void)Ty2; 356 assert(Ty.getSizeInBits() == 1 && "Unsupported size for G_FCMP"); 357 assert(Ty1.getSizeInBits() == Ty2.getSizeInBits() && 358 "Mismatched operand sizes for G_FCMP"); 359 360 unsigned Size = Ty1.getSizeInBits(); 361 assert((Size == 32 || Size == 64) && "Unsupported size for G_FCMP"); 362 363 auto FPRValueMapping = Size == 32 ? &ARM::ValueMappings[ARM::SPR3OpsIdx] 364 : &ARM::ValueMappings[ARM::DPR3OpsIdx]; 365 OperandsMapping = 366 getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr, 367 FPRValueMapping, FPRValueMapping}); 368 break; 369 } 370 case G_MERGE_VALUES: { 371 // We only support G_MERGE_VALUES for creating a double precision floating 372 // point value out of two GPRs. 373 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 374 LLT Ty1 = MRI.getType(MI.getOperand(1).getReg()); 375 LLT Ty2 = MRI.getType(MI.getOperand(2).getReg()); 376 if (Ty.getSizeInBits() != 64 || Ty1.getSizeInBits() != 32 || 377 Ty2.getSizeInBits() != 32) 378 return getInvalidInstructionMapping(); 379 OperandsMapping = 380 getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx], 381 &ARM::ValueMappings[ARM::GPR3OpsIdx], 382 &ARM::ValueMappings[ARM::GPR3OpsIdx]}); 383 break; 384 } 385 case G_UNMERGE_VALUES: { 386 // We only support G_UNMERGE_VALUES for splitting a double precision 387 // floating point value into two GPRs. 388 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 389 LLT Ty1 = MRI.getType(MI.getOperand(1).getReg()); 390 LLT Ty2 = MRI.getType(MI.getOperand(2).getReg()); 391 if (Ty.getSizeInBits() != 32 || Ty1.getSizeInBits() != 32 || 392 Ty2.getSizeInBits() != 64) 393 return getInvalidInstructionMapping(); 394 OperandsMapping = 395 getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], 396 &ARM::ValueMappings[ARM::GPR3OpsIdx], 397 &ARM::ValueMappings[ARM::DPR3OpsIdx]}); 398 break; 399 } 400 case G_BR: 401 OperandsMapping = getOperandsMapping({nullptr}); 402 break; 403 case G_BRCOND: 404 OperandsMapping = 405 getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr}); 406 break; 407 default: 408 return getInvalidInstructionMapping(); 409 } 410 411 #ifndef NDEBUG 412 for (unsigned i = 0; i < NumOperands; i++) { 413 for (const auto &Mapping : OperandsMapping[i]) { 414 assert( 415 (Mapping.RegBank->getID() != ARM::FPRRegBankID || 416 MF.getSubtarget<ARMSubtarget>().hasVFP2()) && 417 "Trying to use floating point register bank on target without vfp"); 418 } 419 } 420 #endif 421 422 return getInstructionMapping(DefaultMappingID, /*Cost=*/1, OperandsMapping, 423 NumOperands); 424 } 425