1 //===- ARMRegisterBankInfo.cpp -----------------------------------*- C++ -*-==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// \file 10 /// This file implements the targeting of the RegisterBankInfo class for ARM. 11 /// \todo This should be generated by TableGen. 12 //===----------------------------------------------------------------------===// 13 14 #include "ARMRegisterBankInfo.h" 15 #include "ARMInstrInfo.h" // For the register classes 16 #include "ARMSubtarget.h" 17 #include "llvm/CodeGen/GlobalISel/RegisterBank.h" 18 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h" 19 #include "llvm/CodeGen/MachineRegisterInfo.h" 20 #include "llvm/Target/TargetRegisterInfo.h" 21 22 #define GET_TARGET_REGBANK_IMPL 23 #include "ARMGenRegisterBank.inc" 24 25 using namespace llvm; 26 27 #ifndef LLVM_BUILD_GLOBAL_ISEL 28 #error "You shouldn't build this" 29 #endif 30 31 // FIXME: TableGen this. 32 // If it grows too much and TableGen still isn't ready to do the job, extract it 33 // into an ARMGenRegisterBankInfo.def (similar to AArch64). 34 namespace llvm { 35 namespace ARM { 36 enum PartialMappingIdx { 37 PMI_GPR, 38 PMI_SPR, 39 PMI_DPR, 40 PMI_Min = PMI_GPR, 41 }; 42 43 RegisterBankInfo::PartialMapping PartMappings[]{ 44 // GPR Partial Mapping 45 {0, 32, GPRRegBank}, 46 // SPR Partial Mapping 47 {0, 32, FPRRegBank}, 48 // DPR Partial Mapping 49 {0, 64, FPRRegBank}, 50 }; 51 52 #ifndef NDEBUG 53 static bool checkPartMapping(const RegisterBankInfo::PartialMapping &PM, 54 unsigned Start, unsigned Length, 55 unsigned RegBankID) { 56 return PM.StartIdx == Start && PM.Length == Length && 57 PM.RegBank->getID() == RegBankID; 58 } 59 60 static void checkPartialMappings() { 61 assert( 62 checkPartMapping(PartMappings[PMI_GPR - PMI_Min], 0, 32, GPRRegBankID) && 63 "Wrong mapping for GPR"); 64 assert( 65 checkPartMapping(PartMappings[PMI_SPR - PMI_Min], 0, 32, FPRRegBankID) && 66 "Wrong mapping for SPR"); 67 assert( 68 checkPartMapping(PartMappings[PMI_DPR - PMI_Min], 0, 64, FPRRegBankID) && 69 "Wrong mapping for DPR"); 70 } 71 #endif 72 73 enum ValueMappingIdx { 74 InvalidIdx = 0, 75 GPR3OpsIdx = 1, 76 SPR3OpsIdx = 4, 77 DPR3OpsIdx = 7, 78 }; 79 80 RegisterBankInfo::ValueMapping ValueMappings[] = { 81 // invalid 82 {nullptr, 0}, 83 // 3 ops in GPRs 84 {&PartMappings[PMI_GPR - PMI_Min], 1}, 85 {&PartMappings[PMI_GPR - PMI_Min], 1}, 86 {&PartMappings[PMI_GPR - PMI_Min], 1}, 87 // 3 ops in SPRs 88 {&PartMappings[PMI_SPR - PMI_Min], 1}, 89 {&PartMappings[PMI_SPR - PMI_Min], 1}, 90 {&PartMappings[PMI_SPR - PMI_Min], 1}, 91 // 3 ops in DPRs 92 {&PartMappings[PMI_DPR - PMI_Min], 1}, 93 {&PartMappings[PMI_DPR - PMI_Min], 1}, 94 {&PartMappings[PMI_DPR - PMI_Min], 1}}; 95 96 #ifndef NDEBUG 97 static bool checkValueMapping(const RegisterBankInfo::ValueMapping &VM, 98 RegisterBankInfo::PartialMapping *BreakDown) { 99 return VM.NumBreakDowns == 1 && VM.BreakDown == BreakDown; 100 } 101 102 static void checkValueMappings() { 103 assert(checkValueMapping(ValueMappings[GPR3OpsIdx], 104 &PartMappings[PMI_GPR - PMI_Min]) && 105 "Wrong value mapping for 3 GPR ops instruction"); 106 assert(checkValueMapping(ValueMappings[GPR3OpsIdx + 1], 107 &PartMappings[PMI_GPR - PMI_Min]) && 108 "Wrong value mapping for 3 GPR ops instruction"); 109 assert(checkValueMapping(ValueMappings[GPR3OpsIdx + 2], 110 &PartMappings[PMI_GPR - PMI_Min]) && 111 "Wrong value mapping for 3 GPR ops instruction"); 112 113 assert(checkValueMapping(ValueMappings[SPR3OpsIdx], 114 &PartMappings[PMI_SPR - PMI_Min]) && 115 "Wrong value mapping for 3 SPR ops instruction"); 116 assert(checkValueMapping(ValueMappings[SPR3OpsIdx + 1], 117 &PartMappings[PMI_SPR - PMI_Min]) && 118 "Wrong value mapping for 3 SPR ops instruction"); 119 assert(checkValueMapping(ValueMappings[SPR3OpsIdx + 2], 120 &PartMappings[PMI_SPR - PMI_Min]) && 121 "Wrong value mapping for 3 SPR ops instruction"); 122 123 assert(checkValueMapping(ValueMappings[DPR3OpsIdx], 124 &PartMappings[PMI_DPR - PMI_Min]) && 125 "Wrong value mapping for 3 DPR ops instruction"); 126 assert(checkValueMapping(ValueMappings[DPR3OpsIdx + 1], 127 &PartMappings[PMI_DPR - PMI_Min]) && 128 "Wrong value mapping for 3 DPR ops instruction"); 129 assert(checkValueMapping(ValueMappings[DPR3OpsIdx + 2], 130 &PartMappings[PMI_DPR - PMI_Min]) && 131 "Wrong value mapping for 3 DPR ops instruction"); 132 } 133 #endif 134 } // end namespace arm 135 } // end namespace llvm 136 137 ARMRegisterBankInfo::ARMRegisterBankInfo(const TargetRegisterInfo &TRI) 138 : ARMGenRegisterBankInfo() { 139 static bool AlreadyInit = false; 140 // We have only one set of register banks, whatever the subtarget 141 // is. Therefore, the initialization of the RegBanks table should be 142 // done only once. Indeed the table of all register banks 143 // (ARM::RegBanks) is unique in the compiler. At some point, it 144 // will get tablegen'ed and the whole constructor becomes empty. 145 if (AlreadyInit) 146 return; 147 AlreadyInit = true; 148 149 const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID); 150 (void)RBGPR; 151 assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up"); 152 153 // Initialize the GPR bank. 154 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) && 155 "Subclass not added?"); 156 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) && 157 "Subclass not added?"); 158 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) && 159 "Subclass not added?"); 160 assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) && 161 "Subclass not added?"); 162 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) && 163 "Subclass not added?"); 164 assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) && 165 "Subclass not added?"); 166 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPR_and_tcGPRRegClassID)) && 167 "Subclass not added?"); 168 assert(RBGPR.getSize() == 32 && "GPRs should hold up to 32-bit"); 169 170 #ifndef NDEBUG 171 ARM::checkPartialMappings(); 172 ARM::checkValueMappings(); 173 #endif 174 } 175 176 const RegisterBank &ARMRegisterBankInfo::getRegBankFromRegClass( 177 const TargetRegisterClass &RC) const { 178 using namespace ARM; 179 180 switch (RC.getID()) { 181 case GPRRegClassID: 182 case GPRnopcRegClassID: 183 case tGPR_and_tcGPRRegClassID: 184 return getRegBank(ARM::GPRRegBankID); 185 case SPR_8RegClassID: 186 case SPRRegClassID: 187 case DPR_8RegClassID: 188 case DPRRegClassID: 189 return getRegBank(ARM::FPRRegBankID); 190 default: 191 llvm_unreachable("Unsupported register kind"); 192 } 193 194 llvm_unreachable("Switch should handle all register classes"); 195 } 196 197 RegisterBankInfo::InstructionMapping 198 ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { 199 auto Opc = MI.getOpcode(); 200 201 // Try the default logic for non-generic instructions that are either copies 202 // or already have some operands assigned to banks. 203 if (!isPreISelGenericOpcode(Opc)) { 204 InstructionMapping Mapping = getInstrMappingImpl(MI); 205 if (Mapping.isValid()) 206 return Mapping; 207 } 208 209 using namespace TargetOpcode; 210 211 const MachineFunction &MF = *MI.getParent()->getParent(); 212 const MachineRegisterInfo &MRI = MF.getRegInfo(); 213 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 214 215 unsigned NumOperands = MI.getNumOperands(); 216 const ValueMapping *OperandsMapping = &ARM::ValueMappings[ARM::GPR3OpsIdx]; 217 218 switch (Opc) { 219 case G_ADD: 220 case G_SEXT: 221 case G_ZEXT: 222 // FIXME: We're abusing the fact that everything lives in a GPR for now; in 223 // the real world we would use different mappings. 224 OperandsMapping = &ARM::ValueMappings[ARM::GPR3OpsIdx]; 225 break; 226 case G_LOAD: 227 OperandsMapping = 228 Ty.getSizeInBits() == 64 229 ? getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx], 230 &ARM::ValueMappings[ARM::GPR3OpsIdx]}) 231 : &ARM::ValueMappings[ARM::GPR3OpsIdx]; 232 break; 233 case G_FADD: 234 assert((Ty.getSizeInBits() == 32 || Ty.getSizeInBits() == 64) && 235 "Unsupported size for G_FADD"); 236 OperandsMapping = Ty.getSizeInBits() == 64 237 ? &ARM::ValueMappings[ARM::DPR3OpsIdx] 238 : &ARM::ValueMappings[ARM::SPR3OpsIdx]; 239 break; 240 case G_FRAME_INDEX: 241 OperandsMapping = 242 getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr}); 243 break; 244 case G_SEQUENCE: { 245 // We only support G_SEQUENCE for creating a double precision floating point 246 // value out of two GPRs. 247 LLT Ty1 = MRI.getType(MI.getOperand(1).getReg()); 248 LLT Ty2 = MRI.getType(MI.getOperand(3).getReg()); 249 if (Ty.getSizeInBits() != 64 || Ty1.getSizeInBits() != 32 || 250 Ty2.getSizeInBits() != 32) 251 return InstructionMapping{}; 252 OperandsMapping = 253 getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx], 254 &ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr, 255 &ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr}); 256 break; 257 } 258 case G_EXTRACT: { 259 // We only support G_EXTRACT for splitting a double precision floating point 260 // value into two GPRs. 261 LLT Ty1 = MRI.getType(MI.getOperand(1).getReg()); 262 LLT Ty2 = MRI.getType(MI.getOperand(2).getReg()); 263 if (Ty.getSizeInBits() != 32 || Ty1.getSizeInBits() != 32 || 264 Ty2.getSizeInBits() != 64) 265 return InstructionMapping{}; 266 OperandsMapping = getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], 267 &ARM::ValueMappings[ARM::GPR3OpsIdx], 268 &ARM::ValueMappings[ARM::DPR3OpsIdx], 269 nullptr, nullptr}); 270 break; 271 } 272 default: 273 return InstructionMapping{}; 274 } 275 276 #ifndef NDEBUG 277 for (unsigned i = 0; i < NumOperands; i++) { 278 for (const auto &Mapping : OperandsMapping[i]) { 279 assert( 280 (Mapping.RegBank->getID() != ARM::FPRRegBankID || 281 MF.getSubtarget<ARMSubtarget>().hasVFP2()) && 282 "Trying to use floating point register bank on target without vfp"); 283 } 284 } 285 #endif 286 287 return InstructionMapping{DefaultMappingID, /*Cost=*/1, OperandsMapping, 288 NumOperands}; 289 } 290