1 //===- ARMLegalizerInfo.cpp --------------------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements the targeting of the Machinelegalizer class for ARM. 10 /// \todo This should be generated by TableGen. 11 //===----------------------------------------------------------------------===// 12 13 #include "ARMLegalizerInfo.h" 14 #include "ARMCallLowering.h" 15 #include "ARMSubtarget.h" 16 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h" 17 #include "llvm/CodeGen/LowLevelType.h" 18 #include "llvm/CodeGen/MachineRegisterInfo.h" 19 #include "llvm/CodeGen/TargetOpcodes.h" 20 #include "llvm/CodeGen/ValueTypes.h" 21 #include "llvm/IR/DerivedTypes.h" 22 #include "llvm/IR/Type.h" 23 24 using namespace llvm; 25 using namespace LegalizeActions; 26 27 /// FIXME: The following static functions are SizeChangeStrategy functions 28 /// that are meant to temporarily mimic the behaviour of the old legalization 29 /// based on doubling/halving non-legal types as closely as possible. This is 30 /// not entirly possible as only legalizing the types that are exactly a power 31 /// of 2 times the size of the legal types would require specifying all those 32 /// sizes explicitly. 33 /// In practice, not specifying those isn't a problem, and the below functions 34 /// should disappear quickly as we add support for legalizing non-power-of-2 35 /// sized types further. 36 static void addAndInterleaveWithUnsupported( 37 LegacyLegalizerInfo::SizeAndActionsVec &result, 38 const LegacyLegalizerInfo::SizeAndActionsVec &v) { 39 for (unsigned i = 0; i < v.size(); ++i) { 40 result.push_back(v[i]); 41 if (i + 1 < v[i].first && i + 1 < v.size() && 42 v[i + 1].first != v[i].first + 1) 43 result.push_back({v[i].first + 1, LegacyLegalizeActions::Unsupported}); 44 } 45 } 46 47 static LegacyLegalizerInfo::SizeAndActionsVec 48 widen_8_16(const LegacyLegalizerInfo::SizeAndActionsVec &v) { 49 assert(v.size() >= 1); 50 assert(v[0].first > 17); 51 LegacyLegalizerInfo::SizeAndActionsVec result = { 52 {1, LegacyLegalizeActions::Unsupported}, 53 {8, LegacyLegalizeActions::WidenScalar}, 54 {9, LegacyLegalizeActions::Unsupported}, 55 {16, LegacyLegalizeActions::WidenScalar}, 56 {17, LegacyLegalizeActions::Unsupported}}; 57 addAndInterleaveWithUnsupported(result, v); 58 auto Largest = result.back().first; 59 result.push_back({Largest + 1, LegacyLegalizeActions::Unsupported}); 60 return result; 61 } 62 63 static bool AEABI(const ARMSubtarget &ST) { 64 return ST.isTargetAEABI() || ST.isTargetGNUAEABI() || ST.isTargetMuslAEABI(); 65 } 66 67 ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) { 68 using namespace TargetOpcode; 69 70 const LLT p0 = LLT::pointer(0, 32); 71 72 const LLT s1 = LLT::scalar(1); 73 const LLT s8 = LLT::scalar(8); 74 const LLT s16 = LLT::scalar(16); 75 const LLT s32 = LLT::scalar(32); 76 const LLT s64 = LLT::scalar(64); 77 78 auto &LegacyInfo = getLegacyLegalizerInfo(); 79 if (ST.isThumb1Only()) { 80 // Thumb1 is not supported yet. 81 LegacyInfo.computeTables(); 82 verify(*ST.getInstrInfo()); 83 return; 84 } 85 86 getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT}) 87 .legalForCartesianProduct({s8, s16, s32}, {s1, s8, s16}); 88 89 getActionDefinitionsBuilder(G_SEXT_INREG).lower(); 90 91 getActionDefinitionsBuilder({G_MUL, G_AND, G_OR, G_XOR}) 92 .legalFor({s32}) 93 .clampScalar(0, s32, s32); 94 95 if (ST.hasNEON()) 96 getActionDefinitionsBuilder({G_ADD, G_SUB}) 97 .legalFor({s32, s64}) 98 .minScalar(0, s32); 99 else 100 getActionDefinitionsBuilder({G_ADD, G_SUB}) 101 .legalFor({s32}) 102 .minScalar(0, s32); 103 104 getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL}) 105 .legalFor({{s32, s32}}) 106 .minScalar(0, s32) 107 .clampScalar(1, s32, s32); 108 109 bool HasHWDivide = (!ST.isThumb() && ST.hasDivideInARMMode()) || 110 (ST.isThumb() && ST.hasDivideInThumbMode()); 111 if (HasHWDivide) 112 getActionDefinitionsBuilder({G_SDIV, G_UDIV}) 113 .legalFor({s32}) 114 .clampScalar(0, s32, s32); 115 else 116 getActionDefinitionsBuilder({G_SDIV, G_UDIV}) 117 .libcallFor({s32}) 118 .clampScalar(0, s32, s32); 119 120 for (unsigned Op : {G_SREM, G_UREM}) { 121 LegacyInfo.setLegalizeScalarToDifferentSizeStrategy(Op, 0, widen_8_16); 122 if (HasHWDivide) 123 LegacyInfo.setAction({Op, s32}, LegacyLegalizeActions::Lower); 124 else if (AEABI(ST)) 125 LegacyInfo.setAction({Op, s32}, LegacyLegalizeActions::Custom); 126 else 127 LegacyInfo.setAction({Op, s32}, LegacyLegalizeActions::Libcall); 128 } 129 130 getActionDefinitionsBuilder(G_INTTOPTR) 131 .legalFor({{p0, s32}}) 132 .minScalar(1, s32); 133 getActionDefinitionsBuilder(G_PTRTOINT) 134 .legalFor({{s32, p0}}) 135 .minScalar(0, s32); 136 137 getActionDefinitionsBuilder(G_CONSTANT) 138 .legalFor({s32, p0}) 139 .clampScalar(0, s32, s32); 140 141 getActionDefinitionsBuilder(G_ICMP) 142 .legalForCartesianProduct({s1}, {s32, p0}) 143 .minScalar(1, s32); 144 145 getActionDefinitionsBuilder(G_SELECT) 146 .legalForCartesianProduct({s32, p0}, {s1}) 147 .minScalar(0, s32); 148 149 // We're keeping these builders around because we'll want to add support for 150 // floating point to them. 151 auto &LoadStoreBuilder = getActionDefinitionsBuilder({G_LOAD, G_STORE}) 152 .legalForTypesWithMemDesc({{s1, p0, 8, 8}, 153 {s8, p0, 8, 8}, 154 {s16, p0, 16, 8}, 155 {s32, p0, 32, 8}, 156 {p0, p0, 32, 8}}) 157 .unsupportedIfMemSizeNotPow2(); 158 159 getActionDefinitionsBuilder(G_FRAME_INDEX).legalFor({p0}); 160 getActionDefinitionsBuilder(G_GLOBAL_VALUE).legalFor({p0}); 161 162 auto &PhiBuilder = 163 getActionDefinitionsBuilder(G_PHI) 164 .legalFor({s32, p0}) 165 .minScalar(0, s32); 166 167 getActionDefinitionsBuilder(G_PTR_ADD) 168 .legalFor({{p0, s32}}) 169 .minScalar(1, s32); 170 171 getActionDefinitionsBuilder(G_BRCOND).legalFor({s1}); 172 173 if (!ST.useSoftFloat() && ST.hasVFP2Base()) { 174 getActionDefinitionsBuilder( 175 {G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FCONSTANT, G_FNEG}) 176 .legalFor({s32, s64}); 177 178 LoadStoreBuilder 179 .legalForTypesWithMemDesc({{s64, p0, 64, 32}}) 180 .maxScalar(0, s32); 181 PhiBuilder.legalFor({s64}); 182 183 getActionDefinitionsBuilder(G_FCMP).legalForCartesianProduct({s1}, 184 {s32, s64}); 185 186 getActionDefinitionsBuilder(G_MERGE_VALUES).legalFor({{s64, s32}}); 187 getActionDefinitionsBuilder(G_UNMERGE_VALUES).legalFor({{s32, s64}}); 188 189 getActionDefinitionsBuilder(G_FPEXT).legalFor({{s64, s32}}); 190 getActionDefinitionsBuilder(G_FPTRUNC).legalFor({{s32, s64}}); 191 192 getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI}) 193 .legalForCartesianProduct({s32}, {s32, s64}); 194 getActionDefinitionsBuilder({G_SITOFP, G_UITOFP}) 195 .legalForCartesianProduct({s32, s64}, {s32}); 196 } else { 197 getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV}) 198 .libcallFor({s32, s64}); 199 200 LoadStoreBuilder.maxScalar(0, s32); 201 202 for (auto Ty : {s32, s64}) 203 LegacyInfo.setAction({G_FNEG, Ty}, LegacyLegalizeActions::Lower); 204 205 getActionDefinitionsBuilder(G_FCONSTANT).customFor({s32, s64}); 206 207 getActionDefinitionsBuilder(G_FCMP).customForCartesianProduct({s1}, 208 {s32, s64}); 209 210 if (AEABI(ST)) 211 setFCmpLibcallsAEABI(); 212 else 213 setFCmpLibcallsGNU(); 214 215 getActionDefinitionsBuilder(G_FPEXT).libcallFor({{s64, s32}}); 216 getActionDefinitionsBuilder(G_FPTRUNC).libcallFor({{s32, s64}}); 217 218 getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI}) 219 .libcallForCartesianProduct({s32}, {s32, s64}); 220 getActionDefinitionsBuilder({G_SITOFP, G_UITOFP}) 221 .libcallForCartesianProduct({s32, s64}, {s32}); 222 } 223 224 if (!ST.useSoftFloat() && ST.hasVFP4Base()) 225 getActionDefinitionsBuilder(G_FMA).legalFor({s32, s64}); 226 else 227 getActionDefinitionsBuilder(G_FMA).libcallFor({s32, s64}); 228 229 getActionDefinitionsBuilder({G_FREM, G_FPOW}).libcallFor({s32, s64}); 230 231 if (ST.hasV5TOps()) { 232 getActionDefinitionsBuilder(G_CTLZ) 233 .legalFor({s32, s32}) 234 .clampScalar(1, s32, s32) 235 .clampScalar(0, s32, s32); 236 getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF) 237 .lowerFor({s32, s32}) 238 .clampScalar(1, s32, s32) 239 .clampScalar(0, s32, s32); 240 } else { 241 getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF) 242 .libcallFor({s32, s32}) 243 .clampScalar(1, s32, s32) 244 .clampScalar(0, s32, s32); 245 getActionDefinitionsBuilder(G_CTLZ) 246 .lowerFor({s32, s32}) 247 .clampScalar(1, s32, s32) 248 .clampScalar(0, s32, s32); 249 } 250 251 LegacyInfo.computeTables(); 252 verify(*ST.getInstrInfo()); 253 } 254 255 void ARMLegalizerInfo::setFCmpLibcallsAEABI() { 256 // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be 257 // default-initialized. 258 FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 259 FCmp32Libcalls[CmpInst::FCMP_OEQ] = { 260 {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE}}; 261 FCmp32Libcalls[CmpInst::FCMP_OGE] = { 262 {RTLIB::OGE_F32, CmpInst::BAD_ICMP_PREDICATE}}; 263 FCmp32Libcalls[CmpInst::FCMP_OGT] = { 264 {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE}}; 265 FCmp32Libcalls[CmpInst::FCMP_OLE] = { 266 {RTLIB::OLE_F32, CmpInst::BAD_ICMP_PREDICATE}}; 267 FCmp32Libcalls[CmpInst::FCMP_OLT] = { 268 {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}}; 269 FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::UO_F32, CmpInst::ICMP_EQ}}; 270 FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_EQ}}; 271 FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_EQ}}; 272 FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_EQ}}; 273 FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_EQ}}; 274 FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_EQ}}; 275 FCmp32Libcalls[CmpInst::FCMP_UNO] = { 276 {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}}; 277 FCmp32Libcalls[CmpInst::FCMP_ONE] = { 278 {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE}, 279 {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}}; 280 FCmp32Libcalls[CmpInst::FCMP_UEQ] = { 281 {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE}, 282 {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}}; 283 284 FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 285 FCmp64Libcalls[CmpInst::FCMP_OEQ] = { 286 {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE}}; 287 FCmp64Libcalls[CmpInst::FCMP_OGE] = { 288 {RTLIB::OGE_F64, CmpInst::BAD_ICMP_PREDICATE}}; 289 FCmp64Libcalls[CmpInst::FCMP_OGT] = { 290 {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE}}; 291 FCmp64Libcalls[CmpInst::FCMP_OLE] = { 292 {RTLIB::OLE_F64, CmpInst::BAD_ICMP_PREDICATE}}; 293 FCmp64Libcalls[CmpInst::FCMP_OLT] = { 294 {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}}; 295 FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::UO_F64, CmpInst::ICMP_EQ}}; 296 FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_EQ}}; 297 FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_EQ}}; 298 FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_EQ}}; 299 FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_EQ}}; 300 FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_EQ}}; 301 FCmp64Libcalls[CmpInst::FCMP_UNO] = { 302 {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}}; 303 FCmp64Libcalls[CmpInst::FCMP_ONE] = { 304 {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE}, 305 {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}}; 306 FCmp64Libcalls[CmpInst::FCMP_UEQ] = { 307 {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE}, 308 {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}}; 309 } 310 311 void ARMLegalizerInfo::setFCmpLibcallsGNU() { 312 // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be 313 // default-initialized. 314 FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 315 FCmp32Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ}}; 316 FCmp32Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F32, CmpInst::ICMP_SGE}}; 317 FCmp32Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT}}; 318 FCmp32Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F32, CmpInst::ICMP_SLE}}; 319 FCmp32Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F32, CmpInst::ICMP_SLT}}; 320 FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::UO_F32, CmpInst::ICMP_EQ}}; 321 FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_SGE}}; 322 FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_SGT}}; 323 FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SLE}}; 324 FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_SLT}}; 325 FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_NE}}; 326 FCmp32Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F32, CmpInst::ICMP_NE}}; 327 FCmp32Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT}, 328 {RTLIB::OLT_F32, CmpInst::ICMP_SLT}}; 329 FCmp32Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ}, 330 {RTLIB::UO_F32, CmpInst::ICMP_NE}}; 331 332 FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 333 FCmp64Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ}}; 334 FCmp64Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F64, CmpInst::ICMP_SGE}}; 335 FCmp64Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT}}; 336 FCmp64Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F64, CmpInst::ICMP_SLE}}; 337 FCmp64Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F64, CmpInst::ICMP_SLT}}; 338 FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::UO_F64, CmpInst::ICMP_EQ}}; 339 FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_SGE}}; 340 FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_SGT}}; 341 FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SLE}}; 342 FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_SLT}}; 343 FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_NE}}; 344 FCmp64Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F64, CmpInst::ICMP_NE}}; 345 FCmp64Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT}, 346 {RTLIB::OLT_F64, CmpInst::ICMP_SLT}}; 347 FCmp64Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ}, 348 {RTLIB::UO_F64, CmpInst::ICMP_NE}}; 349 } 350 351 ARMLegalizerInfo::FCmpLibcallsList 352 ARMLegalizerInfo::getFCmpLibcalls(CmpInst::Predicate Predicate, 353 unsigned Size) const { 354 assert(CmpInst::isFPPredicate(Predicate) && "Unsupported FCmp predicate"); 355 if (Size == 32) 356 return FCmp32Libcalls[Predicate]; 357 if (Size == 64) 358 return FCmp64Libcalls[Predicate]; 359 llvm_unreachable("Unsupported size for FCmp predicate"); 360 } 361 362 bool ARMLegalizerInfo::legalizeCustom(LegalizerHelper &Helper, 363 MachineInstr &MI) const { 364 using namespace TargetOpcode; 365 366 MachineIRBuilder &MIRBuilder = Helper.MIRBuilder; 367 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); 368 LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext(); 369 370 switch (MI.getOpcode()) { 371 default: 372 return false; 373 case G_SREM: 374 case G_UREM: { 375 Register OriginalResult = MI.getOperand(0).getReg(); 376 auto Size = MRI.getType(OriginalResult).getSizeInBits(); 377 if (Size != 32) 378 return false; 379 380 auto Libcall = 381 MI.getOpcode() == G_SREM ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; 382 383 // Our divmod libcalls return a struct containing the quotient and the 384 // remainder. Create a new, unused register for the quotient and use the 385 // destination of the original instruction for the remainder. 386 Type *ArgTy = Type::getInt32Ty(Ctx); 387 StructType *RetTy = StructType::get(Ctx, {ArgTy, ArgTy}, /* Packed */ true); 388 Register RetRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)), 389 OriginalResult}; 390 auto Status = createLibcall(MIRBuilder, Libcall, {RetRegs, RetTy}, 391 {{MI.getOperand(1).getReg(), ArgTy}, 392 {MI.getOperand(2).getReg(), ArgTy}}); 393 if (Status != LegalizerHelper::Legalized) 394 return false; 395 break; 396 } 397 case G_FCMP: { 398 assert(MRI.getType(MI.getOperand(2).getReg()) == 399 MRI.getType(MI.getOperand(3).getReg()) && 400 "Mismatched operands for G_FCMP"); 401 auto OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); 402 403 auto OriginalResult = MI.getOperand(0).getReg(); 404 auto Predicate = 405 static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()); 406 auto Libcalls = getFCmpLibcalls(Predicate, OpSize); 407 408 if (Libcalls.empty()) { 409 assert((Predicate == CmpInst::FCMP_TRUE || 410 Predicate == CmpInst::FCMP_FALSE) && 411 "Predicate needs libcalls, but none specified"); 412 MIRBuilder.buildConstant(OriginalResult, 413 Predicate == CmpInst::FCMP_TRUE ? 1 : 0); 414 MI.eraseFromParent(); 415 return true; 416 } 417 418 assert((OpSize == 32 || OpSize == 64) && "Unsupported operand size"); 419 auto *ArgTy = OpSize == 32 ? Type::getFloatTy(Ctx) : Type::getDoubleTy(Ctx); 420 auto *RetTy = Type::getInt32Ty(Ctx); 421 422 SmallVector<Register, 2> Results; 423 for (auto Libcall : Libcalls) { 424 auto LibcallResult = MRI.createGenericVirtualRegister(LLT::scalar(32)); 425 auto Status = 426 createLibcall(MIRBuilder, Libcall.LibcallID, {LibcallResult, RetTy}, 427 {{MI.getOperand(2).getReg(), ArgTy}, 428 {MI.getOperand(3).getReg(), ArgTy}}); 429 430 if (Status != LegalizerHelper::Legalized) 431 return false; 432 433 auto ProcessedResult = 434 Libcalls.size() == 1 435 ? OriginalResult 436 : MRI.createGenericVirtualRegister(MRI.getType(OriginalResult)); 437 438 // We have a result, but we need to transform it into a proper 1-bit 0 or 439 // 1, taking into account the different peculiarities of the values 440 // returned by the comparison functions. 441 CmpInst::Predicate ResultPred = Libcall.Predicate; 442 if (ResultPred == CmpInst::BAD_ICMP_PREDICATE) { 443 // We have a nice 0 or 1, and we just need to truncate it back to 1 bit 444 // to keep the types consistent. 445 MIRBuilder.buildTrunc(ProcessedResult, LibcallResult); 446 } else { 447 // We need to compare against 0. 448 assert(CmpInst::isIntPredicate(ResultPred) && "Unsupported predicate"); 449 auto Zero = MIRBuilder.buildConstant(LLT::scalar(32), 0); 450 MIRBuilder.buildICmp(ResultPred, ProcessedResult, LibcallResult, Zero); 451 } 452 Results.push_back(ProcessedResult); 453 } 454 455 if (Results.size() != 1) { 456 assert(Results.size() == 2 && "Unexpected number of results"); 457 MIRBuilder.buildOr(OriginalResult, Results[0], Results[1]); 458 } 459 break; 460 } 461 case G_FCONSTANT: { 462 // Convert to integer constants, while preserving the binary representation. 463 auto AsInteger = 464 MI.getOperand(1).getFPImm()->getValueAPF().bitcastToAPInt(); 465 MIRBuilder.buildConstant(MI.getOperand(0), 466 *ConstantInt::get(Ctx, AsInteger)); 467 break; 468 } 469 } 470 471 MI.eraseFromParent(); 472 return true; 473 } 474