1 //===- ARMLegalizerInfo.cpp --------------------------------------*- C++ -*-==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// \file 10 /// This file implements the targeting of the Machinelegalizer class for ARM. 11 /// \todo This should be generated by TableGen. 12 //===----------------------------------------------------------------------===// 13 14 #include "ARMLegalizerInfo.h" 15 #include "ARMCallLowering.h" 16 #include "ARMSubtarget.h" 17 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h" 18 #include "llvm/CodeGen/LowLevelType.h" 19 #include "llvm/CodeGen/MachineRegisterInfo.h" 20 #include "llvm/CodeGen/ValueTypes.h" 21 #include "llvm/IR/DerivedTypes.h" 22 #include "llvm/IR/Type.h" 23 #include "llvm/Target/TargetOpcodes.h" 24 25 using namespace llvm; 26 27 #ifndef LLVM_BUILD_GLOBAL_ISEL 28 #error "You shouldn't build this" 29 #endif 30 31 static bool AEABI(const ARMSubtarget &ST) { 32 return ST.isTargetAEABI() || ST.isTargetGNUAEABI() || ST.isTargetMuslAEABI(); 33 } 34 35 ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) { 36 using namespace TargetOpcode; 37 38 const LLT p0 = LLT::pointer(0, 32); 39 40 const LLT s1 = LLT::scalar(1); 41 const LLT s8 = LLT::scalar(8); 42 const LLT s16 = LLT::scalar(16); 43 const LLT s32 = LLT::scalar(32); 44 const LLT s64 = LLT::scalar(64); 45 46 setAction({G_FRAME_INDEX, p0}, Legal); 47 48 for (unsigned Op : {G_LOAD, G_STORE}) { 49 for (auto Ty : {s1, s8, s16, s32, p0}) 50 setAction({Op, Ty}, Legal); 51 setAction({Op, 1, p0}, Legal); 52 } 53 54 for (unsigned Op : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR}) { 55 for (auto Ty : {s1, s8, s16}) 56 setAction({Op, Ty}, WidenScalar); 57 setAction({Op, s32}, Legal); 58 } 59 60 for (unsigned Op : {G_SDIV, G_UDIV}) { 61 for (auto Ty : {s8, s16}) 62 setAction({Op, Ty}, WidenScalar); 63 if (ST.hasDivideInARMMode()) 64 setAction({Op, s32}, Legal); 65 else 66 setAction({Op, s32}, Libcall); 67 } 68 69 // FIXME: Support s8 and s16 as well 70 for (unsigned Op : {G_SREM, G_UREM}) 71 if (ST.hasDivideInARMMode()) 72 setAction({Op, s32}, Lower); 73 else if (AEABI(ST)) 74 setAction({Op, s32}, Custom); 75 else 76 setAction({Op, s32}, Libcall); 77 78 for (unsigned Op : {G_SEXT, G_ZEXT}) { 79 setAction({Op, s32}, Legal); 80 for (auto Ty : {s1, s8, s16}) 81 setAction({Op, 1, Ty}, Legal); 82 } 83 84 setAction({G_GEP, p0}, Legal); 85 setAction({G_GEP, 1, s32}, Legal); 86 87 setAction({G_SELECT, s32}, Legal); 88 setAction({G_SELECT, p0}, Legal); 89 setAction({G_SELECT, 1, s1}, Legal); 90 91 setAction({G_BRCOND, s1}, Legal); 92 93 setAction({G_CONSTANT, s32}, Legal); 94 for (auto Ty : {s1, s8, s16}) 95 setAction({G_CONSTANT, Ty}, WidenScalar); 96 97 setAction({G_ICMP, s1}, Legal); 98 for (auto Ty : {s8, s16}) 99 setAction({G_ICMP, 1, Ty}, WidenScalar); 100 for (auto Ty : {s32, p0}) 101 setAction({G_ICMP, 1, Ty}, Legal); 102 103 if (!ST.useSoftFloat() && ST.hasVFP2()) { 104 setAction({G_FADD, s32}, Legal); 105 setAction({G_FADD, s64}, Legal); 106 107 setAction({G_LOAD, s64}, Legal); 108 setAction({G_STORE, s64}, Legal); 109 110 setAction({G_FCMP, s1}, Legal); 111 setAction({G_FCMP, 1, s32}, Legal); 112 setAction({G_FCMP, 1, s64}, Legal); 113 } else { 114 for (auto Ty : {s32, s64}) 115 setAction({G_FADD, Ty}, Libcall); 116 117 setAction({G_FCMP, s1}, Legal); 118 setAction({G_FCMP, 1, s32}, Custom); 119 setAction({G_FCMP, 1, s64}, Custom); 120 121 if (AEABI(ST)) 122 setFCmpLibcallsAEABI(); 123 else 124 setFCmpLibcallsGNU(); 125 } 126 127 for (unsigned Op : {G_FREM, G_FPOW}) 128 for (auto Ty : {s32, s64}) 129 setAction({Op, Ty}, Libcall); 130 131 computeTables(); 132 } 133 134 void ARMLegalizerInfo::setFCmpLibcallsAEABI() { 135 // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be 136 // default-initialized. 137 FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 138 FCmp32Libcalls[CmpInst::FCMP_OEQ] = { 139 {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE}}; 140 FCmp32Libcalls[CmpInst::FCMP_OGE] = { 141 {RTLIB::OGE_F32, CmpInst::BAD_ICMP_PREDICATE}}; 142 FCmp32Libcalls[CmpInst::FCMP_OGT] = { 143 {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE}}; 144 FCmp32Libcalls[CmpInst::FCMP_OLE] = { 145 {RTLIB::OLE_F32, CmpInst::BAD_ICMP_PREDICATE}}; 146 FCmp32Libcalls[CmpInst::FCMP_OLT] = { 147 {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}}; 148 FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}}; 149 FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_EQ}}; 150 FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_EQ}}; 151 FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_EQ}}; 152 FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_EQ}}; 153 FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_EQ}}; 154 FCmp32Libcalls[CmpInst::FCMP_UNO] = { 155 {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}}; 156 FCmp32Libcalls[CmpInst::FCMP_ONE] = { 157 {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE}, 158 {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}}; 159 FCmp32Libcalls[CmpInst::FCMP_UEQ] = { 160 {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE}, 161 {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}}; 162 163 FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 164 FCmp64Libcalls[CmpInst::FCMP_OEQ] = { 165 {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE}}; 166 FCmp64Libcalls[CmpInst::FCMP_OGE] = { 167 {RTLIB::OGE_F64, CmpInst::BAD_ICMP_PREDICATE}}; 168 FCmp64Libcalls[CmpInst::FCMP_OGT] = { 169 {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE}}; 170 FCmp64Libcalls[CmpInst::FCMP_OLE] = { 171 {RTLIB::OLE_F64, CmpInst::BAD_ICMP_PREDICATE}}; 172 FCmp64Libcalls[CmpInst::FCMP_OLT] = { 173 {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}}; 174 FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}}; 175 FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_EQ}}; 176 FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_EQ}}; 177 FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_EQ}}; 178 FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_EQ}}; 179 FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_EQ}}; 180 FCmp64Libcalls[CmpInst::FCMP_UNO] = { 181 {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}}; 182 FCmp64Libcalls[CmpInst::FCMP_ONE] = { 183 {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE}, 184 {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}}; 185 FCmp64Libcalls[CmpInst::FCMP_UEQ] = { 186 {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE}, 187 {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}}; 188 } 189 190 void ARMLegalizerInfo::setFCmpLibcallsGNU() { 191 // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be 192 // default-initialized. 193 FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 194 FCmp32Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ}}; 195 FCmp32Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F32, CmpInst::ICMP_SGE}}; 196 FCmp32Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT}}; 197 FCmp32Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F32, CmpInst::ICMP_SLE}}; 198 FCmp32Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F32, CmpInst::ICMP_SLT}}; 199 FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}}; 200 FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_SGE}}; 201 FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_SGT}}; 202 FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SLE}}; 203 FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_SLT}}; 204 FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_NE}}; 205 FCmp32Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F32, CmpInst::ICMP_NE}}; 206 FCmp32Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT}, 207 {RTLIB::OLT_F32, CmpInst::ICMP_SLT}}; 208 FCmp32Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ}, 209 {RTLIB::UO_F32, CmpInst::ICMP_NE}}; 210 211 FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 212 FCmp64Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ}}; 213 FCmp64Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F64, CmpInst::ICMP_SGE}}; 214 FCmp64Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT}}; 215 FCmp64Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F64, CmpInst::ICMP_SLE}}; 216 FCmp64Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F64, CmpInst::ICMP_SLT}}; 217 FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}}; 218 FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_SGE}}; 219 FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_SGT}}; 220 FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SLE}}; 221 FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_SLT}}; 222 FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_NE}}; 223 FCmp64Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F64, CmpInst::ICMP_NE}}; 224 FCmp64Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT}, 225 {RTLIB::OLT_F64, CmpInst::ICMP_SLT}}; 226 FCmp64Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ}, 227 {RTLIB::UO_F64, CmpInst::ICMP_NE}}; 228 } 229 230 ARMLegalizerInfo::FCmpLibcallsList 231 ARMLegalizerInfo::getFCmpLibcalls(CmpInst::Predicate Predicate, 232 unsigned Size) const { 233 assert(CmpInst::isFPPredicate(Predicate) && "Unsupported FCmp predicate"); 234 if (Size == 32) 235 return FCmp32Libcalls[Predicate]; 236 if (Size == 64) 237 return FCmp64Libcalls[Predicate]; 238 llvm_unreachable("Unsupported size for FCmp predicate"); 239 } 240 241 bool ARMLegalizerInfo::legalizeCustom(MachineInstr &MI, 242 MachineRegisterInfo &MRI, 243 MachineIRBuilder &MIRBuilder) const { 244 using namespace TargetOpcode; 245 246 MIRBuilder.setInstr(MI); 247 248 switch (MI.getOpcode()) { 249 default: 250 return false; 251 case G_SREM: 252 case G_UREM: { 253 unsigned OriginalResult = MI.getOperand(0).getReg(); 254 auto Size = MRI.getType(OriginalResult).getSizeInBits(); 255 if (Size != 32) 256 return false; 257 258 auto Libcall = 259 MI.getOpcode() == G_SREM ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; 260 261 // Our divmod libcalls return a struct containing the quotient and the 262 // remainder. We need to create a virtual register for it. 263 auto &Ctx = MIRBuilder.getMF().getFunction()->getContext(); 264 Type *ArgTy = Type::getInt32Ty(Ctx); 265 StructType *RetTy = StructType::get(Ctx, {ArgTy, ArgTy}, /* Packed */ true); 266 auto RetVal = MRI.createGenericVirtualRegister( 267 getLLTForType(*RetTy, MIRBuilder.getMF().getDataLayout())); 268 269 auto Status = createLibcall(MIRBuilder, Libcall, {RetVal, RetTy}, 270 {{MI.getOperand(1).getReg(), ArgTy}, 271 {MI.getOperand(2).getReg(), ArgTy}}); 272 if (Status != LegalizerHelper::Legalized) 273 return false; 274 275 // The remainder is the second result of divmod. Split the return value into 276 // a new, unused register for the quotient and the destination of the 277 // original instruction for the remainder. 278 MIRBuilder.buildUnmerge( 279 {MRI.createGenericVirtualRegister(LLT::scalar(32)), OriginalResult}, 280 RetVal); 281 break; 282 } 283 case G_FCMP: { 284 assert(MRI.getType(MI.getOperand(2).getReg()) == 285 MRI.getType(MI.getOperand(3).getReg()) && 286 "Mismatched operands for G_FCMP"); 287 auto OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); 288 289 auto OriginalResult = MI.getOperand(0).getReg(); 290 auto Predicate = 291 static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()); 292 auto Libcalls = getFCmpLibcalls(Predicate, OpSize); 293 294 if (Libcalls.empty()) { 295 assert((Predicate == CmpInst::FCMP_TRUE || 296 Predicate == CmpInst::FCMP_FALSE) && 297 "Predicate needs libcalls, but none specified"); 298 MIRBuilder.buildConstant(OriginalResult, 299 Predicate == CmpInst::FCMP_TRUE ? 1 : 0); 300 MI.eraseFromParent(); 301 return true; 302 } 303 304 auto &Ctx = MIRBuilder.getMF().getFunction()->getContext(); 305 assert((OpSize == 32 || OpSize == 64) && "Unsupported operand size"); 306 auto *ArgTy = OpSize == 32 ? Type::getFloatTy(Ctx) : Type::getDoubleTy(Ctx); 307 auto *RetTy = Type::getInt32Ty(Ctx); 308 309 SmallVector<unsigned, 2> Results; 310 for (auto Libcall : Libcalls) { 311 auto LibcallResult = MRI.createGenericVirtualRegister(LLT::scalar(32)); 312 auto Status = 313 createLibcall(MIRBuilder, Libcall.LibcallID, {LibcallResult, RetTy}, 314 {{MI.getOperand(2).getReg(), ArgTy}, 315 {MI.getOperand(3).getReg(), ArgTy}}); 316 317 if (Status != LegalizerHelper::Legalized) 318 return false; 319 320 auto ProcessedResult = 321 Libcalls.size() == 1 322 ? OriginalResult 323 : MRI.createGenericVirtualRegister(MRI.getType(OriginalResult)); 324 325 // We have a result, but we need to transform it into a proper 1-bit 0 or 326 // 1, taking into account the different peculiarities of the values 327 // returned by the comparison functions. 328 CmpInst::Predicate ResultPred = Libcall.Predicate; 329 if (ResultPred == CmpInst::BAD_ICMP_PREDICATE) { 330 // We have a nice 0 or 1, and we just need to truncate it back to 1 bit 331 // to keep the types consistent. 332 MIRBuilder.buildTrunc(ProcessedResult, LibcallResult); 333 } else { 334 // We need to compare against 0. 335 assert(CmpInst::isIntPredicate(ResultPred) && "Unsupported predicate"); 336 auto Zero = MRI.createGenericVirtualRegister(LLT::scalar(32)); 337 MIRBuilder.buildConstant(Zero, 0); 338 MIRBuilder.buildICmp(ResultPred, ProcessedResult, LibcallResult, Zero); 339 } 340 Results.push_back(ProcessedResult); 341 } 342 343 if (Results.size() != 1) { 344 assert(Results.size() == 2 && "Unexpected number of results"); 345 MIRBuilder.buildOr(OriginalResult, Results[0], Results[1]); 346 } 347 break; 348 } 349 } 350 351 MI.eraseFromParent(); 352 return true; 353 } 354