1 //===- ARMLegalizerInfo.cpp --------------------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements the targeting of the Machinelegalizer class for ARM. 10 /// \todo This should be generated by TableGen. 11 //===----------------------------------------------------------------------===// 12 13 #include "ARMLegalizerInfo.h" 14 #include "ARMCallLowering.h" 15 #include "ARMSubtarget.h" 16 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h" 17 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" 18 #include "llvm/CodeGen/LowLevelTypeUtils.h" 19 #include "llvm/CodeGen/MachineRegisterInfo.h" 20 #include "llvm/CodeGen/TargetOpcodes.h" 21 #include "llvm/CodeGen/ValueTypes.h" 22 #include "llvm/IR/DerivedTypes.h" 23 #include "llvm/IR/Type.h" 24 25 using namespace llvm; 26 using namespace LegalizeActions; 27 28 static bool AEABI(const ARMSubtarget &ST) { 29 return ST.isTargetAEABI() || ST.isTargetGNUAEABI() || ST.isTargetMuslAEABI(); 30 } 31 32 ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) : ST(ST) { 33 using namespace TargetOpcode; 34 35 const LLT p0 = LLT::pointer(0, 32); 36 37 const LLT s1 = LLT::scalar(1); 38 const LLT s8 = LLT::scalar(8); 39 const LLT s16 = LLT::scalar(16); 40 const LLT s32 = LLT::scalar(32); 41 const LLT s64 = LLT::scalar(64); 42 43 auto &LegacyInfo = getLegacyLegalizerInfo(); 44 if (ST.isThumb1Only()) { 45 // Thumb1 is not supported yet. 46 LegacyInfo.computeTables(); 47 verify(*ST.getInstrInfo()); 48 return; 49 } 50 51 getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT}) 52 .legalForCartesianProduct({s8, s16, s32}, {s1, s8, s16}); 53 54 getActionDefinitionsBuilder(G_SEXT_INREG).lower(); 55 56 getActionDefinitionsBuilder({G_MUL, G_AND, G_OR, G_XOR}) 57 .legalFor({s32}) 58 .clampScalar(0, s32, s32); 59 60 if (ST.hasNEON()) 61 getActionDefinitionsBuilder({G_ADD, G_SUB}) 62 .legalFor({s32, s64}) 63 .minScalar(0, s32); 64 else 65 getActionDefinitionsBuilder({G_ADD, G_SUB}) 66 .legalFor({s32}) 67 .minScalar(0, s32); 68 69 getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL}) 70 .legalFor({{s32, s32}}) 71 .minScalar(0, s32) 72 .clampScalar(1, s32, s32); 73 74 bool HasHWDivide = (!ST.isThumb() && ST.hasDivideInARMMode()) || 75 (ST.isThumb() && ST.hasDivideInThumbMode()); 76 if (HasHWDivide) 77 getActionDefinitionsBuilder({G_SDIV, G_UDIV}) 78 .legalFor({s32}) 79 .clampScalar(0, s32, s32); 80 else 81 getActionDefinitionsBuilder({G_SDIV, G_UDIV}) 82 .libcallFor({s32}) 83 .clampScalar(0, s32, s32); 84 85 auto &REMBuilder = 86 getActionDefinitionsBuilder({G_SREM, G_UREM}).minScalar(0, s32); 87 if (HasHWDivide) 88 REMBuilder.lowerFor({s32}); 89 else if (AEABI(ST)) 90 REMBuilder.customFor({s32}); 91 else 92 REMBuilder.libcallFor({s32}); 93 94 getActionDefinitionsBuilder(G_INTTOPTR) 95 .legalFor({{p0, s32}}) 96 .minScalar(1, s32); 97 getActionDefinitionsBuilder(G_PTRTOINT) 98 .legalFor({{s32, p0}}) 99 .minScalar(0, s32); 100 101 getActionDefinitionsBuilder(G_CONSTANT) 102 .customFor({s32, p0}) 103 .clampScalar(0, s32, s32); 104 105 getActionDefinitionsBuilder(G_CONSTANT_POOL).legalFor({p0}); 106 107 getActionDefinitionsBuilder(G_ICMP) 108 .legalForCartesianProduct({s1}, {s32, p0}) 109 .minScalar(1, s32); 110 111 getActionDefinitionsBuilder(G_SELECT) 112 .legalForCartesianProduct({s32, p0}, {s1}) 113 .minScalar(0, s32); 114 115 // We're keeping these builders around because we'll want to add support for 116 // floating point to them. 117 auto &LoadStoreBuilder = getActionDefinitionsBuilder({G_LOAD, G_STORE}) 118 .legalForTypesWithMemDesc({{s8, p0, s8, 8}, 119 {s16, p0, s16, 8}, 120 {s32, p0, s32, 8}, 121 {p0, p0, p0, 8}}) 122 .unsupportedIfMemSizeNotPow2(); 123 124 getActionDefinitionsBuilder(G_FRAME_INDEX).legalFor({p0}); 125 getActionDefinitionsBuilder(G_GLOBAL_VALUE).legalFor({p0}); 126 127 auto &PhiBuilder = 128 getActionDefinitionsBuilder(G_PHI) 129 .legalFor({s32, p0}) 130 .minScalar(0, s32); 131 132 getActionDefinitionsBuilder(G_PTR_ADD) 133 .legalFor({{p0, s32}}) 134 .minScalar(1, s32); 135 136 getActionDefinitionsBuilder(G_BRCOND).legalFor({s1}); 137 138 if (!ST.useSoftFloat() && ST.hasVFP2Base()) { 139 getActionDefinitionsBuilder( 140 {G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FCONSTANT, G_FNEG}) 141 .legalFor({s32, s64}); 142 143 LoadStoreBuilder 144 .legalForTypesWithMemDesc({{s64, p0, s64, 32}}) 145 .maxScalar(0, s32); 146 PhiBuilder.legalFor({s64}); 147 148 getActionDefinitionsBuilder(G_FCMP).legalForCartesianProduct({s1}, 149 {s32, s64}); 150 151 getActionDefinitionsBuilder(G_MERGE_VALUES).legalFor({{s64, s32}}); 152 getActionDefinitionsBuilder(G_UNMERGE_VALUES).legalFor({{s32, s64}}); 153 154 getActionDefinitionsBuilder(G_FPEXT).legalFor({{s64, s32}}); 155 getActionDefinitionsBuilder(G_FPTRUNC).legalFor({{s32, s64}}); 156 157 getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI}) 158 .legalForCartesianProduct({s32}, {s32, s64}); 159 getActionDefinitionsBuilder({G_SITOFP, G_UITOFP}) 160 .legalForCartesianProduct({s32, s64}, {s32}); 161 162 getActionDefinitionsBuilder({G_GET_FPENV, G_SET_FPENV, G_GET_FPMODE}) 163 .legalFor({s32}); 164 getActionDefinitionsBuilder(G_RESET_FPENV).alwaysLegal(); 165 getActionDefinitionsBuilder(G_SET_FPMODE).customFor({s32}); 166 } else { 167 getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV}) 168 .libcallFor({s32, s64}); 169 170 LoadStoreBuilder.maxScalar(0, s32); 171 172 getActionDefinitionsBuilder(G_FNEG).lowerFor({s32, s64}); 173 174 getActionDefinitionsBuilder(G_FCONSTANT).customFor({s32, s64}); 175 176 getActionDefinitionsBuilder(G_FCMP).customForCartesianProduct({s1}, 177 {s32, s64}); 178 179 if (AEABI(ST)) 180 setFCmpLibcallsAEABI(); 181 else 182 setFCmpLibcallsGNU(); 183 184 getActionDefinitionsBuilder(G_FPEXT).libcallFor({{s64, s32}}); 185 getActionDefinitionsBuilder(G_FPTRUNC).libcallFor({{s32, s64}}); 186 187 getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI}) 188 .libcallForCartesianProduct({s32}, {s32, s64}); 189 getActionDefinitionsBuilder({G_SITOFP, G_UITOFP}) 190 .libcallForCartesianProduct({s32, s64}, {s32}); 191 192 getActionDefinitionsBuilder({G_GET_FPENV, G_SET_FPENV, G_RESET_FPENV}) 193 .libcall(); 194 getActionDefinitionsBuilder({G_GET_FPMODE, G_SET_FPMODE, G_RESET_FPMODE}) 195 .libcall(); 196 } 197 198 // Just expand whatever loads and stores are left. 199 LoadStoreBuilder.lower(); 200 201 if (!ST.useSoftFloat() && ST.hasVFP4Base()) 202 getActionDefinitionsBuilder(G_FMA).legalFor({s32, s64}); 203 else 204 getActionDefinitionsBuilder(G_FMA).libcallFor({s32, s64}); 205 206 getActionDefinitionsBuilder({G_FREM, G_FPOW}).libcallFor({s32, s64}); 207 208 if (ST.hasV5TOps()) { 209 getActionDefinitionsBuilder(G_CTLZ) 210 .legalFor({s32, s32}) 211 .clampScalar(1, s32, s32) 212 .clampScalar(0, s32, s32); 213 getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF) 214 .lowerFor({s32, s32}) 215 .clampScalar(1, s32, s32) 216 .clampScalar(0, s32, s32); 217 } else { 218 getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF) 219 .libcallFor({s32, s32}) 220 .clampScalar(1, s32, s32) 221 .clampScalar(0, s32, s32); 222 getActionDefinitionsBuilder(G_CTLZ) 223 .lowerFor({s32, s32}) 224 .clampScalar(1, s32, s32) 225 .clampScalar(0, s32, s32); 226 } 227 228 LegacyInfo.computeTables(); 229 verify(*ST.getInstrInfo()); 230 } 231 232 void ARMLegalizerInfo::setFCmpLibcallsAEABI() { 233 // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be 234 // default-initialized. 235 FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 236 FCmp32Libcalls[CmpInst::FCMP_OEQ] = { 237 {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE}}; 238 FCmp32Libcalls[CmpInst::FCMP_OGE] = { 239 {RTLIB::OGE_F32, CmpInst::BAD_ICMP_PREDICATE}}; 240 FCmp32Libcalls[CmpInst::FCMP_OGT] = { 241 {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE}}; 242 FCmp32Libcalls[CmpInst::FCMP_OLE] = { 243 {RTLIB::OLE_F32, CmpInst::BAD_ICMP_PREDICATE}}; 244 FCmp32Libcalls[CmpInst::FCMP_OLT] = { 245 {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}}; 246 FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::UO_F32, CmpInst::ICMP_EQ}}; 247 FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_EQ}}; 248 FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_EQ}}; 249 FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_EQ}}; 250 FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_EQ}}; 251 FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_EQ}}; 252 FCmp32Libcalls[CmpInst::FCMP_UNO] = { 253 {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}}; 254 FCmp32Libcalls[CmpInst::FCMP_ONE] = { 255 {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE}, 256 {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}}; 257 FCmp32Libcalls[CmpInst::FCMP_UEQ] = { 258 {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE}, 259 {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}}; 260 261 FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 262 FCmp64Libcalls[CmpInst::FCMP_OEQ] = { 263 {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE}}; 264 FCmp64Libcalls[CmpInst::FCMP_OGE] = { 265 {RTLIB::OGE_F64, CmpInst::BAD_ICMP_PREDICATE}}; 266 FCmp64Libcalls[CmpInst::FCMP_OGT] = { 267 {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE}}; 268 FCmp64Libcalls[CmpInst::FCMP_OLE] = { 269 {RTLIB::OLE_F64, CmpInst::BAD_ICMP_PREDICATE}}; 270 FCmp64Libcalls[CmpInst::FCMP_OLT] = { 271 {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}}; 272 FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::UO_F64, CmpInst::ICMP_EQ}}; 273 FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_EQ}}; 274 FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_EQ}}; 275 FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_EQ}}; 276 FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_EQ}}; 277 FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_EQ}}; 278 FCmp64Libcalls[CmpInst::FCMP_UNO] = { 279 {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}}; 280 FCmp64Libcalls[CmpInst::FCMP_ONE] = { 281 {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE}, 282 {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}}; 283 FCmp64Libcalls[CmpInst::FCMP_UEQ] = { 284 {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE}, 285 {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}}; 286 } 287 288 void ARMLegalizerInfo::setFCmpLibcallsGNU() { 289 // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be 290 // default-initialized. 291 FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 292 FCmp32Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ}}; 293 FCmp32Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F32, CmpInst::ICMP_SGE}}; 294 FCmp32Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT}}; 295 FCmp32Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F32, CmpInst::ICMP_SLE}}; 296 FCmp32Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F32, CmpInst::ICMP_SLT}}; 297 FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::UO_F32, CmpInst::ICMP_EQ}}; 298 FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_SGE}}; 299 FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_SGT}}; 300 FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SLE}}; 301 FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_SLT}}; 302 FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_NE}}; 303 FCmp32Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F32, CmpInst::ICMP_NE}}; 304 FCmp32Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT}, 305 {RTLIB::OLT_F32, CmpInst::ICMP_SLT}}; 306 FCmp32Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ}, 307 {RTLIB::UO_F32, CmpInst::ICMP_NE}}; 308 309 FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 310 FCmp64Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ}}; 311 FCmp64Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F64, CmpInst::ICMP_SGE}}; 312 FCmp64Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT}}; 313 FCmp64Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F64, CmpInst::ICMP_SLE}}; 314 FCmp64Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F64, CmpInst::ICMP_SLT}}; 315 FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::UO_F64, CmpInst::ICMP_EQ}}; 316 FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_SGE}}; 317 FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_SGT}}; 318 FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SLE}}; 319 FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_SLT}}; 320 FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_NE}}; 321 FCmp64Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F64, CmpInst::ICMP_NE}}; 322 FCmp64Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT}, 323 {RTLIB::OLT_F64, CmpInst::ICMP_SLT}}; 324 FCmp64Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ}, 325 {RTLIB::UO_F64, CmpInst::ICMP_NE}}; 326 } 327 328 ARMLegalizerInfo::FCmpLibcallsList 329 ARMLegalizerInfo::getFCmpLibcalls(CmpInst::Predicate Predicate, 330 unsigned Size) const { 331 assert(CmpInst::isFPPredicate(Predicate) && "Unsupported FCmp predicate"); 332 if (Size == 32) 333 return FCmp32Libcalls[Predicate]; 334 if (Size == 64) 335 return FCmp64Libcalls[Predicate]; 336 llvm_unreachable("Unsupported size for FCmp predicate"); 337 } 338 339 bool ARMLegalizerInfo::legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI, 340 LostDebugLocObserver &LocObserver) const { 341 using namespace TargetOpcode; 342 343 MachineIRBuilder &MIRBuilder = Helper.MIRBuilder; 344 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); 345 LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext(); 346 347 switch (MI.getOpcode()) { 348 default: 349 return false; 350 case G_SREM: 351 case G_UREM: { 352 Register OriginalResult = MI.getOperand(0).getReg(); 353 auto Size = MRI.getType(OriginalResult).getSizeInBits(); 354 if (Size != 32) 355 return false; 356 357 auto Libcall = 358 MI.getOpcode() == G_SREM ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; 359 360 // Our divmod libcalls return a struct containing the quotient and the 361 // remainder. Create a new, unused register for the quotient and use the 362 // destination of the original instruction for the remainder. 363 Type *ArgTy = Type::getInt32Ty(Ctx); 364 StructType *RetTy = StructType::get(Ctx, {ArgTy, ArgTy}, /* Packed */ true); 365 Register RetRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)), 366 OriginalResult}; 367 auto Status = createLibcall(MIRBuilder, Libcall, {RetRegs, RetTy, 0}, 368 {{MI.getOperand(1).getReg(), ArgTy, 0}, 369 {MI.getOperand(2).getReg(), ArgTy, 0}}, 370 LocObserver, &MI); 371 if (Status != LegalizerHelper::Legalized) 372 return false; 373 break; 374 } 375 case G_FCMP: { 376 assert(MRI.getType(MI.getOperand(2).getReg()) == 377 MRI.getType(MI.getOperand(3).getReg()) && 378 "Mismatched operands for G_FCMP"); 379 auto OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); 380 381 auto OriginalResult = MI.getOperand(0).getReg(); 382 auto Predicate = 383 static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()); 384 auto Libcalls = getFCmpLibcalls(Predicate, OpSize); 385 386 if (Libcalls.empty()) { 387 assert((Predicate == CmpInst::FCMP_TRUE || 388 Predicate == CmpInst::FCMP_FALSE) && 389 "Predicate needs libcalls, but none specified"); 390 MIRBuilder.buildConstant(OriginalResult, 391 Predicate == CmpInst::FCMP_TRUE ? 1 : 0); 392 MI.eraseFromParent(); 393 return true; 394 } 395 396 assert((OpSize == 32 || OpSize == 64) && "Unsupported operand size"); 397 auto *ArgTy = OpSize == 32 ? Type::getFloatTy(Ctx) : Type::getDoubleTy(Ctx); 398 auto *RetTy = Type::getInt32Ty(Ctx); 399 400 SmallVector<Register, 2> Results; 401 for (auto Libcall : Libcalls) { 402 auto LibcallResult = MRI.createGenericVirtualRegister(LLT::scalar(32)); 403 auto Status = createLibcall(MIRBuilder, Libcall.LibcallID, 404 {LibcallResult, RetTy, 0}, 405 {{MI.getOperand(2).getReg(), ArgTy, 0}, 406 {MI.getOperand(3).getReg(), ArgTy, 0}}, 407 LocObserver, &MI); 408 409 if (Status != LegalizerHelper::Legalized) 410 return false; 411 412 auto ProcessedResult = 413 Libcalls.size() == 1 414 ? OriginalResult 415 : MRI.createGenericVirtualRegister(MRI.getType(OriginalResult)); 416 417 // We have a result, but we need to transform it into a proper 1-bit 0 or 418 // 1, taking into account the different peculiarities of the values 419 // returned by the comparison functions. 420 CmpInst::Predicate ResultPred = Libcall.Predicate; 421 if (ResultPred == CmpInst::BAD_ICMP_PREDICATE) { 422 // We have a nice 0 or 1, and we just need to truncate it back to 1 bit 423 // to keep the types consistent. 424 MIRBuilder.buildTrunc(ProcessedResult, LibcallResult); 425 } else { 426 // We need to compare against 0. 427 assert(CmpInst::isIntPredicate(ResultPred) && "Unsupported predicate"); 428 auto Zero = MIRBuilder.buildConstant(LLT::scalar(32), 0); 429 MIRBuilder.buildICmp(ResultPred, ProcessedResult, LibcallResult, Zero); 430 } 431 Results.push_back(ProcessedResult); 432 } 433 434 if (Results.size() != 1) { 435 assert(Results.size() == 2 && "Unexpected number of results"); 436 MIRBuilder.buildOr(OriginalResult, Results[0], Results[1]); 437 } 438 break; 439 } 440 case G_CONSTANT: { 441 const ConstantInt *ConstVal = MI.getOperand(1).getCImm(); 442 uint64_t ImmVal = ConstVal->getZExtValue(); 443 if (ConstantMaterializationCost(ImmVal, &ST) > 2 && !ST.genExecuteOnly()) 444 return Helper.lowerConstant(MI) == LegalizerHelper::Legalized; 445 return true; 446 } 447 case G_FCONSTANT: { 448 // Convert to integer constants, while preserving the binary representation. 449 auto AsInteger = 450 MI.getOperand(1).getFPImm()->getValueAPF().bitcastToAPInt(); 451 MIRBuilder.buildConstant(MI.getOperand(0), 452 *ConstantInt::get(Ctx, AsInteger)); 453 break; 454 } 455 case G_SET_FPMODE: { 456 // New FPSCR = (FPSCR & FPStatusBits) | (Modes & ~FPStatusBits) 457 LLT FPEnvTy = LLT::scalar(32); 458 auto FPEnv = MRI.createGenericVirtualRegister(FPEnvTy); 459 Register Modes = MI.getOperand(0).getReg(); 460 MIRBuilder.buildGetFPEnv(FPEnv); 461 auto StatusBitMask = MIRBuilder.buildConstant(FPEnvTy, ARM::FPStatusBits); 462 auto StatusBits = MIRBuilder.buildAnd(FPEnvTy, FPEnv, StatusBitMask); 463 auto NotStatusBitMask = 464 MIRBuilder.buildConstant(FPEnvTy, ~ARM::FPStatusBits); 465 auto FPModeBits = MIRBuilder.buildAnd(FPEnvTy, Modes, NotStatusBitMask); 466 auto NewFPSCR = MIRBuilder.buildOr(FPEnvTy, StatusBits, FPModeBits); 467 MIRBuilder.buildSetFPEnv(NewFPSCR); 468 break; 469 } 470 } 471 472 MI.eraseFromParent(); 473 return true; 474 } 475