1 //===- ARMLegalizerInfo.cpp --------------------------------------*- C++ -*-==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// \file 10 /// This file implements the targeting of the Machinelegalizer class for ARM. 11 /// \todo This should be generated by TableGen. 12 //===----------------------------------------------------------------------===// 13 14 #include "ARMLegalizerInfo.h" 15 #include "ARMCallLowering.h" 16 #include "ARMSubtarget.h" 17 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h" 18 #include "llvm/CodeGen/LowLevelType.h" 19 #include "llvm/CodeGen/MachineRegisterInfo.h" 20 #include "llvm/CodeGen/ValueTypes.h" 21 #include "llvm/IR/DerivedTypes.h" 22 #include "llvm/IR/Type.h" 23 #include "llvm/Target/TargetOpcodes.h" 24 25 using namespace llvm; 26 27 #ifndef LLVM_BUILD_GLOBAL_ISEL 28 #error "You shouldn't build this" 29 #endif 30 31 static bool AEABI(const ARMSubtarget &ST) { 32 return ST.isTargetAEABI() || ST.isTargetGNUAEABI() || ST.isTargetMuslAEABI(); 33 } 34 35 ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) { 36 using namespace TargetOpcode; 37 38 const LLT p0 = LLT::pointer(0, 32); 39 40 const LLT s1 = LLT::scalar(1); 41 const LLT s8 = LLT::scalar(8); 42 const LLT s16 = LLT::scalar(16); 43 const LLT s32 = LLT::scalar(32); 44 const LLT s64 = LLT::scalar(64); 45 46 setAction({G_FRAME_INDEX, p0}, Legal); 47 48 for (unsigned Op : {G_LOAD, G_STORE}) { 49 for (auto Ty : {s1, s8, s16, s32, p0}) 50 setAction({Op, Ty}, Legal); 51 setAction({Op, 1, p0}, Legal); 52 } 53 54 for (unsigned Op : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR}) { 55 for (auto Ty : {s1, s8, s16}) 56 setAction({Op, Ty}, WidenScalar); 57 setAction({Op, s32}, Legal); 58 } 59 60 for (unsigned Op : {G_SDIV, G_UDIV}) { 61 for (auto Ty : {s8, s16}) 62 setAction({Op, Ty}, WidenScalar); 63 if (ST.hasDivideInARMMode()) 64 setAction({Op, s32}, Legal); 65 else 66 setAction({Op, s32}, Libcall); 67 } 68 69 // FIXME: Support s8 and s16 as well 70 for (unsigned Op : {G_SREM, G_UREM}) 71 if (ST.hasDivideInARMMode()) 72 setAction({Op, s32}, Lower); 73 else if (AEABI(ST)) 74 setAction({Op, s32}, Custom); 75 else 76 setAction({Op, s32}, Libcall); 77 78 for (unsigned Op : {G_SEXT, G_ZEXT}) { 79 setAction({Op, s32}, Legal); 80 for (auto Ty : {s1, s8, s16}) 81 setAction({Op, 1, Ty}, Legal); 82 } 83 84 setAction({G_GEP, p0}, Legal); 85 setAction({G_GEP, 1, s32}, Legal); 86 87 setAction({G_SELECT, s32}, Legal); 88 setAction({G_SELECT, p0}, Legal); 89 setAction({G_SELECT, 1, s1}, Legal); 90 91 setAction({G_CONSTANT, s32}, Legal); 92 for (auto Ty : {s1, s8, s16}) 93 setAction({G_CONSTANT, Ty}, WidenScalar); 94 95 setAction({G_ICMP, s1}, Legal); 96 for (auto Ty : {s8, s16}) 97 setAction({G_ICMP, 1, Ty}, WidenScalar); 98 for (auto Ty : {s32, p0}) 99 setAction({G_ICMP, 1, Ty}, Legal); 100 101 if (!ST.useSoftFloat() && ST.hasVFP2()) { 102 setAction({G_FADD, s32}, Legal); 103 setAction({G_FADD, s64}, Legal); 104 105 setAction({G_LOAD, s64}, Legal); 106 setAction({G_STORE, s64}, Legal); 107 108 setAction({G_FCMP, s1}, Legal); 109 setAction({G_FCMP, 1, s32}, Legal); 110 setAction({G_FCMP, 1, s64}, Legal); 111 } else { 112 for (auto Ty : {s32, s64}) 113 setAction({G_FADD, Ty}, Libcall); 114 115 setAction({G_FCMP, s1}, Legal); 116 setAction({G_FCMP, 1, s32}, Custom); 117 setAction({G_FCMP, 1, s64}, Custom); 118 119 if (AEABI(ST)) 120 setFCmpLibcallsAEABI(); 121 else 122 setFCmpLibcallsGNU(); 123 } 124 125 for (unsigned Op : {G_FREM, G_FPOW}) 126 for (auto Ty : {s32, s64}) 127 setAction({Op, Ty}, Libcall); 128 129 computeTables(); 130 } 131 132 void ARMLegalizerInfo::setFCmpLibcallsAEABI() { 133 // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be 134 // default-initialized. 135 FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 136 FCmp32Libcalls[CmpInst::FCMP_OEQ] = { 137 {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE}}; 138 FCmp32Libcalls[CmpInst::FCMP_OGE] = { 139 {RTLIB::OGE_F32, CmpInst::BAD_ICMP_PREDICATE}}; 140 FCmp32Libcalls[CmpInst::FCMP_OGT] = { 141 {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE}}; 142 FCmp32Libcalls[CmpInst::FCMP_OLE] = { 143 {RTLIB::OLE_F32, CmpInst::BAD_ICMP_PREDICATE}}; 144 FCmp32Libcalls[CmpInst::FCMP_OLT] = { 145 {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}}; 146 FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}}; 147 FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_EQ}}; 148 FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_EQ}}; 149 FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_EQ}}; 150 FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_EQ}}; 151 FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_EQ}}; 152 FCmp32Libcalls[CmpInst::FCMP_UNO] = { 153 {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}}; 154 FCmp32Libcalls[CmpInst::FCMP_ONE] = { 155 {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE}, 156 {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}}; 157 FCmp32Libcalls[CmpInst::FCMP_UEQ] = { 158 {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE}, 159 {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}}; 160 161 FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 162 FCmp64Libcalls[CmpInst::FCMP_OEQ] = { 163 {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE}}; 164 FCmp64Libcalls[CmpInst::FCMP_OGE] = { 165 {RTLIB::OGE_F64, CmpInst::BAD_ICMP_PREDICATE}}; 166 FCmp64Libcalls[CmpInst::FCMP_OGT] = { 167 {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE}}; 168 FCmp64Libcalls[CmpInst::FCMP_OLE] = { 169 {RTLIB::OLE_F64, CmpInst::BAD_ICMP_PREDICATE}}; 170 FCmp64Libcalls[CmpInst::FCMP_OLT] = { 171 {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}}; 172 FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}}; 173 FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_EQ}}; 174 FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_EQ}}; 175 FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_EQ}}; 176 FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_EQ}}; 177 FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_EQ}}; 178 FCmp64Libcalls[CmpInst::FCMP_UNO] = { 179 {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}}; 180 FCmp64Libcalls[CmpInst::FCMP_ONE] = { 181 {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE}, 182 {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}}; 183 FCmp64Libcalls[CmpInst::FCMP_UEQ] = { 184 {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE}, 185 {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}}; 186 } 187 188 void ARMLegalizerInfo::setFCmpLibcallsGNU() { 189 // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be 190 // default-initialized. 191 FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 192 FCmp32Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ}}; 193 FCmp32Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F32, CmpInst::ICMP_SGE}}; 194 FCmp32Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT}}; 195 FCmp32Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F32, CmpInst::ICMP_SLE}}; 196 FCmp32Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F32, CmpInst::ICMP_SLT}}; 197 FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}}; 198 FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_SGE}}; 199 FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_SGT}}; 200 FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SLE}}; 201 FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_SLT}}; 202 FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_NE}}; 203 FCmp32Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F32, CmpInst::ICMP_NE}}; 204 FCmp32Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT}, 205 {RTLIB::OLT_F32, CmpInst::ICMP_SLT}}; 206 FCmp32Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ}, 207 {RTLIB::UO_F32, CmpInst::ICMP_NE}}; 208 209 FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 210 FCmp64Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ}}; 211 FCmp64Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F64, CmpInst::ICMP_SGE}}; 212 FCmp64Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT}}; 213 FCmp64Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F64, CmpInst::ICMP_SLE}}; 214 FCmp64Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F64, CmpInst::ICMP_SLT}}; 215 FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}}; 216 FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_SGE}}; 217 FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_SGT}}; 218 FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SLE}}; 219 FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_SLT}}; 220 FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_NE}}; 221 FCmp64Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F64, CmpInst::ICMP_NE}}; 222 FCmp64Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT}, 223 {RTLIB::OLT_F64, CmpInst::ICMP_SLT}}; 224 FCmp64Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ}, 225 {RTLIB::UO_F64, CmpInst::ICMP_NE}}; 226 } 227 228 ARMLegalizerInfo::FCmpLibcallsList 229 ARMLegalizerInfo::getFCmpLibcalls(CmpInst::Predicate Predicate, 230 unsigned Size) const { 231 assert(CmpInst::isFPPredicate(Predicate) && "Unsupported FCmp predicate"); 232 if (Size == 32) 233 return FCmp32Libcalls[Predicate]; 234 if (Size == 64) 235 return FCmp64Libcalls[Predicate]; 236 llvm_unreachable("Unsupported size for FCmp predicate"); 237 } 238 239 bool ARMLegalizerInfo::legalizeCustom(MachineInstr &MI, 240 MachineRegisterInfo &MRI, 241 MachineIRBuilder &MIRBuilder) const { 242 using namespace TargetOpcode; 243 244 MIRBuilder.setInstr(MI); 245 246 switch (MI.getOpcode()) { 247 default: 248 return false; 249 case G_SREM: 250 case G_UREM: { 251 unsigned OriginalResult = MI.getOperand(0).getReg(); 252 auto Size = MRI.getType(OriginalResult).getSizeInBits(); 253 if (Size != 32) 254 return false; 255 256 auto Libcall = 257 MI.getOpcode() == G_SREM ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; 258 259 // Our divmod libcalls return a struct containing the quotient and the 260 // remainder. We need to create a virtual register for it. 261 auto &Ctx = MIRBuilder.getMF().getFunction()->getContext(); 262 Type *ArgTy = Type::getInt32Ty(Ctx); 263 StructType *RetTy = StructType::get(Ctx, {ArgTy, ArgTy}, /* Packed */ true); 264 auto RetVal = MRI.createGenericVirtualRegister( 265 getLLTForType(*RetTy, MIRBuilder.getMF().getDataLayout())); 266 267 auto Status = createLibcall(MIRBuilder, Libcall, {RetVal, RetTy}, 268 {{MI.getOperand(1).getReg(), ArgTy}, 269 {MI.getOperand(2).getReg(), ArgTy}}); 270 if (Status != LegalizerHelper::Legalized) 271 return false; 272 273 // The remainder is the second result of divmod. Split the return value into 274 // a new, unused register for the quotient and the destination of the 275 // original instruction for the remainder. 276 MIRBuilder.buildUnmerge( 277 {MRI.createGenericVirtualRegister(LLT::scalar(32)), OriginalResult}, 278 RetVal); 279 break; 280 } 281 case G_FCMP: { 282 assert(MRI.getType(MI.getOperand(2).getReg()) == 283 MRI.getType(MI.getOperand(3).getReg()) && 284 "Mismatched operands for G_FCMP"); 285 auto OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); 286 287 auto OriginalResult = MI.getOperand(0).getReg(); 288 auto Predicate = 289 static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()); 290 auto Libcalls = getFCmpLibcalls(Predicate, OpSize); 291 292 if (Libcalls.empty()) { 293 assert((Predicate == CmpInst::FCMP_TRUE || 294 Predicate == CmpInst::FCMP_FALSE) && 295 "Predicate needs libcalls, but none specified"); 296 MIRBuilder.buildConstant(OriginalResult, 297 Predicate == CmpInst::FCMP_TRUE ? 1 : 0); 298 MI.eraseFromParent(); 299 return true; 300 } 301 302 auto &Ctx = MIRBuilder.getMF().getFunction()->getContext(); 303 assert((OpSize == 32 || OpSize == 64) && "Unsupported operand size"); 304 auto *ArgTy = OpSize == 32 ? Type::getFloatTy(Ctx) : Type::getDoubleTy(Ctx); 305 auto *RetTy = Type::getInt32Ty(Ctx); 306 307 SmallVector<unsigned, 2> Results; 308 for (auto Libcall : Libcalls) { 309 auto LibcallResult = MRI.createGenericVirtualRegister(LLT::scalar(32)); 310 auto Status = 311 createLibcall(MIRBuilder, Libcall.LibcallID, {LibcallResult, RetTy}, 312 {{MI.getOperand(2).getReg(), ArgTy}, 313 {MI.getOperand(3).getReg(), ArgTy}}); 314 315 if (Status != LegalizerHelper::Legalized) 316 return false; 317 318 auto ProcessedResult = 319 Libcalls.size() == 1 320 ? OriginalResult 321 : MRI.createGenericVirtualRegister(MRI.getType(OriginalResult)); 322 323 // We have a result, but we need to transform it into a proper 1-bit 0 or 324 // 1, taking into account the different peculiarities of the values 325 // returned by the comparison functions. 326 CmpInst::Predicate ResultPred = Libcall.Predicate; 327 if (ResultPred == CmpInst::BAD_ICMP_PREDICATE) { 328 // We have a nice 0 or 1, and we just need to truncate it back to 1 bit 329 // to keep the types consistent. 330 MIRBuilder.buildTrunc(ProcessedResult, LibcallResult); 331 } else { 332 // We need to compare against 0. 333 assert(CmpInst::isIntPredicate(ResultPred) && "Unsupported predicate"); 334 auto Zero = MRI.createGenericVirtualRegister(LLT::scalar(32)); 335 MIRBuilder.buildConstant(Zero, 0); 336 MIRBuilder.buildICmp(ResultPred, ProcessedResult, LibcallResult, Zero); 337 } 338 Results.push_back(ProcessedResult); 339 } 340 341 if (Results.size() != 1) { 342 assert(Results.size() == 2 && "Unexpected number of results"); 343 MIRBuilder.buildOr(OriginalResult, Results[0], Results[1]); 344 } 345 break; 346 } 347 } 348 349 MI.eraseFromParent(); 350 return true; 351 } 352