1 //===- ARMLegalizerInfo.cpp --------------------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements the targeting of the Machinelegalizer class for ARM. 10 /// \todo This should be generated by TableGen. 11 //===----------------------------------------------------------------------===// 12 13 #include "ARMLegalizerInfo.h" 14 #include "ARMCallLowering.h" 15 #include "ARMSubtarget.h" 16 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h" 17 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" 18 #include "llvm/CodeGen/LowLevelTypeUtils.h" 19 #include "llvm/CodeGen/MachineRegisterInfo.h" 20 #include "llvm/CodeGen/TargetOpcodes.h" 21 #include "llvm/CodeGen/ValueTypes.h" 22 #include "llvm/IR/DerivedTypes.h" 23 #include "llvm/IR/Type.h" 24 25 using namespace llvm; 26 using namespace LegalizeActions; 27 28 static bool AEABI(const ARMSubtarget &ST) { 29 return ST.isTargetAEABI() || ST.isTargetGNUAEABI() || ST.isTargetMuslAEABI(); 30 } 31 32 ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) { 33 using namespace TargetOpcode; 34 35 const LLT p0 = LLT::pointer(0, 32); 36 37 const LLT s1 = LLT::scalar(1); 38 const LLT s8 = LLT::scalar(8); 39 const LLT s16 = LLT::scalar(16); 40 const LLT s32 = LLT::scalar(32); 41 const LLT s64 = LLT::scalar(64); 42 43 auto &LegacyInfo = getLegacyLegalizerInfo(); 44 if (ST.isThumb1Only()) { 45 // Thumb1 is not supported yet. 46 LegacyInfo.computeTables(); 47 verify(*ST.getInstrInfo()); 48 return; 49 } 50 51 getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT}) 52 .legalForCartesianProduct({s8, s16, s32}, {s1, s8, s16}); 53 54 getActionDefinitionsBuilder(G_SEXT_INREG).lower(); 55 56 getActionDefinitionsBuilder({G_MUL, G_AND, G_OR, G_XOR}) 57 .legalFor({s32}) 58 .clampScalar(0, s32, s32); 59 60 if (ST.hasNEON()) 61 getActionDefinitionsBuilder({G_ADD, G_SUB}) 62 .legalFor({s32, s64}) 63 .minScalar(0, s32); 64 else 65 getActionDefinitionsBuilder({G_ADD, G_SUB}) 66 .legalFor({s32}) 67 .minScalar(0, s32); 68 69 getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL}) 70 .legalFor({{s32, s32}}) 71 .minScalar(0, s32) 72 .clampScalar(1, s32, s32); 73 74 bool HasHWDivide = (!ST.isThumb() && ST.hasDivideInARMMode()) || 75 (ST.isThumb() && ST.hasDivideInThumbMode()); 76 if (HasHWDivide) 77 getActionDefinitionsBuilder({G_SDIV, G_UDIV}) 78 .legalFor({s32}) 79 .clampScalar(0, s32, s32); 80 else 81 getActionDefinitionsBuilder({G_SDIV, G_UDIV}) 82 .libcallFor({s32}) 83 .clampScalar(0, s32, s32); 84 85 auto &REMBuilder = 86 getActionDefinitionsBuilder({G_SREM, G_UREM}).minScalar(0, s32); 87 if (HasHWDivide) 88 REMBuilder.lowerFor({s32}); 89 else if (AEABI(ST)) 90 REMBuilder.customFor({s32}); 91 else 92 REMBuilder.libcallFor({s32}); 93 94 getActionDefinitionsBuilder(G_INTTOPTR) 95 .legalFor({{p0, s32}}) 96 .minScalar(1, s32); 97 getActionDefinitionsBuilder(G_PTRTOINT) 98 .legalFor({{s32, p0}}) 99 .minScalar(0, s32); 100 101 getActionDefinitionsBuilder(G_CONSTANT) 102 .legalFor({s32, p0}) 103 .clampScalar(0, s32, s32); 104 105 getActionDefinitionsBuilder(G_ICMP) 106 .legalForCartesianProduct({s1}, {s32, p0}) 107 .minScalar(1, s32); 108 109 getActionDefinitionsBuilder(G_SELECT) 110 .legalForCartesianProduct({s32, p0}, {s1}) 111 .minScalar(0, s32); 112 113 // We're keeping these builders around because we'll want to add support for 114 // floating point to them. 115 auto &LoadStoreBuilder = getActionDefinitionsBuilder({G_LOAD, G_STORE}) 116 .legalForTypesWithMemDesc({{s8, p0, s8, 8}, 117 {s16, p0, s16, 8}, 118 {s32, p0, s32, 8}, 119 {p0, p0, p0, 8}}) 120 .unsupportedIfMemSizeNotPow2(); 121 122 getActionDefinitionsBuilder(G_FRAME_INDEX).legalFor({p0}); 123 getActionDefinitionsBuilder(G_GLOBAL_VALUE).legalFor({p0}); 124 125 auto &PhiBuilder = 126 getActionDefinitionsBuilder(G_PHI) 127 .legalFor({s32, p0}) 128 .minScalar(0, s32); 129 130 getActionDefinitionsBuilder(G_PTR_ADD) 131 .legalFor({{p0, s32}}) 132 .minScalar(1, s32); 133 134 getActionDefinitionsBuilder(G_BRCOND).legalFor({s1}); 135 136 if (!ST.useSoftFloat() && ST.hasVFP2Base()) { 137 getActionDefinitionsBuilder( 138 {G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FCONSTANT, G_FNEG}) 139 .legalFor({s32, s64}); 140 141 LoadStoreBuilder 142 .legalForTypesWithMemDesc({{s64, p0, s64, 32}}) 143 .maxScalar(0, s32); 144 PhiBuilder.legalFor({s64}); 145 146 getActionDefinitionsBuilder(G_FCMP).legalForCartesianProduct({s1}, 147 {s32, s64}); 148 149 getActionDefinitionsBuilder(G_MERGE_VALUES).legalFor({{s64, s32}}); 150 getActionDefinitionsBuilder(G_UNMERGE_VALUES).legalFor({{s32, s64}}); 151 152 getActionDefinitionsBuilder(G_FPEXT).legalFor({{s64, s32}}); 153 getActionDefinitionsBuilder(G_FPTRUNC).legalFor({{s32, s64}}); 154 155 getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI}) 156 .legalForCartesianProduct({s32}, {s32, s64}); 157 getActionDefinitionsBuilder({G_SITOFP, G_UITOFP}) 158 .legalForCartesianProduct({s32, s64}, {s32}); 159 160 getActionDefinitionsBuilder({G_GET_FPENV, G_SET_FPENV}).legalFor({s32}); 161 getActionDefinitionsBuilder(G_RESET_FPENV).alwaysLegal(); 162 } else { 163 getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV}) 164 .libcallFor({s32, s64}); 165 166 LoadStoreBuilder.maxScalar(0, s32); 167 168 getActionDefinitionsBuilder(G_FNEG).lowerFor({s32, s64}); 169 170 getActionDefinitionsBuilder(G_FCONSTANT).customFor({s32, s64}); 171 172 getActionDefinitionsBuilder(G_FCMP).customForCartesianProduct({s1}, 173 {s32, s64}); 174 175 if (AEABI(ST)) 176 setFCmpLibcallsAEABI(); 177 else 178 setFCmpLibcallsGNU(); 179 180 getActionDefinitionsBuilder(G_FPEXT).libcallFor({{s64, s32}}); 181 getActionDefinitionsBuilder(G_FPTRUNC).libcallFor({{s32, s64}}); 182 183 getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI}) 184 .libcallForCartesianProduct({s32}, {s32, s64}); 185 getActionDefinitionsBuilder({G_SITOFP, G_UITOFP}) 186 .libcallForCartesianProduct({s32, s64}, {s32}); 187 188 getActionDefinitionsBuilder({G_GET_FPENV, G_SET_FPENV, G_RESET_FPENV}) 189 .libcall(); 190 } 191 192 // Just expand whatever loads and stores are left. 193 LoadStoreBuilder.lower(); 194 195 if (!ST.useSoftFloat() && ST.hasVFP4Base()) 196 getActionDefinitionsBuilder(G_FMA).legalFor({s32, s64}); 197 else 198 getActionDefinitionsBuilder(G_FMA).libcallFor({s32, s64}); 199 200 getActionDefinitionsBuilder({G_FREM, G_FPOW}).libcallFor({s32, s64}); 201 202 if (ST.hasV5TOps()) { 203 getActionDefinitionsBuilder(G_CTLZ) 204 .legalFor({s32, s32}) 205 .clampScalar(1, s32, s32) 206 .clampScalar(0, s32, s32); 207 getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF) 208 .lowerFor({s32, s32}) 209 .clampScalar(1, s32, s32) 210 .clampScalar(0, s32, s32); 211 } else { 212 getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF) 213 .libcallFor({s32, s32}) 214 .clampScalar(1, s32, s32) 215 .clampScalar(0, s32, s32); 216 getActionDefinitionsBuilder(G_CTLZ) 217 .lowerFor({s32, s32}) 218 .clampScalar(1, s32, s32) 219 .clampScalar(0, s32, s32); 220 } 221 222 LegacyInfo.computeTables(); 223 verify(*ST.getInstrInfo()); 224 } 225 226 void ARMLegalizerInfo::setFCmpLibcallsAEABI() { 227 // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be 228 // default-initialized. 229 FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 230 FCmp32Libcalls[CmpInst::FCMP_OEQ] = { 231 {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE}}; 232 FCmp32Libcalls[CmpInst::FCMP_OGE] = { 233 {RTLIB::OGE_F32, CmpInst::BAD_ICMP_PREDICATE}}; 234 FCmp32Libcalls[CmpInst::FCMP_OGT] = { 235 {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE}}; 236 FCmp32Libcalls[CmpInst::FCMP_OLE] = { 237 {RTLIB::OLE_F32, CmpInst::BAD_ICMP_PREDICATE}}; 238 FCmp32Libcalls[CmpInst::FCMP_OLT] = { 239 {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}}; 240 FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::UO_F32, CmpInst::ICMP_EQ}}; 241 FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_EQ}}; 242 FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_EQ}}; 243 FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_EQ}}; 244 FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_EQ}}; 245 FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_EQ}}; 246 FCmp32Libcalls[CmpInst::FCMP_UNO] = { 247 {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}}; 248 FCmp32Libcalls[CmpInst::FCMP_ONE] = { 249 {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE}, 250 {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}}; 251 FCmp32Libcalls[CmpInst::FCMP_UEQ] = { 252 {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE}, 253 {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}}; 254 255 FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 256 FCmp64Libcalls[CmpInst::FCMP_OEQ] = { 257 {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE}}; 258 FCmp64Libcalls[CmpInst::FCMP_OGE] = { 259 {RTLIB::OGE_F64, CmpInst::BAD_ICMP_PREDICATE}}; 260 FCmp64Libcalls[CmpInst::FCMP_OGT] = { 261 {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE}}; 262 FCmp64Libcalls[CmpInst::FCMP_OLE] = { 263 {RTLIB::OLE_F64, CmpInst::BAD_ICMP_PREDICATE}}; 264 FCmp64Libcalls[CmpInst::FCMP_OLT] = { 265 {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}}; 266 FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::UO_F64, CmpInst::ICMP_EQ}}; 267 FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_EQ}}; 268 FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_EQ}}; 269 FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_EQ}}; 270 FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_EQ}}; 271 FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_EQ}}; 272 FCmp64Libcalls[CmpInst::FCMP_UNO] = { 273 {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}}; 274 FCmp64Libcalls[CmpInst::FCMP_ONE] = { 275 {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE}, 276 {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}}; 277 FCmp64Libcalls[CmpInst::FCMP_UEQ] = { 278 {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE}, 279 {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}}; 280 } 281 282 void ARMLegalizerInfo::setFCmpLibcallsGNU() { 283 // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be 284 // default-initialized. 285 FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 286 FCmp32Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ}}; 287 FCmp32Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F32, CmpInst::ICMP_SGE}}; 288 FCmp32Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT}}; 289 FCmp32Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F32, CmpInst::ICMP_SLE}}; 290 FCmp32Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F32, CmpInst::ICMP_SLT}}; 291 FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::UO_F32, CmpInst::ICMP_EQ}}; 292 FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_SGE}}; 293 FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_SGT}}; 294 FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SLE}}; 295 FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_SLT}}; 296 FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_NE}}; 297 FCmp32Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F32, CmpInst::ICMP_NE}}; 298 FCmp32Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT}, 299 {RTLIB::OLT_F32, CmpInst::ICMP_SLT}}; 300 FCmp32Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ}, 301 {RTLIB::UO_F32, CmpInst::ICMP_NE}}; 302 303 FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 304 FCmp64Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ}}; 305 FCmp64Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F64, CmpInst::ICMP_SGE}}; 306 FCmp64Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT}}; 307 FCmp64Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F64, CmpInst::ICMP_SLE}}; 308 FCmp64Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F64, CmpInst::ICMP_SLT}}; 309 FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::UO_F64, CmpInst::ICMP_EQ}}; 310 FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_SGE}}; 311 FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_SGT}}; 312 FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SLE}}; 313 FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_SLT}}; 314 FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_NE}}; 315 FCmp64Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F64, CmpInst::ICMP_NE}}; 316 FCmp64Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT}, 317 {RTLIB::OLT_F64, CmpInst::ICMP_SLT}}; 318 FCmp64Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ}, 319 {RTLIB::UO_F64, CmpInst::ICMP_NE}}; 320 } 321 322 ARMLegalizerInfo::FCmpLibcallsList 323 ARMLegalizerInfo::getFCmpLibcalls(CmpInst::Predicate Predicate, 324 unsigned Size) const { 325 assert(CmpInst::isFPPredicate(Predicate) && "Unsupported FCmp predicate"); 326 if (Size == 32) 327 return FCmp32Libcalls[Predicate]; 328 if (Size == 64) 329 return FCmp64Libcalls[Predicate]; 330 llvm_unreachable("Unsupported size for FCmp predicate"); 331 } 332 333 bool ARMLegalizerInfo::legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI, 334 LostDebugLocObserver &LocObserver) const { 335 using namespace TargetOpcode; 336 337 MachineIRBuilder &MIRBuilder = Helper.MIRBuilder; 338 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); 339 LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext(); 340 341 switch (MI.getOpcode()) { 342 default: 343 return false; 344 case G_SREM: 345 case G_UREM: { 346 Register OriginalResult = MI.getOperand(0).getReg(); 347 auto Size = MRI.getType(OriginalResult).getSizeInBits(); 348 if (Size != 32) 349 return false; 350 351 auto Libcall = 352 MI.getOpcode() == G_SREM ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; 353 354 // Our divmod libcalls return a struct containing the quotient and the 355 // remainder. Create a new, unused register for the quotient and use the 356 // destination of the original instruction for the remainder. 357 Type *ArgTy = Type::getInt32Ty(Ctx); 358 StructType *RetTy = StructType::get(Ctx, {ArgTy, ArgTy}, /* Packed */ true); 359 Register RetRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)), 360 OriginalResult}; 361 auto Status = createLibcall(MIRBuilder, Libcall, {RetRegs, RetTy, 0}, 362 {{MI.getOperand(1).getReg(), ArgTy, 0}, 363 {MI.getOperand(2).getReg(), ArgTy, 0}}, 364 LocObserver, &MI); 365 if (Status != LegalizerHelper::Legalized) 366 return false; 367 break; 368 } 369 case G_FCMP: { 370 assert(MRI.getType(MI.getOperand(2).getReg()) == 371 MRI.getType(MI.getOperand(3).getReg()) && 372 "Mismatched operands for G_FCMP"); 373 auto OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); 374 375 auto OriginalResult = MI.getOperand(0).getReg(); 376 auto Predicate = 377 static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()); 378 auto Libcalls = getFCmpLibcalls(Predicate, OpSize); 379 380 if (Libcalls.empty()) { 381 assert((Predicate == CmpInst::FCMP_TRUE || 382 Predicate == CmpInst::FCMP_FALSE) && 383 "Predicate needs libcalls, but none specified"); 384 MIRBuilder.buildConstant(OriginalResult, 385 Predicate == CmpInst::FCMP_TRUE ? 1 : 0); 386 MI.eraseFromParent(); 387 return true; 388 } 389 390 assert((OpSize == 32 || OpSize == 64) && "Unsupported operand size"); 391 auto *ArgTy = OpSize == 32 ? Type::getFloatTy(Ctx) : Type::getDoubleTy(Ctx); 392 auto *RetTy = Type::getInt32Ty(Ctx); 393 394 SmallVector<Register, 2> Results; 395 for (auto Libcall : Libcalls) { 396 auto LibcallResult = MRI.createGenericVirtualRegister(LLT::scalar(32)); 397 auto Status = createLibcall(MIRBuilder, Libcall.LibcallID, 398 {LibcallResult, RetTy, 0}, 399 {{MI.getOperand(2).getReg(), ArgTy, 0}, 400 {MI.getOperand(3).getReg(), ArgTy, 0}}, 401 LocObserver, &MI); 402 403 if (Status != LegalizerHelper::Legalized) 404 return false; 405 406 auto ProcessedResult = 407 Libcalls.size() == 1 408 ? OriginalResult 409 : MRI.createGenericVirtualRegister(MRI.getType(OriginalResult)); 410 411 // We have a result, but we need to transform it into a proper 1-bit 0 or 412 // 1, taking into account the different peculiarities of the values 413 // returned by the comparison functions. 414 CmpInst::Predicate ResultPred = Libcall.Predicate; 415 if (ResultPred == CmpInst::BAD_ICMP_PREDICATE) { 416 // We have a nice 0 or 1, and we just need to truncate it back to 1 bit 417 // to keep the types consistent. 418 MIRBuilder.buildTrunc(ProcessedResult, LibcallResult); 419 } else { 420 // We need to compare against 0. 421 assert(CmpInst::isIntPredicate(ResultPred) && "Unsupported predicate"); 422 auto Zero = MIRBuilder.buildConstant(LLT::scalar(32), 0); 423 MIRBuilder.buildICmp(ResultPred, ProcessedResult, LibcallResult, Zero); 424 } 425 Results.push_back(ProcessedResult); 426 } 427 428 if (Results.size() != 1) { 429 assert(Results.size() == 2 && "Unexpected number of results"); 430 MIRBuilder.buildOr(OriginalResult, Results[0], Results[1]); 431 } 432 break; 433 } 434 case G_FCONSTANT: { 435 // Convert to integer constants, while preserving the binary representation. 436 auto AsInteger = 437 MI.getOperand(1).getFPImm()->getValueAPF().bitcastToAPInt(); 438 MIRBuilder.buildConstant(MI.getOperand(0), 439 *ConstantInt::get(Ctx, AsInteger)); 440 break; 441 } 442 } 443 444 MI.eraseFromParent(); 445 return true; 446 } 447