1 //===- ARMLegalizerInfo.cpp --------------------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements the targeting of the Machinelegalizer class for ARM. 10 /// \todo This should be generated by TableGen. 11 //===----------------------------------------------------------------------===// 12 13 #include "ARMLegalizerInfo.h" 14 #include "ARMCallLowering.h" 15 #include "ARMSubtarget.h" 16 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h" 17 #include "llvm/CodeGen/LowLevelType.h" 18 #include "llvm/CodeGen/MachineRegisterInfo.h" 19 #include "llvm/CodeGen/TargetOpcodes.h" 20 #include "llvm/CodeGen/ValueTypes.h" 21 #include "llvm/IR/DerivedTypes.h" 22 #include "llvm/IR/Type.h" 23 24 using namespace llvm; 25 using namespace LegalizeActions; 26 27 /// FIXME: The following static functions are SizeChangeStrategy functions 28 /// that are meant to temporarily mimic the behaviour of the old legalization 29 /// based on doubling/halving non-legal types as closely as possible. This is 30 /// not entirly possible as only legalizing the types that are exactly a power 31 /// of 2 times the size of the legal types would require specifying all those 32 /// sizes explicitly. 33 /// In practice, not specifying those isn't a problem, and the below functions 34 /// should disappear quickly as we add support for legalizing non-power-of-2 35 /// sized types further. 36 static void 37 addAndInterleaveWithUnsupported(LegalizerInfo::SizeAndActionsVec &result, 38 const LegalizerInfo::SizeAndActionsVec &v) { 39 for (unsigned i = 0; i < v.size(); ++i) { 40 result.push_back(v[i]); 41 if (i + 1 < v[i].first && i + 1 < v.size() && 42 v[i + 1].first != v[i].first + 1) 43 result.push_back({v[i].first + 1, Unsupported}); 44 } 45 } 46 47 static LegalizerInfo::SizeAndActionsVec 48 widen_8_16(const LegalizerInfo::SizeAndActionsVec &v) { 49 assert(v.size() >= 1); 50 assert(v[0].first > 17); 51 LegalizerInfo::SizeAndActionsVec result = {{1, Unsupported}, 52 {8, WidenScalar}, 53 {9, Unsupported}, 54 {16, WidenScalar}, 55 {17, Unsupported}}; 56 addAndInterleaveWithUnsupported(result, v); 57 auto Largest = result.back().first; 58 result.push_back({Largest + 1, Unsupported}); 59 return result; 60 } 61 62 static bool AEABI(const ARMSubtarget &ST) { 63 return ST.isTargetAEABI() || ST.isTargetGNUAEABI() || ST.isTargetMuslAEABI(); 64 } 65 66 ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) { 67 using namespace TargetOpcode; 68 69 const LLT p0 = LLT::pointer(0, 32); 70 71 const LLT s1 = LLT::scalar(1); 72 const LLT s8 = LLT::scalar(8); 73 const LLT s16 = LLT::scalar(16); 74 const LLT s32 = LLT::scalar(32); 75 const LLT s64 = LLT::scalar(64); 76 77 if (ST.isThumb1Only()) { 78 // Thumb1 is not supported yet. 79 computeTables(); 80 verify(*ST.getInstrInfo()); 81 return; 82 } 83 84 getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT}) 85 .legalForCartesianProduct({s8, s16, s32}, {s1, s8, s16}); 86 87 getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR}) 88 .legalFor({s32}) 89 .minScalar(0, s32); 90 91 getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL}) 92 .legalFor({{s32, s32}}) 93 .minScalar(0, s32) 94 .clampScalar(1, s32, s32); 95 96 bool HasHWDivide = (!ST.isThumb() && ST.hasDivideInARMMode()) || 97 (ST.isThumb() && ST.hasDivideInThumbMode()); 98 if (HasHWDivide) 99 getActionDefinitionsBuilder({G_SDIV, G_UDIV}) 100 .legalFor({s32}) 101 .clampScalar(0, s32, s32); 102 else 103 getActionDefinitionsBuilder({G_SDIV, G_UDIV}) 104 .libcallFor({s32}) 105 .clampScalar(0, s32, s32); 106 107 for (unsigned Op : {G_SREM, G_UREM}) { 108 setLegalizeScalarToDifferentSizeStrategy(Op, 0, widen_8_16); 109 if (HasHWDivide) 110 setAction({Op, s32}, Lower); 111 else if (AEABI(ST)) 112 setAction({Op, s32}, Custom); 113 else 114 setAction({Op, s32}, Libcall); 115 } 116 117 getActionDefinitionsBuilder(G_INTTOPTR) 118 .legalFor({{p0, s32}}) 119 .minScalar(1, s32); 120 getActionDefinitionsBuilder(G_PTRTOINT) 121 .legalFor({{s32, p0}}) 122 .minScalar(0, s32); 123 124 getActionDefinitionsBuilder(G_CONSTANT) 125 .legalFor({s32, p0}) 126 .clampScalar(0, s32, s32); 127 128 getActionDefinitionsBuilder(G_ICMP) 129 .legalForCartesianProduct({s1}, {s32, p0}) 130 .minScalar(1, s32); 131 132 getActionDefinitionsBuilder(G_SELECT) 133 .legalForCartesianProduct({s32, p0}, {s1}) 134 .minScalar(0, s32); 135 136 // We're keeping these builders around because we'll want to add support for 137 // floating point to them. 138 auto &LoadStoreBuilder = getActionDefinitionsBuilder({G_LOAD, G_STORE}) 139 .legalForTypesWithMemDesc({{s1, p0, 8, 8}, 140 {s8, p0, 8, 8}, 141 {s16, p0, 16, 8}, 142 {s32, p0, 32, 8}, 143 {p0, p0, 32, 8}}) 144 .unsupportedIfMemSizeNotPow2(); 145 146 getActionDefinitionsBuilder(G_FRAME_INDEX).legalFor({p0}); 147 getActionDefinitionsBuilder(G_GLOBAL_VALUE).legalFor({p0}); 148 149 auto &PhiBuilder = 150 getActionDefinitionsBuilder(G_PHI) 151 .legalFor({s32, p0}) 152 .minScalar(0, s32); 153 154 getActionDefinitionsBuilder(G_GEP) 155 .legalFor({{p0, s32}}) 156 .minScalar(1, s32); 157 158 getActionDefinitionsBuilder(G_BRCOND).legalFor({s1}); 159 160 if (!ST.useSoftFloat() && ST.hasVFP2()) { 161 getActionDefinitionsBuilder( 162 {G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FCONSTANT, G_FNEG}) 163 .legalFor({s32, s64}); 164 165 LoadStoreBuilder 166 .legalForTypesWithMemDesc({{s64, p0, 64, 32}}) 167 .maxScalar(0, s32); 168 PhiBuilder.legalFor({s64}); 169 170 getActionDefinitionsBuilder(G_FCMP).legalForCartesianProduct({s1}, 171 {s32, s64}); 172 173 getActionDefinitionsBuilder(G_MERGE_VALUES).legalFor({{s64, s32}}); 174 getActionDefinitionsBuilder(G_UNMERGE_VALUES).legalFor({{s32, s64}}); 175 176 getActionDefinitionsBuilder(G_FPEXT).legalFor({{s64, s32}}); 177 getActionDefinitionsBuilder(G_FPTRUNC).legalFor({{s32, s64}}); 178 179 getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI}) 180 .legalForCartesianProduct({s32}, {s32, s64}); 181 getActionDefinitionsBuilder({G_SITOFP, G_UITOFP}) 182 .legalForCartesianProduct({s32, s64}, {s32}); 183 } else { 184 getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV}) 185 .libcallFor({s32, s64}); 186 187 LoadStoreBuilder.maxScalar(0, s32); 188 189 for (auto Ty : {s32, s64}) 190 setAction({G_FNEG, Ty}, Lower); 191 192 getActionDefinitionsBuilder(G_FCONSTANT).customFor({s32, s64}); 193 194 getActionDefinitionsBuilder(G_FCMP).customForCartesianProduct({s1}, 195 {s32, s64}); 196 197 if (AEABI(ST)) 198 setFCmpLibcallsAEABI(); 199 else 200 setFCmpLibcallsGNU(); 201 202 getActionDefinitionsBuilder(G_FPEXT).libcallFor({{s64, s32}}); 203 getActionDefinitionsBuilder(G_FPTRUNC).libcallFor({{s32, s64}}); 204 205 getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI}) 206 .libcallForCartesianProduct({s32}, {s32, s64}); 207 getActionDefinitionsBuilder({G_SITOFP, G_UITOFP}) 208 .libcallForCartesianProduct({s32, s64}, {s32}); 209 } 210 211 if (!ST.useSoftFloat() && ST.hasVFP4()) 212 getActionDefinitionsBuilder(G_FMA).legalFor({s32, s64}); 213 else 214 getActionDefinitionsBuilder(G_FMA).libcallFor({s32, s64}); 215 216 getActionDefinitionsBuilder({G_FREM, G_FPOW}).libcallFor({s32, s64}); 217 218 if (ST.hasV5TOps()) { 219 getActionDefinitionsBuilder(G_CTLZ) 220 .legalFor({s32, s32}) 221 .clampScalar(1, s32, s32) 222 .clampScalar(0, s32, s32); 223 getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF) 224 .lowerFor({s32, s32}) 225 .clampScalar(1, s32, s32) 226 .clampScalar(0, s32, s32); 227 } else { 228 getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF) 229 .libcallFor({s32, s32}) 230 .clampScalar(1, s32, s32) 231 .clampScalar(0, s32, s32); 232 getActionDefinitionsBuilder(G_CTLZ) 233 .lowerFor({s32, s32}) 234 .clampScalar(1, s32, s32) 235 .clampScalar(0, s32, s32); 236 } 237 238 computeTables(); 239 verify(*ST.getInstrInfo()); 240 } 241 242 void ARMLegalizerInfo::setFCmpLibcallsAEABI() { 243 // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be 244 // default-initialized. 245 FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 246 FCmp32Libcalls[CmpInst::FCMP_OEQ] = { 247 {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE}}; 248 FCmp32Libcalls[CmpInst::FCMP_OGE] = { 249 {RTLIB::OGE_F32, CmpInst::BAD_ICMP_PREDICATE}}; 250 FCmp32Libcalls[CmpInst::FCMP_OGT] = { 251 {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE}}; 252 FCmp32Libcalls[CmpInst::FCMP_OLE] = { 253 {RTLIB::OLE_F32, CmpInst::BAD_ICMP_PREDICATE}}; 254 FCmp32Libcalls[CmpInst::FCMP_OLT] = { 255 {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}}; 256 FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}}; 257 FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_EQ}}; 258 FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_EQ}}; 259 FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_EQ}}; 260 FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_EQ}}; 261 FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_EQ}}; 262 FCmp32Libcalls[CmpInst::FCMP_UNO] = { 263 {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}}; 264 FCmp32Libcalls[CmpInst::FCMP_ONE] = { 265 {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE}, 266 {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}}; 267 FCmp32Libcalls[CmpInst::FCMP_UEQ] = { 268 {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE}, 269 {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}}; 270 271 FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 272 FCmp64Libcalls[CmpInst::FCMP_OEQ] = { 273 {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE}}; 274 FCmp64Libcalls[CmpInst::FCMP_OGE] = { 275 {RTLIB::OGE_F64, CmpInst::BAD_ICMP_PREDICATE}}; 276 FCmp64Libcalls[CmpInst::FCMP_OGT] = { 277 {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE}}; 278 FCmp64Libcalls[CmpInst::FCMP_OLE] = { 279 {RTLIB::OLE_F64, CmpInst::BAD_ICMP_PREDICATE}}; 280 FCmp64Libcalls[CmpInst::FCMP_OLT] = { 281 {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}}; 282 FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}}; 283 FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_EQ}}; 284 FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_EQ}}; 285 FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_EQ}}; 286 FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_EQ}}; 287 FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_EQ}}; 288 FCmp64Libcalls[CmpInst::FCMP_UNO] = { 289 {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}}; 290 FCmp64Libcalls[CmpInst::FCMP_ONE] = { 291 {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE}, 292 {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}}; 293 FCmp64Libcalls[CmpInst::FCMP_UEQ] = { 294 {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE}, 295 {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}}; 296 } 297 298 void ARMLegalizerInfo::setFCmpLibcallsGNU() { 299 // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be 300 // default-initialized. 301 FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 302 FCmp32Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ}}; 303 FCmp32Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F32, CmpInst::ICMP_SGE}}; 304 FCmp32Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT}}; 305 FCmp32Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F32, CmpInst::ICMP_SLE}}; 306 FCmp32Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F32, CmpInst::ICMP_SLT}}; 307 FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}}; 308 FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_SGE}}; 309 FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_SGT}}; 310 FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SLE}}; 311 FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_SLT}}; 312 FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_NE}}; 313 FCmp32Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F32, CmpInst::ICMP_NE}}; 314 FCmp32Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT}, 315 {RTLIB::OLT_F32, CmpInst::ICMP_SLT}}; 316 FCmp32Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ}, 317 {RTLIB::UO_F32, CmpInst::ICMP_NE}}; 318 319 FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 320 FCmp64Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ}}; 321 FCmp64Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F64, CmpInst::ICMP_SGE}}; 322 FCmp64Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT}}; 323 FCmp64Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F64, CmpInst::ICMP_SLE}}; 324 FCmp64Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F64, CmpInst::ICMP_SLT}}; 325 FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}}; 326 FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_SGE}}; 327 FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_SGT}}; 328 FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SLE}}; 329 FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_SLT}}; 330 FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_NE}}; 331 FCmp64Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F64, CmpInst::ICMP_NE}}; 332 FCmp64Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT}, 333 {RTLIB::OLT_F64, CmpInst::ICMP_SLT}}; 334 FCmp64Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ}, 335 {RTLIB::UO_F64, CmpInst::ICMP_NE}}; 336 } 337 338 ARMLegalizerInfo::FCmpLibcallsList 339 ARMLegalizerInfo::getFCmpLibcalls(CmpInst::Predicate Predicate, 340 unsigned Size) const { 341 assert(CmpInst::isFPPredicate(Predicate) && "Unsupported FCmp predicate"); 342 if (Size == 32) 343 return FCmp32Libcalls[Predicate]; 344 if (Size == 64) 345 return FCmp64Libcalls[Predicate]; 346 llvm_unreachable("Unsupported size for FCmp predicate"); 347 } 348 349 bool ARMLegalizerInfo::legalizeCustom(MachineInstr &MI, 350 MachineRegisterInfo &MRI, 351 MachineIRBuilder &MIRBuilder, 352 GISelChangeObserver &Observer) const { 353 using namespace TargetOpcode; 354 355 MIRBuilder.setInstr(MI); 356 LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext(); 357 358 switch (MI.getOpcode()) { 359 default: 360 return false; 361 case G_SREM: 362 case G_UREM: { 363 unsigned OriginalResult = MI.getOperand(0).getReg(); 364 auto Size = MRI.getType(OriginalResult).getSizeInBits(); 365 if (Size != 32) 366 return false; 367 368 auto Libcall = 369 MI.getOpcode() == G_SREM ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; 370 371 // Our divmod libcalls return a struct containing the quotient and the 372 // remainder. We need to create a virtual register for it. 373 Type *ArgTy = Type::getInt32Ty(Ctx); 374 StructType *RetTy = StructType::get(Ctx, {ArgTy, ArgTy}, /* Packed */ true); 375 auto RetVal = MRI.createGenericVirtualRegister( 376 getLLTForType(*RetTy, MIRBuilder.getMF().getDataLayout())); 377 378 auto Status = createLibcall(MIRBuilder, Libcall, {RetVal, RetTy}, 379 {{MI.getOperand(1).getReg(), ArgTy}, 380 {MI.getOperand(2).getReg(), ArgTy}}); 381 if (Status != LegalizerHelper::Legalized) 382 return false; 383 384 // The remainder is the second result of divmod. Split the return value into 385 // a new, unused register for the quotient and the destination of the 386 // original instruction for the remainder. 387 MIRBuilder.buildUnmerge( 388 {MRI.createGenericVirtualRegister(LLT::scalar(32)), OriginalResult}, 389 RetVal); 390 break; 391 } 392 case G_FCMP: { 393 assert(MRI.getType(MI.getOperand(2).getReg()) == 394 MRI.getType(MI.getOperand(3).getReg()) && 395 "Mismatched operands for G_FCMP"); 396 auto OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); 397 398 auto OriginalResult = MI.getOperand(0).getReg(); 399 auto Predicate = 400 static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()); 401 auto Libcalls = getFCmpLibcalls(Predicate, OpSize); 402 403 if (Libcalls.empty()) { 404 assert((Predicate == CmpInst::FCMP_TRUE || 405 Predicate == CmpInst::FCMP_FALSE) && 406 "Predicate needs libcalls, but none specified"); 407 MIRBuilder.buildConstant(OriginalResult, 408 Predicate == CmpInst::FCMP_TRUE ? 1 : 0); 409 MI.eraseFromParent(); 410 return true; 411 } 412 413 assert((OpSize == 32 || OpSize == 64) && "Unsupported operand size"); 414 auto *ArgTy = OpSize == 32 ? Type::getFloatTy(Ctx) : Type::getDoubleTy(Ctx); 415 auto *RetTy = Type::getInt32Ty(Ctx); 416 417 SmallVector<unsigned, 2> Results; 418 for (auto Libcall : Libcalls) { 419 auto LibcallResult = MRI.createGenericVirtualRegister(LLT::scalar(32)); 420 auto Status = 421 createLibcall(MIRBuilder, Libcall.LibcallID, {LibcallResult, RetTy}, 422 {{MI.getOperand(2).getReg(), ArgTy}, 423 {MI.getOperand(3).getReg(), ArgTy}}); 424 425 if (Status != LegalizerHelper::Legalized) 426 return false; 427 428 auto ProcessedResult = 429 Libcalls.size() == 1 430 ? OriginalResult 431 : MRI.createGenericVirtualRegister(MRI.getType(OriginalResult)); 432 433 // We have a result, but we need to transform it into a proper 1-bit 0 or 434 // 1, taking into account the different peculiarities of the values 435 // returned by the comparison functions. 436 CmpInst::Predicate ResultPred = Libcall.Predicate; 437 if (ResultPred == CmpInst::BAD_ICMP_PREDICATE) { 438 // We have a nice 0 or 1, and we just need to truncate it back to 1 bit 439 // to keep the types consistent. 440 MIRBuilder.buildTrunc(ProcessedResult, LibcallResult); 441 } else { 442 // We need to compare against 0. 443 assert(CmpInst::isIntPredicate(ResultPred) && "Unsupported predicate"); 444 auto Zero = MRI.createGenericVirtualRegister(LLT::scalar(32)); 445 MIRBuilder.buildConstant(Zero, 0); 446 MIRBuilder.buildICmp(ResultPred, ProcessedResult, LibcallResult, Zero); 447 } 448 Results.push_back(ProcessedResult); 449 } 450 451 if (Results.size() != 1) { 452 assert(Results.size() == 2 && "Unexpected number of results"); 453 MIRBuilder.buildOr(OriginalResult, Results[0], Results[1]); 454 } 455 break; 456 } 457 case G_FCONSTANT: { 458 // Convert to integer constants, while preserving the binary representation. 459 auto AsInteger = 460 MI.getOperand(1).getFPImm()->getValueAPF().bitcastToAPInt(); 461 MIRBuilder.buildConstant(MI.getOperand(0).getReg(), 462 *ConstantInt::get(Ctx, AsInteger)); 463 break; 464 } 465 } 466 467 MI.eraseFromParent(); 468 return true; 469 } 470