1 //=======- ARMFrameLowering.cpp - ARM Frame Information --------*- C++ -*-====// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the ARM implementation of TargetFrameLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "ARMFrameLowering.h" 15 #include "ARMAddressingModes.h" 16 #include "ARMBaseInstrInfo.h" 17 #include "ARMBaseRegisterInfo.h" 18 #include "ARMMachineFunctionInfo.h" 19 #include "llvm/CodeGen/MachineFrameInfo.h" 20 #include "llvm/CodeGen/MachineFunction.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/MachineRegisterInfo.h" 23 #include "llvm/CodeGen/RegisterScavenging.h" 24 #include "llvm/Target/TargetOptions.h" 25 26 using namespace llvm; 27 28 /// hasFP - Return true if the specified function should have a dedicated frame 29 /// pointer register. This is true if the function has variable sized allocas 30 /// or if frame pointer elimination is disabled. 31 bool ARMFrameLowering::hasFP(const MachineFunction &MF) const { 32 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); 33 34 // Mac OS X requires FP not to be clobbered for backtracing purpose. 35 if (STI.isTargetDarwin()) 36 return true; 37 38 const MachineFrameInfo *MFI = MF.getFrameInfo(); 39 // Always eliminate non-leaf frame pointers. 40 return ((DisableFramePointerElim(MF) && MFI->hasCalls()) || 41 RegInfo->needsStackRealignment(MF) || 42 MFI->hasVarSizedObjects() || 43 MFI->isFrameAddressTaken()); 44 } 45 46 /// hasReservedCallFrame - Under normal circumstances, when a frame pointer is 47 /// not required, we reserve argument space for call sites in the function 48 /// immediately on entry to the current function. This eliminates the need for 49 /// add/sub sp brackets around call sites. Returns true if the call frame is 50 /// included as part of the stack frame. 51 bool ARMFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { 52 const MachineFrameInfo *FFI = MF.getFrameInfo(); 53 unsigned CFSize = FFI->getMaxCallFrameSize(); 54 // It's not always a good idea to include the call frame as part of the 55 // stack frame. ARM (especially Thumb) has small immediate offset to 56 // address the stack frame. So a large call frame can cause poor codegen 57 // and may even makes it impossible to scavenge a register. 58 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12 59 return false; 60 61 return !MF.getFrameInfo()->hasVarSizedObjects(); 62 } 63 64 /// canSimplifyCallFramePseudos - If there is a reserved call frame, the 65 /// call frame pseudos can be simplified. Unlike most targets, having a FP 66 /// is not sufficient here since we still may reference some objects via SP 67 /// even when FP is available in Thumb2 mode. 68 bool 69 ARMFrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const { 70 return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects(); 71 } 72 73 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { 74 for (unsigned i = 0; CSRegs[i]; ++i) 75 if (Reg == CSRegs[i]) 76 return true; 77 return false; 78 } 79 80 static bool isCSRestore(MachineInstr *MI, 81 const ARMBaseInstrInfo &TII, 82 const unsigned *CSRegs) { 83 // Integer spill area is handled with "pop". 84 if (MI->getOpcode() == ARM::LDMIA_RET || 85 MI->getOpcode() == ARM::t2LDMIA_RET || 86 MI->getOpcode() == ARM::LDMIA_UPD || 87 MI->getOpcode() == ARM::t2LDMIA_UPD || 88 MI->getOpcode() == ARM::VLDMDIA_UPD) { 89 // The first two operands are predicates. The last two are 90 // imp-def and imp-use of SP. Check everything in between. 91 for (int i = 5, e = MI->getNumOperands(); i != e; ++i) 92 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs)) 93 return false; 94 return true; 95 } 96 if ((MI->getOpcode() == ARM::LDR_POST || 97 MI->getOpcode() == ARM::t2LDR_POST) && 98 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs) && 99 MI->getOperand(1).getReg() == ARM::SP) 100 return true; 101 102 return false; 103 } 104 105 static void 106 emitSPUpdate(bool isARM, 107 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 108 DebugLoc dl, const ARMBaseInstrInfo &TII, 109 int NumBytes, unsigned MIFlags = MachineInstr::NoFlags) { 110 if (isARM) 111 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 112 ARMCC::AL, 0, TII, MIFlags); 113 else 114 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 115 ARMCC::AL, 0, TII, MIFlags); 116 } 117 118 void ARMFrameLowering::emitPrologue(MachineFunction &MF) const { 119 MachineBasicBlock &MBB = MF.front(); 120 MachineBasicBlock::iterator MBBI = MBB.begin(); 121 MachineFrameInfo *MFI = MF.getFrameInfo(); 122 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 123 const ARMBaseRegisterInfo *RegInfo = 124 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo()); 125 const ARMBaseInstrInfo &TII = 126 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo()); 127 assert(!AFI->isThumb1OnlyFunction() && 128 "This emitPrologue does not support Thumb1!"); 129 bool isARM = !AFI->isThumbFunction(); 130 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 131 unsigned NumBytes = MFI->getStackSize(); 132 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 133 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); 134 unsigned FramePtr = RegInfo->getFrameRegister(MF); 135 136 // Determine the sizes of each callee-save spill areas and record which frame 137 // belongs to which callee-save spill areas. 138 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 139 int FramePtrSpillFI = 0; 140 141 // Allocate the vararg register save area. This is not counted in NumBytes. 142 if (VARegSaveSize) 143 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize, 144 MachineInstr::FrameSetup); 145 146 if (!AFI->hasStackFrame()) { 147 if (NumBytes != 0) 148 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes, 149 MachineInstr::FrameSetup); 150 return; 151 } 152 153 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 154 unsigned Reg = CSI[i].getReg(); 155 int FI = CSI[i].getFrameIdx(); 156 switch (Reg) { 157 case ARM::R4: 158 case ARM::R5: 159 case ARM::R6: 160 case ARM::R7: 161 case ARM::LR: 162 if (Reg == FramePtr) 163 FramePtrSpillFI = FI; 164 AFI->addGPRCalleeSavedArea1Frame(FI); 165 GPRCS1Size += 4; 166 break; 167 case ARM::R8: 168 case ARM::R9: 169 case ARM::R10: 170 case ARM::R11: 171 if (Reg == FramePtr) 172 FramePtrSpillFI = FI; 173 if (STI.isTargetDarwin()) { 174 AFI->addGPRCalleeSavedArea2Frame(FI); 175 GPRCS2Size += 4; 176 } else { 177 AFI->addGPRCalleeSavedArea1Frame(FI); 178 GPRCS1Size += 4; 179 } 180 break; 181 default: 182 AFI->addDPRCalleeSavedAreaFrame(FI); 183 DPRCSSize += 8; 184 } 185 } 186 187 // Move past area 1. 188 if (GPRCS1Size > 0) MBBI++; 189 190 // Set FP to point to the stack slot that contains the previous FP. 191 // For Darwin, FP is R7, which has now been stored in spill area 1. 192 // Otherwise, if this is not Darwin, all the callee-saved registers go 193 // into spill area 1, including the FP in R11. In either case, it is 194 // now safe to emit this assignment. 195 bool HasFP = hasFP(MF); 196 if (HasFP) { 197 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri; 198 MachineInstrBuilder MIB = 199 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr) 200 .addFrameIndex(FramePtrSpillFI).addImm(0) 201 .setMIFlag(MachineInstr::FrameSetup); 202 AddDefaultCC(AddDefaultPred(MIB)); 203 } 204 205 // Move past area 2. 206 if (GPRCS2Size > 0) MBBI++; 207 208 // Determine starting offsets of spill areas. 209 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); 210 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; 211 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; 212 if (HasFP) 213 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + 214 NumBytes); 215 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 216 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 217 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 218 219 // Move past area 3. 220 if (DPRCSSize > 0) { 221 MBBI++; 222 // Since vpush register list cannot have gaps, there may be multiple vpush 223 // instructions in the prologue. 224 while (MBBI->getOpcode() == ARM::VSTMDDB_UPD) 225 MBBI++; 226 } 227 228 NumBytes = DPRCSOffset; 229 if (NumBytes) { 230 // Adjust SP after all the callee-save spills. 231 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes, 232 MachineInstr::FrameSetup); 233 if (HasFP && isARM) 234 // Restore from fp only in ARM mode: e.g. sub sp, r7, #24 235 // Note it's not safe to do this in Thumb2 mode because it would have 236 // taken two instructions: 237 // mov sp, r7 238 // sub sp, #24 239 // If an interrupt is taken between the two instructions, then sp is in 240 // an inconsistent state (pointing to the middle of callee-saved area). 241 // The interrupt handler can end up clobbering the registers. 242 AFI->setShouldRestoreSPFromFP(true); 243 } 244 245 if (STI.isTargetELF() && hasFP(MF)) 246 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() - 247 AFI->getFramePtrSpillOffset()); 248 249 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 250 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 251 AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 252 253 // If we need dynamic stack realignment, do it here. Be paranoid and make 254 // sure if we also have VLAs, we have a base pointer for frame access. 255 if (RegInfo->needsStackRealignment(MF)) { 256 unsigned MaxAlign = MFI->getMaxAlignment(); 257 assert (!AFI->isThumb1OnlyFunction()); 258 if (!AFI->isThumbFunction()) { 259 // Emit bic sp, sp, MaxAlign 260 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, 261 TII.get(ARM::BICri), ARM::SP) 262 .addReg(ARM::SP, RegState::Kill) 263 .addImm(MaxAlign-1))); 264 } else { 265 // We cannot use sp as source/dest register here, thus we're emitting the 266 // following sequence: 267 // mov r4, sp 268 // bic r4, r4, MaxAlign 269 // mov sp, r4 270 // FIXME: It will be better just to find spare register here. 271 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4) 272 .addReg(ARM::SP, RegState::Kill)); 273 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, 274 TII.get(ARM::t2BICri), ARM::R4) 275 .addReg(ARM::R4, RegState::Kill) 276 .addImm(MaxAlign-1))); 277 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) 278 .addReg(ARM::R4, RegState::Kill)); 279 } 280 281 AFI->setShouldRestoreSPFromFP(true); 282 } 283 284 // If we need a base pointer, set it up here. It's whatever the value 285 // of the stack pointer is at this point. Any variable size objects 286 // will be allocated after this, so we can still use the base pointer 287 // to reference locals. 288 // FIXME: Clarify FrameSetup flags here. 289 if (RegInfo->hasBasePointer(MF)) { 290 if (isARM) 291 BuildMI(MBB, MBBI, dl, 292 TII.get(ARM::MOVr), RegInfo->getBaseRegister()) 293 .addReg(ARM::SP) 294 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 295 else 296 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), 297 RegInfo->getBaseRegister()) 298 .addReg(ARM::SP)); 299 } 300 301 // If the frame has variable sized objects then the epilogue must restore 302 // the sp from fp. We can assume there's an FP here since hasFP already 303 // checks for hasVarSizedObjects. 304 if (MFI->hasVarSizedObjects()) 305 AFI->setShouldRestoreSPFromFP(true); 306 } 307 308 void ARMFrameLowering::emitEpilogue(MachineFunction &MF, 309 MachineBasicBlock &MBB) const { 310 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 311 assert(MBBI->getDesc().isReturn() && 312 "Can only insert epilog into returning blocks"); 313 unsigned RetOpcode = MBBI->getOpcode(); 314 DebugLoc dl = MBBI->getDebugLoc(); 315 MachineFrameInfo *MFI = MF.getFrameInfo(); 316 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 317 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); 318 const ARMBaseInstrInfo &TII = 319 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo()); 320 assert(!AFI->isThumb1OnlyFunction() && 321 "This emitEpilogue does not support Thumb1!"); 322 bool isARM = !AFI->isThumbFunction(); 323 324 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 325 int NumBytes = (int)MFI->getStackSize(); 326 unsigned FramePtr = RegInfo->getFrameRegister(MF); 327 328 if (!AFI->hasStackFrame()) { 329 if (NumBytes != 0) 330 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes); 331 } else { 332 // Unwind MBBI to point to first LDR / VLDRD. 333 const unsigned *CSRegs = RegInfo->getCalleeSavedRegs(); 334 if (MBBI != MBB.begin()) { 335 do 336 --MBBI; 337 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs)); 338 if (!isCSRestore(MBBI, TII, CSRegs)) 339 ++MBBI; 340 } 341 342 // Move SP to start of FP callee save spill area. 343 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + 344 AFI->getGPRCalleeSavedArea2Size() + 345 AFI->getDPRCalleeSavedAreaSize()); 346 347 // Reset SP based on frame pointer only if the stack frame extends beyond 348 // frame pointer stack slot or target is ELF and the function has FP. 349 if (AFI->shouldRestoreSPFromFP()) { 350 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 351 if (NumBytes) { 352 if (isARM) 353 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes, 354 ARMCC::AL, 0, TII); 355 else { 356 // It's not possible to restore SP from FP in a single instruction. 357 // For Darwin, this looks like: 358 // mov sp, r7 359 // sub sp, #24 360 // This is bad, if an interrupt is taken after the mov, sp is in an 361 // inconsistent state. 362 // Use the first callee-saved register as a scratch register. 363 assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) && 364 "No scratch register to restore SP from FP!"); 365 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes, 366 ARMCC::AL, 0, TII); 367 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), 368 ARM::SP) 369 .addReg(ARM::R4)); 370 } 371 } else { 372 // Thumb2 or ARM. 373 if (isARM) 374 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP) 375 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 376 else 377 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), 378 ARM::SP) 379 .addReg(FramePtr)); 380 } 381 } else if (NumBytes) 382 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes); 383 384 // Increment past our save areas. 385 if (AFI->getDPRCalleeSavedAreaSize()) { 386 MBBI++; 387 // Since vpop register list cannot have gaps, there may be multiple vpop 388 // instructions in the epilogue. 389 while (MBBI->getOpcode() == ARM::VLDMDIA_UPD) 390 MBBI++; 391 } 392 if (AFI->getGPRCalleeSavedArea2Size()) MBBI++; 393 if (AFI->getGPRCalleeSavedArea1Size()) MBBI++; 394 } 395 396 if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND || 397 RetOpcode == ARM::TCRETURNri || RetOpcode == ARM::TCRETURNriND) { 398 // Tail call return: adjust the stack pointer and jump to callee. 399 MBBI = MBB.getLastNonDebugInstr(); 400 MachineOperand &JumpTarget = MBBI->getOperand(0); 401 402 // Jump to label or value in register. 403 if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND) { 404 unsigned TCOpcode = (RetOpcode == ARM::TCRETURNdi) 405 ? (STI.isThumb() ? ARM::tTAILJMPd : ARM::TAILJMPd) 406 : (STI.isThumb() ? ARM::tTAILJMPdND : ARM::TAILJMPdND); 407 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode)); 408 if (JumpTarget.isGlobal()) 409 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), 410 JumpTarget.getTargetFlags()); 411 else { 412 assert(JumpTarget.isSymbol()); 413 MIB.addExternalSymbol(JumpTarget.getSymbolName(), 414 JumpTarget.getTargetFlags()); 415 } 416 } else if (RetOpcode == ARM::TCRETURNri) { 417 BuildMI(MBB, MBBI, dl, 418 TII.get(STI.isThumb() ? ARM::tTAILJMPr : ARM::TAILJMPr)). 419 addReg(JumpTarget.getReg(), RegState::Kill); 420 } else if (RetOpcode == ARM::TCRETURNriND) { 421 BuildMI(MBB, MBBI, dl, 422 TII.get(STI.isThumb() ? ARM::tTAILJMPrND : ARM::TAILJMPrND)). 423 addReg(JumpTarget.getReg(), RegState::Kill); 424 } 425 426 MachineInstr *NewMI = prior(MBBI); 427 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i) 428 NewMI->addOperand(MBBI->getOperand(i)); 429 430 // Delete the pseudo instruction TCRETURN. 431 MBB.erase(MBBI); 432 MBBI = NewMI; 433 } 434 435 if (VARegSaveSize) 436 emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize); 437 } 438 439 /// getFrameIndexReference - Provide a base+offset reference to an FI slot for 440 /// debug info. It's the same as what we use for resolving the code-gen 441 /// references for now. FIXME: This can go wrong when references are 442 /// SP-relative and simple call frames aren't used. 443 int 444 ARMFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, 445 unsigned &FrameReg) const { 446 return ResolveFrameIndexReference(MF, FI, FrameReg, 0); 447 } 448 449 int 450 ARMFrameLowering::ResolveFrameIndexReference(const MachineFunction &MF, 451 int FI, unsigned &FrameReg, 452 int SPAdj) const { 453 const MachineFrameInfo *MFI = MF.getFrameInfo(); 454 const ARMBaseRegisterInfo *RegInfo = 455 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo()); 456 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 457 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize(); 458 int FPOffset = Offset - AFI->getFramePtrSpillOffset(); 459 bool isFixed = MFI->isFixedObjectIndex(FI); 460 461 FrameReg = ARM::SP; 462 Offset += SPAdj; 463 if (AFI->isGPRCalleeSavedArea1Frame(FI)) 464 return Offset - AFI->getGPRCalleeSavedArea1Offset(); 465 else if (AFI->isGPRCalleeSavedArea2Frame(FI)) 466 return Offset - AFI->getGPRCalleeSavedArea2Offset(); 467 else if (AFI->isDPRCalleeSavedAreaFrame(FI)) 468 return Offset - AFI->getDPRCalleeSavedAreaOffset(); 469 470 // When dynamically realigning the stack, use the frame pointer for 471 // parameters, and the stack/base pointer for locals. 472 if (RegInfo->needsStackRealignment(MF)) { 473 assert (hasFP(MF) && "dynamic stack realignment without a FP!"); 474 if (isFixed) { 475 FrameReg = RegInfo->getFrameRegister(MF); 476 Offset = FPOffset; 477 } else if (MFI->hasVarSizedObjects()) { 478 assert(RegInfo->hasBasePointer(MF) && 479 "VLAs and dynamic stack alignment, but missing base pointer!"); 480 FrameReg = RegInfo->getBaseRegister(); 481 } 482 return Offset; 483 } 484 485 // If there is a frame pointer, use it when we can. 486 if (hasFP(MF) && AFI->hasStackFrame()) { 487 // Use frame pointer to reference fixed objects. Use it for locals if 488 // there are VLAs (and thus the SP isn't reliable as a base). 489 if (isFixed || (MFI->hasVarSizedObjects() && 490 !RegInfo->hasBasePointer(MF))) { 491 FrameReg = RegInfo->getFrameRegister(MF); 492 return FPOffset; 493 } else if (MFI->hasVarSizedObjects()) { 494 assert(RegInfo->hasBasePointer(MF) && "missing base pointer!"); 495 if (AFI->isThumb2Function()) { 496 // Try to use the frame pointer if we can, else use the base pointer 497 // since it's available. This is handy for the emergency spill slot, in 498 // particular. 499 if (FPOffset >= -255 && FPOffset < 0) { 500 FrameReg = RegInfo->getFrameRegister(MF); 501 return FPOffset; 502 } 503 } 504 } else if (AFI->isThumb2Function()) { 505 // Use add <rd>, sp, #<imm8> 506 // ldr <rd>, [sp, #<imm8>] 507 // if at all possible to save space. 508 if (Offset >= 0 && (Offset & 3) == 0 && Offset <= 1020) 509 return Offset; 510 // In Thumb2 mode, the negative offset is very limited. Try to avoid 511 // out of range references. ldr <rt>,[<rn>, #-<imm8>] 512 if (FPOffset >= -255 && FPOffset < 0) { 513 FrameReg = RegInfo->getFrameRegister(MF); 514 return FPOffset; 515 } 516 } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) { 517 // Otherwise, use SP or FP, whichever is closer to the stack slot. 518 FrameReg = RegInfo->getFrameRegister(MF); 519 return FPOffset; 520 } 521 } 522 // Use the base pointer if we have one. 523 if (RegInfo->hasBasePointer(MF)) 524 FrameReg = RegInfo->getBaseRegister(); 525 return Offset; 526 } 527 528 int ARMFrameLowering::getFrameIndexOffset(const MachineFunction &MF, 529 int FI) const { 530 unsigned FrameReg; 531 return getFrameIndexReference(MF, FI, FrameReg); 532 } 533 534 void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB, 535 MachineBasicBlock::iterator MI, 536 const std::vector<CalleeSavedInfo> &CSI, 537 unsigned StmOpc, unsigned StrOpc, 538 bool NoGap, 539 bool(*Func)(unsigned, bool), 540 unsigned MIFlags) const { 541 MachineFunction &MF = *MBB.getParent(); 542 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 543 544 DebugLoc DL; 545 if (MI != MBB.end()) DL = MI->getDebugLoc(); 546 547 SmallVector<std::pair<unsigned,bool>, 4> Regs; 548 unsigned i = CSI.size(); 549 while (i != 0) { 550 unsigned LastReg = 0; 551 for (; i != 0; --i) { 552 unsigned Reg = CSI[i-1].getReg(); 553 if (!(Func)(Reg, STI.isTargetDarwin())) continue; 554 555 // Add the callee-saved register as live-in unless it's LR and 556 // @llvm.returnaddress is called. If LR is returned for 557 // @llvm.returnaddress then it's already added to the function and 558 // entry block live-in sets. 559 bool isKill = true; 560 if (Reg == ARM::LR) { 561 if (MF.getFrameInfo()->isReturnAddressTaken() && 562 MF.getRegInfo().isLiveIn(Reg)) 563 isKill = false; 564 } 565 566 if (isKill) 567 MBB.addLiveIn(Reg); 568 569 // If NoGap is true, push consecutive registers and then leave the rest 570 // for other instructions. e.g. 571 // vpush {d8, d10, d11} -> vpush {d8}, vpush {d10, d11} 572 if (NoGap && LastReg && LastReg != Reg-1) 573 break; 574 LastReg = Reg; 575 Regs.push_back(std::make_pair(Reg, isKill)); 576 } 577 578 if (Regs.empty()) 579 continue; 580 if (Regs.size() > 1 || StrOpc== 0) { 581 MachineInstrBuilder MIB = 582 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP) 583 .addReg(ARM::SP).setMIFlags(MIFlags)); 584 for (unsigned i = 0, e = Regs.size(); i < e; ++i) 585 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second)); 586 } else if (Regs.size() == 1) { 587 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc), 588 ARM::SP) 589 .addReg(Regs[0].first, getKillRegState(Regs[0].second)) 590 .addReg(ARM::SP).setMIFlags(MIFlags); 591 // ARM mode needs an extra reg0 here due to addrmode2. Will go away once 592 // that refactoring is complete (eventually). 593 if (StrOpc == ARM::STR_PRE) { 594 MIB.addReg(0); 595 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::sub, 4, ARM_AM::no_shift)); 596 } else 597 MIB.addImm(-4); 598 AddDefaultPred(MIB); 599 } 600 Regs.clear(); 601 } 602 } 603 604 void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB, 605 MachineBasicBlock::iterator MI, 606 const std::vector<CalleeSavedInfo> &CSI, 607 unsigned LdmOpc, unsigned LdrOpc, 608 bool isVarArg, bool NoGap, 609 bool(*Func)(unsigned, bool)) const { 610 MachineFunction &MF = *MBB.getParent(); 611 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 612 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 613 DebugLoc DL = MI->getDebugLoc(); 614 unsigned RetOpcode = MI->getOpcode(); 615 bool isTailCall = (RetOpcode == ARM::TCRETURNdi || 616 RetOpcode == ARM::TCRETURNdiND || 617 RetOpcode == ARM::TCRETURNri || 618 RetOpcode == ARM::TCRETURNriND); 619 620 SmallVector<unsigned, 4> Regs; 621 unsigned i = CSI.size(); 622 while (i != 0) { 623 unsigned LastReg = 0; 624 bool DeleteRet = false; 625 for (; i != 0; --i) { 626 unsigned Reg = CSI[i-1].getReg(); 627 if (!(Func)(Reg, STI.isTargetDarwin())) continue; 628 629 if (Reg == ARM::LR && !isTailCall && !isVarArg && STI.hasV5TOps()) { 630 Reg = ARM::PC; 631 LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET; 632 // Fold the return instruction into the LDM. 633 DeleteRet = true; 634 } 635 636 // If NoGap is true, pop consecutive registers and then leave the rest 637 // for other instructions. e.g. 638 // vpop {d8, d10, d11} -> vpop {d8}, vpop {d10, d11} 639 if (NoGap && LastReg && LastReg != Reg-1) 640 break; 641 642 LastReg = Reg; 643 Regs.push_back(Reg); 644 } 645 646 if (Regs.empty()) 647 continue; 648 if (Regs.size() > 1 || LdrOpc == 0) { 649 MachineInstrBuilder MIB = 650 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP) 651 .addReg(ARM::SP)); 652 for (unsigned i = 0, e = Regs.size(); i < e; ++i) 653 MIB.addReg(Regs[i], getDefRegState(true)); 654 if (DeleteRet) 655 MI->eraseFromParent(); 656 MI = MIB; 657 } else if (Regs.size() == 1) { 658 // If we adjusted the reg to PC from LR above, switch it back here. We 659 // only do that for LDM. 660 if (Regs[0] == ARM::PC) 661 Regs[0] = ARM::LR; 662 MachineInstrBuilder MIB = 663 BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0]) 664 .addReg(ARM::SP, RegState::Define) 665 .addReg(ARM::SP); 666 // ARM mode needs an extra reg0 here due to addrmode2. Will go away once 667 // that refactoring is complete (eventually). 668 if (LdrOpc == ARM::LDR_POST) { 669 MIB.addReg(0); 670 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift)); 671 } else 672 MIB.addImm(4); 673 AddDefaultPred(MIB); 674 } 675 Regs.clear(); 676 } 677 } 678 679 bool ARMFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 680 MachineBasicBlock::iterator MI, 681 const std::vector<CalleeSavedInfo> &CSI, 682 const TargetRegisterInfo *TRI) const { 683 if (CSI.empty()) 684 return false; 685 686 MachineFunction &MF = *MBB.getParent(); 687 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 688 689 unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD; 690 unsigned PushOneOpc = AFI->isThumbFunction() ? ARM::t2STR_PRE : ARM::STR_PRE; 691 unsigned FltOpc = ARM::VSTMDDB_UPD; 692 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea1Register, 693 MachineInstr::FrameSetup); 694 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea2Register, 695 MachineInstr::FrameSetup); 696 emitPushInst(MBB, MI, CSI, FltOpc, 0, true, &isARMArea3Register, 697 MachineInstr::FrameSetup); 698 699 return true; 700 } 701 702 bool ARMFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 703 MachineBasicBlock::iterator MI, 704 const std::vector<CalleeSavedInfo> &CSI, 705 const TargetRegisterInfo *TRI) const { 706 if (CSI.empty()) 707 return false; 708 709 MachineFunction &MF = *MBB.getParent(); 710 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 711 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0; 712 713 unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD; 714 unsigned LdrOpc = AFI->isThumbFunction() ? ARM::t2LDR_POST : ARM::LDR_POST; 715 unsigned FltOpc = ARM::VLDMDIA_UPD; 716 emitPopInst(MBB, MI, CSI, FltOpc, 0, isVarArg, true, &isARMArea3Register); 717 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false, 718 &isARMArea2Register); 719 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false, 720 &isARMArea1Register); 721 722 return true; 723 } 724 725 // FIXME: Make generic? 726 static unsigned GetFunctionSizeInBytes(const MachineFunction &MF, 727 const ARMBaseInstrInfo &TII) { 728 unsigned FnSize = 0; 729 for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end(); 730 MBBI != E; ++MBBI) { 731 const MachineBasicBlock &MBB = *MBBI; 732 for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end(); 733 I != E; ++I) 734 FnSize += TII.GetInstSizeInBytes(I); 735 } 736 return FnSize; 737 } 738 739 /// estimateStackSize - Estimate and return the size of the frame. 740 /// FIXME: Make generic? 741 static unsigned estimateStackSize(MachineFunction &MF) { 742 const MachineFrameInfo *MFI = MF.getFrameInfo(); 743 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 744 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); 745 unsigned MaxAlign = MFI->getMaxAlignment(); 746 int Offset = 0; 747 748 // This code is very, very similar to PEI::calculateFrameObjectOffsets(). 749 // It really should be refactored to share code. Until then, changes 750 // should keep in mind that there's tight coupling between the two. 751 752 for (int i = MFI->getObjectIndexBegin(); i != 0; ++i) { 753 int FixedOff = -MFI->getObjectOffset(i); 754 if (FixedOff > Offset) Offset = FixedOff; 755 } 756 for (unsigned i = 0, e = MFI->getObjectIndexEnd(); i != e; ++i) { 757 if (MFI->isDeadObjectIndex(i)) 758 continue; 759 Offset += MFI->getObjectSize(i); 760 unsigned Align = MFI->getObjectAlignment(i); 761 // Adjust to alignment boundary 762 Offset = (Offset+Align-1)/Align*Align; 763 764 MaxAlign = std::max(Align, MaxAlign); 765 } 766 767 if (MFI->adjustsStack() && TFI->hasReservedCallFrame(MF)) 768 Offset += MFI->getMaxCallFrameSize(); 769 770 // Round up the size to a multiple of the alignment. If the function has 771 // any calls or alloca's, align to the target's StackAlignment value to 772 // ensure that the callee's frame or the alloca data is suitably aligned; 773 // otherwise, for leaf functions, align to the TransientStackAlignment 774 // value. 775 unsigned StackAlign; 776 if (MFI->adjustsStack() || MFI->hasVarSizedObjects() || 777 (RegInfo->needsStackRealignment(MF) && MFI->getObjectIndexEnd() != 0)) 778 StackAlign = TFI->getStackAlignment(); 779 else 780 StackAlign = TFI->getTransientStackAlignment(); 781 782 // If the frame pointer is eliminated, all frame offsets will be relative to 783 // SP not FP. Align to MaxAlign so this works. 784 StackAlign = std::max(StackAlign, MaxAlign); 785 unsigned AlignMask = StackAlign - 1; 786 Offset = (Offset + AlignMask) & ~uint64_t(AlignMask); 787 788 return (unsigned)Offset; 789 } 790 791 /// estimateRSStackSizeLimit - Look at each instruction that references stack 792 /// frames and return the stack size limit beyond which some of these 793 /// instructions will require a scratch register during their expansion later. 794 // FIXME: Move to TII? 795 static unsigned estimateRSStackSizeLimit(MachineFunction &MF, 796 const TargetFrameLowering *TFI) { 797 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 798 unsigned Limit = (1 << 12) - 1; 799 for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) { 800 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); 801 I != E; ++I) { 802 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) { 803 if (!I->getOperand(i).isFI()) continue; 804 805 // When using ADDri to get the address of a stack object, 255 is the 806 // largest offset guaranteed to fit in the immediate offset. 807 if (I->getOpcode() == ARM::ADDri) { 808 Limit = std::min(Limit, (1U << 8) - 1); 809 break; 810 } 811 812 // Otherwise check the addressing mode. 813 switch (I->getDesc().TSFlags & ARMII::AddrModeMask) { 814 case ARMII::AddrMode3: 815 case ARMII::AddrModeT2_i8: 816 Limit = std::min(Limit, (1U << 8) - 1); 817 break; 818 case ARMII::AddrMode5: 819 case ARMII::AddrModeT2_i8s4: 820 Limit = std::min(Limit, ((1U << 8) - 1) * 4); 821 break; 822 case ARMII::AddrModeT2_i12: 823 // i12 supports only positive offset so these will be converted to 824 // i8 opcodes. See llvm::rewriteT2FrameIndex. 825 if (TFI->hasFP(MF) && AFI->hasStackFrame()) 826 Limit = std::min(Limit, (1U << 8) - 1); 827 break; 828 case ARMII::AddrMode4: 829 case ARMII::AddrMode6: 830 // Addressing modes 4 & 6 (load/store) instructions can't encode an 831 // immediate offset for stack references. 832 return 0; 833 default: 834 break; 835 } 836 break; // At most one FI per instruction 837 } 838 } 839 } 840 841 return Limit; 842 } 843 844 void 845 ARMFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 846 RegScavenger *RS) const { 847 // This tells PEI to spill the FP as if it is any other callee-save register 848 // to take advantage the eliminateFrameIndex machinery. This also ensures it 849 // is spilled in the order specified by getCalleeSavedRegs() to make it easier 850 // to combine multiple loads / stores. 851 bool CanEliminateFrame = true; 852 bool CS1Spilled = false; 853 bool LRSpilled = false; 854 unsigned NumGPRSpills = 0; 855 SmallVector<unsigned, 4> UnspilledCS1GPRs; 856 SmallVector<unsigned, 4> UnspilledCS2GPRs; 857 const ARMBaseRegisterInfo *RegInfo = 858 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo()); 859 const ARMBaseInstrInfo &TII = 860 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo()); 861 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 862 MachineFrameInfo *MFI = MF.getFrameInfo(); 863 unsigned FramePtr = RegInfo->getFrameRegister(MF); 864 865 // Spill R4 if Thumb2 function requires stack realignment - it will be used as 866 // scratch register. Also spill R4 if Thumb2 function has varsized objects, 867 // since it's not always possible to restore sp from fp in a single 868 // instruction. 869 // FIXME: It will be better just to find spare register here. 870 if (AFI->isThumb2Function() && 871 (MFI->hasVarSizedObjects() || RegInfo->needsStackRealignment(MF))) 872 MF.getRegInfo().setPhysRegUsed(ARM::R4); 873 874 if (AFI->isThumb1OnlyFunction()) { 875 // Spill LR if Thumb1 function uses variable length argument lists. 876 if (AFI->getVarArgsRegSaveSize() > 0) 877 MF.getRegInfo().setPhysRegUsed(ARM::LR); 878 879 // Spill R4 if Thumb1 epilogue has to restore SP from FP. We don't know 880 // for sure what the stack size will be, but for this, an estimate is good 881 // enough. If there anything changes it, it'll be a spill, which implies 882 // we've used all the registers and so R4 is already used, so not marking 883 // it here will be OK. 884 // FIXME: It will be better just to find spare register here. 885 unsigned StackSize = estimateStackSize(MF); 886 if (MFI->hasVarSizedObjects() || StackSize > 508) 887 MF.getRegInfo().setPhysRegUsed(ARM::R4); 888 } 889 890 // Spill the BasePtr if it's used. 891 if (RegInfo->hasBasePointer(MF)) 892 MF.getRegInfo().setPhysRegUsed(RegInfo->getBaseRegister()); 893 894 // Don't spill FP if the frame can be eliminated. This is determined 895 // by scanning the callee-save registers to see if any is used. 896 const unsigned *CSRegs = RegInfo->getCalleeSavedRegs(); 897 for (unsigned i = 0; CSRegs[i]; ++i) { 898 unsigned Reg = CSRegs[i]; 899 bool Spilled = false; 900 if (MF.getRegInfo().isPhysRegUsed(Reg)) { 901 Spilled = true; 902 CanEliminateFrame = false; 903 } else { 904 // Check alias registers too. 905 for (const unsigned *Aliases = 906 RegInfo->getAliasSet(Reg); *Aliases; ++Aliases) { 907 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) { 908 Spilled = true; 909 CanEliminateFrame = false; 910 } 911 } 912 } 913 914 if (!ARM::GPRRegisterClass->contains(Reg)) 915 continue; 916 917 if (Spilled) { 918 NumGPRSpills++; 919 920 if (!STI.isTargetDarwin()) { 921 if (Reg == ARM::LR) 922 LRSpilled = true; 923 CS1Spilled = true; 924 continue; 925 } 926 927 // Keep track if LR and any of R4, R5, R6, and R7 is spilled. 928 switch (Reg) { 929 case ARM::LR: 930 LRSpilled = true; 931 // Fallthrough 932 case ARM::R4: case ARM::R5: 933 case ARM::R6: case ARM::R7: 934 CS1Spilled = true; 935 break; 936 default: 937 break; 938 } 939 } else { 940 if (!STI.isTargetDarwin()) { 941 UnspilledCS1GPRs.push_back(Reg); 942 continue; 943 } 944 945 switch (Reg) { 946 case ARM::R4: case ARM::R5: 947 case ARM::R6: case ARM::R7: 948 case ARM::LR: 949 UnspilledCS1GPRs.push_back(Reg); 950 break; 951 default: 952 UnspilledCS2GPRs.push_back(Reg); 953 break; 954 } 955 } 956 } 957 958 bool ForceLRSpill = false; 959 if (!LRSpilled && AFI->isThumb1OnlyFunction()) { 960 unsigned FnSize = GetFunctionSizeInBytes(MF, TII); 961 // Force LR to be spilled if the Thumb function size is > 2048. This enables 962 // use of BL to implement far jump. If it turns out that it's not needed 963 // then the branch fix up path will undo it. 964 if (FnSize >= (1 << 11)) { 965 CanEliminateFrame = false; 966 ForceLRSpill = true; 967 } 968 } 969 970 // If any of the stack slot references may be out of range of an immediate 971 // offset, make sure a register (or a spill slot) is available for the 972 // register scavenger. Note that if we're indexing off the frame pointer, the 973 // effective stack size is 4 bytes larger since the FP points to the stack 974 // slot of the previous FP. Also, if we have variable sized objects in the 975 // function, stack slot references will often be negative, and some of 976 // our instructions are positive-offset only, so conservatively consider 977 // that case to want a spill slot (or register) as well. Similarly, if 978 // the function adjusts the stack pointer during execution and the 979 // adjustments aren't already part of our stack size estimate, our offset 980 // calculations may be off, so be conservative. 981 // FIXME: We could add logic to be more precise about negative offsets 982 // and which instructions will need a scratch register for them. Is it 983 // worth the effort and added fragility? 984 bool BigStack = 985 (RS && 986 (estimateStackSize(MF) + ((hasFP(MF) && AFI->hasStackFrame()) ? 4:0) >= 987 estimateRSStackSizeLimit(MF, this))) 988 || MFI->hasVarSizedObjects() 989 || (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF)); 990 991 bool ExtraCSSpill = false; 992 if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF)) { 993 AFI->setHasStackFrame(true); 994 995 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. 996 // Spill LR as well so we can fold BX_RET to the registers restore (LDM). 997 if (!LRSpilled && CS1Spilled) { 998 MF.getRegInfo().setPhysRegUsed(ARM::LR); 999 NumGPRSpills++; 1000 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(), 1001 UnspilledCS1GPRs.end(), (unsigned)ARM::LR)); 1002 ForceLRSpill = false; 1003 ExtraCSSpill = true; 1004 } 1005 1006 if (hasFP(MF)) { 1007 MF.getRegInfo().setPhysRegUsed(FramePtr); 1008 NumGPRSpills++; 1009 } 1010 1011 // If stack and double are 8-byte aligned and we are spilling an odd number 1012 // of GPRs, spill one extra callee save GPR so we won't have to pad between 1013 // the integer and double callee save areas. 1014 unsigned TargetAlign = getStackAlignment(); 1015 if (TargetAlign == 8 && (NumGPRSpills & 1)) { 1016 if (CS1Spilled && !UnspilledCS1GPRs.empty()) { 1017 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) { 1018 unsigned Reg = UnspilledCS1GPRs[i]; 1019 // Don't spill high register if the function is thumb1 1020 if (!AFI->isThumb1OnlyFunction() || 1021 isARMLowRegister(Reg) || Reg == ARM::LR) { 1022 MF.getRegInfo().setPhysRegUsed(Reg); 1023 if (!RegInfo->isReservedReg(MF, Reg)) 1024 ExtraCSSpill = true; 1025 break; 1026 } 1027 } 1028 } else if (!UnspilledCS2GPRs.empty() && !AFI->isThumb1OnlyFunction()) { 1029 unsigned Reg = UnspilledCS2GPRs.front(); 1030 MF.getRegInfo().setPhysRegUsed(Reg); 1031 if (!RegInfo->isReservedReg(MF, Reg)) 1032 ExtraCSSpill = true; 1033 } 1034 } 1035 1036 // Estimate if we might need to scavenge a register at some point in order 1037 // to materialize a stack offset. If so, either spill one additional 1038 // callee-saved register or reserve a special spill slot to facilitate 1039 // register scavenging. Thumb1 needs a spill slot for stack pointer 1040 // adjustments also, even when the frame itself is small. 1041 if (BigStack && !ExtraCSSpill) { 1042 // If any non-reserved CS register isn't spilled, just spill one or two 1043 // extra. That should take care of it! 1044 unsigned NumExtras = TargetAlign / 4; 1045 SmallVector<unsigned, 2> Extras; 1046 while (NumExtras && !UnspilledCS1GPRs.empty()) { 1047 unsigned Reg = UnspilledCS1GPRs.back(); 1048 UnspilledCS1GPRs.pop_back(); 1049 if (!RegInfo->isReservedReg(MF, Reg) && 1050 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) || 1051 Reg == ARM::LR)) { 1052 Extras.push_back(Reg); 1053 NumExtras--; 1054 } 1055 } 1056 // For non-Thumb1 functions, also check for hi-reg CS registers 1057 if (!AFI->isThumb1OnlyFunction()) { 1058 while (NumExtras && !UnspilledCS2GPRs.empty()) { 1059 unsigned Reg = UnspilledCS2GPRs.back(); 1060 UnspilledCS2GPRs.pop_back(); 1061 if (!RegInfo->isReservedReg(MF, Reg)) { 1062 Extras.push_back(Reg); 1063 NumExtras--; 1064 } 1065 } 1066 } 1067 if (Extras.size() && NumExtras == 0) { 1068 for (unsigned i = 0, e = Extras.size(); i != e; ++i) { 1069 MF.getRegInfo().setPhysRegUsed(Extras[i]); 1070 } 1071 } else if (!AFI->isThumb1OnlyFunction()) { 1072 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot 1073 // closest to SP or frame pointer. 1074 const TargetRegisterClass *RC = ARM::GPRRegisterClass; 1075 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1076 RC->getAlignment(), 1077 false)); 1078 } 1079 } 1080 } 1081 1082 if (ForceLRSpill) { 1083 MF.getRegInfo().setPhysRegUsed(ARM::LR); 1084 AFI->setLRIsSpilledForFarJump(true); 1085 } 1086 } 1087