1 //===-- ARMFrameLowering.cpp - ARM Frame Information ----------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the ARM implementation of TargetFrameLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "ARMFrameLowering.h" 15 #include "ARMBaseInstrInfo.h" 16 #include "ARMBaseRegisterInfo.h" 17 #include "ARMConstantPoolValue.h" 18 #include "ARMMachineFunctionInfo.h" 19 #include "MCTargetDesc/ARMAddressingModes.h" 20 #include "llvm/CodeGen/MachineFrameInfo.h" 21 #include "llvm/CodeGen/MachineFunction.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineModuleInfo.h" 24 #include "llvm/CodeGen/MachineRegisterInfo.h" 25 #include "llvm/CodeGen/RegisterScavenging.h" 26 #include "llvm/IR/CallingConv.h" 27 #include "llvm/IR/Function.h" 28 #include "llvm/MC/MCContext.h" 29 #include "llvm/Support/CommandLine.h" 30 #include "llvm/Target/TargetOptions.h" 31 32 using namespace llvm; 33 34 static cl::opt<bool> 35 SpillAlignedNEONRegs("align-neon-spills", cl::Hidden, cl::init(true), 36 cl::desc("Align ARM NEON spills in prolog and epilog")); 37 38 static MachineBasicBlock::iterator 39 skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI, 40 unsigned NumAlignedDPRCS2Regs); 41 42 ARMFrameLowering::ARMFrameLowering(const ARMSubtarget &sti) 43 : TargetFrameLowering(StackGrowsDown, sti.getStackAlignment(), 0, 4), 44 STI(sti) {} 45 46 bool ARMFrameLowering::noFramePointerElim(const MachineFunction &MF) const { 47 // iOS always has a FP for backtracking, force other targets to keep their FP 48 // when doing FastISel. The emitted code is currently superior, and in cases 49 // like test-suite's lencod FastISel isn't quite correct when FP is eliminated. 50 return TargetFrameLowering::noFramePointerElim(MF) || 51 MF.getSubtarget<ARMSubtarget>().useFastISel(); 52 } 53 54 /// hasFP - Return true if the specified function should have a dedicated frame 55 /// pointer register. This is true if the function has variable sized allocas 56 /// or if frame pointer elimination is disabled. 57 bool ARMFrameLowering::hasFP(const MachineFunction &MF) const { 58 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); 59 60 // iOS requires FP not to be clobbered for backtracing purpose. 61 if (STI.isTargetIOS()) 62 return true; 63 64 const MachineFrameInfo *MFI = MF.getFrameInfo(); 65 // Always eliminate non-leaf frame pointers. 66 return ((MF.getTarget().Options.DisableFramePointerElim(MF) && 67 MFI->hasCalls()) || 68 RegInfo->needsStackRealignment(MF) || 69 MFI->hasVarSizedObjects() || 70 MFI->isFrameAddressTaken()); 71 } 72 73 /// hasReservedCallFrame - Under normal circumstances, when a frame pointer is 74 /// not required, we reserve argument space for call sites in the function 75 /// immediately on entry to the current function. This eliminates the need for 76 /// add/sub sp brackets around call sites. Returns true if the call frame is 77 /// included as part of the stack frame. 78 bool ARMFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { 79 const MachineFrameInfo *FFI = MF.getFrameInfo(); 80 unsigned CFSize = FFI->getMaxCallFrameSize(); 81 // It's not always a good idea to include the call frame as part of the 82 // stack frame. ARM (especially Thumb) has small immediate offset to 83 // address the stack frame. So a large call frame can cause poor codegen 84 // and may even makes it impossible to scavenge a register. 85 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12 86 return false; 87 88 return !MF.getFrameInfo()->hasVarSizedObjects(); 89 } 90 91 /// canSimplifyCallFramePseudos - If there is a reserved call frame, the 92 /// call frame pseudos can be simplified. Unlike most targets, having a FP 93 /// is not sufficient here since we still may reference some objects via SP 94 /// even when FP is available in Thumb2 mode. 95 bool 96 ARMFrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const { 97 return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects(); 98 } 99 100 static bool isCSRestore(MachineInstr *MI, 101 const ARMBaseInstrInfo &TII, 102 const MCPhysReg *CSRegs) { 103 // Integer spill area is handled with "pop". 104 if (isPopOpcode(MI->getOpcode())) { 105 // The first two operands are predicates. The last two are 106 // imp-def and imp-use of SP. Check everything in between. 107 for (int i = 5, e = MI->getNumOperands(); i != e; ++i) 108 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs)) 109 return false; 110 return true; 111 } 112 if ((MI->getOpcode() == ARM::LDR_POST_IMM || 113 MI->getOpcode() == ARM::LDR_POST_REG || 114 MI->getOpcode() == ARM::t2LDR_POST) && 115 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs) && 116 MI->getOperand(1).getReg() == ARM::SP) 117 return true; 118 119 return false; 120 } 121 122 static void emitRegPlusImmediate(bool isARM, MachineBasicBlock &MBB, 123 MachineBasicBlock::iterator &MBBI, DebugLoc dl, 124 const ARMBaseInstrInfo &TII, unsigned DestReg, 125 unsigned SrcReg, int NumBytes, 126 unsigned MIFlags = MachineInstr::NoFlags, 127 ARMCC::CondCodes Pred = ARMCC::AL, 128 unsigned PredReg = 0) { 129 if (isARM) 130 emitARMRegPlusImmediate(MBB, MBBI, dl, DestReg, SrcReg, NumBytes, 131 Pred, PredReg, TII, MIFlags); 132 else 133 emitT2RegPlusImmediate(MBB, MBBI, dl, DestReg, SrcReg, NumBytes, 134 Pred, PredReg, TII, MIFlags); 135 } 136 137 static void emitSPUpdate(bool isARM, MachineBasicBlock &MBB, 138 MachineBasicBlock::iterator &MBBI, DebugLoc dl, 139 const ARMBaseInstrInfo &TII, int NumBytes, 140 unsigned MIFlags = MachineInstr::NoFlags, 141 ARMCC::CondCodes Pred = ARMCC::AL, 142 unsigned PredReg = 0) { 143 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes, 144 MIFlags, Pred, PredReg); 145 } 146 147 static int sizeOfSPAdjustment(const MachineInstr *MI) { 148 int RegSize; 149 switch (MI->getOpcode()) { 150 case ARM::VSTMDDB_UPD: 151 RegSize = 8; 152 break; 153 case ARM::STMDB_UPD: 154 case ARM::t2STMDB_UPD: 155 RegSize = 4; 156 break; 157 case ARM::t2STR_PRE: 158 case ARM::STR_PRE_IMM: 159 return 4; 160 default: 161 llvm_unreachable("Unknown push or pop like instruction"); 162 } 163 164 int count = 0; 165 // ARM and Thumb2 push/pop insts have explicit "sp, sp" operands (+ 166 // pred) so the list starts at 4. 167 for (int i = MI->getNumOperands() - 1; i >= 4; --i) 168 count += RegSize; 169 return count; 170 } 171 172 static bool WindowsRequiresStackProbe(const MachineFunction &MF, 173 size_t StackSizeInBytes) { 174 const MachineFrameInfo *MFI = MF.getFrameInfo(); 175 const Function *F = MF.getFunction(); 176 unsigned StackProbeSize = (MFI->getStackProtectorIndex() > 0) ? 4080 : 4096; 177 if (F->hasFnAttribute("stack-probe-size")) 178 F->getFnAttribute("stack-probe-size") 179 .getValueAsString() 180 .getAsInteger(0, StackProbeSize); 181 return StackSizeInBytes >= StackProbeSize; 182 } 183 184 namespace { 185 struct StackAdjustingInsts { 186 struct InstInfo { 187 MachineBasicBlock::iterator I; 188 unsigned SPAdjust; 189 bool BeforeFPSet; 190 }; 191 192 SmallVector<InstInfo, 4> Insts; 193 194 void addInst(MachineBasicBlock::iterator I, unsigned SPAdjust, 195 bool BeforeFPSet = false) { 196 InstInfo Info = {I, SPAdjust, BeforeFPSet}; 197 Insts.push_back(Info); 198 } 199 200 void addExtraBytes(const MachineBasicBlock::iterator I, unsigned ExtraBytes) { 201 auto Info = std::find_if(Insts.begin(), Insts.end(), 202 [&](InstInfo &Info) { return Info.I == I; }); 203 assert(Info != Insts.end() && "invalid sp adjusting instruction"); 204 Info->SPAdjust += ExtraBytes; 205 } 206 207 void emitDefCFAOffsets(MachineModuleInfo &MMI, MachineBasicBlock &MBB, 208 DebugLoc dl, const ARMBaseInstrInfo &TII, bool HasFP) { 209 unsigned CFAOffset = 0; 210 for (auto &Info : Insts) { 211 if (HasFP && !Info.BeforeFPSet) 212 return; 213 214 CFAOffset -= Info.SPAdjust; 215 unsigned CFIIndex = MMI.addFrameInst( 216 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset)); 217 BuildMI(MBB, std::next(Info.I), dl, 218 TII.get(TargetOpcode::CFI_INSTRUCTION)) 219 .addCFIIndex(CFIIndex) 220 .setMIFlags(MachineInstr::FrameSetup); 221 } 222 } 223 }; 224 } 225 226 /// Emit an instruction sequence that will align the address in 227 /// register Reg by zero-ing out the lower bits. For versions of the 228 /// architecture that support Neon, this must be done in a single 229 /// instruction, since skipAlignedDPRCS2Spills assumes it is done in a 230 /// single instruction. That function only gets called when optimizing 231 /// spilling of D registers on a core with the Neon instruction set 232 /// present. 233 static void emitAligningInstructions(MachineFunction &MF, ARMFunctionInfo *AFI, 234 const TargetInstrInfo &TII, 235 MachineBasicBlock &MBB, 236 MachineBasicBlock::iterator MBBI, 237 DebugLoc DL, const unsigned Reg, 238 const unsigned Alignment, 239 const bool MustBeSingleInstruction) { 240 const ARMSubtarget &AST = 241 static_cast<const ARMSubtarget &>(MF.getSubtarget()); 242 const bool CanUseBFC = AST.hasV6T2Ops() || AST.hasV7Ops(); 243 const unsigned AlignMask = Alignment - 1; 244 const unsigned NrBitsToZero = countTrailingZeros(Alignment); 245 assert(!AFI->isThumb1OnlyFunction() && "Thumb1 not supported"); 246 if (!AFI->isThumbFunction()) { 247 // if the BFC instruction is available, use that to zero the lower 248 // bits: 249 // bfc Reg, #0, log2(Alignment) 250 // otherwise use BIC, if the mask to zero the required number of bits 251 // can be encoded in the bic immediate field 252 // bic Reg, Reg, Alignment-1 253 // otherwise, emit 254 // lsr Reg, Reg, log2(Alignment) 255 // lsl Reg, Reg, log2(Alignment) 256 if (CanUseBFC) { 257 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::BFC), Reg) 258 .addReg(Reg, RegState::Kill) 259 .addImm(~AlignMask)); 260 } else if (AlignMask <= 255) { 261 AddDefaultCC( 262 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::BICri), Reg) 263 .addReg(Reg, RegState::Kill) 264 .addImm(AlignMask))); 265 } else { 266 assert(!MustBeSingleInstruction && 267 "Shouldn't call emitAligningInstructions demanding a single " 268 "instruction to be emitted for large stack alignment for a target " 269 "without BFC."); 270 AddDefaultCC(AddDefaultPred( 271 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg) 272 .addReg(Reg, RegState::Kill) 273 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsr, NrBitsToZero)))); 274 AddDefaultCC(AddDefaultPred( 275 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg) 276 .addReg(Reg, RegState::Kill) 277 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, NrBitsToZero)))); 278 } 279 } else { 280 // Since this is only reached for Thumb-2 targets, the BFC instruction 281 // should always be available. 282 assert(CanUseBFC); 283 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::t2BFC), Reg) 284 .addReg(Reg, RegState::Kill) 285 .addImm(~AlignMask)); 286 } 287 } 288 289 void ARMFrameLowering::emitPrologue(MachineFunction &MF, 290 MachineBasicBlock &MBB) const { 291 MachineBasicBlock::iterator MBBI = MBB.begin(); 292 MachineFrameInfo *MFI = MF.getFrameInfo(); 293 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 294 MachineModuleInfo &MMI = MF.getMMI(); 295 MCContext &Context = MMI.getContext(); 296 const TargetMachine &TM = MF.getTarget(); 297 const MCRegisterInfo *MRI = Context.getRegisterInfo(); 298 const ARMBaseRegisterInfo *RegInfo = STI.getRegisterInfo(); 299 const ARMBaseInstrInfo &TII = *STI.getInstrInfo(); 300 assert(!AFI->isThumb1OnlyFunction() && 301 "This emitPrologue does not support Thumb1!"); 302 bool isARM = !AFI->isThumbFunction(); 303 unsigned Align = STI.getFrameLowering()->getStackAlignment(); 304 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(); 305 unsigned NumBytes = MFI->getStackSize(); 306 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 307 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); 308 unsigned FramePtr = RegInfo->getFrameRegister(MF); 309 310 // Determine the sizes of each callee-save spill areas and record which frame 311 // belongs to which callee-save spill areas. 312 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 313 int FramePtrSpillFI = 0; 314 int D8SpillFI = 0; 315 316 // All calls are tail calls in GHC calling conv, and functions have no 317 // prologue/epilogue. 318 if (MF.getFunction()->getCallingConv() == CallingConv::GHC) 319 return; 320 321 StackAdjustingInsts DefCFAOffsetCandidates; 322 bool HasFP = hasFP(MF); 323 324 // Allocate the vararg register save area. 325 if (ArgRegsSaveSize) { 326 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -ArgRegsSaveSize, 327 MachineInstr::FrameSetup); 328 DefCFAOffsetCandidates.addInst(std::prev(MBBI), ArgRegsSaveSize, true); 329 } 330 331 if (!AFI->hasStackFrame() && 332 (!STI.isTargetWindows() || !WindowsRequiresStackProbe(MF, NumBytes))) { 333 if (NumBytes - ArgRegsSaveSize != 0) { 334 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -(NumBytes - ArgRegsSaveSize), 335 MachineInstr::FrameSetup); 336 DefCFAOffsetCandidates.addInst(std::prev(MBBI), 337 NumBytes - ArgRegsSaveSize, true); 338 } 339 DefCFAOffsetCandidates.emitDefCFAOffsets(MMI, MBB, dl, TII, HasFP); 340 return; 341 } 342 343 // Determine spill area sizes. 344 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 345 unsigned Reg = CSI[i].getReg(); 346 int FI = CSI[i].getFrameIdx(); 347 switch (Reg) { 348 case ARM::R8: 349 case ARM::R9: 350 case ARM::R10: 351 case ARM::R11: 352 case ARM::R12: 353 if (STI.isTargetDarwin()) { 354 GPRCS2Size += 4; 355 break; 356 } 357 // fallthrough 358 case ARM::R0: 359 case ARM::R1: 360 case ARM::R2: 361 case ARM::R3: 362 case ARM::R4: 363 case ARM::R5: 364 case ARM::R6: 365 case ARM::R7: 366 case ARM::LR: 367 if (Reg == FramePtr) 368 FramePtrSpillFI = FI; 369 GPRCS1Size += 4; 370 break; 371 default: 372 // This is a DPR. Exclude the aligned DPRCS2 spills. 373 if (Reg == ARM::D8) 374 D8SpillFI = FI; 375 if (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs()) 376 DPRCSSize += 8; 377 } 378 } 379 380 // Move past area 1. 381 MachineBasicBlock::iterator LastPush = MBB.end(), GPRCS1Push, GPRCS2Push; 382 if (GPRCS1Size > 0) { 383 GPRCS1Push = LastPush = MBBI++; 384 DefCFAOffsetCandidates.addInst(LastPush, GPRCS1Size, true); 385 } 386 387 // Determine starting offsets of spill areas. 388 unsigned GPRCS1Offset = NumBytes - ArgRegsSaveSize - GPRCS1Size; 389 unsigned GPRCS2Offset = GPRCS1Offset - GPRCS2Size; 390 unsigned DPRAlign = DPRCSSize ? std::min(8U, Align) : 4U; 391 unsigned DPRGapSize = (GPRCS1Size + GPRCS2Size + ArgRegsSaveSize) % DPRAlign; 392 unsigned DPRCSOffset = GPRCS2Offset - DPRGapSize - DPRCSSize; 393 int FramePtrOffsetInPush = 0; 394 if (HasFP) { 395 FramePtrOffsetInPush = 396 MFI->getObjectOffset(FramePtrSpillFI) + ArgRegsSaveSize; 397 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + 398 NumBytes); 399 } 400 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 401 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 402 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 403 404 // Move past area 2. 405 if (GPRCS2Size > 0) { 406 GPRCS2Push = LastPush = MBBI++; 407 DefCFAOffsetCandidates.addInst(LastPush, GPRCS2Size); 408 } 409 410 // Prolog/epilog inserter assumes we correctly align DPRs on the stack, so our 411 // .cfi_offset operations will reflect that. 412 if (DPRGapSize) { 413 assert(DPRGapSize == 4 && "unexpected alignment requirements for DPRs"); 414 if (tryFoldSPUpdateIntoPushPop(STI, MF, LastPush, DPRGapSize)) 415 DefCFAOffsetCandidates.addExtraBytes(LastPush, DPRGapSize); 416 else { 417 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRGapSize, 418 MachineInstr::FrameSetup); 419 DefCFAOffsetCandidates.addInst(std::prev(MBBI), DPRGapSize); 420 } 421 } 422 423 // Move past area 3. 424 if (DPRCSSize > 0) { 425 // Since vpush register list cannot have gaps, there may be multiple vpush 426 // instructions in the prologue. 427 while (MBBI->getOpcode() == ARM::VSTMDDB_UPD) { 428 DefCFAOffsetCandidates.addInst(MBBI, sizeOfSPAdjustment(MBBI)); 429 LastPush = MBBI++; 430 } 431 } 432 433 // Move past the aligned DPRCS2 area. 434 if (AFI->getNumAlignedDPRCS2Regs() > 0) { 435 MBBI = skipAlignedDPRCS2Spills(MBBI, AFI->getNumAlignedDPRCS2Regs()); 436 // The code inserted by emitAlignedDPRCS2Spills realigns the stack, and 437 // leaves the stack pointer pointing to the DPRCS2 area. 438 // 439 // Adjust NumBytes to represent the stack slots below the DPRCS2 area. 440 NumBytes += MFI->getObjectOffset(D8SpillFI); 441 } else 442 NumBytes = DPRCSOffset; 443 444 if (STI.isTargetWindows() && WindowsRequiresStackProbe(MF, NumBytes)) { 445 uint32_t NumWords = NumBytes >> 2; 446 447 if (NumWords < 65536) 448 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4) 449 .addImm(NumWords) 450 .setMIFlags(MachineInstr::FrameSetup)); 451 else 452 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R4) 453 .addImm(NumWords) 454 .setMIFlags(MachineInstr::FrameSetup); 455 456 switch (TM.getCodeModel()) { 457 case CodeModel::Small: 458 case CodeModel::Medium: 459 case CodeModel::Default: 460 case CodeModel::Kernel: 461 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL)) 462 .addImm((unsigned)ARMCC::AL).addReg(0) 463 .addExternalSymbol("__chkstk") 464 .addReg(ARM::R4, RegState::Implicit) 465 .setMIFlags(MachineInstr::FrameSetup); 466 break; 467 case CodeModel::Large: 468 case CodeModel::JITDefault: 469 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12) 470 .addExternalSymbol("__chkstk") 471 .setMIFlags(MachineInstr::FrameSetup); 472 473 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBLXr)) 474 .addImm((unsigned)ARMCC::AL).addReg(0) 475 .addReg(ARM::R12, RegState::Kill) 476 .addReg(ARM::R4, RegState::Implicit) 477 .setMIFlags(MachineInstr::FrameSetup); 478 break; 479 } 480 481 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), 482 ARM::SP) 483 .addReg(ARM::SP, RegState::Define) 484 .addReg(ARM::R4, RegState::Kill) 485 .setMIFlags(MachineInstr::FrameSetup))); 486 NumBytes = 0; 487 } 488 489 if (NumBytes) { 490 // Adjust SP after all the callee-save spills. 491 if (AFI->getNumAlignedDPRCS2Regs() == 0 && 492 tryFoldSPUpdateIntoPushPop(STI, MF, LastPush, NumBytes)) 493 DefCFAOffsetCandidates.addExtraBytes(LastPush, NumBytes); 494 else { 495 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes, 496 MachineInstr::FrameSetup); 497 DefCFAOffsetCandidates.addInst(std::prev(MBBI), NumBytes); 498 } 499 500 if (HasFP && isARM) 501 // Restore from fp only in ARM mode: e.g. sub sp, r7, #24 502 // Note it's not safe to do this in Thumb2 mode because it would have 503 // taken two instructions: 504 // mov sp, r7 505 // sub sp, #24 506 // If an interrupt is taken between the two instructions, then sp is in 507 // an inconsistent state (pointing to the middle of callee-saved area). 508 // The interrupt handler can end up clobbering the registers. 509 AFI->setShouldRestoreSPFromFP(true); 510 } 511 512 // Set FP to point to the stack slot that contains the previous FP. 513 // For iOS, FP is R7, which has now been stored in spill area 1. 514 // Otherwise, if this is not iOS, all the callee-saved registers go 515 // into spill area 1, including the FP in R11. In either case, it 516 // is in area one and the adjustment needs to take place just after 517 // that push. 518 if (HasFP) { 519 MachineBasicBlock::iterator AfterPush = std::next(GPRCS1Push); 520 unsigned PushSize = sizeOfSPAdjustment(GPRCS1Push); 521 emitRegPlusImmediate(!AFI->isThumbFunction(), MBB, AfterPush, 522 dl, TII, FramePtr, ARM::SP, 523 PushSize + FramePtrOffsetInPush, 524 MachineInstr::FrameSetup); 525 if (FramePtrOffsetInPush + PushSize != 0) { 526 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfa( 527 nullptr, MRI->getDwarfRegNum(FramePtr, true), 528 -(ArgRegsSaveSize - FramePtrOffsetInPush))); 529 BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 530 .addCFIIndex(CFIIndex) 531 .setMIFlags(MachineInstr::FrameSetup); 532 } else { 533 unsigned CFIIndex = 534 MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister( 535 nullptr, MRI->getDwarfRegNum(FramePtr, true))); 536 BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 537 .addCFIIndex(CFIIndex) 538 .setMIFlags(MachineInstr::FrameSetup); 539 } 540 } 541 542 // Now that the prologue's actual instructions are finalised, we can insert 543 // the necessary DWARF cf instructions to describe the situation. Start by 544 // recording where each register ended up: 545 if (GPRCS1Size > 0) { 546 MachineBasicBlock::iterator Pos = std::next(GPRCS1Push); 547 int CFIIndex; 548 for (const auto &Entry : CSI) { 549 unsigned Reg = Entry.getReg(); 550 int FI = Entry.getFrameIdx(); 551 switch (Reg) { 552 case ARM::R8: 553 case ARM::R9: 554 case ARM::R10: 555 case ARM::R11: 556 case ARM::R12: 557 if (STI.isTargetDarwin()) 558 break; 559 // fallthrough 560 case ARM::R0: 561 case ARM::R1: 562 case ARM::R2: 563 case ARM::R3: 564 case ARM::R4: 565 case ARM::R5: 566 case ARM::R6: 567 case ARM::R7: 568 case ARM::LR: 569 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset( 570 nullptr, MRI->getDwarfRegNum(Reg, true), MFI->getObjectOffset(FI))); 571 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 572 .addCFIIndex(CFIIndex) 573 .setMIFlags(MachineInstr::FrameSetup); 574 break; 575 } 576 } 577 } 578 579 if (GPRCS2Size > 0) { 580 MachineBasicBlock::iterator Pos = std::next(GPRCS2Push); 581 for (const auto &Entry : CSI) { 582 unsigned Reg = Entry.getReg(); 583 int FI = Entry.getFrameIdx(); 584 switch (Reg) { 585 case ARM::R8: 586 case ARM::R9: 587 case ARM::R10: 588 case ARM::R11: 589 case ARM::R12: 590 if (STI.isTargetDarwin()) { 591 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true); 592 unsigned Offset = MFI->getObjectOffset(FI); 593 unsigned CFIIndex = MMI.addFrameInst( 594 MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset)); 595 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 596 .addCFIIndex(CFIIndex) 597 .setMIFlags(MachineInstr::FrameSetup); 598 } 599 break; 600 } 601 } 602 } 603 604 if (DPRCSSize > 0) { 605 // Since vpush register list cannot have gaps, there may be multiple vpush 606 // instructions in the prologue. 607 MachineBasicBlock::iterator Pos = std::next(LastPush); 608 for (const auto &Entry : CSI) { 609 unsigned Reg = Entry.getReg(); 610 int FI = Entry.getFrameIdx(); 611 if ((Reg >= ARM::D0 && Reg <= ARM::D31) && 612 (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())) { 613 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true); 614 unsigned Offset = MFI->getObjectOffset(FI); 615 unsigned CFIIndex = MMI.addFrameInst( 616 MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset)); 617 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 618 .addCFIIndex(CFIIndex) 619 .setMIFlags(MachineInstr::FrameSetup); 620 } 621 } 622 } 623 624 // Now we can emit descriptions of where the canonical frame address was 625 // throughout the process. If we have a frame pointer, it takes over the job 626 // half-way through, so only the first few .cfi_def_cfa_offset instructions 627 // actually get emitted. 628 DefCFAOffsetCandidates.emitDefCFAOffsets(MMI, MBB, dl, TII, HasFP); 629 630 if (STI.isTargetELF() && hasFP(MF)) 631 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() - 632 AFI->getFramePtrSpillOffset()); 633 634 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 635 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 636 AFI->setDPRCalleeSavedGapSize(DPRGapSize); 637 AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 638 639 // If we need dynamic stack realignment, do it here. Be paranoid and make 640 // sure if we also have VLAs, we have a base pointer for frame access. 641 // If aligned NEON registers were spilled, the stack has already been 642 // realigned. 643 if (!AFI->getNumAlignedDPRCS2Regs() && RegInfo->needsStackRealignment(MF)) { 644 unsigned MaxAlign = MFI->getMaxAlignment(); 645 assert(!AFI->isThumb1OnlyFunction()); 646 if (!AFI->isThumbFunction()) { 647 emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::SP, MaxAlign, 648 false); 649 } else { 650 // We cannot use sp as source/dest register here, thus we're using r4 to 651 // perform the calculations. We're emitting the following sequence: 652 // mov r4, sp 653 // -- use emitAligningInstructions to produce best sequence to zero 654 // -- out lower bits in r4 655 // mov sp, r4 656 // FIXME: It will be better just to find spare register here. 657 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4) 658 .addReg(ARM::SP, RegState::Kill)); 659 emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::R4, MaxAlign, 660 false); 661 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) 662 .addReg(ARM::R4, RegState::Kill)); 663 } 664 665 AFI->setShouldRestoreSPFromFP(true); 666 } 667 668 // If we need a base pointer, set it up here. It's whatever the value 669 // of the stack pointer is at this point. Any variable size objects 670 // will be allocated after this, so we can still use the base pointer 671 // to reference locals. 672 // FIXME: Clarify FrameSetup flags here. 673 if (RegInfo->hasBasePointer(MF)) { 674 if (isARM) 675 BuildMI(MBB, MBBI, dl, 676 TII.get(ARM::MOVr), RegInfo->getBaseRegister()) 677 .addReg(ARM::SP) 678 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 679 else 680 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), 681 RegInfo->getBaseRegister()) 682 .addReg(ARM::SP)); 683 } 684 685 // If the frame has variable sized objects then the epilogue must restore 686 // the sp from fp. We can assume there's an FP here since hasFP already 687 // checks for hasVarSizedObjects. 688 if (MFI->hasVarSizedObjects()) 689 AFI->setShouldRestoreSPFromFP(true); 690 } 691 692 void ARMFrameLowering::emitEpilogue(MachineFunction &MF, 693 MachineBasicBlock &MBB) const { 694 MachineFrameInfo *MFI = MF.getFrameInfo(); 695 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 696 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); 697 const ARMBaseInstrInfo &TII = 698 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo()); 699 assert(!AFI->isThumb1OnlyFunction() && 700 "This emitEpilogue does not support Thumb1!"); 701 bool isARM = !AFI->isThumbFunction(); 702 703 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(); 704 int NumBytes = (int)MFI->getStackSize(); 705 unsigned FramePtr = RegInfo->getFrameRegister(MF); 706 707 // All calls are tail calls in GHC calling conv, and functions have no 708 // prologue/epilogue. 709 if (MF.getFunction()->getCallingConv() == CallingConv::GHC) 710 return; 711 712 // First put ourselves on the first (from top) terminator instructions. 713 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator(); 714 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); 715 716 if (!AFI->hasStackFrame()) { 717 if (NumBytes - ArgRegsSaveSize != 0) 718 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes - ArgRegsSaveSize); 719 } else { 720 // Unwind MBBI to point to first LDR / VLDRD. 721 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF); 722 if (MBBI != MBB.begin()) { 723 do { 724 --MBBI; 725 } while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs)); 726 if (!isCSRestore(MBBI, TII, CSRegs)) 727 ++MBBI; 728 } 729 730 // Move SP to start of FP callee save spill area. 731 NumBytes -= (ArgRegsSaveSize + 732 AFI->getGPRCalleeSavedArea1Size() + 733 AFI->getGPRCalleeSavedArea2Size() + 734 AFI->getDPRCalleeSavedGapSize() + 735 AFI->getDPRCalleeSavedAreaSize()); 736 737 // Reset SP based on frame pointer only if the stack frame extends beyond 738 // frame pointer stack slot or target is ELF and the function has FP. 739 if (AFI->shouldRestoreSPFromFP()) { 740 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 741 if (NumBytes) { 742 if (isARM) 743 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes, 744 ARMCC::AL, 0, TII); 745 else { 746 // It's not possible to restore SP from FP in a single instruction. 747 // For iOS, this looks like: 748 // mov sp, r7 749 // sub sp, #24 750 // This is bad, if an interrupt is taken after the mov, sp is in an 751 // inconsistent state. 752 // Use the first callee-saved register as a scratch register. 753 assert(!MFI->getPristineRegs(MF).test(ARM::R4) && 754 "No scratch register to restore SP from FP!"); 755 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes, 756 ARMCC::AL, 0, TII); 757 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), 758 ARM::SP) 759 .addReg(ARM::R4)); 760 } 761 } else { 762 // Thumb2 or ARM. 763 if (isARM) 764 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP) 765 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 766 else 767 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), 768 ARM::SP) 769 .addReg(FramePtr)); 770 } 771 } else if (NumBytes && 772 !tryFoldSPUpdateIntoPushPop(STI, MF, MBBI, NumBytes)) 773 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes); 774 775 // Increment past our save areas. 776 if (AFI->getDPRCalleeSavedAreaSize()) { 777 MBBI++; 778 // Since vpop register list cannot have gaps, there may be multiple vpop 779 // instructions in the epilogue. 780 while (MBBI->getOpcode() == ARM::VLDMDIA_UPD) 781 MBBI++; 782 } 783 if (AFI->getDPRCalleeSavedGapSize()) { 784 assert(AFI->getDPRCalleeSavedGapSize() == 4 && 785 "unexpected DPR alignment gap"); 786 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedGapSize()); 787 } 788 789 if (AFI->getGPRCalleeSavedArea2Size()) MBBI++; 790 if (AFI->getGPRCalleeSavedArea1Size()) MBBI++; 791 } 792 793 if (ArgRegsSaveSize) 794 emitSPUpdate(isARM, MBB, MBBI, dl, TII, ArgRegsSaveSize); 795 } 796 797 /// getFrameIndexReference - Provide a base+offset reference to an FI slot for 798 /// debug info. It's the same as what we use for resolving the code-gen 799 /// references for now. FIXME: This can go wrong when references are 800 /// SP-relative and simple call frames aren't used. 801 int 802 ARMFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, 803 unsigned &FrameReg) const { 804 return ResolveFrameIndexReference(MF, FI, FrameReg, 0); 805 } 806 807 int 808 ARMFrameLowering::ResolveFrameIndexReference(const MachineFunction &MF, 809 int FI, unsigned &FrameReg, 810 int SPAdj) const { 811 const MachineFrameInfo *MFI = MF.getFrameInfo(); 812 const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>( 813 MF.getSubtarget().getRegisterInfo()); 814 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 815 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize(); 816 int FPOffset = Offset - AFI->getFramePtrSpillOffset(); 817 bool isFixed = MFI->isFixedObjectIndex(FI); 818 819 FrameReg = ARM::SP; 820 Offset += SPAdj; 821 822 // SP can move around if there are allocas. We may also lose track of SP 823 // when emergency spilling inside a non-reserved call frame setup. 824 bool hasMovingSP = !hasReservedCallFrame(MF); 825 826 // When dynamically realigning the stack, use the frame pointer for 827 // parameters, and the stack/base pointer for locals. 828 if (RegInfo->needsStackRealignment(MF)) { 829 assert (hasFP(MF) && "dynamic stack realignment without a FP!"); 830 if (isFixed) { 831 FrameReg = RegInfo->getFrameRegister(MF); 832 Offset = FPOffset; 833 } else if (hasMovingSP) { 834 assert(RegInfo->hasBasePointer(MF) && 835 "VLAs and dynamic stack alignment, but missing base pointer!"); 836 FrameReg = RegInfo->getBaseRegister(); 837 } 838 return Offset; 839 } 840 841 // If there is a frame pointer, use it when we can. 842 if (hasFP(MF) && AFI->hasStackFrame()) { 843 // Use frame pointer to reference fixed objects. Use it for locals if 844 // there are VLAs (and thus the SP isn't reliable as a base). 845 if (isFixed || (hasMovingSP && !RegInfo->hasBasePointer(MF))) { 846 FrameReg = RegInfo->getFrameRegister(MF); 847 return FPOffset; 848 } else if (hasMovingSP) { 849 assert(RegInfo->hasBasePointer(MF) && "missing base pointer!"); 850 if (AFI->isThumb2Function()) { 851 // Try to use the frame pointer if we can, else use the base pointer 852 // since it's available. This is handy for the emergency spill slot, in 853 // particular. 854 if (FPOffset >= -255 && FPOffset < 0) { 855 FrameReg = RegInfo->getFrameRegister(MF); 856 return FPOffset; 857 } 858 } 859 } else if (AFI->isThumb2Function()) { 860 // Use add <rd>, sp, #<imm8> 861 // ldr <rd>, [sp, #<imm8>] 862 // if at all possible to save space. 863 if (Offset >= 0 && (Offset & 3) == 0 && Offset <= 1020) 864 return Offset; 865 // In Thumb2 mode, the negative offset is very limited. Try to avoid 866 // out of range references. ldr <rt>,[<rn>, #-<imm8>] 867 if (FPOffset >= -255 && FPOffset < 0) { 868 FrameReg = RegInfo->getFrameRegister(MF); 869 return FPOffset; 870 } 871 } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) { 872 // Otherwise, use SP or FP, whichever is closer to the stack slot. 873 FrameReg = RegInfo->getFrameRegister(MF); 874 return FPOffset; 875 } 876 } 877 // Use the base pointer if we have one. 878 if (RegInfo->hasBasePointer(MF)) 879 FrameReg = RegInfo->getBaseRegister(); 880 return Offset; 881 } 882 883 void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB, 884 MachineBasicBlock::iterator MI, 885 const std::vector<CalleeSavedInfo> &CSI, 886 unsigned StmOpc, unsigned StrOpc, 887 bool NoGap, 888 bool(*Func)(unsigned, bool), 889 unsigned NumAlignedDPRCS2Regs, 890 unsigned MIFlags) const { 891 MachineFunction &MF = *MBB.getParent(); 892 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 893 894 DebugLoc DL; 895 if (MI != MBB.end()) DL = MI->getDebugLoc(); 896 897 SmallVector<std::pair<unsigned,bool>, 4> Regs; 898 unsigned i = CSI.size(); 899 while (i != 0) { 900 unsigned LastReg = 0; 901 for (; i != 0; --i) { 902 unsigned Reg = CSI[i-1].getReg(); 903 if (!(Func)(Reg, STI.isTargetDarwin())) continue; 904 905 // D-registers in the aligned area DPRCS2 are NOT spilled here. 906 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs) 907 continue; 908 909 // Add the callee-saved register as live-in unless it's LR and 910 // @llvm.returnaddress is called. If LR is returned for 911 // @llvm.returnaddress then it's already added to the function and 912 // entry block live-in sets. 913 bool isKill = true; 914 if (Reg == ARM::LR) { 915 if (MF.getFrameInfo()->isReturnAddressTaken() && 916 MF.getRegInfo().isLiveIn(Reg)) 917 isKill = false; 918 } 919 920 if (isKill) 921 MBB.addLiveIn(Reg); 922 923 // If NoGap is true, push consecutive registers and then leave the rest 924 // for other instructions. e.g. 925 // vpush {d8, d10, d11} -> vpush {d8}, vpush {d10, d11} 926 if (NoGap && LastReg && LastReg != Reg-1) 927 break; 928 LastReg = Reg; 929 Regs.push_back(std::make_pair(Reg, isKill)); 930 } 931 932 if (Regs.empty()) 933 continue; 934 if (Regs.size() > 1 || StrOpc== 0) { 935 MachineInstrBuilder MIB = 936 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP) 937 .addReg(ARM::SP).setMIFlags(MIFlags)); 938 for (unsigned i = 0, e = Regs.size(); i < e; ++i) 939 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second)); 940 } else if (Regs.size() == 1) { 941 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc), 942 ARM::SP) 943 .addReg(Regs[0].first, getKillRegState(Regs[0].second)) 944 .addReg(ARM::SP).setMIFlags(MIFlags) 945 .addImm(-4); 946 AddDefaultPred(MIB); 947 } 948 Regs.clear(); 949 950 // Put any subsequent vpush instructions before this one: they will refer to 951 // higher register numbers so need to be pushed first in order to preserve 952 // monotonicity. 953 if (MI != MBB.begin()) 954 --MI; 955 } 956 } 957 958 void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB, 959 MachineBasicBlock::iterator MI, 960 const std::vector<CalleeSavedInfo> &CSI, 961 unsigned LdmOpc, unsigned LdrOpc, 962 bool isVarArg, bool NoGap, 963 bool(*Func)(unsigned, bool), 964 unsigned NumAlignedDPRCS2Regs) const { 965 MachineFunction &MF = *MBB.getParent(); 966 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 967 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 968 DebugLoc DL; 969 bool isTailCall = false; 970 bool isInterrupt = false; 971 bool isTrap = false; 972 if (MBB.end() != MI) { 973 DL = MI->getDebugLoc(); 974 unsigned RetOpcode = MI->getOpcode(); 975 isTailCall = (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNri); 976 isInterrupt = 977 RetOpcode == ARM::SUBS_PC_LR || RetOpcode == ARM::t2SUBS_PC_LR; 978 isTrap = 979 RetOpcode == ARM::TRAP || RetOpcode == ARM::TRAPNaCl || 980 RetOpcode == ARM::tTRAP; 981 } 982 983 SmallVector<unsigned, 4> Regs; 984 unsigned i = CSI.size(); 985 while (i != 0) { 986 unsigned LastReg = 0; 987 bool DeleteRet = false; 988 for (; i != 0; --i) { 989 unsigned Reg = CSI[i-1].getReg(); 990 if (!(Func)(Reg, STI.isTargetDarwin())) continue; 991 992 // The aligned reloads from area DPRCS2 are not inserted here. 993 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs) 994 continue; 995 996 if (Reg == ARM::LR && !isTailCall && !isVarArg && !isInterrupt && 997 !isTrap && STI.hasV5TOps()) { 998 if (MBB.succ_empty()) { 999 Reg = ARM::PC; 1000 DeleteRet = true; 1001 LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET; 1002 } else 1003 LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD; 1004 // Fold the return instruction into the LDM. 1005 } 1006 1007 // If NoGap is true, pop consecutive registers and then leave the rest 1008 // for other instructions. e.g. 1009 // vpop {d8, d10, d11} -> vpop {d8}, vpop {d10, d11} 1010 if (NoGap && LastReg && LastReg != Reg-1) 1011 break; 1012 1013 LastReg = Reg; 1014 Regs.push_back(Reg); 1015 } 1016 1017 if (Regs.empty()) 1018 continue; 1019 if (Regs.size() > 1 || LdrOpc == 0) { 1020 MachineInstrBuilder MIB = 1021 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP) 1022 .addReg(ARM::SP)); 1023 for (unsigned i = 0, e = Regs.size(); i < e; ++i) 1024 MIB.addReg(Regs[i], getDefRegState(true)); 1025 if (DeleteRet && MI != MBB.end()) { 1026 MIB.copyImplicitOps(&*MI); 1027 MI->eraseFromParent(); 1028 } 1029 MI = MIB; 1030 } else if (Regs.size() == 1) { 1031 // If we adjusted the reg to PC from LR above, switch it back here. We 1032 // only do that for LDM. 1033 if (Regs[0] == ARM::PC) 1034 Regs[0] = ARM::LR; 1035 MachineInstrBuilder MIB = 1036 BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0]) 1037 .addReg(ARM::SP, RegState::Define) 1038 .addReg(ARM::SP); 1039 // ARM mode needs an extra reg0 here due to addrmode2. Will go away once 1040 // that refactoring is complete (eventually). 1041 if (LdrOpc == ARM::LDR_POST_REG || LdrOpc == ARM::LDR_POST_IMM) { 1042 MIB.addReg(0); 1043 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift)); 1044 } else 1045 MIB.addImm(4); 1046 AddDefaultPred(MIB); 1047 } 1048 Regs.clear(); 1049 1050 // Put any subsequent vpop instructions after this one: they will refer to 1051 // higher register numbers so need to be popped afterwards. 1052 if (MI != MBB.end()) 1053 ++MI; 1054 } 1055 } 1056 1057 /// Emit aligned spill instructions for NumAlignedDPRCS2Regs D-registers 1058 /// starting from d8. Also insert stack realignment code and leave the stack 1059 /// pointer pointing to the d8 spill slot. 1060 static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB, 1061 MachineBasicBlock::iterator MI, 1062 unsigned NumAlignedDPRCS2Regs, 1063 const std::vector<CalleeSavedInfo> &CSI, 1064 const TargetRegisterInfo *TRI) { 1065 MachineFunction &MF = *MBB.getParent(); 1066 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1067 DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc(); 1068 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 1069 MachineFrameInfo &MFI = *MF.getFrameInfo(); 1070 1071 // Mark the D-register spill slots as properly aligned. Since MFI computes 1072 // stack slot layout backwards, this can actually mean that the d-reg stack 1073 // slot offsets can be wrong. The offset for d8 will always be correct. 1074 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1075 unsigned DNum = CSI[i].getReg() - ARM::D8; 1076 if (DNum >= 8) 1077 continue; 1078 int FI = CSI[i].getFrameIdx(); 1079 // The even-numbered registers will be 16-byte aligned, the odd-numbered 1080 // registers will be 8-byte aligned. 1081 MFI.setObjectAlignment(FI, DNum % 2 ? 8 : 16); 1082 1083 // The stack slot for D8 needs to be maximally aligned because this is 1084 // actually the point where we align the stack pointer. MachineFrameInfo 1085 // computes all offsets relative to the incoming stack pointer which is a 1086 // bit weird when realigning the stack. Any extra padding for this 1087 // over-alignment is not realized because the code inserted below adjusts 1088 // the stack pointer by numregs * 8 before aligning the stack pointer. 1089 if (DNum == 0) 1090 MFI.setObjectAlignment(FI, MFI.getMaxAlignment()); 1091 } 1092 1093 // Move the stack pointer to the d8 spill slot, and align it at the same 1094 // time. Leave the stack slot address in the scratch register r4. 1095 // 1096 // sub r4, sp, #numregs * 8 1097 // bic r4, r4, #align - 1 1098 // mov sp, r4 1099 // 1100 bool isThumb = AFI->isThumbFunction(); 1101 assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1"); 1102 AFI->setShouldRestoreSPFromFP(true); 1103 1104 // sub r4, sp, #numregs * 8 1105 // The immediate is <= 64, so it doesn't need any special encoding. 1106 unsigned Opc = isThumb ? ARM::t2SUBri : ARM::SUBri; 1107 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4) 1108 .addReg(ARM::SP) 1109 .addImm(8 * NumAlignedDPRCS2Regs))); 1110 1111 unsigned MaxAlign = MF.getFrameInfo()->getMaxAlignment(); 1112 // We must set parameter MustBeSingleInstruction to true, since 1113 // skipAlignedDPRCS2Spills expects exactly 3 instructions to perform 1114 // stack alignment. Luckily, this can always be done since all ARM 1115 // architecture versions that support Neon also support the BFC 1116 // instruction. 1117 emitAligningInstructions(MF, AFI, TII, MBB, MI, DL, ARM::R4, MaxAlign, true); 1118 1119 // mov sp, r4 1120 // The stack pointer must be adjusted before spilling anything, otherwise 1121 // the stack slots could be clobbered by an interrupt handler. 1122 // Leave r4 live, it is used below. 1123 Opc = isThumb ? ARM::tMOVr : ARM::MOVr; 1124 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP) 1125 .addReg(ARM::R4); 1126 MIB = AddDefaultPred(MIB); 1127 if (!isThumb) 1128 AddDefaultCC(MIB); 1129 1130 // Now spill NumAlignedDPRCS2Regs registers starting from d8. 1131 // r4 holds the stack slot address. 1132 unsigned NextReg = ARM::D8; 1133 1134 // 16-byte aligned vst1.64 with 4 d-regs and address writeback. 1135 // The writeback is only needed when emitting two vst1.64 instructions. 1136 if (NumAlignedDPRCS2Regs >= 6) { 1137 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, 1138 &ARM::QQPRRegClass); 1139 MBB.addLiveIn(SupReg); 1140 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed), 1141 ARM::R4) 1142 .addReg(ARM::R4, RegState::Kill).addImm(16) 1143 .addReg(NextReg) 1144 .addReg(SupReg, RegState::ImplicitKill)); 1145 NextReg += 4; 1146 NumAlignedDPRCS2Regs -= 4; 1147 } 1148 1149 // We won't modify r4 beyond this point. It currently points to the next 1150 // register to be spilled. 1151 unsigned R4BaseReg = NextReg; 1152 1153 // 16-byte aligned vst1.64 with 4 d-regs, no writeback. 1154 if (NumAlignedDPRCS2Regs >= 4) { 1155 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, 1156 &ARM::QQPRRegClass); 1157 MBB.addLiveIn(SupReg); 1158 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Q)) 1159 .addReg(ARM::R4).addImm(16).addReg(NextReg) 1160 .addReg(SupReg, RegState::ImplicitKill)); 1161 NextReg += 4; 1162 NumAlignedDPRCS2Regs -= 4; 1163 } 1164 1165 // 16-byte aligned vst1.64 with 2 d-regs. 1166 if (NumAlignedDPRCS2Regs >= 2) { 1167 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, 1168 &ARM::QPRRegClass); 1169 MBB.addLiveIn(SupReg); 1170 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64)) 1171 .addReg(ARM::R4).addImm(16).addReg(SupReg)); 1172 NextReg += 2; 1173 NumAlignedDPRCS2Regs -= 2; 1174 } 1175 1176 // Finally, use a vanilla vstr.64 for the odd last register. 1177 if (NumAlignedDPRCS2Regs) { 1178 MBB.addLiveIn(NextReg); 1179 // vstr.64 uses addrmode5 which has an offset scale of 4. 1180 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VSTRD)) 1181 .addReg(NextReg) 1182 .addReg(ARM::R4).addImm((NextReg-R4BaseReg)*2)); 1183 } 1184 1185 // The last spill instruction inserted should kill the scratch register r4. 1186 std::prev(MI)->addRegisterKilled(ARM::R4, TRI); 1187 } 1188 1189 /// Skip past the code inserted by emitAlignedDPRCS2Spills, and return an 1190 /// iterator to the following instruction. 1191 static MachineBasicBlock::iterator 1192 skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI, 1193 unsigned NumAlignedDPRCS2Regs) { 1194 // sub r4, sp, #numregs * 8 1195 // bic r4, r4, #align - 1 1196 // mov sp, r4 1197 ++MI; ++MI; ++MI; 1198 assert(MI->mayStore() && "Expecting spill instruction"); 1199 1200 // These switches all fall through. 1201 switch(NumAlignedDPRCS2Regs) { 1202 case 7: 1203 ++MI; 1204 assert(MI->mayStore() && "Expecting spill instruction"); 1205 default: 1206 ++MI; 1207 assert(MI->mayStore() && "Expecting spill instruction"); 1208 case 1: 1209 case 2: 1210 case 4: 1211 assert(MI->killsRegister(ARM::R4) && "Missed kill flag"); 1212 ++MI; 1213 } 1214 return MI; 1215 } 1216 1217 /// Emit aligned reload instructions for NumAlignedDPRCS2Regs D-registers 1218 /// starting from d8. These instructions are assumed to execute while the 1219 /// stack is still aligned, unlike the code inserted by emitPopInst. 1220 static void emitAlignedDPRCS2Restores(MachineBasicBlock &MBB, 1221 MachineBasicBlock::iterator MI, 1222 unsigned NumAlignedDPRCS2Regs, 1223 const std::vector<CalleeSavedInfo> &CSI, 1224 const TargetRegisterInfo *TRI) { 1225 MachineFunction &MF = *MBB.getParent(); 1226 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1227 DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc(); 1228 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 1229 1230 // Find the frame index assigned to d8. 1231 int D8SpillFI = 0; 1232 for (unsigned i = 0, e = CSI.size(); i != e; ++i) 1233 if (CSI[i].getReg() == ARM::D8) { 1234 D8SpillFI = CSI[i].getFrameIdx(); 1235 break; 1236 } 1237 1238 // Materialize the address of the d8 spill slot into the scratch register r4. 1239 // This can be fairly complicated if the stack frame is large, so just use 1240 // the normal frame index elimination mechanism to do it. This code runs as 1241 // the initial part of the epilog where the stack and base pointers haven't 1242 // been changed yet. 1243 bool isThumb = AFI->isThumbFunction(); 1244 assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1"); 1245 1246 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri; 1247 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4) 1248 .addFrameIndex(D8SpillFI).addImm(0))); 1249 1250 // Now restore NumAlignedDPRCS2Regs registers starting from d8. 1251 unsigned NextReg = ARM::D8; 1252 1253 // 16-byte aligned vld1.64 with 4 d-regs and writeback. 1254 if (NumAlignedDPRCS2Regs >= 6) { 1255 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, 1256 &ARM::QQPRRegClass); 1257 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg) 1258 .addReg(ARM::R4, RegState::Define) 1259 .addReg(ARM::R4, RegState::Kill).addImm(16) 1260 .addReg(SupReg, RegState::ImplicitDefine)); 1261 NextReg += 4; 1262 NumAlignedDPRCS2Regs -= 4; 1263 } 1264 1265 // We won't modify r4 beyond this point. It currently points to the next 1266 // register to be spilled. 1267 unsigned R4BaseReg = NextReg; 1268 1269 // 16-byte aligned vld1.64 with 4 d-regs, no writeback. 1270 if (NumAlignedDPRCS2Regs >= 4) { 1271 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, 1272 &ARM::QQPRRegClass); 1273 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg) 1274 .addReg(ARM::R4).addImm(16) 1275 .addReg(SupReg, RegState::ImplicitDefine)); 1276 NextReg += 4; 1277 NumAlignedDPRCS2Regs -= 4; 1278 } 1279 1280 // 16-byte aligned vld1.64 with 2 d-regs. 1281 if (NumAlignedDPRCS2Regs >= 2) { 1282 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, 1283 &ARM::QPRRegClass); 1284 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), SupReg) 1285 .addReg(ARM::R4).addImm(16)); 1286 NextReg += 2; 1287 NumAlignedDPRCS2Regs -= 2; 1288 } 1289 1290 // Finally, use a vanilla vldr.64 for the remaining odd register. 1291 if (NumAlignedDPRCS2Regs) 1292 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg) 1293 .addReg(ARM::R4).addImm(2*(NextReg-R4BaseReg))); 1294 1295 // Last store kills r4. 1296 std::prev(MI)->addRegisterKilled(ARM::R4, TRI); 1297 } 1298 1299 bool ARMFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 1300 MachineBasicBlock::iterator MI, 1301 const std::vector<CalleeSavedInfo> &CSI, 1302 const TargetRegisterInfo *TRI) const { 1303 if (CSI.empty()) 1304 return false; 1305 1306 MachineFunction &MF = *MBB.getParent(); 1307 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1308 1309 unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD; 1310 unsigned PushOneOpc = AFI->isThumbFunction() ? 1311 ARM::t2STR_PRE : ARM::STR_PRE_IMM; 1312 unsigned FltOpc = ARM::VSTMDDB_UPD; 1313 unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs(); 1314 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea1Register, 0, 1315 MachineInstr::FrameSetup); 1316 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea2Register, 0, 1317 MachineInstr::FrameSetup); 1318 emitPushInst(MBB, MI, CSI, FltOpc, 0, true, &isARMArea3Register, 1319 NumAlignedDPRCS2Regs, MachineInstr::FrameSetup); 1320 1321 // The code above does not insert spill code for the aligned DPRCS2 registers. 1322 // The stack realignment code will be inserted between the push instructions 1323 // and these spills. 1324 if (NumAlignedDPRCS2Regs) 1325 emitAlignedDPRCS2Spills(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI); 1326 1327 return true; 1328 } 1329 1330 bool ARMFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 1331 MachineBasicBlock::iterator MI, 1332 const std::vector<CalleeSavedInfo> &CSI, 1333 const TargetRegisterInfo *TRI) const { 1334 if (CSI.empty()) 1335 return false; 1336 1337 MachineFunction &MF = *MBB.getParent(); 1338 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1339 bool isVarArg = AFI->getArgRegsSaveSize() > 0; 1340 unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs(); 1341 1342 // The emitPopInst calls below do not insert reloads for the aligned DPRCS2 1343 // registers. Do that here instead. 1344 if (NumAlignedDPRCS2Regs) 1345 emitAlignedDPRCS2Restores(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI); 1346 1347 unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD; 1348 unsigned LdrOpc = AFI->isThumbFunction() ? ARM::t2LDR_POST :ARM::LDR_POST_IMM; 1349 unsigned FltOpc = ARM::VLDMDIA_UPD; 1350 emitPopInst(MBB, MI, CSI, FltOpc, 0, isVarArg, true, &isARMArea3Register, 1351 NumAlignedDPRCS2Regs); 1352 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false, 1353 &isARMArea2Register, 0); 1354 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false, 1355 &isARMArea1Register, 0); 1356 1357 return true; 1358 } 1359 1360 // FIXME: Make generic? 1361 static unsigned GetFunctionSizeInBytes(const MachineFunction &MF, 1362 const ARMBaseInstrInfo &TII) { 1363 unsigned FnSize = 0; 1364 for (auto &MBB : MF) { 1365 for (auto &MI : MBB) 1366 FnSize += TII.GetInstSizeInBytes(&MI); 1367 } 1368 return FnSize; 1369 } 1370 1371 /// estimateRSStackSizeLimit - Look at each instruction that references stack 1372 /// frames and return the stack size limit beyond which some of these 1373 /// instructions will require a scratch register during their expansion later. 1374 // FIXME: Move to TII? 1375 static unsigned estimateRSStackSizeLimit(MachineFunction &MF, 1376 const TargetFrameLowering *TFI) { 1377 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1378 unsigned Limit = (1 << 12) - 1; 1379 for (auto &MBB : MF) { 1380 for (auto &MI : MBB) { 1381 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 1382 if (!MI.getOperand(i).isFI()) 1383 continue; 1384 1385 // When using ADDri to get the address of a stack object, 255 is the 1386 // largest offset guaranteed to fit in the immediate offset. 1387 if (MI.getOpcode() == ARM::ADDri) { 1388 Limit = std::min(Limit, (1U << 8) - 1); 1389 break; 1390 } 1391 1392 // Otherwise check the addressing mode. 1393 switch (MI.getDesc().TSFlags & ARMII::AddrModeMask) { 1394 case ARMII::AddrMode3: 1395 case ARMII::AddrModeT2_i8: 1396 Limit = std::min(Limit, (1U << 8) - 1); 1397 break; 1398 case ARMII::AddrMode5: 1399 case ARMII::AddrModeT2_i8s4: 1400 Limit = std::min(Limit, ((1U << 8) - 1) * 4); 1401 break; 1402 case ARMII::AddrModeT2_i12: 1403 // i12 supports only positive offset so these will be converted to 1404 // i8 opcodes. See llvm::rewriteT2FrameIndex. 1405 if (TFI->hasFP(MF) && AFI->hasStackFrame()) 1406 Limit = std::min(Limit, (1U << 8) - 1); 1407 break; 1408 case ARMII::AddrMode4: 1409 case ARMII::AddrMode6: 1410 // Addressing modes 4 & 6 (load/store) instructions can't encode an 1411 // immediate offset for stack references. 1412 return 0; 1413 default: 1414 break; 1415 } 1416 break; // At most one FI per instruction 1417 } 1418 } 1419 } 1420 1421 return Limit; 1422 } 1423 1424 // In functions that realign the stack, it can be an advantage to spill the 1425 // callee-saved vector registers after realigning the stack. The vst1 and vld1 1426 // instructions take alignment hints that can improve performance. 1427 // 1428 static void 1429 checkNumAlignedDPRCS2Regs(MachineFunction &MF, BitVector &SavedRegs) { 1430 MF.getInfo<ARMFunctionInfo>()->setNumAlignedDPRCS2Regs(0); 1431 if (!SpillAlignedNEONRegs) 1432 return; 1433 1434 // Naked functions don't spill callee-saved registers. 1435 if (MF.getFunction()->hasFnAttribute(Attribute::Naked)) 1436 return; 1437 1438 // We are planning to use NEON instructions vst1 / vld1. 1439 if (!static_cast<const ARMSubtarget &>(MF.getSubtarget()).hasNEON()) 1440 return; 1441 1442 // Don't bother if the default stack alignment is sufficiently high. 1443 if (MF.getSubtarget().getFrameLowering()->getStackAlignment() >= 8) 1444 return; 1445 1446 // Aligned spills require stack realignment. 1447 if (!static_cast<const ARMBaseRegisterInfo *>( 1448 MF.getSubtarget().getRegisterInfo())->canRealignStack(MF)) 1449 return; 1450 1451 // We always spill contiguous d-registers starting from d8. Count how many 1452 // needs spilling. The register allocator will almost always use the 1453 // callee-saved registers in order, but it can happen that there are holes in 1454 // the range. Registers above the hole will be spilled to the standard DPRCS 1455 // area. 1456 unsigned NumSpills = 0; 1457 for (; NumSpills < 8; ++NumSpills) 1458 if (!SavedRegs.test(ARM::D8 + NumSpills)) 1459 break; 1460 1461 // Don't do this for just one d-register. It's not worth it. 1462 if (NumSpills < 2) 1463 return; 1464 1465 // Spill the first NumSpills D-registers after realigning the stack. 1466 MF.getInfo<ARMFunctionInfo>()->setNumAlignedDPRCS2Regs(NumSpills); 1467 1468 // A scratch register is required for the vst1 / vld1 instructions. 1469 SavedRegs.set(ARM::R4); 1470 } 1471 1472 void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF, 1473 BitVector &SavedRegs, 1474 RegScavenger *RS) const { 1475 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS); 1476 // This tells PEI to spill the FP as if it is any other callee-save register 1477 // to take advantage the eliminateFrameIndex machinery. This also ensures it 1478 // is spilled in the order specified by getCalleeSavedRegs() to make it easier 1479 // to combine multiple loads / stores. 1480 bool CanEliminateFrame = true; 1481 bool CS1Spilled = false; 1482 bool LRSpilled = false; 1483 unsigned NumGPRSpills = 0; 1484 SmallVector<unsigned, 4> UnspilledCS1GPRs; 1485 SmallVector<unsigned, 4> UnspilledCS2GPRs; 1486 const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>( 1487 MF.getSubtarget().getRegisterInfo()); 1488 const ARMBaseInstrInfo &TII = 1489 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo()); 1490 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1491 MachineFrameInfo *MFI = MF.getFrameInfo(); 1492 MachineRegisterInfo &MRI = MF.getRegInfo(); 1493 unsigned FramePtr = RegInfo->getFrameRegister(MF); 1494 1495 // Spill R4 if Thumb2 function requires stack realignment - it will be used as 1496 // scratch register. Also spill R4 if Thumb2 function has varsized objects, 1497 // since it's not always possible to restore sp from fp in a single 1498 // instruction. 1499 // FIXME: It will be better just to find spare register here. 1500 if (AFI->isThumb2Function() && 1501 (MFI->hasVarSizedObjects() || RegInfo->needsStackRealignment(MF))) 1502 SavedRegs.set(ARM::R4); 1503 1504 if (AFI->isThumb1OnlyFunction()) { 1505 // Spill LR if Thumb1 function uses variable length argument lists. 1506 if (AFI->getArgRegsSaveSize() > 0) 1507 SavedRegs.set(ARM::LR); 1508 1509 // Spill R4 if Thumb1 epilogue has to restore SP from FP. We don't know 1510 // for sure what the stack size will be, but for this, an estimate is good 1511 // enough. If there anything changes it, it'll be a spill, which implies 1512 // we've used all the registers and so R4 is already used, so not marking 1513 // it here will be OK. 1514 // FIXME: It will be better just to find spare register here. 1515 unsigned StackSize = MFI->estimateStackSize(MF); 1516 if (MFI->hasVarSizedObjects() || StackSize > 508) 1517 SavedRegs.set(ARM::R4); 1518 } 1519 1520 // See if we can spill vector registers to aligned stack. 1521 checkNumAlignedDPRCS2Regs(MF, SavedRegs); 1522 1523 // Spill the BasePtr if it's used. 1524 if (RegInfo->hasBasePointer(MF)) 1525 SavedRegs.set(RegInfo->getBaseRegister()); 1526 1527 // Don't spill FP if the frame can be eliminated. This is determined 1528 // by scanning the callee-save registers to see if any is modified. 1529 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF); 1530 for (unsigned i = 0; CSRegs[i]; ++i) { 1531 unsigned Reg = CSRegs[i]; 1532 bool Spilled = false; 1533 if (SavedRegs.test(Reg)) { 1534 Spilled = true; 1535 CanEliminateFrame = false; 1536 } 1537 1538 if (!ARM::GPRRegClass.contains(Reg)) 1539 continue; 1540 1541 if (Spilled) { 1542 NumGPRSpills++; 1543 1544 if (!STI.isTargetDarwin()) { 1545 if (Reg == ARM::LR) 1546 LRSpilled = true; 1547 CS1Spilled = true; 1548 continue; 1549 } 1550 1551 // Keep track if LR and any of R4, R5, R6, and R7 is spilled. 1552 switch (Reg) { 1553 case ARM::LR: 1554 LRSpilled = true; 1555 // Fallthrough 1556 case ARM::R0: case ARM::R1: 1557 case ARM::R2: case ARM::R3: 1558 case ARM::R4: case ARM::R5: 1559 case ARM::R6: case ARM::R7: 1560 CS1Spilled = true; 1561 break; 1562 default: 1563 break; 1564 } 1565 } else { 1566 if (!STI.isTargetDarwin()) { 1567 UnspilledCS1GPRs.push_back(Reg); 1568 continue; 1569 } 1570 1571 switch (Reg) { 1572 case ARM::R0: case ARM::R1: 1573 case ARM::R2: case ARM::R3: 1574 case ARM::R4: case ARM::R5: 1575 case ARM::R6: case ARM::R7: 1576 case ARM::LR: 1577 UnspilledCS1GPRs.push_back(Reg); 1578 break; 1579 default: 1580 UnspilledCS2GPRs.push_back(Reg); 1581 break; 1582 } 1583 } 1584 } 1585 1586 bool ForceLRSpill = false; 1587 if (!LRSpilled && AFI->isThumb1OnlyFunction()) { 1588 unsigned FnSize = GetFunctionSizeInBytes(MF, TII); 1589 // Force LR to be spilled if the Thumb function size is > 2048. This enables 1590 // use of BL to implement far jump. If it turns out that it's not needed 1591 // then the branch fix up path will undo it. 1592 if (FnSize >= (1 << 11)) { 1593 CanEliminateFrame = false; 1594 ForceLRSpill = true; 1595 } 1596 } 1597 1598 // If any of the stack slot references may be out of range of an immediate 1599 // offset, make sure a register (or a spill slot) is available for the 1600 // register scavenger. Note that if we're indexing off the frame pointer, the 1601 // effective stack size is 4 bytes larger since the FP points to the stack 1602 // slot of the previous FP. Also, if we have variable sized objects in the 1603 // function, stack slot references will often be negative, and some of 1604 // our instructions are positive-offset only, so conservatively consider 1605 // that case to want a spill slot (or register) as well. Similarly, if 1606 // the function adjusts the stack pointer during execution and the 1607 // adjustments aren't already part of our stack size estimate, our offset 1608 // calculations may be off, so be conservative. 1609 // FIXME: We could add logic to be more precise about negative offsets 1610 // and which instructions will need a scratch register for them. Is it 1611 // worth the effort and added fragility? 1612 bool BigStack = (RS && (MFI->estimateStackSize(MF) + 1613 ((hasFP(MF) && AFI->hasStackFrame()) ? 4 : 0) >= 1614 estimateRSStackSizeLimit(MF, this))) || 1615 MFI->hasVarSizedObjects() || 1616 (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF)); 1617 1618 bool ExtraCSSpill = false; 1619 if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF)) { 1620 AFI->setHasStackFrame(true); 1621 1622 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. 1623 // Spill LR as well so we can fold BX_RET to the registers restore (LDM). 1624 if (!LRSpilled && CS1Spilled) { 1625 SavedRegs.set(ARM::LR); 1626 NumGPRSpills++; 1627 SmallVectorImpl<unsigned>::iterator LRPos; 1628 LRPos = std::find(UnspilledCS1GPRs.begin(), UnspilledCS1GPRs.end(), 1629 (unsigned)ARM::LR); 1630 if (LRPos != UnspilledCS1GPRs.end()) 1631 UnspilledCS1GPRs.erase(LRPos); 1632 1633 ForceLRSpill = false; 1634 ExtraCSSpill = true; 1635 } 1636 1637 if (hasFP(MF)) { 1638 SavedRegs.set(FramePtr); 1639 auto FPPos = std::find(UnspilledCS1GPRs.begin(), UnspilledCS1GPRs.end(), 1640 FramePtr); 1641 if (FPPos != UnspilledCS1GPRs.end()) 1642 UnspilledCS1GPRs.erase(FPPos); 1643 NumGPRSpills++; 1644 } 1645 1646 // If stack and double are 8-byte aligned and we are spilling an odd number 1647 // of GPRs, spill one extra callee save GPR so we won't have to pad between 1648 // the integer and double callee save areas. 1649 unsigned TargetAlign = getStackAlignment(); 1650 if (TargetAlign >= 8 && (NumGPRSpills & 1)) { 1651 if (CS1Spilled && !UnspilledCS1GPRs.empty()) { 1652 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) { 1653 unsigned Reg = UnspilledCS1GPRs[i]; 1654 // Don't spill high register if the function is thumb. In the case of 1655 // Windows on ARM, accept R11 (frame pointer) 1656 if (!AFI->isThumbFunction() || 1657 (STI.isTargetWindows() && Reg == ARM::R11) || 1658 isARMLowRegister(Reg) || Reg == ARM::LR) { 1659 SavedRegs.set(Reg); 1660 if (!MRI.isReserved(Reg)) 1661 ExtraCSSpill = true; 1662 break; 1663 } 1664 } 1665 } else if (!UnspilledCS2GPRs.empty() && !AFI->isThumb1OnlyFunction()) { 1666 unsigned Reg = UnspilledCS2GPRs.front(); 1667 SavedRegs.set(Reg); 1668 if (!MRI.isReserved(Reg)) 1669 ExtraCSSpill = true; 1670 } 1671 } 1672 1673 // Estimate if we might need to scavenge a register at some point in order 1674 // to materialize a stack offset. If so, either spill one additional 1675 // callee-saved register or reserve a special spill slot to facilitate 1676 // register scavenging. Thumb1 needs a spill slot for stack pointer 1677 // adjustments also, even when the frame itself is small. 1678 if (BigStack && !ExtraCSSpill) { 1679 // If any non-reserved CS register isn't spilled, just spill one or two 1680 // extra. That should take care of it! 1681 unsigned NumExtras = TargetAlign / 4; 1682 SmallVector<unsigned, 2> Extras; 1683 while (NumExtras && !UnspilledCS1GPRs.empty()) { 1684 unsigned Reg = UnspilledCS1GPRs.back(); 1685 UnspilledCS1GPRs.pop_back(); 1686 if (!MRI.isReserved(Reg) && 1687 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) || 1688 Reg == ARM::LR)) { 1689 Extras.push_back(Reg); 1690 NumExtras--; 1691 } 1692 } 1693 // For non-Thumb1 functions, also check for hi-reg CS registers 1694 if (!AFI->isThumb1OnlyFunction()) { 1695 while (NumExtras && !UnspilledCS2GPRs.empty()) { 1696 unsigned Reg = UnspilledCS2GPRs.back(); 1697 UnspilledCS2GPRs.pop_back(); 1698 if (!MRI.isReserved(Reg)) { 1699 Extras.push_back(Reg); 1700 NumExtras--; 1701 } 1702 } 1703 } 1704 if (Extras.size() && NumExtras == 0) { 1705 for (unsigned i = 0, e = Extras.size(); i != e; ++i) { 1706 SavedRegs.set(Extras[i]); 1707 } 1708 } else if (!AFI->isThumb1OnlyFunction()) { 1709 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot 1710 // closest to SP or frame pointer. 1711 const TargetRegisterClass *RC = &ARM::GPRRegClass; 1712 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1713 RC->getAlignment(), 1714 false)); 1715 } 1716 } 1717 } 1718 1719 if (ForceLRSpill) { 1720 SavedRegs.set(ARM::LR); 1721 AFI->setLRIsSpilledForFarJump(true); 1722 } 1723 } 1724 1725 1726 void ARMFrameLowering:: 1727 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 1728 MachineBasicBlock::iterator I) const { 1729 const ARMBaseInstrInfo &TII = 1730 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo()); 1731 if (!hasReservedCallFrame(MF)) { 1732 // If we have alloca, convert as follows: 1733 // ADJCALLSTACKDOWN -> sub, sp, sp, amount 1734 // ADJCALLSTACKUP -> add, sp, sp, amount 1735 MachineInstr *Old = I; 1736 DebugLoc dl = Old->getDebugLoc(); 1737 unsigned Amount = Old->getOperand(0).getImm(); 1738 if (Amount != 0) { 1739 // We need to keep the stack aligned properly. To do this, we round the 1740 // amount of space needed for the outgoing arguments up to the next 1741 // alignment boundary. 1742 Amount = alignSPAdjust(Amount); 1743 1744 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1745 assert(!AFI->isThumb1OnlyFunction() && 1746 "This eliminateCallFramePseudoInstr does not support Thumb1!"); 1747 bool isARM = !AFI->isThumbFunction(); 1748 1749 // Replace the pseudo instruction with a new instruction... 1750 unsigned Opc = Old->getOpcode(); 1751 int PIdx = Old->findFirstPredOperandIdx(); 1752 ARMCC::CondCodes Pred = (PIdx == -1) 1753 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm(); 1754 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { 1755 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN. 1756 unsigned PredReg = Old->getOperand(2).getReg(); 1757 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, MachineInstr::NoFlags, 1758 Pred, PredReg); 1759 } else { 1760 // Note: PredReg is operand 3 for ADJCALLSTACKUP. 1761 unsigned PredReg = Old->getOperand(3).getReg(); 1762 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); 1763 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, MachineInstr::NoFlags, 1764 Pred, PredReg); 1765 } 1766 } 1767 } 1768 MBB.erase(I); 1769 } 1770 1771 /// Get the minimum constant for ARM that is greater than or equal to the 1772 /// argument. In ARM, constants can have any value that can be produced by 1773 /// rotating an 8-bit value to the right by an even number of bits within a 1774 /// 32-bit word. 1775 static uint32_t alignToARMConstant(uint32_t Value) { 1776 unsigned Shifted = 0; 1777 1778 if (Value == 0) 1779 return 0; 1780 1781 while (!(Value & 0xC0000000)) { 1782 Value = Value << 2; 1783 Shifted += 2; 1784 } 1785 1786 bool Carry = (Value & 0x00FFFFFF); 1787 Value = ((Value & 0xFF000000) >> 24) + Carry; 1788 1789 if (Value & 0x0000100) 1790 Value = Value & 0x000001FC; 1791 1792 if (Shifted > 24) 1793 Value = Value >> (Shifted - 24); 1794 else 1795 Value = Value << (24 - Shifted); 1796 1797 return Value; 1798 } 1799 1800 // The stack limit in the TCB is set to this many bytes above the actual 1801 // stack limit. 1802 static const uint64_t kSplitStackAvailable = 256; 1803 1804 // Adjust the function prologue to enable split stacks. This currently only 1805 // supports android and linux. 1806 // 1807 // The ABI of the segmented stack prologue is a little arbitrarily chosen, but 1808 // must be well defined in order to allow for consistent implementations of the 1809 // __morestack helper function. The ABI is also not a normal ABI in that it 1810 // doesn't follow the normal calling conventions because this allows the 1811 // prologue of each function to be optimized further. 1812 // 1813 // Currently, the ABI looks like (when calling __morestack) 1814 // 1815 // * r4 holds the minimum stack size requested for this function call 1816 // * r5 holds the stack size of the arguments to the function 1817 // * the beginning of the function is 3 instructions after the call to 1818 // __morestack 1819 // 1820 // Implementations of __morestack should use r4 to allocate a new stack, r5 to 1821 // place the arguments on to the new stack, and the 3-instruction knowledge to 1822 // jump directly to the body of the function when working on the new stack. 1823 // 1824 // An old (and possibly no longer compatible) implementation of __morestack for 1825 // ARM can be found at [1]. 1826 // 1827 // [1] - https://github.com/mozilla/rust/blob/86efd9/src/rt/arch/arm/morestack.S 1828 void ARMFrameLowering::adjustForSegmentedStacks( 1829 MachineFunction &MF, MachineBasicBlock &PrologueMBB) const { 1830 unsigned Opcode; 1831 unsigned CFIIndex; 1832 const ARMSubtarget *ST = &MF.getSubtarget<ARMSubtarget>(); 1833 bool Thumb = ST->isThumb(); 1834 1835 // Sadly, this currently doesn't support varargs, platforms other than 1836 // android/linux. Note that thumb1/thumb2 are support for android/linux. 1837 if (MF.getFunction()->isVarArg()) 1838 report_fatal_error("Segmented stacks do not support vararg functions."); 1839 if (!ST->isTargetAndroid() && !ST->isTargetLinux()) 1840 report_fatal_error("Segmented stacks not supported on this platform."); 1841 1842 MachineFrameInfo *MFI = MF.getFrameInfo(); 1843 MachineModuleInfo &MMI = MF.getMMI(); 1844 MCContext &Context = MMI.getContext(); 1845 const MCRegisterInfo *MRI = Context.getRegisterInfo(); 1846 const ARMBaseInstrInfo &TII = 1847 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo()); 1848 ARMFunctionInfo *ARMFI = MF.getInfo<ARMFunctionInfo>(); 1849 DebugLoc DL; 1850 1851 uint64_t StackSize = MFI->getStackSize(); 1852 1853 // Do not generate a prologue for functions with a stack of size zero 1854 if (StackSize == 0) 1855 return; 1856 1857 // Use R4 and R5 as scratch registers. 1858 // We save R4 and R5 before use and restore them before leaving the function. 1859 unsigned ScratchReg0 = ARM::R4; 1860 unsigned ScratchReg1 = ARM::R5; 1861 uint64_t AlignedStackSize; 1862 1863 MachineBasicBlock *PrevStackMBB = MF.CreateMachineBasicBlock(); 1864 MachineBasicBlock *PostStackMBB = MF.CreateMachineBasicBlock(); 1865 MachineBasicBlock *AllocMBB = MF.CreateMachineBasicBlock(); 1866 MachineBasicBlock *GetMBB = MF.CreateMachineBasicBlock(); 1867 MachineBasicBlock *McrMBB = MF.CreateMachineBasicBlock(); 1868 1869 // Grab everything that reaches PrologueMBB to update there liveness as well. 1870 SmallPtrSet<MachineBasicBlock *, 8> BeforePrologueRegion; 1871 SmallVector<MachineBasicBlock *, 2> WalkList; 1872 WalkList.push_back(&PrologueMBB); 1873 1874 do { 1875 MachineBasicBlock *CurMBB = WalkList.pop_back_val(); 1876 for (MachineBasicBlock *PredBB : CurMBB->predecessors()) { 1877 if (BeforePrologueRegion.insert(PredBB).second) 1878 WalkList.push_back(PredBB); 1879 } 1880 } while (!WalkList.empty()); 1881 1882 // The order in that list is important. 1883 // The blocks will all be inserted before PrologueMBB using that order. 1884 // Therefore the block that should appear first in the CFG should appear 1885 // first in the list. 1886 MachineBasicBlock *AddedBlocks[] = {PrevStackMBB, McrMBB, GetMBB, AllocMBB, 1887 PostStackMBB}; 1888 const int NbAddedBlocks = sizeof(AddedBlocks) / sizeof(AddedBlocks[0]); 1889 1890 for (int Idx = 0; Idx < NbAddedBlocks; ++Idx) 1891 BeforePrologueRegion.insert(AddedBlocks[Idx]); 1892 1893 for (const auto &LI : PrologueMBB.liveins()) { 1894 for (MachineBasicBlock *PredBB : BeforePrologueRegion) 1895 PredBB->addLiveIn(LI); 1896 } 1897 1898 // Remove the newly added blocks from the list, since we know 1899 // we do not have to do the following updates for them. 1900 for (int Idx = 0; Idx < NbAddedBlocks; ++Idx) { 1901 BeforePrologueRegion.erase(AddedBlocks[Idx]); 1902 MF.insert(PrologueMBB.getIterator(), AddedBlocks[Idx]); 1903 } 1904 1905 for (MachineBasicBlock *MBB : BeforePrologueRegion) { 1906 // Make sure the LiveIns are still sorted and unique. 1907 MBB->sortUniqueLiveIns(); 1908 // Replace the edges to PrologueMBB by edges to the sequences 1909 // we are about to add. 1910 MBB->ReplaceUsesOfBlockWith(&PrologueMBB, AddedBlocks[0]); 1911 } 1912 1913 // The required stack size that is aligned to ARM constant criterion. 1914 AlignedStackSize = alignToARMConstant(StackSize); 1915 1916 // When the frame size is less than 256 we just compare the stack 1917 // boundary directly to the value of the stack pointer, per gcc. 1918 bool CompareStackPointer = AlignedStackSize < kSplitStackAvailable; 1919 1920 // We will use two of the callee save registers as scratch registers so we 1921 // need to save those registers onto the stack. 1922 // We will use SR0 to hold stack limit and SR1 to hold the stack size 1923 // requested and arguments for __morestack(). 1924 // SR0: Scratch Register #0 1925 // SR1: Scratch Register #1 1926 // push {SR0, SR1} 1927 if (Thumb) { 1928 AddDefaultPred(BuildMI(PrevStackMBB, DL, TII.get(ARM::tPUSH))) 1929 .addReg(ScratchReg0).addReg(ScratchReg1); 1930 } else { 1931 AddDefaultPred(BuildMI(PrevStackMBB, DL, TII.get(ARM::STMDB_UPD)) 1932 .addReg(ARM::SP, RegState::Define).addReg(ARM::SP)) 1933 .addReg(ScratchReg0).addReg(ScratchReg1); 1934 } 1935 1936 // Emit the relevant DWARF information about the change in stack pointer as 1937 // well as where to find both r4 and r5 (the callee-save registers) 1938 CFIIndex = 1939 MMI.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, -8)); 1940 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) 1941 .addCFIIndex(CFIIndex); 1942 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset( 1943 nullptr, MRI->getDwarfRegNum(ScratchReg1, true), -4)); 1944 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) 1945 .addCFIIndex(CFIIndex); 1946 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset( 1947 nullptr, MRI->getDwarfRegNum(ScratchReg0, true), -8)); 1948 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) 1949 .addCFIIndex(CFIIndex); 1950 1951 // mov SR1, sp 1952 if (Thumb) { 1953 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::tMOVr), ScratchReg1) 1954 .addReg(ARM::SP)); 1955 } else if (CompareStackPointer) { 1956 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::MOVr), ScratchReg1) 1957 .addReg(ARM::SP)).addReg(0); 1958 } 1959 1960 // sub SR1, sp, #StackSize 1961 if (!CompareStackPointer && Thumb) { 1962 AddDefaultPred( 1963 AddDefaultCC(BuildMI(McrMBB, DL, TII.get(ARM::tSUBi8), ScratchReg1)) 1964 .addReg(ScratchReg1).addImm(AlignedStackSize)); 1965 } else if (!CompareStackPointer) { 1966 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::SUBri), ScratchReg1) 1967 .addReg(ARM::SP).addImm(AlignedStackSize)).addReg(0); 1968 } 1969 1970 if (Thumb && ST->isThumb1Only()) { 1971 unsigned PCLabelId = ARMFI->createPICLabelUId(); 1972 ARMConstantPoolValue *NewCPV = ARMConstantPoolSymbol::Create( 1973 MF.getFunction()->getContext(), "__STACK_LIMIT", PCLabelId, 0); 1974 MachineConstantPool *MCP = MF.getConstantPool(); 1975 unsigned CPI = MCP->getConstantPoolIndex(NewCPV, 4); 1976 1977 // ldr SR0, [pc, offset(STACK_LIMIT)] 1978 AddDefaultPred(BuildMI(GetMBB, DL, TII.get(ARM::tLDRpci), ScratchReg0) 1979 .addConstantPoolIndex(CPI)); 1980 1981 // ldr SR0, [SR0] 1982 AddDefaultPred(BuildMI(GetMBB, DL, TII.get(ARM::tLDRi), ScratchReg0) 1983 .addReg(ScratchReg0).addImm(0)); 1984 } else { 1985 // Get TLS base address from the coprocessor 1986 // mrc p15, #0, SR0, c13, c0, #3 1987 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::MRC), ScratchReg0) 1988 .addImm(15) 1989 .addImm(0) 1990 .addImm(13) 1991 .addImm(0) 1992 .addImm(3)); 1993 1994 // Use the last tls slot on android and a private field of the TCP on linux. 1995 assert(ST->isTargetAndroid() || ST->isTargetLinux()); 1996 unsigned TlsOffset = ST->isTargetAndroid() ? 63 : 1; 1997 1998 // Get the stack limit from the right offset 1999 // ldr SR0, [sr0, #4 * TlsOffset] 2000 AddDefaultPred(BuildMI(GetMBB, DL, TII.get(ARM::LDRi12), ScratchReg0) 2001 .addReg(ScratchReg0).addImm(4 * TlsOffset)); 2002 } 2003 2004 // Compare stack limit with stack size requested. 2005 // cmp SR0, SR1 2006 Opcode = Thumb ? ARM::tCMPr : ARM::CMPrr; 2007 AddDefaultPred(BuildMI(GetMBB, DL, TII.get(Opcode)) 2008 .addReg(ScratchReg0) 2009 .addReg(ScratchReg1)); 2010 2011 // This jump is taken if StackLimit < SP - stack required. 2012 Opcode = Thumb ? ARM::tBcc : ARM::Bcc; 2013 BuildMI(GetMBB, DL, TII.get(Opcode)).addMBB(PostStackMBB) 2014 .addImm(ARMCC::LO) 2015 .addReg(ARM::CPSR); 2016 2017 2018 // Calling __morestack(StackSize, Size of stack arguments). 2019 // __morestack knows that the stack size requested is in SR0(r4) 2020 // and amount size of stack arguments is in SR1(r5). 2021 2022 // Pass first argument for the __morestack by Scratch Register #0. 2023 // The amount size of stack required 2024 if (Thumb) { 2025 AddDefaultPred(AddDefaultCC(BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), 2026 ScratchReg0)).addImm(AlignedStackSize)); 2027 } else { 2028 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg0) 2029 .addImm(AlignedStackSize)).addReg(0); 2030 } 2031 // Pass second argument for the __morestack by Scratch Register #1. 2032 // The amount size of stack consumed to save function arguments. 2033 if (Thumb) { 2034 AddDefaultPred( 2035 AddDefaultCC(BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg1)) 2036 .addImm(alignToARMConstant(ARMFI->getArgumentStackSize()))); 2037 } else { 2038 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg1) 2039 .addImm(alignToARMConstant(ARMFI->getArgumentStackSize()))) 2040 .addReg(0); 2041 } 2042 2043 // push {lr} - Save return address of this function. 2044 if (Thumb) { 2045 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tPUSH))) 2046 .addReg(ARM::LR); 2047 } else { 2048 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::STMDB_UPD)) 2049 .addReg(ARM::SP, RegState::Define) 2050 .addReg(ARM::SP)) 2051 .addReg(ARM::LR); 2052 } 2053 2054 // Emit the DWARF info about the change in stack as well as where to find the 2055 // previous link register 2056 CFIIndex = 2057 MMI.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, -12)); 2058 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) 2059 .addCFIIndex(CFIIndex); 2060 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset( 2061 nullptr, MRI->getDwarfRegNum(ARM::LR, true), -12)); 2062 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) 2063 .addCFIIndex(CFIIndex); 2064 2065 // Call __morestack(). 2066 if (Thumb) { 2067 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tBL))) 2068 .addExternalSymbol("__morestack"); 2069 } else { 2070 BuildMI(AllocMBB, DL, TII.get(ARM::BL)) 2071 .addExternalSymbol("__morestack"); 2072 } 2073 2074 // pop {lr} - Restore return address of this original function. 2075 if (Thumb) { 2076 if (ST->isThumb1Only()) { 2077 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tPOP))) 2078 .addReg(ScratchReg0); 2079 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tMOVr), ARM::LR) 2080 .addReg(ScratchReg0)); 2081 } else { 2082 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::t2LDR_POST)) 2083 .addReg(ARM::LR, RegState::Define) 2084 .addReg(ARM::SP, RegState::Define) 2085 .addReg(ARM::SP) 2086 .addImm(4)); 2087 } 2088 } else { 2089 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD)) 2090 .addReg(ARM::SP, RegState::Define) 2091 .addReg(ARM::SP)) 2092 .addReg(ARM::LR); 2093 } 2094 2095 // Restore SR0 and SR1 in case of __morestack() was called. 2096 // __morestack() will skip PostStackMBB block so we need to restore 2097 // scratch registers from here. 2098 // pop {SR0, SR1} 2099 if (Thumb) { 2100 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tPOP))) 2101 .addReg(ScratchReg0) 2102 .addReg(ScratchReg1); 2103 } else { 2104 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD)) 2105 .addReg(ARM::SP, RegState::Define) 2106 .addReg(ARM::SP)) 2107 .addReg(ScratchReg0) 2108 .addReg(ScratchReg1); 2109 } 2110 2111 // Update the CFA offset now that we've popped 2112 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0)); 2113 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) 2114 .addCFIIndex(CFIIndex); 2115 2116 // bx lr - Return from this function. 2117 Opcode = Thumb ? ARM::tBX_RET : ARM::BX_RET; 2118 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(Opcode))); 2119 2120 // Restore SR0 and SR1 in case of __morestack() was not called. 2121 // pop {SR0, SR1} 2122 if (Thumb) { 2123 AddDefaultPred(BuildMI(PostStackMBB, DL, TII.get(ARM::tPOP))) 2124 .addReg(ScratchReg0) 2125 .addReg(ScratchReg1); 2126 } else { 2127 AddDefaultPred(BuildMI(PostStackMBB, DL, TII.get(ARM::LDMIA_UPD)) 2128 .addReg(ARM::SP, RegState::Define) 2129 .addReg(ARM::SP)) 2130 .addReg(ScratchReg0) 2131 .addReg(ScratchReg1); 2132 } 2133 2134 // Update the CFA offset now that we've popped 2135 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0)); 2136 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) 2137 .addCFIIndex(CFIIndex); 2138 2139 // Tell debuggers that r4 and r5 are now the same as they were in the 2140 // previous function, that they're the "Same Value". 2141 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createSameValue( 2142 nullptr, MRI->getDwarfRegNum(ScratchReg0, true))); 2143 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) 2144 .addCFIIndex(CFIIndex); 2145 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createSameValue( 2146 nullptr, MRI->getDwarfRegNum(ScratchReg1, true))); 2147 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) 2148 .addCFIIndex(CFIIndex); 2149 2150 // Organizing MBB lists 2151 PostStackMBB->addSuccessor(&PrologueMBB); 2152 2153 AllocMBB->addSuccessor(PostStackMBB); 2154 2155 GetMBB->addSuccessor(PostStackMBB); 2156 GetMBB->addSuccessor(AllocMBB); 2157 2158 McrMBB->addSuccessor(GetMBB); 2159 2160 PrevStackMBB->addSuccessor(McrMBB); 2161 2162 #ifdef XDEBUG 2163 MF.verify(); 2164 #endif 2165 } 2166