1 //===-- AMDGPUPALMetadata.cpp - Accumulate and print AMDGPU PAL metadata -===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// 11 /// This class has methods called by AMDGPUAsmPrinter to accumulate and print 12 /// the PAL metadata. 13 // 14 //===----------------------------------------------------------------------===// 15 // 16 17 #include "AMDGPUPALMetadata.h" 18 #include "AMDGPU.h" 19 #include "AMDGPUAsmPrinter.h" 20 #include "MCTargetDesc/AMDGPUTargetStreamer.h" 21 #include "SIDefines.h" 22 #include "llvm/BinaryFormat/ELF.h" 23 #include "llvm/IR/CallingConv.h" 24 #include "llvm/Support/AMDGPUMetadata.h" 25 #include "llvm/Support/EndianStream.h" 26 27 using namespace llvm; 28 using namespace llvm::AMDGPU; 29 30 // Read the PAL metadata from IR metadata, where it was put by the frontend. 31 void AMDGPUPALMetadata::readFromIR(Module &M) { 32 auto NamedMD = M.getNamedMetadata("amdgpu.pal.metadata.msgpack"); 33 if (NamedMD && NamedMD->getNumOperands()) { 34 // This is the new msgpack format for metadata. It is a NamedMD containing 35 // an MDTuple containing an MDString containing the msgpack data. 36 BlobType = ELF::NT_AMDGPU_METADATA; 37 auto MDN = dyn_cast<MDTuple>(NamedMD->getOperand(0)); 38 if (MDN && MDN->getNumOperands()) { 39 if (auto MDS = dyn_cast<MDString>(MDN->getOperand(0))) 40 setFromMsgPackBlob(MDS->getString()); 41 } 42 return; 43 } 44 BlobType = ELF::NT_AMD_AMDGPU_PAL_METADATA; 45 NamedMD = M.getNamedMetadata("amdgpu.pal.metadata"); 46 if (!NamedMD || !NamedMD->getNumOperands()) 47 return; 48 // This is the old reg=value pair format for metadata. It is a NamedMD 49 // containing an MDTuple containing a number of MDNodes each of which is an 50 // integer value, and each two integer values forms a key=value pair that we 51 // store as Registers[key]=value in the map. 52 auto Tuple = dyn_cast<MDTuple>(NamedMD->getOperand(0)); 53 if (!Tuple) 54 return; 55 for (unsigned I = 0, E = Tuple->getNumOperands() & -2; I != E; I += 2) { 56 auto Key = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I)); 57 auto Val = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I + 1)); 58 if (!Key || !Val) 59 continue; 60 setRegister(Key->getZExtValue(), Val->getZExtValue()); 61 } 62 } 63 64 // Set PAL metadata from a binary blob from the applicable .note record. 65 // Returns false if bad format. Blob must remain valid for the lifetime of the 66 // Metadata. 67 bool AMDGPUPALMetadata::setFromBlob(unsigned Type, StringRef Blob) { 68 BlobType = Type; 69 if (Type == ELF::NT_AMD_AMDGPU_PAL_METADATA) 70 return setFromLegacyBlob(Blob); 71 return setFromMsgPackBlob(Blob); 72 } 73 74 // Set PAL metadata from legacy (array of key=value pairs) blob. 75 bool AMDGPUPALMetadata::setFromLegacyBlob(StringRef Blob) { 76 auto Data = reinterpret_cast<const uint32_t *>(Blob.data()); 77 for (unsigned I = 0; I != Blob.size() / sizeof(uint32_t) / 2; ++I) 78 setRegister(Data[I * 2], Data[I * 2 + 1]); 79 return true; 80 } 81 82 // Set PAL metadata from msgpack blob. 83 bool AMDGPUPALMetadata::setFromMsgPackBlob(StringRef Blob) { 84 msgpack::Reader Reader(Blob); 85 return MsgPackDoc.readFromBlob(Blob, /*Multi=*/false); 86 } 87 88 // Given the calling convention, calculate the register number for rsrc1. In 89 // principle the register number could change in future hardware, but we know 90 // it is the same for gfx6-9 (except that LS and ES don't exist on gfx9), so 91 // we can use fixed values. 92 static unsigned getRsrc1Reg(CallingConv::ID CC) { 93 switch (CC) { 94 default: 95 return PALMD::R_2E12_COMPUTE_PGM_RSRC1; 96 case CallingConv::AMDGPU_LS: 97 return PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS; 98 case CallingConv::AMDGPU_HS: 99 return PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS; 100 case CallingConv::AMDGPU_ES: 101 return PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES; 102 case CallingConv::AMDGPU_GS: 103 return PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS; 104 case CallingConv::AMDGPU_VS: 105 return PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS; 106 case CallingConv::AMDGPU_PS: 107 return PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS; 108 } 109 } 110 111 // Calculate the PAL metadata key for *S_SCRATCH_SIZE. It can be used 112 // with a constant offset to access any non-register shader-specific PAL 113 // metadata key. 114 static unsigned getScratchSizeKey(CallingConv::ID CC) { 115 switch (CC) { 116 case CallingConv::AMDGPU_PS: 117 return PALMD::Key::PS_SCRATCH_SIZE; 118 case CallingConv::AMDGPU_VS: 119 return PALMD::Key::VS_SCRATCH_SIZE; 120 case CallingConv::AMDGPU_GS: 121 return PALMD::Key::GS_SCRATCH_SIZE; 122 case CallingConv::AMDGPU_ES: 123 return PALMD::Key::ES_SCRATCH_SIZE; 124 case CallingConv::AMDGPU_HS: 125 return PALMD::Key::HS_SCRATCH_SIZE; 126 case CallingConv::AMDGPU_LS: 127 return PALMD::Key::LS_SCRATCH_SIZE; 128 default: 129 return PALMD::Key::CS_SCRATCH_SIZE; 130 } 131 } 132 133 // Set the rsrc1 register in the metadata for a particular shader stage. 134 // In fact this ORs the value into any previous setting of the register. 135 void AMDGPUPALMetadata::setRsrc1(CallingConv::ID CC, unsigned Val) { 136 setRegister(getRsrc1Reg(CC), Val); 137 } 138 139 // Set the rsrc2 register in the metadata for a particular shader stage. 140 // In fact this ORs the value into any previous setting of the register. 141 void AMDGPUPALMetadata::setRsrc2(CallingConv::ID CC, unsigned Val) { 142 setRegister(getRsrc1Reg(CC) + 1, Val); 143 } 144 145 // Set the SPI_PS_INPUT_ENA register in the metadata. 146 // In fact this ORs the value into any previous setting of the register. 147 void AMDGPUPALMetadata::setSpiPsInputEna(unsigned Val) { 148 setRegister(PALMD::R_A1B3_SPI_PS_INPUT_ENA, Val); 149 } 150 151 // Set the SPI_PS_INPUT_ADDR register in the metadata. 152 // In fact this ORs the value into any previous setting of the register. 153 void AMDGPUPALMetadata::setSpiPsInputAddr(unsigned Val) { 154 setRegister(PALMD::R_A1B4_SPI_PS_INPUT_ADDR, Val); 155 } 156 157 // Get a register from the metadata, or 0 if not currently set. 158 unsigned AMDGPUPALMetadata::getRegister(unsigned Reg) { 159 auto Regs = getRegisters(); 160 auto It = Regs.find(MsgPackDoc.getNode(Reg)); 161 if (It == Regs.end()) 162 return 0; 163 auto N = It->second; 164 if (N.getKind() != msgpack::Type::UInt) 165 return 0; 166 return N.getUInt(); 167 } 168 169 // Set a register in the metadata. 170 // In fact this ORs the value into any previous setting of the register. 171 void AMDGPUPALMetadata::setRegister(unsigned Reg, unsigned Val) { 172 if (!isLegacy()) { 173 // In the new MsgPack format, ignore register numbered >= 0x10000000. It 174 // is a PAL ABI pseudo-register in the old non-MsgPack format. 175 if (Reg >= 0x10000000) 176 return; 177 } 178 auto &N = getRegisters()[MsgPackDoc.getNode(Reg)]; 179 if (N.getKind() == msgpack::Type::UInt) 180 Val |= N.getUInt(); 181 N = N.getDocument()->getNode(Val); 182 } 183 184 // Set the entry point name for one shader. 185 void AMDGPUPALMetadata::setEntryPoint(unsigned CC, StringRef Name) { 186 if (isLegacy()) 187 return; 188 // Msgpack format. 189 getHwStage(CC)[".entry_point"] = MsgPackDoc.getNode(Name, /*Copy=*/true); 190 } 191 192 // Set the number of used vgprs in the metadata. This is an optional 193 // advisory record for logging etc; wave dispatch actually uses the rsrc1 194 // register for the shader stage to determine the number of vgprs to 195 // allocate. 196 void AMDGPUPALMetadata::setNumUsedVgprs(CallingConv::ID CC, unsigned Val) { 197 if (isLegacy()) { 198 // Old non-msgpack format. 199 unsigned NumUsedVgprsKey = getScratchSizeKey(CC) + 200 PALMD::Key::VS_NUM_USED_VGPRS - 201 PALMD::Key::VS_SCRATCH_SIZE; 202 setRegister(NumUsedVgprsKey, Val); 203 return; 204 } 205 // Msgpack format. 206 getHwStage(CC)[".vgpr_count"] = MsgPackDoc.getNode(Val); 207 } 208 209 // Set the number of used sgprs in the metadata. This is an optional advisory 210 // record for logging etc; wave dispatch actually uses the rsrc1 register for 211 // the shader stage to determine the number of sgprs to allocate. 212 void AMDGPUPALMetadata::setNumUsedSgprs(CallingConv::ID CC, unsigned Val) { 213 if (isLegacy()) { 214 // Old non-msgpack format. 215 unsigned NumUsedSgprsKey = getScratchSizeKey(CC) + 216 PALMD::Key::VS_NUM_USED_SGPRS - 217 PALMD::Key::VS_SCRATCH_SIZE; 218 setRegister(NumUsedSgprsKey, Val); 219 return; 220 } 221 // Msgpack format. 222 getHwStage(CC)[".sgpr_count"] = MsgPackDoc.getNode(Val); 223 } 224 225 // Set the scratch size in the metadata. 226 void AMDGPUPALMetadata::setScratchSize(CallingConv::ID CC, unsigned Val) { 227 if (isLegacy()) { 228 // Old non-msgpack format. 229 setRegister(getScratchSizeKey(CC), Val); 230 return; 231 } 232 // Msgpack format. 233 getHwStage(CC)[".scratch_memory_size"] = MsgPackDoc.getNode(Val); 234 } 235 236 // Convert a register number to name, for display by toString(). 237 // Returns nullptr if none. 238 static const char *getRegisterName(unsigned RegNum) { 239 // Table of registers. 240 static const struct RegInfo { 241 unsigned Num; 242 const char *Name; 243 } RegInfoTable[] = { 244 // Registers that code generation sets/modifies metadata for. 245 {PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS, "SPI_SHADER_PGM_RSRC1_VS"}, 246 {PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS + 1, "SPI_SHADER_PGM_RSRC2_VS"}, 247 {PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS, "SPI_SHADER_PGM_RSRC1_LS"}, 248 {PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS + 1, "SPI_SHADER_PGM_RSRC2_LS"}, 249 {PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS, "SPI_SHADER_PGM_RSRC1_HS"}, 250 {PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS + 1, "SPI_SHADER_PGM_RSRC2_HS"}, 251 {PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES, "SPI_SHADER_PGM_RSRC1_ES"}, 252 {PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES + 1, "SPI_SHADER_PGM_RSRC2_ES"}, 253 {PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS, "SPI_SHADER_PGM_RSRC1_GS"}, 254 {PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS + 1, "SPI_SHADER_PGM_RSRC2_GS"}, 255 {PALMD::R_2E00_COMPUTE_DISPATCH_INITIATOR, "COMPUTE_DISPATCH_INITIATOR"}, 256 {PALMD::R_2E12_COMPUTE_PGM_RSRC1, "COMPUTE_PGM_RSRC1"}, 257 {PALMD::R_2E12_COMPUTE_PGM_RSRC1 + 1, "COMPUTE_PGM_RSRC2"}, 258 {PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS, "SPI_SHADER_PGM_RSRC1_PS"}, 259 {PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS + 1, "SPI_SHADER_PGM_RSRC2_PS"}, 260 {PALMD::R_A1B3_SPI_PS_INPUT_ENA, "SPI_PS_INPUT_ENA"}, 261 {PALMD::R_A1B4_SPI_PS_INPUT_ADDR, "SPI_PS_INPUT_ADDR"}, 262 {PALMD::R_A1B6_SPI_PS_IN_CONTROL, "SPI_PS_IN_CONTROL"}, 263 {PALMD::R_A2D5_VGT_SHADER_STAGES_EN, "VGT_SHADER_STAGES_EN"}, 264 265 // Registers not known to code generation. 266 {0x2c07, "SPI_SHADER_PGM_RSRC3_PS"}, 267 {0x2c46, "SPI_SHADER_PGM_RSRC3_VS"}, 268 {0x2c87, "SPI_SHADER_PGM_RSRC3_GS"}, 269 {0x2cc7, "SPI_SHADER_PGM_RSRC3_ES"}, 270 {0x2d07, "SPI_SHADER_PGM_RSRC3_HS"}, 271 {0x2d47, "SPI_SHADER_PGM_RSRC3_LS"}, 272 273 {0xa1c3, "SPI_SHADER_POS_FORMAT"}, 274 {0xa1b1, "SPI_VS_OUT_CONFIG"}, 275 {0xa207, "PA_CL_VS_OUT_CNTL"}, 276 {0xa204, "PA_CL_CLIP_CNTL"}, 277 {0xa206, "PA_CL_VTE_CNTL"}, 278 {0xa2f9, "PA_SU_VTX_CNTL"}, 279 {0xa293, "PA_SC_MODE_CNTL_1"}, 280 {0xa2a1, "VGT_PRIMITIVEID_EN"}, 281 {0x2c81, "SPI_SHADER_PGM_RSRC4_GS"}, 282 {0x2e18, "COMPUTE_TMPRING_SIZE"}, 283 {0xa1b5, "SPI_INTERP_CONTROL_0"}, 284 {0xa1ba, "SPI_TMPRING_SIZE"}, 285 {0xa1c4, "SPI_SHADER_Z_FORMAT"}, 286 {0xa1c5, "SPI_SHADER_COL_FORMAT"}, 287 {0xa203, "DB_SHADER_CONTROL"}, 288 {0xa08f, "CB_SHADER_MASK"}, 289 {0xa191, "SPI_PS_INPUT_CNTL_0"}, 290 {0xa192, "SPI_PS_INPUT_CNTL_1"}, 291 {0xa193, "SPI_PS_INPUT_CNTL_2"}, 292 {0xa194, "SPI_PS_INPUT_CNTL_3"}, 293 {0xa195, "SPI_PS_INPUT_CNTL_4"}, 294 {0xa196, "SPI_PS_INPUT_CNTL_5"}, 295 {0xa197, "SPI_PS_INPUT_CNTL_6"}, 296 {0xa198, "SPI_PS_INPUT_CNTL_7"}, 297 {0xa199, "SPI_PS_INPUT_CNTL_8"}, 298 {0xa19a, "SPI_PS_INPUT_CNTL_9"}, 299 {0xa19b, "SPI_PS_INPUT_CNTL_10"}, 300 {0xa19c, "SPI_PS_INPUT_CNTL_11"}, 301 {0xa19d, "SPI_PS_INPUT_CNTL_12"}, 302 {0xa19e, "SPI_PS_INPUT_CNTL_13"}, 303 {0xa19f, "SPI_PS_INPUT_CNTL_14"}, 304 {0xa1a0, "SPI_PS_INPUT_CNTL_15"}, 305 {0xa1a1, "SPI_PS_INPUT_CNTL_16"}, 306 {0xa1a2, "SPI_PS_INPUT_CNTL_17"}, 307 {0xa1a3, "SPI_PS_INPUT_CNTL_18"}, 308 {0xa1a4, "SPI_PS_INPUT_CNTL_19"}, 309 {0xa1a5, "SPI_PS_INPUT_CNTL_20"}, 310 {0xa1a6, "SPI_PS_INPUT_CNTL_21"}, 311 {0xa1a7, "SPI_PS_INPUT_CNTL_22"}, 312 {0xa1a8, "SPI_PS_INPUT_CNTL_23"}, 313 {0xa1a9, "SPI_PS_INPUT_CNTL_24"}, 314 {0xa1aa, "SPI_PS_INPUT_CNTL_25"}, 315 {0xa1ab, "SPI_PS_INPUT_CNTL_26"}, 316 {0xa1ac, "SPI_PS_INPUT_CNTL_27"}, 317 {0xa1ad, "SPI_PS_INPUT_CNTL_28"}, 318 {0xa1ae, "SPI_PS_INPUT_CNTL_29"}, 319 {0xa1af, "SPI_PS_INPUT_CNTL_30"}, 320 {0xa1b0, "SPI_PS_INPUT_CNTL_31"}, 321 322 {0xa2ce, "VGT_GS_MAX_VERT_OUT"}, 323 {0xa2ab, "VGT_ESGS_RING_ITEMSIZE"}, 324 {0xa290, "VGT_GS_MODE"}, 325 {0xa291, "VGT_GS_ONCHIP_CNTL"}, 326 {0xa2d7, "VGT_GS_VERT_ITEMSIZE"}, 327 {0xa2d8, "VGT_GS_VERT_ITEMSIZE_1"}, 328 {0xa2d9, "VGT_GS_VERT_ITEMSIZE_2"}, 329 {0xa2da, "VGT_GS_VERT_ITEMSIZE_3"}, 330 {0xa298, "VGT_GSVS_RING_OFFSET_1"}, 331 {0xa299, "VGT_GSVS_RING_OFFSET_2"}, 332 {0xa29a, "VGT_GSVS_RING_OFFSET_3"}, 333 334 {0xa2e4, "VGT_GS_INSTANCE_CNT"}, 335 {0xa297, "VGT_GS_PER_VS"}, 336 {0xa29b, "VGT_GS_OUT_PRIM_TYPE"}, 337 {0xa2ac, "VGT_GSVS_RING_ITEMSIZE"}, 338 339 {0xa2ad, "VGT_REUSE_OFF"}, 340 {0xa1b8, "SPI_BARYC_CNTL"}, 341 342 {0x2c4c, "SPI_SHADER_USER_DATA_VS_0"}, 343 {0x2c4d, "SPI_SHADER_USER_DATA_VS_1"}, 344 {0x2c4e, "SPI_SHADER_USER_DATA_VS_2"}, 345 {0x2c4f, "SPI_SHADER_USER_DATA_VS_3"}, 346 {0x2c50, "SPI_SHADER_USER_DATA_VS_4"}, 347 {0x2c51, "SPI_SHADER_USER_DATA_VS_5"}, 348 {0x2c52, "SPI_SHADER_USER_DATA_VS_6"}, 349 {0x2c53, "SPI_SHADER_USER_DATA_VS_7"}, 350 {0x2c54, "SPI_SHADER_USER_DATA_VS_8"}, 351 {0x2c55, "SPI_SHADER_USER_DATA_VS_9"}, 352 {0x2c56, "SPI_SHADER_USER_DATA_VS_10"}, 353 {0x2c57, "SPI_SHADER_USER_DATA_VS_11"}, 354 {0x2c58, "SPI_SHADER_USER_DATA_VS_12"}, 355 {0x2c59, "SPI_SHADER_USER_DATA_VS_13"}, 356 {0x2c5a, "SPI_SHADER_USER_DATA_VS_14"}, 357 {0x2c5b, "SPI_SHADER_USER_DATA_VS_15"}, 358 {0x2c5c, "SPI_SHADER_USER_DATA_VS_16"}, 359 {0x2c5d, "SPI_SHADER_USER_DATA_VS_17"}, 360 {0x2c5e, "SPI_SHADER_USER_DATA_VS_18"}, 361 {0x2c5f, "SPI_SHADER_USER_DATA_VS_19"}, 362 {0x2c60, "SPI_SHADER_USER_DATA_VS_20"}, 363 {0x2c61, "SPI_SHADER_USER_DATA_VS_21"}, 364 {0x2c62, "SPI_SHADER_USER_DATA_VS_22"}, 365 {0x2c63, "SPI_SHADER_USER_DATA_VS_23"}, 366 {0x2c64, "SPI_SHADER_USER_DATA_VS_24"}, 367 {0x2c65, "SPI_SHADER_USER_DATA_VS_25"}, 368 {0x2c66, "SPI_SHADER_USER_DATA_VS_26"}, 369 {0x2c67, "SPI_SHADER_USER_DATA_VS_27"}, 370 {0x2c68, "SPI_SHADER_USER_DATA_VS_28"}, 371 {0x2c69, "SPI_SHADER_USER_DATA_VS_29"}, 372 {0x2c6a, "SPI_SHADER_USER_DATA_VS_30"}, 373 {0x2c6b, "SPI_SHADER_USER_DATA_VS_31"}, 374 375 {0x2ccc, "SPI_SHADER_USER_DATA_ES_0"}, 376 {0x2ccd, "SPI_SHADER_USER_DATA_ES_1"}, 377 {0x2cce, "SPI_SHADER_USER_DATA_ES_2"}, 378 {0x2ccf, "SPI_SHADER_USER_DATA_ES_3"}, 379 {0x2cd0, "SPI_SHADER_USER_DATA_ES_4"}, 380 {0x2cd1, "SPI_SHADER_USER_DATA_ES_5"}, 381 {0x2cd2, "SPI_SHADER_USER_DATA_ES_6"}, 382 {0x2cd3, "SPI_SHADER_USER_DATA_ES_7"}, 383 {0x2cd4, "SPI_SHADER_USER_DATA_ES_8"}, 384 {0x2cd5, "SPI_SHADER_USER_DATA_ES_9"}, 385 {0x2cd6, "SPI_SHADER_USER_DATA_ES_10"}, 386 {0x2cd7, "SPI_SHADER_USER_DATA_ES_11"}, 387 {0x2cd8, "SPI_SHADER_USER_DATA_ES_12"}, 388 {0x2cd9, "SPI_SHADER_USER_DATA_ES_13"}, 389 {0x2cda, "SPI_SHADER_USER_DATA_ES_14"}, 390 {0x2cdb, "SPI_SHADER_USER_DATA_ES_15"}, 391 {0x2cdc, "SPI_SHADER_USER_DATA_ES_16"}, 392 {0x2cdd, "SPI_SHADER_USER_DATA_ES_17"}, 393 {0x2cde, "SPI_SHADER_USER_DATA_ES_18"}, 394 {0x2cdf, "SPI_SHADER_USER_DATA_ES_19"}, 395 {0x2ce0, "SPI_SHADER_USER_DATA_ES_20"}, 396 {0x2ce1, "SPI_SHADER_USER_DATA_ES_21"}, 397 {0x2ce2, "SPI_SHADER_USER_DATA_ES_22"}, 398 {0x2ce3, "SPI_SHADER_USER_DATA_ES_23"}, 399 {0x2ce4, "SPI_SHADER_USER_DATA_ES_24"}, 400 {0x2ce5, "SPI_SHADER_USER_DATA_ES_25"}, 401 {0x2ce6, "SPI_SHADER_USER_DATA_ES_26"}, 402 {0x2ce7, "SPI_SHADER_USER_DATA_ES_27"}, 403 {0x2ce8, "SPI_SHADER_USER_DATA_ES_28"}, 404 {0x2ce9, "SPI_SHADER_USER_DATA_ES_29"}, 405 {0x2cea, "SPI_SHADER_USER_DATA_ES_30"}, 406 {0x2ceb, "SPI_SHADER_USER_DATA_ES_31"}, 407 408 {0x2c0c, "SPI_SHADER_USER_DATA_PS_0"}, 409 {0x2c0d, "SPI_SHADER_USER_DATA_PS_1"}, 410 {0x2c0e, "SPI_SHADER_USER_DATA_PS_2"}, 411 {0x2c0f, "SPI_SHADER_USER_DATA_PS_3"}, 412 {0x2c10, "SPI_SHADER_USER_DATA_PS_4"}, 413 {0x2c11, "SPI_SHADER_USER_DATA_PS_5"}, 414 {0x2c12, "SPI_SHADER_USER_DATA_PS_6"}, 415 {0x2c13, "SPI_SHADER_USER_DATA_PS_7"}, 416 {0x2c14, "SPI_SHADER_USER_DATA_PS_8"}, 417 {0x2c15, "SPI_SHADER_USER_DATA_PS_9"}, 418 {0x2c16, "SPI_SHADER_USER_DATA_PS_10"}, 419 {0x2c17, "SPI_SHADER_USER_DATA_PS_11"}, 420 {0x2c18, "SPI_SHADER_USER_DATA_PS_12"}, 421 {0x2c19, "SPI_SHADER_USER_DATA_PS_13"}, 422 {0x2c1a, "SPI_SHADER_USER_DATA_PS_14"}, 423 {0x2c1b, "SPI_SHADER_USER_DATA_PS_15"}, 424 {0x2c1c, "SPI_SHADER_USER_DATA_PS_16"}, 425 {0x2c1d, "SPI_SHADER_USER_DATA_PS_17"}, 426 {0x2c1e, "SPI_SHADER_USER_DATA_PS_18"}, 427 {0x2c1f, "SPI_SHADER_USER_DATA_PS_19"}, 428 {0x2c20, "SPI_SHADER_USER_DATA_PS_20"}, 429 {0x2c21, "SPI_SHADER_USER_DATA_PS_21"}, 430 {0x2c22, "SPI_SHADER_USER_DATA_PS_22"}, 431 {0x2c23, "SPI_SHADER_USER_DATA_PS_23"}, 432 {0x2c24, "SPI_SHADER_USER_DATA_PS_24"}, 433 {0x2c25, "SPI_SHADER_USER_DATA_PS_25"}, 434 {0x2c26, "SPI_SHADER_USER_DATA_PS_26"}, 435 {0x2c27, "SPI_SHADER_USER_DATA_PS_27"}, 436 {0x2c28, "SPI_SHADER_USER_DATA_PS_28"}, 437 {0x2c29, "SPI_SHADER_USER_DATA_PS_29"}, 438 {0x2c2a, "SPI_SHADER_USER_DATA_PS_30"}, 439 {0x2c2b, "SPI_SHADER_USER_DATA_PS_31"}, 440 441 {0x2e40, "COMPUTE_USER_DATA_0"}, 442 {0x2e41, "COMPUTE_USER_DATA_1"}, 443 {0x2e42, "COMPUTE_USER_DATA_2"}, 444 {0x2e43, "COMPUTE_USER_DATA_3"}, 445 {0x2e44, "COMPUTE_USER_DATA_4"}, 446 {0x2e45, "COMPUTE_USER_DATA_5"}, 447 {0x2e46, "COMPUTE_USER_DATA_6"}, 448 {0x2e47, "COMPUTE_USER_DATA_7"}, 449 {0x2e48, "COMPUTE_USER_DATA_8"}, 450 {0x2e49, "COMPUTE_USER_DATA_9"}, 451 {0x2e4a, "COMPUTE_USER_DATA_10"}, 452 {0x2e4b, "COMPUTE_USER_DATA_11"}, 453 {0x2e4c, "COMPUTE_USER_DATA_12"}, 454 {0x2e4d, "COMPUTE_USER_DATA_13"}, 455 {0x2e4e, "COMPUTE_USER_DATA_14"}, 456 {0x2e4f, "COMPUTE_USER_DATA_15"}, 457 458 {0x2e07, "COMPUTE_NUM_THREAD_X"}, 459 {0x2e08, "COMPUTE_NUM_THREAD_Y"}, 460 {0x2e09, "COMPUTE_NUM_THREAD_Z"}, 461 {0xa2db, "VGT_TF_PARAM"}, 462 {0xa2d6, "VGT_LS_HS_CONFIG"}, 463 {0xa287, "VGT_HOS_MIN_TESS_LEVEL"}, 464 {0xa286, "VGT_HOS_MAX_TESS_LEVEL"}, 465 {0xa2f8, "PA_SC_AA_CONFIG"}, 466 {0xa310, "PA_SC_SHADER_CONTROL"}, 467 {0xa313, "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL"}, 468 469 {0x2d0c, "SPI_SHADER_USER_DATA_LS_0"}, 470 {0x2d0d, "SPI_SHADER_USER_DATA_LS_1"}, 471 {0x2d0e, "SPI_SHADER_USER_DATA_LS_2"}, 472 {0x2d0f, "SPI_SHADER_USER_DATA_LS_3"}, 473 {0x2d10, "SPI_SHADER_USER_DATA_LS_4"}, 474 {0x2d11, "SPI_SHADER_USER_DATA_LS_5"}, 475 {0x2d12, "SPI_SHADER_USER_DATA_LS_6"}, 476 {0x2d13, "SPI_SHADER_USER_DATA_LS_7"}, 477 {0x2d14, "SPI_SHADER_USER_DATA_LS_8"}, 478 {0x2d15, "SPI_SHADER_USER_DATA_LS_9"}, 479 {0x2d16, "SPI_SHADER_USER_DATA_LS_10"}, 480 {0x2d17, "SPI_SHADER_USER_DATA_LS_11"}, 481 {0x2d18, "SPI_SHADER_USER_DATA_LS_12"}, 482 {0x2d19, "SPI_SHADER_USER_DATA_LS_13"}, 483 {0x2d1a, "SPI_SHADER_USER_DATA_LS_14"}, 484 {0x2d1b, "SPI_SHADER_USER_DATA_LS_15"}, 485 {0x2d1c, "SPI_SHADER_USER_DATA_LS_16"}, 486 {0x2d1d, "SPI_SHADER_USER_DATA_LS_17"}, 487 {0x2d1e, "SPI_SHADER_USER_DATA_LS_18"}, 488 {0x2d1f, "SPI_SHADER_USER_DATA_LS_19"}, 489 {0x2d20, "SPI_SHADER_USER_DATA_LS_20"}, 490 {0x2d21, "SPI_SHADER_USER_DATA_LS_21"}, 491 {0x2d22, "SPI_SHADER_USER_DATA_LS_22"}, 492 {0x2d23, "SPI_SHADER_USER_DATA_LS_23"}, 493 {0x2d24, "SPI_SHADER_USER_DATA_LS_24"}, 494 {0x2d25, "SPI_SHADER_USER_DATA_LS_25"}, 495 {0x2d26, "SPI_SHADER_USER_DATA_LS_26"}, 496 {0x2d27, "SPI_SHADER_USER_DATA_LS_27"}, 497 {0x2d28, "SPI_SHADER_USER_DATA_LS_28"}, 498 {0x2d29, "SPI_SHADER_USER_DATA_LS_29"}, 499 {0x2d2a, "SPI_SHADER_USER_DATA_LS_30"}, 500 {0x2d2b, "SPI_SHADER_USER_DATA_LS_31"}, 501 502 {0xa2aa, "IA_MULTI_VGT_PARAM"}, 503 {0xa2a5, "VGT_GS_MAX_PRIMS_PER_SUBGROUP"}, 504 {0xa2e6, "VGT_STRMOUT_BUFFER_CONFIG"}, 505 {0xa2e5, "VGT_STRMOUT_CONFIG"}, 506 {0xa2b5, "VGT_STRMOUT_VTX_STRIDE_0"}, 507 {0xa2b9, "VGT_STRMOUT_VTX_STRIDE_1"}, 508 {0xa2bd, "VGT_STRMOUT_VTX_STRIDE_2"}, 509 {0xa2c1, "VGT_STRMOUT_VTX_STRIDE_3"}, 510 {0xa316, "VGT_VERTEX_REUSE_BLOCK_CNTL"}, 511 512 {0, nullptr}}; 513 auto Entry = RegInfoTable; 514 for (; Entry->Num && Entry->Num != RegNum; ++Entry) 515 ; 516 return Entry->Name; 517 } 518 519 // Convert the accumulated PAL metadata into an asm directive. 520 void AMDGPUPALMetadata::toString(std::string &String) { 521 String.clear(); 522 if (!BlobType) 523 return; 524 raw_string_ostream Stream(String); 525 if (isLegacy()) { 526 if (MsgPackDoc.getRoot().getKind() == msgpack::Type::Nil) 527 return; 528 // Old linear reg=val format. 529 Stream << '\t' << AMDGPU::PALMD::AssemblerDirective << ' '; 530 auto Regs = getRegisters(); 531 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I) { 532 if (I != Regs.begin()) 533 Stream << ','; 534 unsigned Reg = I->first.getUInt(); 535 unsigned Val = I->second.getUInt(); 536 Stream << "0x" << Twine::utohexstr(Reg) << ",0x" << Twine::utohexstr(Val); 537 } 538 Stream << '\n'; 539 return; 540 } 541 542 // New msgpack-based format -- output as YAML (with unsigned numbers in hex), 543 // but first change the registers map to use names. 544 MsgPackDoc.setHexMode(); 545 auto &RegsObj = refRegisters(); 546 auto OrigRegs = RegsObj.getMap(); 547 RegsObj = MsgPackDoc.getMapNode(); 548 for (auto I : OrigRegs) { 549 auto Key = I.first; 550 if (const char *RegName = getRegisterName(Key.getUInt())) { 551 std::string KeyName = Key.toString(); 552 KeyName += " ("; 553 KeyName += RegName; 554 KeyName += ')'; 555 Key = MsgPackDoc.getNode(KeyName, /*Copy=*/true); 556 } 557 RegsObj.getMap()[Key] = I.second; 558 } 559 560 // Output as YAML. 561 Stream << '\t' << AMDGPU::PALMD::AssemblerDirectiveBegin << '\n'; 562 MsgPackDoc.toYAML(Stream); 563 Stream << '\t' << AMDGPU::PALMD::AssemblerDirectiveEnd << '\n'; 564 565 // Restore original registers map. 566 RegsObj = OrigRegs; 567 } 568 569 // Convert the accumulated PAL metadata into a binary blob for writing as 570 // a .note record of the specified AMD type. Returns an empty blob if 571 // there is no PAL metadata, 572 void AMDGPUPALMetadata::toBlob(unsigned Type, std::string &Blob) { 573 if (Type == ELF::NT_AMD_AMDGPU_PAL_METADATA) 574 toLegacyBlob(Blob); 575 else if (Type) 576 toMsgPackBlob(Blob); 577 } 578 579 void AMDGPUPALMetadata::toLegacyBlob(std::string &Blob) { 580 Blob.clear(); 581 auto Registers = getRegisters(); 582 if (Registers.getMap().empty()) 583 return; 584 raw_string_ostream OS(Blob); 585 support::endian::Writer EW(OS, support::endianness::little); 586 for (auto I : Registers.getMap()) { 587 EW.write(uint32_t(I.first.getUInt())); 588 EW.write(uint32_t(I.second.getUInt())); 589 } 590 } 591 592 void AMDGPUPALMetadata::toMsgPackBlob(std::string &Blob) { 593 Blob.clear(); 594 MsgPackDoc.writeToBlob(Blob); 595 } 596 597 // Set PAL metadata from YAML text. Returns false if failed. 598 bool AMDGPUPALMetadata::setFromString(StringRef S) { 599 BlobType = ELF::NT_AMDGPU_METADATA; 600 if (!MsgPackDoc.fromYAML(S)) 601 return false; 602 603 // In the registers map, some keys may be of the form "0xa191 604 // (SPI_PS_INPUT_CNTL_0)", in which case the YAML input code made it a 605 // string. We need to turn it into a number. 606 auto &RegsObj = refRegisters(); 607 auto OrigRegs = RegsObj; 608 RegsObj = MsgPackDoc.getMapNode(); 609 Registers = RegsObj.getMap(); 610 bool Ok = true; 611 for (auto I : OrigRegs.getMap()) { 612 auto Key = I.first; 613 if (Key.getKind() == msgpack::Type::String) { 614 StringRef S = Key.getString(); 615 uint64_t Val; 616 if (S.consumeInteger(0, Val)) { 617 Ok = false; 618 errs() << "Unrecognized PAL metadata register key '" << S << "'\n"; 619 continue; 620 } 621 Key = MsgPackDoc.getNode(uint64_t(Val)); 622 } 623 Registers.getMap()[Key] = I.second; 624 } 625 return Ok; 626 } 627 628 // Reference (create if necessary) the node for the registers map. 629 msgpack::DocNode &AMDGPUPALMetadata::refRegisters() { 630 auto &N = 631 MsgPackDoc.getRoot() 632 .getMap(/*Convert=*/true)[MsgPackDoc.getNode("amdpal.pipelines")] 633 .getArray(/*Convert=*/true)[0] 634 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(".registers")]; 635 N.getMap(/*Convert=*/true); 636 return N; 637 } 638 639 // Get (create if necessary) the registers map. 640 msgpack::MapDocNode AMDGPUPALMetadata::getRegisters() { 641 if (Registers.isEmpty()) 642 Registers = refRegisters(); 643 return Registers.getMap(); 644 } 645 646 // Return the PAL metadata hardware shader stage name. 647 static const char *getStageName(CallingConv::ID CC) { 648 switch (CC) { 649 case CallingConv::AMDGPU_PS: 650 return ".ps"; 651 case CallingConv::AMDGPU_VS: 652 return ".vs"; 653 case CallingConv::AMDGPU_GS: 654 return ".gs"; 655 case CallingConv::AMDGPU_ES: 656 return ".es"; 657 case CallingConv::AMDGPU_HS: 658 return ".hs"; 659 case CallingConv::AMDGPU_LS: 660 return ".ls"; 661 default: 662 return ".cs"; 663 } 664 } 665 666 // Get (create if necessary) the .hardware_stages entry for the given calling 667 // convention. 668 msgpack::MapDocNode AMDGPUPALMetadata::getHwStage(unsigned CC) { 669 if (HwStages.isEmpty()) 670 HwStages = MsgPackDoc.getRoot() 671 .getMap(/*Convert=*/true)["amdpal.pipelines"] 672 .getArray(/*Convert=*/true)[0] 673 .getMap(/*Convert=*/true)[".hardware_stages"] 674 .getMap(/*Convert=*/true); 675 return HwStages.getMap()[getStageName(CC)].getMap(/*Convert=*/true); 676 } 677 678 // Get .note record vendor name of metadata blob to be emitted. 679 const char *AMDGPUPALMetadata::getVendor() const { 680 return isLegacy() ? ElfNote::NoteNameV2 : ElfNote::NoteNameV3; 681 } 682 683 // Get .note record type of metadata blob to be emitted: 684 // ELF::NT_AMD_AMDGPU_PAL_METADATA (legacy key=val format), or 685 // ELF::NT_AMDGPU_METADATA (MsgPack format), or 686 // 0 (no PAL metadata). 687 unsigned AMDGPUPALMetadata::getType() const { 688 return BlobType; 689 } 690 691 // Return whether the blob type is legacy PAL metadata. 692 bool AMDGPUPALMetadata::isLegacy() const { 693 return BlobType == ELF::NT_AMD_AMDGPU_PAL_METADATA; 694 } 695 696 // Set legacy PAL metadata format. 697 void AMDGPUPALMetadata::setLegacy() { 698 BlobType = ELF::NT_AMD_AMDGPU_PAL_METADATA; 699 } 700 701