xref: /llvm-project/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h (revision fcc40d9c17d9f4a5bf24a88d900859a4c1f451a2) 
1 //==- SIMachineFunctionInfo.h - SIMachineFunctionInfo interface --*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
14 #define LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
15 
16 #include "AMDGPUArgumentUsageInfo.h"
17 #include "AMDGPUMachineFunction.h"
18 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
19 #include "SIInstrInfo.h"
20 #include "llvm/ADT/MapVector.h"
21 #include "llvm/CodeGen/MIRYamlMapping.h"
22 #include "llvm/CodeGen/PseudoSourceValue.h"
23 #include "llvm/Support/raw_ostream.h"
24 
25 namespace llvm {
26 
27 class MachineFrameInfo;
28 class MachineFunction;
29 class TargetRegisterClass;
30 class SIMachineFunctionInfo;
31 class SIRegisterInfo;
32 
33 class AMDGPUPseudoSourceValue : public PseudoSourceValue {
34 public:
35   enum AMDGPUPSVKind : unsigned {
36     PSVBuffer = PseudoSourceValue::TargetCustom,
37     PSVImage,
38     GWSResource
39   };
40 
41 protected:
42   AMDGPUPseudoSourceValue(unsigned Kind, const TargetInstrInfo &TII)
43       : PseudoSourceValue(Kind, TII) {}
44 
45 public:
46   bool isConstant(const MachineFrameInfo *) const override {
47     // This should probably be true for most images, but we will start by being
48     // conservative.
49     return false;
50   }
51 
52   bool isAliased(const MachineFrameInfo *) const override {
53     return true;
54   }
55 
56   bool mayAlias(const MachineFrameInfo *) const override {
57     return true;
58   }
59 };
60 
61 class AMDGPUBufferPseudoSourceValue final : public AMDGPUPseudoSourceValue {
62 public:
63   explicit AMDGPUBufferPseudoSourceValue(const TargetInstrInfo &TII)
64       : AMDGPUPseudoSourceValue(PSVBuffer, TII) {}
65 
66   static bool classof(const PseudoSourceValue *V) {
67     return V->kind() == PSVBuffer;
68   }
69 
70   void printCustom(raw_ostream &OS) const override { OS << "BufferResource"; }
71 };
72 
73 class AMDGPUImagePseudoSourceValue final : public AMDGPUPseudoSourceValue {
74 public:
75   // TODO: Is the img rsrc useful?
76   explicit AMDGPUImagePseudoSourceValue(const TargetInstrInfo &TII)
77       : AMDGPUPseudoSourceValue(PSVImage, TII) {}
78 
79   static bool classof(const PseudoSourceValue *V) {
80     return V->kind() == PSVImage;
81   }
82 
83   void printCustom(raw_ostream &OS) const override { OS << "ImageResource"; }
84 };
85 
86 class AMDGPUGWSResourcePseudoSourceValue final : public AMDGPUPseudoSourceValue {
87 public:
88   explicit AMDGPUGWSResourcePseudoSourceValue(const TargetInstrInfo &TII)
89       : AMDGPUPseudoSourceValue(GWSResource, TII) {}
90 
91   static bool classof(const PseudoSourceValue *V) {
92     return V->kind() == GWSResource;
93   }
94 
95   // These are inaccessible memory from IR.
96   bool isAliased(const MachineFrameInfo *) const override {
97     return false;
98   }
99 
100   // These are inaccessible memory from IR.
101   bool mayAlias(const MachineFrameInfo *) const override {
102     return false;
103   }
104 
105   void printCustom(raw_ostream &OS) const override {
106     OS << "GWSResource";
107   }
108 };
109 
110 namespace yaml {
111 
112 struct SIArgument {
113   bool IsRegister;
114   union {
115     StringValue RegisterName;
116     unsigned StackOffset;
117   };
118   Optional<unsigned> Mask;
119 
120   // Default constructor, which creates a stack argument.
121   SIArgument() : IsRegister(false), StackOffset(0) {}
122   SIArgument(const SIArgument &Other) {
123     IsRegister = Other.IsRegister;
124     if (IsRegister) {
125       ::new ((void *)std::addressof(RegisterName))
126           StringValue(Other.RegisterName);
127     } else
128       StackOffset = Other.StackOffset;
129     Mask = Other.Mask;
130   }
131   SIArgument &operator=(const SIArgument &Other) {
132     IsRegister = Other.IsRegister;
133     if (IsRegister) {
134       ::new ((void *)std::addressof(RegisterName))
135           StringValue(Other.RegisterName);
136     } else
137       StackOffset = Other.StackOffset;
138     Mask = Other.Mask;
139     return *this;
140   }
141   ~SIArgument() {
142     if (IsRegister)
143       RegisterName.~StringValue();
144   }
145 
146   // Helper to create a register or stack argument.
147   static inline SIArgument createArgument(bool IsReg) {
148     if (IsReg)
149       return SIArgument(IsReg);
150     return SIArgument();
151   }
152 
153 private:
154   // Construct a register argument.
155   SIArgument(bool) : IsRegister(true), RegisterName() {}
156 };
157 
158 template <> struct MappingTraits<SIArgument> {
159   static void mapping(IO &YamlIO, SIArgument &A) {
160     if (YamlIO.outputting()) {
161       if (A.IsRegister)
162         YamlIO.mapRequired("reg", A.RegisterName);
163       else
164         YamlIO.mapRequired("offset", A.StackOffset);
165     } else {
166       auto Keys = YamlIO.keys();
167       if (is_contained(Keys, "reg")) {
168         A = SIArgument::createArgument(true);
169         YamlIO.mapRequired("reg", A.RegisterName);
170       } else if (is_contained(Keys, "offset"))
171         YamlIO.mapRequired("offset", A.StackOffset);
172       else
173         YamlIO.setError("missing required key 'reg' or 'offset'");
174     }
175     YamlIO.mapOptional("mask", A.Mask);
176   }
177   static const bool flow = true;
178 };
179 
180 struct SIArgumentInfo {
181   Optional<SIArgument> PrivateSegmentBuffer;
182   Optional<SIArgument> DispatchPtr;
183   Optional<SIArgument> QueuePtr;
184   Optional<SIArgument> KernargSegmentPtr;
185   Optional<SIArgument> DispatchID;
186   Optional<SIArgument> FlatScratchInit;
187   Optional<SIArgument> PrivateSegmentSize;
188 
189   Optional<SIArgument> WorkGroupIDX;
190   Optional<SIArgument> WorkGroupIDY;
191   Optional<SIArgument> WorkGroupIDZ;
192   Optional<SIArgument> WorkGroupInfo;
193   Optional<SIArgument> PrivateSegmentWaveByteOffset;
194 
195   Optional<SIArgument> ImplicitArgPtr;
196   Optional<SIArgument> ImplicitBufferPtr;
197 
198   Optional<SIArgument> WorkItemIDX;
199   Optional<SIArgument> WorkItemIDY;
200   Optional<SIArgument> WorkItemIDZ;
201 };
202 
203 template <> struct MappingTraits<SIArgumentInfo> {
204   static void mapping(IO &YamlIO, SIArgumentInfo &AI) {
205     YamlIO.mapOptional("privateSegmentBuffer", AI.PrivateSegmentBuffer);
206     YamlIO.mapOptional("dispatchPtr", AI.DispatchPtr);
207     YamlIO.mapOptional("queuePtr", AI.QueuePtr);
208     YamlIO.mapOptional("kernargSegmentPtr", AI.KernargSegmentPtr);
209     YamlIO.mapOptional("dispatchID", AI.DispatchID);
210     YamlIO.mapOptional("flatScratchInit", AI.FlatScratchInit);
211     YamlIO.mapOptional("privateSegmentSize", AI.PrivateSegmentSize);
212 
213     YamlIO.mapOptional("workGroupIDX", AI.WorkGroupIDX);
214     YamlIO.mapOptional("workGroupIDY", AI.WorkGroupIDY);
215     YamlIO.mapOptional("workGroupIDZ", AI.WorkGroupIDZ);
216     YamlIO.mapOptional("workGroupInfo", AI.WorkGroupInfo);
217     YamlIO.mapOptional("privateSegmentWaveByteOffset",
218                        AI.PrivateSegmentWaveByteOffset);
219 
220     YamlIO.mapOptional("implicitArgPtr", AI.ImplicitArgPtr);
221     YamlIO.mapOptional("implicitBufferPtr", AI.ImplicitBufferPtr);
222 
223     YamlIO.mapOptional("workItemIDX", AI.WorkItemIDX);
224     YamlIO.mapOptional("workItemIDY", AI.WorkItemIDY);
225     YamlIO.mapOptional("workItemIDZ", AI.WorkItemIDZ);
226   }
227 };
228 
229 // Default to default mode for default calling convention.
230 struct SIMode {
231   bool IEEE = true;
232   bool DX10Clamp = true;
233   bool FP32InputDenormals = true;
234   bool FP32OutputDenormals = true;
235   bool FP64FP16InputDenormals = true;
236   bool FP64FP16OutputDenormals = true;
237 
238   SIMode() = default;
239 
240   SIMode(const AMDGPU::SIModeRegisterDefaults &Mode) {
241     IEEE = Mode.IEEE;
242     DX10Clamp = Mode.DX10Clamp;
243     FP32InputDenormals = Mode.FP32InputDenormals;
244     FP32OutputDenormals = Mode.FP32OutputDenormals;
245     FP64FP16InputDenormals = Mode.FP64FP16InputDenormals;
246     FP64FP16OutputDenormals = Mode.FP64FP16OutputDenormals;
247   }
248 
249   bool operator ==(const SIMode Other) const {
250     return IEEE == Other.IEEE &&
251            DX10Clamp == Other.DX10Clamp &&
252            FP32InputDenormals == Other.FP32InputDenormals &&
253            FP32OutputDenormals == Other.FP32OutputDenormals &&
254            FP64FP16InputDenormals == Other.FP64FP16InputDenormals &&
255            FP64FP16OutputDenormals == Other.FP64FP16OutputDenormals;
256   }
257 };
258 
259 template <> struct MappingTraits<SIMode> {
260   static void mapping(IO &YamlIO, SIMode &Mode) {
261     YamlIO.mapOptional("ieee", Mode.IEEE, true);
262     YamlIO.mapOptional("dx10-clamp", Mode.DX10Clamp, true);
263     YamlIO.mapOptional("fp32-input-denormals", Mode.FP32InputDenormals, true);
264     YamlIO.mapOptional("fp32-output-denormals", Mode.FP32OutputDenormals, true);
265     YamlIO.mapOptional("fp64-fp16-input-denormals", Mode.FP64FP16InputDenormals, true);
266     YamlIO.mapOptional("fp64-fp16-output-denormals", Mode.FP64FP16OutputDenormals, true);
267   }
268 };
269 
270 struct SIMachineFunctionInfo final : public yaml::MachineFunctionInfo {
271   uint64_t ExplicitKernArgSize = 0;
272   unsigned MaxKernArgAlign = 0;
273   unsigned LDSSize = 0;
274   Align DynLDSAlign;
275   bool IsEntryFunction = false;
276   bool NoSignedZerosFPMath = false;
277   bool MemoryBound = false;
278   bool WaveLimiter = false;
279   bool HasSpilledSGPRs = false;
280   bool HasSpilledVGPRs = false;
281   uint32_t HighBitsOf32BitAddress = 0;
282 
283   // TODO: 10 may be a better default since it's the maximum.
284   unsigned Occupancy = 0;
285 
286   StringValue ScratchRSrcReg = "$private_rsrc_reg";
287   StringValue FrameOffsetReg = "$fp_reg";
288   StringValue StackPtrOffsetReg = "$sp_reg";
289 
290   Optional<SIArgumentInfo> ArgInfo;
291   SIMode Mode;
292 
293   SIMachineFunctionInfo() = default;
294   SIMachineFunctionInfo(const llvm::SIMachineFunctionInfo &,
295                         const TargetRegisterInfo &TRI);
296 
297   void mappingImpl(yaml::IO &YamlIO) override;
298   ~SIMachineFunctionInfo() = default;
299 };
300 
301 template <> struct MappingTraits<SIMachineFunctionInfo> {
302   static void mapping(IO &YamlIO, SIMachineFunctionInfo &MFI) {
303     YamlIO.mapOptional("explicitKernArgSize", MFI.ExplicitKernArgSize,
304                        UINT64_C(0));
305     YamlIO.mapOptional("maxKernArgAlign", MFI.MaxKernArgAlign, 0u);
306     YamlIO.mapOptional("ldsSize", MFI.LDSSize, 0u);
307     YamlIO.mapOptional("dynLDSAlign", MFI.DynLDSAlign, Align());
308     YamlIO.mapOptional("isEntryFunction", MFI.IsEntryFunction, false);
309     YamlIO.mapOptional("noSignedZerosFPMath", MFI.NoSignedZerosFPMath, false);
310     YamlIO.mapOptional("memoryBound", MFI.MemoryBound, false);
311     YamlIO.mapOptional("waveLimiter", MFI.WaveLimiter, false);
312     YamlIO.mapOptional("hasSpilledSGPRs", MFI.HasSpilledSGPRs, false);
313     YamlIO.mapOptional("hasSpilledVGPRs", MFI.HasSpilledVGPRs, false);
314     YamlIO.mapOptional("scratchRSrcReg", MFI.ScratchRSrcReg,
315                        StringValue("$private_rsrc_reg"));
316     YamlIO.mapOptional("frameOffsetReg", MFI.FrameOffsetReg,
317                        StringValue("$fp_reg"));
318     YamlIO.mapOptional("stackPtrOffsetReg", MFI.StackPtrOffsetReg,
319                        StringValue("$sp_reg"));
320     YamlIO.mapOptional("argumentInfo", MFI.ArgInfo);
321     YamlIO.mapOptional("mode", MFI.Mode, SIMode());
322     YamlIO.mapOptional("highBitsOf32BitAddress",
323                        MFI.HighBitsOf32BitAddress, 0u);
324     YamlIO.mapOptional("occupancy", MFI.Occupancy, 0);
325   }
326 };
327 
328 } // end namespace yaml
329 
330 /// This class keeps track of the SPI_SP_INPUT_ADDR config register, which
331 /// tells the hardware which interpolation parameters to load.
332 class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
333   friend class GCNTargetMachine;
334 
335   Register TIDReg = AMDGPU::NoRegister;
336 
337   // Registers that may be reserved for spilling purposes. These may be the same
338   // as the input registers.
339   Register ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG;
340 
341   // This is the the unswizzled offset from the current dispatch's scratch wave
342   // base to the beginning of the current function's frame.
343   Register FrameOffsetReg = AMDGPU::FP_REG;
344 
345   // This is an ABI register used in the non-entry calling convention to
346   // communicate the unswizzled offset from the current dispatch's scratch wave
347   // base to the beginning of the new function's frame.
348   Register StackPtrOffsetReg = AMDGPU::SP_REG;
349 
350   AMDGPUFunctionArgInfo ArgInfo;
351 
352   // Graphics info.
353   unsigned PSInputAddr = 0;
354   unsigned PSInputEnable = 0;
355 
356   /// Number of bytes of arguments this function has on the stack. If the callee
357   /// is expected to restore the argument stack this should be a multiple of 16,
358   /// all usable during a tail call.
359   ///
360   /// The alternative would forbid tail call optimisation in some cases: if we
361   /// want to transfer control from a function with 8-bytes of stack-argument
362   /// space to a function with 16-bytes then misalignment of this value would
363   /// make a stack adjustment necessary, which could not be undone by the
364   /// callee.
365   unsigned BytesInStackArgArea = 0;
366 
367   bool ReturnsVoid = true;
368 
369   // A pair of default/requested minimum/maximum flat work group sizes.
370   // Minimum - first, maximum - second.
371   std::pair<unsigned, unsigned> FlatWorkGroupSizes = {0, 0};
372 
373   // A pair of default/requested minimum/maximum number of waves per execution
374   // unit. Minimum - first, maximum - second.
375   std::pair<unsigned, unsigned> WavesPerEU = {0, 0};
376 
377   std::unique_ptr<const AMDGPUBufferPseudoSourceValue> BufferPSV;
378   std::unique_ptr<const AMDGPUImagePseudoSourceValue> ImagePSV;
379   std::unique_ptr<const AMDGPUGWSResourcePseudoSourceValue> GWSResourcePSV;
380 
381 private:
382   unsigned LDSWaveSpillSize = 0;
383   unsigned NumUserSGPRs = 0;
384   unsigned NumSystemSGPRs = 0;
385 
386   bool HasSpilledSGPRs = false;
387   bool HasSpilledVGPRs = false;
388   bool HasNonSpillStackObjects = false;
389   bool IsStackRealigned = false;
390 
391   unsigned NumSpilledSGPRs = 0;
392   unsigned NumSpilledVGPRs = 0;
393 
394   // Feature bits required for inputs passed in user SGPRs.
395   bool PrivateSegmentBuffer : 1;
396   bool DispatchPtr : 1;
397   bool QueuePtr : 1;
398   bool KernargSegmentPtr : 1;
399   bool DispatchID : 1;
400   bool FlatScratchInit : 1;
401 
402   // Feature bits required for inputs passed in system SGPRs.
403   bool WorkGroupIDX : 1; // Always initialized.
404   bool WorkGroupIDY : 1;
405   bool WorkGroupIDZ : 1;
406   bool WorkGroupInfo : 1;
407   bool PrivateSegmentWaveByteOffset : 1;
408 
409   bool WorkItemIDX : 1; // Always initialized.
410   bool WorkItemIDY : 1;
411   bool WorkItemIDZ : 1;
412 
413   // Private memory buffer
414   // Compute directly in sgpr[0:1]
415   // Other shaders indirect 64-bits at sgpr[0:1]
416   bool ImplicitBufferPtr : 1;
417 
418   // Pointer to where the ABI inserts special kernel arguments separate from the
419   // user arguments. This is an offset from the KernargSegmentPtr.
420   bool ImplicitArgPtr : 1;
421 
422   // The hard-wired high half of the address of the global information table
423   // for AMDPAL OS type. 0xffffffff represents no hard-wired high half, since
424   // current hardware only allows a 16 bit value.
425   unsigned GITPtrHigh;
426 
427   unsigned HighBitsOf32BitAddress;
428   unsigned GDSSize;
429 
430   // Current recorded maximum possible occupancy.
431   unsigned Occupancy;
432 
433   MCPhysReg getNextUserSGPR() const;
434 
435   MCPhysReg getNextSystemSGPR() const;
436 
437 public:
438   struct SpilledReg {
439     Register VGPR;
440     int Lane = -1;
441 
442     SpilledReg() = default;
443     SpilledReg(Register R, int L) : VGPR (R), Lane (L) {}
444 
445     bool hasLane() { return Lane != -1;}
446     bool hasReg() { return VGPR != 0;}
447   };
448 
449   struct SGPRSpillVGPR {
450     // VGPR used for SGPR spills
451     Register VGPR;
452 
453     // If the VGPR is is used for SGPR spills in a non-entrypoint function, the
454     // stack slot used to save/restore it in the prolog/epilog.
455     Optional<int> FI;
456 
457     SGPRSpillVGPR(Register V, Optional<int> F) : VGPR(V), FI(F) {}
458   };
459 
460   struct VGPRSpillToAGPR {
461     SmallVector<MCPhysReg, 32> Lanes;
462     bool FullyAllocated = false;
463   };
464 
465   // Map WWM VGPR to a stack slot that is used to save/restore it in the
466   // prolog/epilog.
467   MapVector<Register, Optional<int>> WWMReservedRegs;
468 
469 private:
470   // Track VGPR + wave index for each subregister of the SGPR spilled to
471   // frameindex key.
472   DenseMap<int, std::vector<SpilledReg>> SGPRToVGPRSpills;
473   unsigned NumVGPRSpillLanes = 0;
474   SmallVector<SGPRSpillVGPR, 2> SpillVGPRs;
475 
476   DenseMap<int, VGPRSpillToAGPR> VGPRToAGPRSpills;
477 
478   // AGPRs used for VGPR spills.
479   SmallVector<MCPhysReg, 32> SpillAGPR;
480 
481   // VGPRs used for AGPR spills.
482   SmallVector<MCPhysReg, 32> SpillVGPR;
483 
484   // Emergency stack slot. Sometimes, we create this before finalizing the stack
485   // frame, so save it here and add it to the RegScavenger later.
486   Optional<int> ScavengeFI;
487 
488 public: // FIXME
489   /// If this is set, an SGPR used for save/restore of the register used for the
490   /// frame pointer.
491   Register SGPRForFPSaveRestoreCopy;
492   Optional<int> FramePointerSaveIndex;
493 
494   /// If this is set, an SGPR used for save/restore of the register used for the
495   /// base pointer.
496   Register SGPRForBPSaveRestoreCopy;
497   Optional<int> BasePointerSaveIndex;
498 
499   Register VGPRReservedForSGPRSpill;
500   bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg);
501 
502 public:
503   SIMachineFunctionInfo(const MachineFunction &MF);
504 
505   bool initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI);
506 
507   void reserveWWMRegister(Register Reg, Optional<int> FI) {
508     WWMReservedRegs.insert(std::make_pair(Reg, FI));
509   }
510 
511   ArrayRef<SpilledReg> getSGPRToVGPRSpills(int FrameIndex) const {
512     auto I = SGPRToVGPRSpills.find(FrameIndex);
513     return (I == SGPRToVGPRSpills.end()) ?
514       ArrayRef<SpilledReg>() : makeArrayRef(I->second);
515   }
516 
517   ArrayRef<SGPRSpillVGPR> getSGPRSpillVGPRs() const { return SpillVGPRs; }
518 
519   void setSGPRSpillVGPRs(Register NewVGPR, Optional<int> newFI, int Index) {
520     SpillVGPRs[Index].VGPR = NewVGPR;
521     SpillVGPRs[Index].FI = newFI;
522     VGPRReservedForSGPRSpill = NewVGPR;
523   }
524 
525   bool removeVGPRForSGPRSpill(Register ReservedVGPR, MachineFunction &MF);
526 
527   ArrayRef<MCPhysReg> getAGPRSpillVGPRs() const {
528     return SpillAGPR;
529   }
530 
531   ArrayRef<MCPhysReg> getVGPRSpillAGPRs() const {
532     return SpillVGPR;
533   }
534 
535   MCPhysReg getVGPRToAGPRSpill(int FrameIndex, unsigned Lane) const {
536     auto I = VGPRToAGPRSpills.find(FrameIndex);
537     return (I == VGPRToAGPRSpills.end()) ? (MCPhysReg)AMDGPU::NoRegister
538                                          : I->second.Lanes[Lane];
539   }
540 
541   bool haveFreeLanesForSGPRSpill(const MachineFunction &MF,
542                                  unsigned NumLane) const;
543   bool allocateSGPRSpillToVGPR(MachineFunction &MF, int FI);
544   bool reserveVGPRforSGPRSpills(MachineFunction &MF);
545   bool allocateVGPRSpillToAGPR(MachineFunction &MF, int FI, bool isAGPRtoVGPR);
546   void removeDeadFrameIndices(MachineFrameInfo &MFI);
547 
548   int getScavengeFI(MachineFrameInfo &MFI, const SIRegisterInfo &TRI);
549 
550   bool hasCalculatedTID() const { return TIDReg != 0; };
551   Register getTIDReg() const { return TIDReg; };
552   void setTIDReg(Register Reg) { TIDReg = Reg; }
553 
554   unsigned getBytesInStackArgArea() const {
555     return BytesInStackArgArea;
556   }
557 
558   void setBytesInStackArgArea(unsigned Bytes) {
559     BytesInStackArgArea = Bytes;
560   }
561 
562   // Add user SGPRs.
563   Register addPrivateSegmentBuffer(const SIRegisterInfo &TRI);
564   Register addDispatchPtr(const SIRegisterInfo &TRI);
565   Register addQueuePtr(const SIRegisterInfo &TRI);
566   Register addKernargSegmentPtr(const SIRegisterInfo &TRI);
567   Register addDispatchID(const SIRegisterInfo &TRI);
568   Register addFlatScratchInit(const SIRegisterInfo &TRI);
569   Register addImplicitBufferPtr(const SIRegisterInfo &TRI);
570 
571   // Add system SGPRs.
572   Register addWorkGroupIDX() {
573     ArgInfo.WorkGroupIDX = ArgDescriptor::createRegister(getNextSystemSGPR());
574     NumSystemSGPRs += 1;
575     return ArgInfo.WorkGroupIDX.getRegister();
576   }
577 
578   Register addWorkGroupIDY() {
579     ArgInfo.WorkGroupIDY = ArgDescriptor::createRegister(getNextSystemSGPR());
580     NumSystemSGPRs += 1;
581     return ArgInfo.WorkGroupIDY.getRegister();
582   }
583 
584   Register addWorkGroupIDZ() {
585     ArgInfo.WorkGroupIDZ = ArgDescriptor::createRegister(getNextSystemSGPR());
586     NumSystemSGPRs += 1;
587     return ArgInfo.WorkGroupIDZ.getRegister();
588   }
589 
590   Register addWorkGroupInfo() {
591     ArgInfo.WorkGroupInfo = ArgDescriptor::createRegister(getNextSystemSGPR());
592     NumSystemSGPRs += 1;
593     return ArgInfo.WorkGroupInfo.getRegister();
594   }
595 
596   // Add special VGPR inputs
597   void setWorkItemIDX(ArgDescriptor Arg) {
598     ArgInfo.WorkItemIDX = Arg;
599   }
600 
601   void setWorkItemIDY(ArgDescriptor Arg) {
602     ArgInfo.WorkItemIDY = Arg;
603   }
604 
605   void setWorkItemIDZ(ArgDescriptor Arg) {
606     ArgInfo.WorkItemIDZ = Arg;
607   }
608 
609   Register addPrivateSegmentWaveByteOffset() {
610     ArgInfo.PrivateSegmentWaveByteOffset
611       = ArgDescriptor::createRegister(getNextSystemSGPR());
612     NumSystemSGPRs += 1;
613     return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
614   }
615 
616   void setPrivateSegmentWaveByteOffset(Register Reg) {
617     ArgInfo.PrivateSegmentWaveByteOffset = ArgDescriptor::createRegister(Reg);
618   }
619 
620   bool hasPrivateSegmentBuffer() const {
621     return PrivateSegmentBuffer;
622   }
623 
624   bool hasDispatchPtr() const {
625     return DispatchPtr;
626   }
627 
628   bool hasQueuePtr() const {
629     return QueuePtr;
630   }
631 
632   bool hasKernargSegmentPtr() const {
633     return KernargSegmentPtr;
634   }
635 
636   bool hasDispatchID() const {
637     return DispatchID;
638   }
639 
640   bool hasFlatScratchInit() const {
641     return FlatScratchInit;
642   }
643 
644   bool hasWorkGroupIDX() const {
645     return WorkGroupIDX;
646   }
647 
648   bool hasWorkGroupIDY() const {
649     return WorkGroupIDY;
650   }
651 
652   bool hasWorkGroupIDZ() const {
653     return WorkGroupIDZ;
654   }
655 
656   bool hasWorkGroupInfo() const {
657     return WorkGroupInfo;
658   }
659 
660   bool hasPrivateSegmentWaveByteOffset() const {
661     return PrivateSegmentWaveByteOffset;
662   }
663 
664   bool hasWorkItemIDX() const {
665     return WorkItemIDX;
666   }
667 
668   bool hasWorkItemIDY() const {
669     return WorkItemIDY;
670   }
671 
672   bool hasWorkItemIDZ() const {
673     return WorkItemIDZ;
674   }
675 
676   bool hasImplicitArgPtr() const {
677     return ImplicitArgPtr;
678   }
679 
680   bool hasImplicitBufferPtr() const {
681     return ImplicitBufferPtr;
682   }
683 
684   AMDGPUFunctionArgInfo &getArgInfo() {
685     return ArgInfo;
686   }
687 
688   const AMDGPUFunctionArgInfo &getArgInfo() const {
689     return ArgInfo;
690   }
691 
692   std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
693   getPreloadedValue(AMDGPUFunctionArgInfo::PreloadedValue Value) const {
694     return ArgInfo.getPreloadedValue(Value);
695   }
696 
697   MCRegister getPreloadedReg(AMDGPUFunctionArgInfo::PreloadedValue Value) const {
698     auto Arg = std::get<0>(ArgInfo.getPreloadedValue(Value));
699     return Arg ? Arg->getRegister() : MCRegister();
700   }
701 
702   unsigned getGITPtrHigh() const {
703     return GITPtrHigh;
704   }
705 
706   Register getGITPtrLoReg(const MachineFunction &MF) const;
707 
708   uint32_t get32BitAddressHighBits() const {
709     return HighBitsOf32BitAddress;
710   }
711 
712   unsigned getGDSSize() const {
713     return GDSSize;
714   }
715 
716   unsigned getNumUserSGPRs() const {
717     return NumUserSGPRs;
718   }
719 
720   unsigned getNumPreloadedSGPRs() const {
721     return NumUserSGPRs + NumSystemSGPRs;
722   }
723 
724   Register getPrivateSegmentWaveByteOffsetSystemSGPR() const {
725     return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
726   }
727 
728   /// Returns the physical register reserved for use as the resource
729   /// descriptor for scratch accesses.
730   Register getScratchRSrcReg() const {
731     return ScratchRSrcReg;
732   }
733 
734   void setScratchRSrcReg(Register Reg) {
735     assert(Reg != 0 && "Should never be unset");
736     ScratchRSrcReg = Reg;
737   }
738 
739   Register getFrameOffsetReg() const {
740     return FrameOffsetReg;
741   }
742 
743   void setFrameOffsetReg(Register Reg) {
744     assert(Reg != 0 && "Should never be unset");
745     FrameOffsetReg = Reg;
746   }
747 
748   void setStackPtrOffsetReg(Register Reg) {
749     assert(Reg != 0 && "Should never be unset");
750     StackPtrOffsetReg = Reg;
751   }
752 
753   // Note the unset value for this is AMDGPU::SP_REG rather than
754   // NoRegister. This is mostly a workaround for MIR tests where state that
755   // can't be directly computed from the function is not preserved in serialized
756   // MIR.
757   Register getStackPtrOffsetReg() const {
758     return StackPtrOffsetReg;
759   }
760 
761   Register getQueuePtrUserSGPR() const {
762     return ArgInfo.QueuePtr.getRegister();
763   }
764 
765   Register getImplicitBufferPtrUserSGPR() const {
766     return ArgInfo.ImplicitBufferPtr.getRegister();
767   }
768 
769   bool hasSpilledSGPRs() const {
770     return HasSpilledSGPRs;
771   }
772 
773   void setHasSpilledSGPRs(bool Spill = true) {
774     HasSpilledSGPRs = Spill;
775   }
776 
777   bool hasSpilledVGPRs() const {
778     return HasSpilledVGPRs;
779   }
780 
781   void setHasSpilledVGPRs(bool Spill = true) {
782     HasSpilledVGPRs = Spill;
783   }
784 
785   bool hasNonSpillStackObjects() const {
786     return HasNonSpillStackObjects;
787   }
788 
789   void setHasNonSpillStackObjects(bool StackObject = true) {
790     HasNonSpillStackObjects = StackObject;
791   }
792 
793   bool isStackRealigned() const {
794     return IsStackRealigned;
795   }
796 
797   void setIsStackRealigned(bool Realigned = true) {
798     IsStackRealigned = Realigned;
799   }
800 
801   unsigned getNumSpilledSGPRs() const {
802     return NumSpilledSGPRs;
803   }
804 
805   unsigned getNumSpilledVGPRs() const {
806     return NumSpilledVGPRs;
807   }
808 
809   void addToSpilledSGPRs(unsigned num) {
810     NumSpilledSGPRs += num;
811   }
812 
813   void addToSpilledVGPRs(unsigned num) {
814     NumSpilledVGPRs += num;
815   }
816 
817   unsigned getPSInputAddr() const {
818     return PSInputAddr;
819   }
820 
821   unsigned getPSInputEnable() const {
822     return PSInputEnable;
823   }
824 
825   bool isPSInputAllocated(unsigned Index) const {
826     return PSInputAddr & (1 << Index);
827   }
828 
829   void markPSInputAllocated(unsigned Index) {
830     PSInputAddr |= 1 << Index;
831   }
832 
833   void markPSInputEnabled(unsigned Index) {
834     PSInputEnable |= 1 << Index;
835   }
836 
837   bool returnsVoid() const {
838     return ReturnsVoid;
839   }
840 
841   void setIfReturnsVoid(bool Value) {
842     ReturnsVoid = Value;
843   }
844 
845   /// \returns A pair of default/requested minimum/maximum flat work group sizes
846   /// for this function.
847   std::pair<unsigned, unsigned> getFlatWorkGroupSizes() const {
848     return FlatWorkGroupSizes;
849   }
850 
851   /// \returns Default/requested minimum flat work group size for this function.
852   unsigned getMinFlatWorkGroupSize() const {
853     return FlatWorkGroupSizes.first;
854   }
855 
856   /// \returns Default/requested maximum flat work group size for this function.
857   unsigned getMaxFlatWorkGroupSize() const {
858     return FlatWorkGroupSizes.second;
859   }
860 
861   /// \returns A pair of default/requested minimum/maximum number of waves per
862   /// execution unit.
863   std::pair<unsigned, unsigned> getWavesPerEU() const {
864     return WavesPerEU;
865   }
866 
867   /// \returns Default/requested minimum number of waves per execution unit.
868   unsigned getMinWavesPerEU() const {
869     return WavesPerEU.first;
870   }
871 
872   /// \returns Default/requested maximum number of waves per execution unit.
873   unsigned getMaxWavesPerEU() const {
874     return WavesPerEU.second;
875   }
876 
877   /// \returns SGPR used for \p Dim's work group ID.
878   Register getWorkGroupIDSGPR(unsigned Dim) const {
879     switch (Dim) {
880     case 0:
881       assert(hasWorkGroupIDX());
882       return ArgInfo.WorkGroupIDX.getRegister();
883     case 1:
884       assert(hasWorkGroupIDY());
885       return ArgInfo.WorkGroupIDY.getRegister();
886     case 2:
887       assert(hasWorkGroupIDZ());
888       return ArgInfo.WorkGroupIDZ.getRegister();
889     }
890     llvm_unreachable("unexpected dimension");
891   }
892 
893   unsigned getLDSWaveSpillSize() const {
894     return LDSWaveSpillSize;
895   }
896 
897   const AMDGPUBufferPseudoSourceValue *getBufferPSV(const SIInstrInfo &TII) {
898     if (!BufferPSV)
899       BufferPSV = std::make_unique<AMDGPUBufferPseudoSourceValue>(TII);
900 
901     return BufferPSV.get();
902   }
903 
904   const AMDGPUImagePseudoSourceValue *getImagePSV(const SIInstrInfo &TII) {
905     if (!ImagePSV)
906       ImagePSV = std::make_unique<AMDGPUImagePseudoSourceValue>(TII);
907 
908     return ImagePSV.get();
909   }
910 
911   const AMDGPUGWSResourcePseudoSourceValue *getGWSPSV(const SIInstrInfo &TII) {
912     if (!GWSResourcePSV) {
913       GWSResourcePSV =
914           std::make_unique<AMDGPUGWSResourcePseudoSourceValue>(TII);
915     }
916 
917     return GWSResourcePSV.get();
918   }
919 
920   unsigned getOccupancy() const {
921     return Occupancy;
922   }
923 
924   unsigned getMinAllowedOccupancy() const {
925     if (!isMemoryBound() && !needsWaveLimiter())
926       return Occupancy;
927     return (Occupancy < 4) ? Occupancy : 4;
928   }
929 
930   void limitOccupancy(const MachineFunction &MF);
931 
932   void limitOccupancy(unsigned Limit) {
933     if (Occupancy > Limit)
934       Occupancy = Limit;
935   }
936 
937   void increaseOccupancy(const MachineFunction &MF, unsigned Limit) {
938     if (Occupancy < Limit)
939       Occupancy = Limit;
940     limitOccupancy(MF);
941   }
942 };
943 
944 } // end namespace llvm
945 
946 #endif // LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
947