xref: /llvm-project/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h (revision db099f994b5fb14209e29487b87bc2be54b3725d) 
1 //==- SIMachineFunctionInfo.h - SIMachineFunctionInfo interface --*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
14 #define LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
15 
16 #include "AMDGPUArgumentUsageInfo.h"
17 #include "AMDGPUMachineFunction.h"
18 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
19 #include "SIInstrInfo.h"
20 #include "SIRegisterInfo.h"
21 #include "llvm/ADT/ArrayRef.h"
22 #include "llvm/ADT/DenseMap.h"
23 #include "llvm/ADT/Optional.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/SmallVector.h"
26 #include "llvm/ADT/SparseBitVector.h"
27 #include "llvm/CodeGen/MIRYamlMapping.h"
28 #include "llvm/CodeGen/PseudoSourceValue.h"
29 #include "llvm/CodeGen/TargetInstrInfo.h"
30 #include "llvm/MC/MCRegisterInfo.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include <array>
33 #include <cassert>
34 #include <utility>
35 #include <vector>
36 
37 namespace llvm {
38 
39 class MachineFrameInfo;
40 class MachineFunction;
41 class TargetRegisterClass;
42 
43 class AMDGPUPseudoSourceValue : public PseudoSourceValue {
44 public:
45   enum AMDGPUPSVKind : unsigned {
46     PSVBuffer = PseudoSourceValue::TargetCustom,
47     PSVImage,
48     GWSResource
49   };
50 
51 protected:
52   AMDGPUPseudoSourceValue(unsigned Kind, const TargetInstrInfo &TII)
53       : PseudoSourceValue(Kind, TII) {}
54 
55 public:
56   bool isConstant(const MachineFrameInfo *) const override {
57     // This should probably be true for most images, but we will start by being
58     // conservative.
59     return false;
60   }
61 
62   bool isAliased(const MachineFrameInfo *) const override {
63     return true;
64   }
65 
66   bool mayAlias(const MachineFrameInfo *) const override {
67     return true;
68   }
69 };
70 
71 class AMDGPUBufferPseudoSourceValue final : public AMDGPUPseudoSourceValue {
72 public:
73   explicit AMDGPUBufferPseudoSourceValue(const TargetInstrInfo &TII)
74       : AMDGPUPseudoSourceValue(PSVBuffer, TII) {}
75 
76   static bool classof(const PseudoSourceValue *V) {
77     return V->kind() == PSVBuffer;
78   }
79 };
80 
81 class AMDGPUImagePseudoSourceValue final : public AMDGPUPseudoSourceValue {
82 public:
83   // TODO: Is the img rsrc useful?
84   explicit AMDGPUImagePseudoSourceValue(const TargetInstrInfo &TII)
85       : AMDGPUPseudoSourceValue(PSVImage, TII) {}
86 
87   static bool classof(const PseudoSourceValue *V) {
88     return V->kind() == PSVImage;
89   }
90 };
91 
92 class AMDGPUGWSResourcePseudoSourceValue final : public AMDGPUPseudoSourceValue {
93 public:
94   explicit AMDGPUGWSResourcePseudoSourceValue(const TargetInstrInfo &TII)
95       : AMDGPUPseudoSourceValue(GWSResource, TII) {}
96 
97   static bool classof(const PseudoSourceValue *V) {
98     return V->kind() == GWSResource;
99   }
100 
101   // These are inaccessible memory from IR.
102   bool isAliased(const MachineFrameInfo *) const override {
103     return false;
104   }
105 
106   // These are inaccessible memory from IR.
107   bool mayAlias(const MachineFrameInfo *) const override {
108     return false;
109   }
110 
111   void printCustom(raw_ostream &OS) const override {
112     OS << "GWSResource";
113   }
114 };
115 
116 namespace yaml {
117 
118 struct SIArgument {
119   bool IsRegister;
120   union {
121     StringValue RegisterName;
122     unsigned StackOffset;
123   };
124   Optional<unsigned> Mask;
125 
126   // Default constructor, which creates a stack argument.
127   SIArgument() : IsRegister(false), StackOffset(0) {}
128   SIArgument(const SIArgument &Other) {
129     IsRegister = Other.IsRegister;
130     if (IsRegister) {
131       ::new ((void *)std::addressof(RegisterName))
132           StringValue(Other.RegisterName);
133     } else
134       StackOffset = Other.StackOffset;
135     Mask = Other.Mask;
136   }
137   SIArgument &operator=(const SIArgument &Other) {
138     IsRegister = Other.IsRegister;
139     if (IsRegister) {
140       ::new ((void *)std::addressof(RegisterName))
141           StringValue(Other.RegisterName);
142     } else
143       StackOffset = Other.StackOffset;
144     Mask = Other.Mask;
145     return *this;
146   }
147   ~SIArgument() {
148     if (IsRegister)
149       RegisterName.~StringValue();
150   }
151 
152   // Helper to create a register or stack argument.
153   static inline SIArgument createArgument(bool IsReg) {
154     if (IsReg)
155       return SIArgument(IsReg);
156     return SIArgument();
157   }
158 
159 private:
160   // Construct a register argument.
161   SIArgument(bool) : IsRegister(true), RegisterName() {}
162 };
163 
164 template <> struct MappingTraits<SIArgument> {
165   static void mapping(IO &YamlIO, SIArgument &A) {
166     if (YamlIO.outputting()) {
167       if (A.IsRegister)
168         YamlIO.mapRequired("reg", A.RegisterName);
169       else
170         YamlIO.mapRequired("offset", A.StackOffset);
171     } else {
172       auto Keys = YamlIO.keys();
173       if (is_contained(Keys, "reg")) {
174         A = SIArgument::createArgument(true);
175         YamlIO.mapRequired("reg", A.RegisterName);
176       } else if (is_contained(Keys, "offset"))
177         YamlIO.mapRequired("offset", A.StackOffset);
178       else
179         YamlIO.setError("missing required key 'reg' or 'offset'");
180     }
181     YamlIO.mapOptional("mask", A.Mask);
182   }
183   static const bool flow = true;
184 };
185 
186 struct SIArgumentInfo {
187   Optional<SIArgument> PrivateSegmentBuffer;
188   Optional<SIArgument> DispatchPtr;
189   Optional<SIArgument> QueuePtr;
190   Optional<SIArgument> KernargSegmentPtr;
191   Optional<SIArgument> DispatchID;
192   Optional<SIArgument> FlatScratchInit;
193   Optional<SIArgument> PrivateSegmentSize;
194 
195   Optional<SIArgument> WorkGroupIDX;
196   Optional<SIArgument> WorkGroupIDY;
197   Optional<SIArgument> WorkGroupIDZ;
198   Optional<SIArgument> WorkGroupInfo;
199   Optional<SIArgument> PrivateSegmentWaveByteOffset;
200 
201   Optional<SIArgument> ImplicitArgPtr;
202   Optional<SIArgument> ImplicitBufferPtr;
203 
204   Optional<SIArgument> WorkItemIDX;
205   Optional<SIArgument> WorkItemIDY;
206   Optional<SIArgument> WorkItemIDZ;
207 };
208 
209 template <> struct MappingTraits<SIArgumentInfo> {
210   static void mapping(IO &YamlIO, SIArgumentInfo &AI) {
211     YamlIO.mapOptional("privateSegmentBuffer", AI.PrivateSegmentBuffer);
212     YamlIO.mapOptional("dispatchPtr", AI.DispatchPtr);
213     YamlIO.mapOptional("queuePtr", AI.QueuePtr);
214     YamlIO.mapOptional("kernargSegmentPtr", AI.KernargSegmentPtr);
215     YamlIO.mapOptional("dispatchID", AI.DispatchID);
216     YamlIO.mapOptional("flatScratchInit", AI.FlatScratchInit);
217     YamlIO.mapOptional("privateSegmentSize", AI.PrivateSegmentSize);
218 
219     YamlIO.mapOptional("workGroupIDX", AI.WorkGroupIDX);
220     YamlIO.mapOptional("workGroupIDY", AI.WorkGroupIDY);
221     YamlIO.mapOptional("workGroupIDZ", AI.WorkGroupIDZ);
222     YamlIO.mapOptional("workGroupInfo", AI.WorkGroupInfo);
223     YamlIO.mapOptional("privateSegmentWaveByteOffset",
224                        AI.PrivateSegmentWaveByteOffset);
225 
226     YamlIO.mapOptional("implicitArgPtr", AI.ImplicitArgPtr);
227     YamlIO.mapOptional("implicitBufferPtr", AI.ImplicitBufferPtr);
228 
229     YamlIO.mapOptional("workItemIDX", AI.WorkItemIDX);
230     YamlIO.mapOptional("workItemIDY", AI.WorkItemIDY);
231     YamlIO.mapOptional("workItemIDZ", AI.WorkItemIDZ);
232   }
233 };
234 
235 // Default to default mode for default calling convention.
236 struct SIMode {
237   bool IEEE = true;
238   bool DX10Clamp = true;
239   bool FP32InputDenormals = true;
240   bool FP32OutputDenormals = true;
241   bool FP64FP16InputDenormals = true;
242   bool FP64FP16OutputDenormals = true;
243 
244   SIMode() = default;
245 
246   SIMode(const AMDGPU::SIModeRegisterDefaults &Mode) {
247     IEEE = Mode.IEEE;
248     DX10Clamp = Mode.DX10Clamp;
249     FP32InputDenormals = Mode.FP32InputDenormals;
250     FP32OutputDenormals = Mode.FP32OutputDenormals;
251     FP64FP16InputDenormals = Mode.FP64FP16InputDenormals;
252     FP64FP16OutputDenormals = Mode.FP64FP16OutputDenormals;
253   }
254 
255   bool operator ==(const SIMode Other) const {
256     return IEEE == Other.IEEE &&
257            DX10Clamp == Other.DX10Clamp &&
258            FP32InputDenormals == Other.FP32InputDenormals &&
259            FP32OutputDenormals == Other.FP32OutputDenormals &&
260            FP64FP16InputDenormals == Other.FP64FP16InputDenormals &&
261            FP64FP16OutputDenormals == Other.FP64FP16OutputDenormals;
262   }
263 };
264 
265 template <> struct MappingTraits<SIMode> {
266   static void mapping(IO &YamlIO, SIMode &Mode) {
267     YamlIO.mapOptional("ieee", Mode.IEEE, true);
268     YamlIO.mapOptional("dx10-clamp", Mode.DX10Clamp, true);
269     YamlIO.mapOptional("fp32-input-denormals", Mode.FP32InputDenormals, true);
270     YamlIO.mapOptional("fp32-output-denormals", Mode.FP32OutputDenormals, true);
271     YamlIO.mapOptional("fp64-fp16-input-denormals", Mode.FP64FP16InputDenormals, true);
272     YamlIO.mapOptional("fp64-fp16-output-denormals", Mode.FP64FP16OutputDenormals, true);
273   }
274 };
275 
276 struct SIMachineFunctionInfo final : public yaml::MachineFunctionInfo {
277   uint64_t ExplicitKernArgSize = 0;
278   unsigned MaxKernArgAlign = 0;
279   unsigned LDSSize = 0;
280   bool IsEntryFunction = false;
281   bool NoSignedZerosFPMath = false;
282   bool MemoryBound = false;
283   bool WaveLimiter = false;
284   uint32_t HighBitsOf32BitAddress = 0;
285 
286   StringValue ScratchRSrcReg = "$private_rsrc_reg";
287   StringValue ScratchWaveOffsetReg = "$scratch_wave_offset_reg";
288   StringValue FrameOffsetReg = "$fp_reg";
289   StringValue StackPtrOffsetReg = "$sp_reg";
290 
291   Optional<SIArgumentInfo> ArgInfo;
292   SIMode Mode;
293 
294   SIMachineFunctionInfo() = default;
295   SIMachineFunctionInfo(const llvm::SIMachineFunctionInfo &,
296                         const TargetRegisterInfo &TRI);
297 
298   void mappingImpl(yaml::IO &YamlIO) override;
299   ~SIMachineFunctionInfo() = default;
300 };
301 
302 template <> struct MappingTraits<SIMachineFunctionInfo> {
303   static void mapping(IO &YamlIO, SIMachineFunctionInfo &MFI) {
304     YamlIO.mapOptional("explicitKernArgSize", MFI.ExplicitKernArgSize,
305                        UINT64_C(0));
306     YamlIO.mapOptional("maxKernArgAlign", MFI.MaxKernArgAlign, 0u);
307     YamlIO.mapOptional("ldsSize", MFI.LDSSize, 0u);
308     YamlIO.mapOptional("isEntryFunction", MFI.IsEntryFunction, false);
309     YamlIO.mapOptional("noSignedZerosFPMath", MFI.NoSignedZerosFPMath, false);
310     YamlIO.mapOptional("memoryBound", MFI.MemoryBound, false);
311     YamlIO.mapOptional("waveLimiter", MFI.WaveLimiter, false);
312     YamlIO.mapOptional("scratchRSrcReg", MFI.ScratchRSrcReg,
313                        StringValue("$private_rsrc_reg"));
314     YamlIO.mapOptional("scratchWaveOffsetReg", MFI.ScratchWaveOffsetReg,
315                        StringValue("$scratch_wave_offset_reg"));
316     YamlIO.mapOptional("frameOffsetReg", MFI.FrameOffsetReg,
317                        StringValue("$fp_reg"));
318     YamlIO.mapOptional("stackPtrOffsetReg", MFI.StackPtrOffsetReg,
319                        StringValue("$sp_reg"));
320     YamlIO.mapOptional("argumentInfo", MFI.ArgInfo);
321     YamlIO.mapOptional("mode", MFI.Mode, SIMode());
322     YamlIO.mapOptional("highBitsOf32BitAddress",
323                        MFI.HighBitsOf32BitAddress, 0u);
324   }
325 };
326 
327 } // end namespace yaml
328 
329 /// This class keeps track of the SPI_SP_INPUT_ADDR config register, which
330 /// tells the hardware which interpolation parameters to load.
331 class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
332   friend class GCNTargetMachine;
333 
334   Register TIDReg = AMDGPU::NoRegister;
335 
336   // Registers that may be reserved for spilling purposes. These may be the same
337   // as the input registers.
338   Register ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG;
339   Register ScratchWaveOffsetReg = AMDGPU::SCRATCH_WAVE_OFFSET_REG;
340 
341   // This is the current function's incremented size from the kernel's scratch
342   // wave offset register. For an entry function, this is exactly the same as
343   // the ScratchWaveOffsetReg.
344   Register FrameOffsetReg = AMDGPU::FP_REG;
345 
346   // Top of the stack SGPR offset derived from the ScratchWaveOffsetReg.
347   Register StackPtrOffsetReg = AMDGPU::SP_REG;
348 
349   AMDGPUFunctionArgInfo ArgInfo;
350 
351   // Graphics info.
352   unsigned PSInputAddr = 0;
353   unsigned PSInputEnable = 0;
354 
355   /// Number of bytes of arguments this function has on the stack. If the callee
356   /// is expected to restore the argument stack this should be a multiple of 16,
357   /// all usable during a tail call.
358   ///
359   /// The alternative would forbid tail call optimisation in some cases: if we
360   /// want to transfer control from a function with 8-bytes of stack-argument
361   /// space to a function with 16-bytes then misalignment of this value would
362   /// make a stack adjustment necessary, which could not be undone by the
363   /// callee.
364   unsigned BytesInStackArgArea = 0;
365 
366   bool ReturnsVoid = true;
367 
368   // A pair of default/requested minimum/maximum flat work group sizes.
369   // Minimum - first, maximum - second.
370   std::pair<unsigned, unsigned> FlatWorkGroupSizes = {0, 0};
371 
372   // A pair of default/requested minimum/maximum number of waves per execution
373   // unit. Minimum - first, maximum - second.
374   std::pair<unsigned, unsigned> WavesPerEU = {0, 0};
375 
376   DenseMap<const Value *,
377            std::unique_ptr<const AMDGPUBufferPseudoSourceValue>> BufferPSVs;
378   DenseMap<const Value *,
379            std::unique_ptr<const AMDGPUImagePseudoSourceValue>> ImagePSVs;
380   std::unique_ptr<const AMDGPUGWSResourcePseudoSourceValue> GWSResourcePSV;
381 
382 private:
383   unsigned LDSWaveSpillSize = 0;
384   unsigned NumUserSGPRs = 0;
385   unsigned NumSystemSGPRs = 0;
386 
387   bool HasSpilledSGPRs = false;
388   bool HasSpilledVGPRs = false;
389   bool HasNonSpillStackObjects = false;
390   bool IsStackRealigned = false;
391 
392   unsigned NumSpilledSGPRs = 0;
393   unsigned NumSpilledVGPRs = 0;
394 
395   // Feature bits required for inputs passed in user SGPRs.
396   bool PrivateSegmentBuffer : 1;
397   bool DispatchPtr : 1;
398   bool QueuePtr : 1;
399   bool KernargSegmentPtr : 1;
400   bool DispatchID : 1;
401   bool FlatScratchInit : 1;
402 
403   // Feature bits required for inputs passed in system SGPRs.
404   bool WorkGroupIDX : 1; // Always initialized.
405   bool WorkGroupIDY : 1;
406   bool WorkGroupIDZ : 1;
407   bool WorkGroupInfo : 1;
408   bool PrivateSegmentWaveByteOffset : 1;
409 
410   bool WorkItemIDX : 1; // Always initialized.
411   bool WorkItemIDY : 1;
412   bool WorkItemIDZ : 1;
413 
414   // Private memory buffer
415   // Compute directly in sgpr[0:1]
416   // Other shaders indirect 64-bits at sgpr[0:1]
417   bool ImplicitBufferPtr : 1;
418 
419   // Pointer to where the ABI inserts special kernel arguments separate from the
420   // user arguments. This is an offset from the KernargSegmentPtr.
421   bool ImplicitArgPtr : 1;
422 
423   // The hard-wired high half of the address of the global information table
424   // for AMDPAL OS type. 0xffffffff represents no hard-wired high half, since
425   // current hardware only allows a 16 bit value.
426   unsigned GITPtrHigh;
427 
428   unsigned HighBitsOf32BitAddress;
429   unsigned GDSSize;
430 
431   // Current recorded maximum possible occupancy.
432   unsigned Occupancy;
433 
434   MCPhysReg getNextUserSGPR() const;
435 
436   MCPhysReg getNextSystemSGPR() const;
437 
438 public:
439   struct SpilledReg {
440     Register VGPR;
441     int Lane = -1;
442 
443     SpilledReg() = default;
444     SpilledReg(Register R, int L) : VGPR (R), Lane (L) {}
445 
446     bool hasLane() { return Lane != -1;}
447     bool hasReg() { return VGPR != 0;}
448   };
449 
450   struct SGPRSpillVGPRCSR {
451     // VGPR used for SGPR spills
452     Register VGPR;
453 
454     // If the VGPR is a CSR, the stack slot used to save/restore it in the
455     // prolog/epilog.
456     Optional<int> FI;
457 
458     SGPRSpillVGPRCSR(Register V, Optional<int> F) : VGPR(V), FI(F) {}
459   };
460 
461   struct VGPRSpillToAGPR {
462     SmallVector<MCPhysReg, 32> Lanes;
463     bool FullyAllocated = false;
464   };
465 
466   SparseBitVector<> WWMReservedRegs;
467 
468   void ReserveWWMRegister(Register Reg) { WWMReservedRegs.set(Reg); }
469 
470 private:
471   // Track VGPR + wave index for each subregister of the SGPR spilled to
472   // frameindex key.
473   DenseMap<int, std::vector<SpilledReg>> SGPRToVGPRSpills;
474   unsigned NumVGPRSpillLanes = 0;
475   SmallVector<SGPRSpillVGPRCSR, 2> SpillVGPRs;
476 
477   DenseMap<int, VGPRSpillToAGPR> VGPRToAGPRSpills;
478 
479   // AGPRs used for VGPR spills.
480   SmallVector<MCPhysReg, 32> SpillAGPR;
481 
482   // VGPRs used for AGPR spills.
483   SmallVector<MCPhysReg, 32> SpillVGPR;
484 
485 public: // FIXME
486   /// If this is set, an SGPR used for save/restore of the register used for the
487   /// frame pointer.
488   Register SGPRForFPSaveRestoreCopy;
489   Optional<int> FramePointerSaveIndex;
490 
491 public:
492   SIMachineFunctionInfo(const MachineFunction &MF);
493 
494   bool initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI);
495 
496   ArrayRef<SpilledReg> getSGPRToVGPRSpills(int FrameIndex) const {
497     auto I = SGPRToVGPRSpills.find(FrameIndex);
498     return (I == SGPRToVGPRSpills.end()) ?
499       ArrayRef<SpilledReg>() : makeArrayRef(I->second);
500   }
501 
502   ArrayRef<SGPRSpillVGPRCSR> getSGPRSpillVGPRs() const {
503     return SpillVGPRs;
504   }
505 
506   ArrayRef<MCPhysReg> getAGPRSpillVGPRs() const {
507     return SpillAGPR;
508   }
509 
510   ArrayRef<MCPhysReg> getVGPRSpillAGPRs() const {
511     return SpillVGPR;
512   }
513 
514   MCPhysReg getVGPRToAGPRSpill(int FrameIndex, unsigned Lane) const {
515     auto I = VGPRToAGPRSpills.find(FrameIndex);
516     return (I == VGPRToAGPRSpills.end()) ? (MCPhysReg)AMDGPU::NoRegister
517                                          : I->second.Lanes[Lane];
518   }
519 
520   bool haveFreeLanesForSGPRSpill(const MachineFunction &MF,
521                                  unsigned NumLane) const;
522   bool allocateSGPRSpillToVGPR(MachineFunction &MF, int FI);
523   bool allocateVGPRSpillToAGPR(MachineFunction &MF, int FI, bool isAGPRtoVGPR);
524   void removeDeadFrameIndices(MachineFrameInfo &MFI);
525 
526   bool hasCalculatedTID() const { return TIDReg != 0; };
527   Register getTIDReg() const { return TIDReg; };
528   void setTIDReg(Register Reg) { TIDReg = Reg; }
529 
530   unsigned getBytesInStackArgArea() const {
531     return BytesInStackArgArea;
532   }
533 
534   void setBytesInStackArgArea(unsigned Bytes) {
535     BytesInStackArgArea = Bytes;
536   }
537 
538   // Add user SGPRs.
539   Register addPrivateSegmentBuffer(const SIRegisterInfo &TRI);
540   Register addDispatchPtr(const SIRegisterInfo &TRI);
541   Register addQueuePtr(const SIRegisterInfo &TRI);
542   Register addKernargSegmentPtr(const SIRegisterInfo &TRI);
543   Register addDispatchID(const SIRegisterInfo &TRI);
544   Register addFlatScratchInit(const SIRegisterInfo &TRI);
545   Register addImplicitBufferPtr(const SIRegisterInfo &TRI);
546 
547   // Add system SGPRs.
548   Register addWorkGroupIDX() {
549     ArgInfo.WorkGroupIDX = ArgDescriptor::createRegister(getNextSystemSGPR());
550     NumSystemSGPRs += 1;
551     return ArgInfo.WorkGroupIDX.getRegister();
552   }
553 
554   Register addWorkGroupIDY() {
555     ArgInfo.WorkGroupIDY = ArgDescriptor::createRegister(getNextSystemSGPR());
556     NumSystemSGPRs += 1;
557     return ArgInfo.WorkGroupIDY.getRegister();
558   }
559 
560   Register addWorkGroupIDZ() {
561     ArgInfo.WorkGroupIDZ = ArgDescriptor::createRegister(getNextSystemSGPR());
562     NumSystemSGPRs += 1;
563     return ArgInfo.WorkGroupIDZ.getRegister();
564   }
565 
566   Register addWorkGroupInfo() {
567     ArgInfo.WorkGroupInfo = ArgDescriptor::createRegister(getNextSystemSGPR());
568     NumSystemSGPRs += 1;
569     return ArgInfo.WorkGroupInfo.getRegister();
570   }
571 
572   // Add special VGPR inputs
573   void setWorkItemIDX(ArgDescriptor Arg) {
574     ArgInfo.WorkItemIDX = Arg;
575   }
576 
577   void setWorkItemIDY(ArgDescriptor Arg) {
578     ArgInfo.WorkItemIDY = Arg;
579   }
580 
581   void setWorkItemIDZ(ArgDescriptor Arg) {
582     ArgInfo.WorkItemIDZ = Arg;
583   }
584 
585   Register addPrivateSegmentWaveByteOffset() {
586     ArgInfo.PrivateSegmentWaveByteOffset
587       = ArgDescriptor::createRegister(getNextSystemSGPR());
588     NumSystemSGPRs += 1;
589     return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
590   }
591 
592   void setPrivateSegmentWaveByteOffset(Register Reg) {
593     ArgInfo.PrivateSegmentWaveByteOffset = ArgDescriptor::createRegister(Reg);
594   }
595 
596   bool hasPrivateSegmentBuffer() const {
597     return PrivateSegmentBuffer;
598   }
599 
600   bool hasDispatchPtr() const {
601     return DispatchPtr;
602   }
603 
604   bool hasQueuePtr() const {
605     return QueuePtr;
606   }
607 
608   bool hasKernargSegmentPtr() const {
609     return KernargSegmentPtr;
610   }
611 
612   bool hasDispatchID() const {
613     return DispatchID;
614   }
615 
616   bool hasFlatScratchInit() const {
617     return FlatScratchInit;
618   }
619 
620   bool hasWorkGroupIDX() const {
621     return WorkGroupIDX;
622   }
623 
624   bool hasWorkGroupIDY() const {
625     return WorkGroupIDY;
626   }
627 
628   bool hasWorkGroupIDZ() const {
629     return WorkGroupIDZ;
630   }
631 
632   bool hasWorkGroupInfo() const {
633     return WorkGroupInfo;
634   }
635 
636   bool hasPrivateSegmentWaveByteOffset() const {
637     return PrivateSegmentWaveByteOffset;
638   }
639 
640   bool hasWorkItemIDX() const {
641     return WorkItemIDX;
642   }
643 
644   bool hasWorkItemIDY() const {
645     return WorkItemIDY;
646   }
647 
648   bool hasWorkItemIDZ() const {
649     return WorkItemIDZ;
650   }
651 
652   bool hasImplicitArgPtr() const {
653     return ImplicitArgPtr;
654   }
655 
656   bool hasImplicitBufferPtr() const {
657     return ImplicitBufferPtr;
658   }
659 
660   AMDGPUFunctionArgInfo &getArgInfo() {
661     return ArgInfo;
662   }
663 
664   const AMDGPUFunctionArgInfo &getArgInfo() const {
665     return ArgInfo;
666   }
667 
668   std::pair<const ArgDescriptor *, const TargetRegisterClass *>
669   getPreloadedValue(AMDGPUFunctionArgInfo::PreloadedValue Value) const {
670     return ArgInfo.getPreloadedValue(Value);
671   }
672 
673   Register getPreloadedReg(AMDGPUFunctionArgInfo::PreloadedValue Value) const {
674     auto Arg = ArgInfo.getPreloadedValue(Value).first;
675     return Arg ? Arg->getRegister() : Register();
676   }
677 
678   unsigned getGITPtrHigh() const {
679     return GITPtrHigh;
680   }
681 
682   uint32_t get32BitAddressHighBits() const {
683     return HighBitsOf32BitAddress;
684   }
685 
686   unsigned getGDSSize() const {
687     return GDSSize;
688   }
689 
690   unsigned getNumUserSGPRs() const {
691     return NumUserSGPRs;
692   }
693 
694   unsigned getNumPreloadedSGPRs() const {
695     return NumUserSGPRs + NumSystemSGPRs;
696   }
697 
698   Register getPrivateSegmentWaveByteOffsetSystemSGPR() const {
699     return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
700   }
701 
702   /// Returns the physical register reserved for use as the resource
703   /// descriptor for scratch accesses.
704   Register getScratchRSrcReg() const {
705     return ScratchRSrcReg;
706   }
707 
708   void setScratchRSrcReg(Register Reg) {
709     assert(Reg != 0 && "Should never be unset");
710     ScratchRSrcReg = Reg;
711   }
712 
713   Register getScratchWaveOffsetReg() const {
714     return ScratchWaveOffsetReg;
715   }
716 
717   Register getFrameOffsetReg() const {
718     return FrameOffsetReg;
719   }
720 
721   void setFrameOffsetReg(Register Reg) {
722     assert(Reg != 0 && "Should never be unset");
723     FrameOffsetReg = Reg;
724   }
725 
726   void setStackPtrOffsetReg(Register Reg) {
727     assert(Reg != 0 && "Should never be unset");
728     StackPtrOffsetReg = Reg;
729   }
730 
731   // Note the unset value for this is AMDGPU::SP_REG rather than
732   // NoRegister. This is mostly a workaround for MIR tests where state that
733   // can't be directly computed from the function is not preserved in serialized
734   // MIR.
735   Register getStackPtrOffsetReg() const {
736     return StackPtrOffsetReg;
737   }
738 
739   void setScratchWaveOffsetReg(Register Reg) {
740     assert(Reg != 0 && "Should never be unset");
741     ScratchWaveOffsetReg = Reg;
742   }
743 
744   Register getQueuePtrUserSGPR() const {
745     return ArgInfo.QueuePtr.getRegister();
746   }
747 
748   Register getImplicitBufferPtrUserSGPR() const {
749     return ArgInfo.ImplicitBufferPtr.getRegister();
750   }
751 
752   bool hasSpilledSGPRs() const {
753     return HasSpilledSGPRs;
754   }
755 
756   void setHasSpilledSGPRs(bool Spill = true) {
757     HasSpilledSGPRs = Spill;
758   }
759 
760   bool hasSpilledVGPRs() const {
761     return HasSpilledVGPRs;
762   }
763 
764   void setHasSpilledVGPRs(bool Spill = true) {
765     HasSpilledVGPRs = Spill;
766   }
767 
768   bool hasNonSpillStackObjects() const {
769     return HasNonSpillStackObjects;
770   }
771 
772   void setHasNonSpillStackObjects(bool StackObject = true) {
773     HasNonSpillStackObjects = StackObject;
774   }
775 
776   bool isStackRealigned() const {
777     return IsStackRealigned;
778   }
779 
780   void setIsStackRealigned(bool Realigned = true) {
781     IsStackRealigned = Realigned;
782   }
783 
784   unsigned getNumSpilledSGPRs() const {
785     return NumSpilledSGPRs;
786   }
787 
788   unsigned getNumSpilledVGPRs() const {
789     return NumSpilledVGPRs;
790   }
791 
792   void addToSpilledSGPRs(unsigned num) {
793     NumSpilledSGPRs += num;
794   }
795 
796   void addToSpilledVGPRs(unsigned num) {
797     NumSpilledVGPRs += num;
798   }
799 
800   unsigned getPSInputAddr() const {
801     return PSInputAddr;
802   }
803 
804   unsigned getPSInputEnable() const {
805     return PSInputEnable;
806   }
807 
808   bool isPSInputAllocated(unsigned Index) const {
809     return PSInputAddr & (1 << Index);
810   }
811 
812   void markPSInputAllocated(unsigned Index) {
813     PSInputAddr |= 1 << Index;
814   }
815 
816   void markPSInputEnabled(unsigned Index) {
817     PSInputEnable |= 1 << Index;
818   }
819 
820   bool returnsVoid() const {
821     return ReturnsVoid;
822   }
823 
824   void setIfReturnsVoid(bool Value) {
825     ReturnsVoid = Value;
826   }
827 
828   /// \returns A pair of default/requested minimum/maximum flat work group sizes
829   /// for this function.
830   std::pair<unsigned, unsigned> getFlatWorkGroupSizes() const {
831     return FlatWorkGroupSizes;
832   }
833 
834   /// \returns Default/requested minimum flat work group size for this function.
835   unsigned getMinFlatWorkGroupSize() const {
836     return FlatWorkGroupSizes.first;
837   }
838 
839   /// \returns Default/requested maximum flat work group size for this function.
840   unsigned getMaxFlatWorkGroupSize() const {
841     return FlatWorkGroupSizes.second;
842   }
843 
844   /// \returns A pair of default/requested minimum/maximum number of waves per
845   /// execution unit.
846   std::pair<unsigned, unsigned> getWavesPerEU() const {
847     return WavesPerEU;
848   }
849 
850   /// \returns Default/requested minimum number of waves per execution unit.
851   unsigned getMinWavesPerEU() const {
852     return WavesPerEU.first;
853   }
854 
855   /// \returns Default/requested maximum number of waves per execution unit.
856   unsigned getMaxWavesPerEU() const {
857     return WavesPerEU.second;
858   }
859 
860   /// \returns SGPR used for \p Dim's work group ID.
861   Register getWorkGroupIDSGPR(unsigned Dim) const {
862     switch (Dim) {
863     case 0:
864       assert(hasWorkGroupIDX());
865       return ArgInfo.WorkGroupIDX.getRegister();
866     case 1:
867       assert(hasWorkGroupIDY());
868       return ArgInfo.WorkGroupIDY.getRegister();
869     case 2:
870       assert(hasWorkGroupIDZ());
871       return ArgInfo.WorkGroupIDZ.getRegister();
872     }
873     llvm_unreachable("unexpected dimension");
874   }
875 
876   unsigned getLDSWaveSpillSize() const {
877     return LDSWaveSpillSize;
878   }
879 
880   const AMDGPUBufferPseudoSourceValue *getBufferPSV(const SIInstrInfo &TII,
881                                                     const Value *BufferRsrc) {
882     assert(BufferRsrc);
883     auto PSV = BufferPSVs.try_emplace(
884       BufferRsrc,
885       std::make_unique<AMDGPUBufferPseudoSourceValue>(TII));
886     return PSV.first->second.get();
887   }
888 
889   const AMDGPUImagePseudoSourceValue *getImagePSV(const SIInstrInfo &TII,
890                                                   const Value *ImgRsrc) {
891     assert(ImgRsrc);
892     auto PSV = ImagePSVs.try_emplace(
893       ImgRsrc,
894       std::make_unique<AMDGPUImagePseudoSourceValue>(TII));
895     return PSV.first->second.get();
896   }
897 
898   const AMDGPUGWSResourcePseudoSourceValue *getGWSPSV(const SIInstrInfo &TII) {
899     if (!GWSResourcePSV) {
900       GWSResourcePSV =
901           std::make_unique<AMDGPUGWSResourcePseudoSourceValue>(TII);
902     }
903 
904     return GWSResourcePSV.get();
905   }
906 
907   unsigned getOccupancy() const {
908     return Occupancy;
909   }
910 
911   unsigned getMinAllowedOccupancy() const {
912     if (!isMemoryBound() && !needsWaveLimiter())
913       return Occupancy;
914     return (Occupancy < 4) ? Occupancy : 4;
915   }
916 
917   void limitOccupancy(const MachineFunction &MF);
918 
919   void limitOccupancy(unsigned Limit) {
920     if (Occupancy > Limit)
921       Occupancy = Limit;
922   }
923 
924   void increaseOccupancy(const MachineFunction &MF, unsigned Limit) {
925     if (Occupancy < Limit)
926       Occupancy = Limit;
927     limitOccupancy(MF);
928   }
929 };
930 
931 } // end namespace llvm
932 
933 #endif // LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
934