xref: /llvm-project/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h (revision d8f99bb6e0641474b6bc1728295b40a8fa279f9a) 
1 //==- SIMachineFunctionInfo.h - SIMachineFunctionInfo interface --*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
14 #define LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
15 
16 #include "AMDGPUArgumentUsageInfo.h"
17 #include "AMDGPUMachineFunction.h"
18 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
19 #include "SIInstrInfo.h"
20 #include "llvm/ADT/MapVector.h"
21 #include "llvm/CodeGen/MIRYamlMapping.h"
22 #include "llvm/CodeGen/PseudoSourceValue.h"
23 #include "llvm/Support/raw_ostream.h"
24 
25 namespace llvm {
26 
27 class MachineFrameInfo;
28 class MachineFunction;
29 class SIMachineFunctionInfo;
30 class SIRegisterInfo;
31 class TargetRegisterClass;
32 
33 class AMDGPUPseudoSourceValue : public PseudoSourceValue {
34 public:
35   enum AMDGPUPSVKind : unsigned {
36     PSVBuffer = PseudoSourceValue::TargetCustom,
37     PSVImage,
38     GWSResource
39   };
40 
41 protected:
42   AMDGPUPseudoSourceValue(unsigned Kind, const TargetInstrInfo &TII)
43       : PseudoSourceValue(Kind, TII) {}
44 
45 public:
46   bool isConstant(const MachineFrameInfo *) const override {
47     // This should probably be true for most images, but we will start by being
48     // conservative.
49     return false;
50   }
51 
52   bool isAliased(const MachineFrameInfo *) const override {
53     return true;
54   }
55 
56   bool mayAlias(const MachineFrameInfo *) const override {
57     return true;
58   }
59 };
60 
61 class AMDGPUBufferPseudoSourceValue final : public AMDGPUPseudoSourceValue {
62 public:
63   explicit AMDGPUBufferPseudoSourceValue(const TargetInstrInfo &TII)
64       : AMDGPUPseudoSourceValue(PSVBuffer, TII) {}
65 
66   static bool classof(const PseudoSourceValue *V) {
67     return V->kind() == PSVBuffer;
68   }
69 
70   void printCustom(raw_ostream &OS) const override { OS << "BufferResource"; }
71 };
72 
73 class AMDGPUImagePseudoSourceValue final : public AMDGPUPseudoSourceValue {
74 public:
75   // TODO: Is the img rsrc useful?
76   explicit AMDGPUImagePseudoSourceValue(const TargetInstrInfo &TII)
77       : AMDGPUPseudoSourceValue(PSVImage, TII) {}
78 
79   static bool classof(const PseudoSourceValue *V) {
80     return V->kind() == PSVImage;
81   }
82 
83   void printCustom(raw_ostream &OS) const override { OS << "ImageResource"; }
84 };
85 
86 class AMDGPUGWSResourcePseudoSourceValue final : public AMDGPUPseudoSourceValue {
87 public:
88   explicit AMDGPUGWSResourcePseudoSourceValue(const TargetInstrInfo &TII)
89       : AMDGPUPseudoSourceValue(GWSResource, TII) {}
90 
91   static bool classof(const PseudoSourceValue *V) {
92     return V->kind() == GWSResource;
93   }
94 
95   // These are inaccessible memory from IR.
96   bool isAliased(const MachineFrameInfo *) const override {
97     return false;
98   }
99 
100   // These are inaccessible memory from IR.
101   bool mayAlias(const MachineFrameInfo *) const override {
102     return false;
103   }
104 
105   void printCustom(raw_ostream &OS) const override {
106     OS << "GWSResource";
107   }
108 };
109 
110 namespace yaml {
111 
112 struct SIArgument {
113   bool IsRegister;
114   union {
115     StringValue RegisterName;
116     unsigned StackOffset;
117   };
118   Optional<unsigned> Mask;
119 
120   // Default constructor, which creates a stack argument.
121   SIArgument() : IsRegister(false), StackOffset(0) {}
122   SIArgument(const SIArgument &Other) {
123     IsRegister = Other.IsRegister;
124     if (IsRegister) {
125       ::new ((void *)std::addressof(RegisterName))
126           StringValue(Other.RegisterName);
127     } else
128       StackOffset = Other.StackOffset;
129     Mask = Other.Mask;
130   }
131   SIArgument &operator=(const SIArgument &Other) {
132     IsRegister = Other.IsRegister;
133     if (IsRegister) {
134       ::new ((void *)std::addressof(RegisterName))
135           StringValue(Other.RegisterName);
136     } else
137       StackOffset = Other.StackOffset;
138     Mask = Other.Mask;
139     return *this;
140   }
141   ~SIArgument() {
142     if (IsRegister)
143       RegisterName.~StringValue();
144   }
145 
146   // Helper to create a register or stack argument.
147   static inline SIArgument createArgument(bool IsReg) {
148     if (IsReg)
149       return SIArgument(IsReg);
150     return SIArgument();
151   }
152 
153 private:
154   // Construct a register argument.
155   SIArgument(bool) : IsRegister(true), RegisterName() {}
156 };
157 
158 template <> struct MappingTraits<SIArgument> {
159   static void mapping(IO &YamlIO, SIArgument &A) {
160     if (YamlIO.outputting()) {
161       if (A.IsRegister)
162         YamlIO.mapRequired("reg", A.RegisterName);
163       else
164         YamlIO.mapRequired("offset", A.StackOffset);
165     } else {
166       auto Keys = YamlIO.keys();
167       if (is_contained(Keys, "reg")) {
168         A = SIArgument::createArgument(true);
169         YamlIO.mapRequired("reg", A.RegisterName);
170       } else if (is_contained(Keys, "offset"))
171         YamlIO.mapRequired("offset", A.StackOffset);
172       else
173         YamlIO.setError("missing required key 'reg' or 'offset'");
174     }
175     YamlIO.mapOptional("mask", A.Mask);
176   }
177   static const bool flow = true;
178 };
179 
180 struct SIArgumentInfo {
181   Optional<SIArgument> PrivateSegmentBuffer;
182   Optional<SIArgument> DispatchPtr;
183   Optional<SIArgument> QueuePtr;
184   Optional<SIArgument> KernargSegmentPtr;
185   Optional<SIArgument> DispatchID;
186   Optional<SIArgument> FlatScratchInit;
187   Optional<SIArgument> PrivateSegmentSize;
188 
189   Optional<SIArgument> WorkGroupIDX;
190   Optional<SIArgument> WorkGroupIDY;
191   Optional<SIArgument> WorkGroupIDZ;
192   Optional<SIArgument> WorkGroupInfo;
193   Optional<SIArgument> PrivateSegmentWaveByteOffset;
194 
195   Optional<SIArgument> ImplicitArgPtr;
196   Optional<SIArgument> ImplicitBufferPtr;
197 
198   Optional<SIArgument> WorkItemIDX;
199   Optional<SIArgument> WorkItemIDY;
200   Optional<SIArgument> WorkItemIDZ;
201 };
202 
203 template <> struct MappingTraits<SIArgumentInfo> {
204   static void mapping(IO &YamlIO, SIArgumentInfo &AI) {
205     YamlIO.mapOptional("privateSegmentBuffer", AI.PrivateSegmentBuffer);
206     YamlIO.mapOptional("dispatchPtr", AI.DispatchPtr);
207     YamlIO.mapOptional("queuePtr", AI.QueuePtr);
208     YamlIO.mapOptional("kernargSegmentPtr", AI.KernargSegmentPtr);
209     YamlIO.mapOptional("dispatchID", AI.DispatchID);
210     YamlIO.mapOptional("flatScratchInit", AI.FlatScratchInit);
211     YamlIO.mapOptional("privateSegmentSize", AI.PrivateSegmentSize);
212 
213     YamlIO.mapOptional("workGroupIDX", AI.WorkGroupIDX);
214     YamlIO.mapOptional("workGroupIDY", AI.WorkGroupIDY);
215     YamlIO.mapOptional("workGroupIDZ", AI.WorkGroupIDZ);
216     YamlIO.mapOptional("workGroupInfo", AI.WorkGroupInfo);
217     YamlIO.mapOptional("privateSegmentWaveByteOffset",
218                        AI.PrivateSegmentWaveByteOffset);
219 
220     YamlIO.mapOptional("implicitArgPtr", AI.ImplicitArgPtr);
221     YamlIO.mapOptional("implicitBufferPtr", AI.ImplicitBufferPtr);
222 
223     YamlIO.mapOptional("workItemIDX", AI.WorkItemIDX);
224     YamlIO.mapOptional("workItemIDY", AI.WorkItemIDY);
225     YamlIO.mapOptional("workItemIDZ", AI.WorkItemIDZ);
226   }
227 };
228 
229 // Default to default mode for default calling convention.
230 struct SIMode {
231   bool IEEE = true;
232   bool DX10Clamp = true;
233   bool FP32InputDenormals = true;
234   bool FP32OutputDenormals = true;
235   bool FP64FP16InputDenormals = true;
236   bool FP64FP16OutputDenormals = true;
237 
238   SIMode() = default;
239 
240   SIMode(const AMDGPU::SIModeRegisterDefaults &Mode) {
241     IEEE = Mode.IEEE;
242     DX10Clamp = Mode.DX10Clamp;
243     FP32InputDenormals = Mode.FP32InputDenormals;
244     FP32OutputDenormals = Mode.FP32OutputDenormals;
245     FP64FP16InputDenormals = Mode.FP64FP16InputDenormals;
246     FP64FP16OutputDenormals = Mode.FP64FP16OutputDenormals;
247   }
248 
249   bool operator ==(const SIMode Other) const {
250     return IEEE == Other.IEEE &&
251            DX10Clamp == Other.DX10Clamp &&
252            FP32InputDenormals == Other.FP32InputDenormals &&
253            FP32OutputDenormals == Other.FP32OutputDenormals &&
254            FP64FP16InputDenormals == Other.FP64FP16InputDenormals &&
255            FP64FP16OutputDenormals == Other.FP64FP16OutputDenormals;
256   }
257 };
258 
259 template <> struct MappingTraits<SIMode> {
260   static void mapping(IO &YamlIO, SIMode &Mode) {
261     YamlIO.mapOptional("ieee", Mode.IEEE, true);
262     YamlIO.mapOptional("dx10-clamp", Mode.DX10Clamp, true);
263     YamlIO.mapOptional("fp32-input-denormals", Mode.FP32InputDenormals, true);
264     YamlIO.mapOptional("fp32-output-denormals", Mode.FP32OutputDenormals, true);
265     YamlIO.mapOptional("fp64-fp16-input-denormals", Mode.FP64FP16InputDenormals, true);
266     YamlIO.mapOptional("fp64-fp16-output-denormals", Mode.FP64FP16OutputDenormals, true);
267   }
268 };
269 
270 struct SIMachineFunctionInfo final : public yaml::MachineFunctionInfo {
271   uint64_t ExplicitKernArgSize = 0;
272   unsigned MaxKernArgAlign = 0;
273   unsigned LDSSize = 0;
274   Align DynLDSAlign;
275   bool IsEntryFunction = false;
276   bool NoSignedZerosFPMath = false;
277   bool MemoryBound = false;
278   bool WaveLimiter = false;
279   bool HasSpilledSGPRs = false;
280   bool HasSpilledVGPRs = false;
281   uint32_t HighBitsOf32BitAddress = 0;
282 
283   // TODO: 10 may be a better default since it's the maximum.
284   unsigned Occupancy = 0;
285 
286   StringValue ScratchRSrcReg = "$private_rsrc_reg";
287   StringValue FrameOffsetReg = "$fp_reg";
288   StringValue StackPtrOffsetReg = "$sp_reg";
289 
290   Optional<SIArgumentInfo> ArgInfo;
291   SIMode Mode;
292   Optional<FrameIndex> ScavengeFI;
293 
294   SIMachineFunctionInfo() = default;
295   SIMachineFunctionInfo(const llvm::SIMachineFunctionInfo &,
296                         const TargetRegisterInfo &TRI,
297                         const llvm::MachineFunction &MF);
298 
299   void mappingImpl(yaml::IO &YamlIO) override;
300   ~SIMachineFunctionInfo() = default;
301 };
302 
303 template <> struct MappingTraits<SIMachineFunctionInfo> {
304   static void mapping(IO &YamlIO, SIMachineFunctionInfo &MFI) {
305     YamlIO.mapOptional("explicitKernArgSize", MFI.ExplicitKernArgSize,
306                        UINT64_C(0));
307     YamlIO.mapOptional("maxKernArgAlign", MFI.MaxKernArgAlign, 0u);
308     YamlIO.mapOptional("ldsSize", MFI.LDSSize, 0u);
309     YamlIO.mapOptional("dynLDSAlign", MFI.DynLDSAlign, Align());
310     YamlIO.mapOptional("isEntryFunction", MFI.IsEntryFunction, false);
311     YamlIO.mapOptional("noSignedZerosFPMath", MFI.NoSignedZerosFPMath, false);
312     YamlIO.mapOptional("memoryBound", MFI.MemoryBound, false);
313     YamlIO.mapOptional("waveLimiter", MFI.WaveLimiter, false);
314     YamlIO.mapOptional("hasSpilledSGPRs", MFI.HasSpilledSGPRs, false);
315     YamlIO.mapOptional("hasSpilledVGPRs", MFI.HasSpilledVGPRs, false);
316     YamlIO.mapOptional("scratchRSrcReg", MFI.ScratchRSrcReg,
317                        StringValue("$private_rsrc_reg"));
318     YamlIO.mapOptional("frameOffsetReg", MFI.FrameOffsetReg,
319                        StringValue("$fp_reg"));
320     YamlIO.mapOptional("stackPtrOffsetReg", MFI.StackPtrOffsetReg,
321                        StringValue("$sp_reg"));
322     YamlIO.mapOptional("argumentInfo", MFI.ArgInfo);
323     YamlIO.mapOptional("mode", MFI.Mode, SIMode());
324     YamlIO.mapOptional("highBitsOf32BitAddress",
325                        MFI.HighBitsOf32BitAddress, 0u);
326     YamlIO.mapOptional("occupancy", MFI.Occupancy, 0);
327     YamlIO.mapOptional("scavengeFI", MFI.ScavengeFI);
328   }
329 };
330 
331 } // end namespace yaml
332 
333 /// This class keeps track of the SPI_SP_INPUT_ADDR config register, which
334 /// tells the hardware which interpolation parameters to load.
335 class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
336   friend class GCNTargetMachine;
337 
338   Register TIDReg = AMDGPU::NoRegister;
339 
340   // Registers that may be reserved for spilling purposes. These may be the same
341   // as the input registers.
342   Register ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG;
343 
344   // This is the the unswizzled offset from the current dispatch's scratch wave
345   // base to the beginning of the current function's frame.
346   Register FrameOffsetReg = AMDGPU::FP_REG;
347 
348   // This is an ABI register used in the non-entry calling convention to
349   // communicate the unswizzled offset from the current dispatch's scratch wave
350   // base to the beginning of the new function's frame.
351   Register StackPtrOffsetReg = AMDGPU::SP_REG;
352 
353   AMDGPUFunctionArgInfo ArgInfo;
354 
355   // Graphics info.
356   unsigned PSInputAddr = 0;
357   unsigned PSInputEnable = 0;
358 
359   /// Number of bytes of arguments this function has on the stack. If the callee
360   /// is expected to restore the argument stack this should be a multiple of 16,
361   /// all usable during a tail call.
362   ///
363   /// The alternative would forbid tail call optimisation in some cases: if we
364   /// want to transfer control from a function with 8-bytes of stack-argument
365   /// space to a function with 16-bytes then misalignment of this value would
366   /// make a stack adjustment necessary, which could not be undone by the
367   /// callee.
368   unsigned BytesInStackArgArea = 0;
369 
370   bool ReturnsVoid = true;
371 
372   // A pair of default/requested minimum/maximum flat work group sizes.
373   // Minimum - first, maximum - second.
374   std::pair<unsigned, unsigned> FlatWorkGroupSizes = {0, 0};
375 
376   // A pair of default/requested minimum/maximum number of waves per execution
377   // unit. Minimum - first, maximum - second.
378   std::pair<unsigned, unsigned> WavesPerEU = {0, 0};
379 
380   std::unique_ptr<const AMDGPUBufferPseudoSourceValue> BufferPSV;
381   std::unique_ptr<const AMDGPUImagePseudoSourceValue> ImagePSV;
382   std::unique_ptr<const AMDGPUGWSResourcePseudoSourceValue> GWSResourcePSV;
383 
384 private:
385   unsigned LDSWaveSpillSize = 0;
386   unsigned NumUserSGPRs = 0;
387   unsigned NumSystemSGPRs = 0;
388 
389   bool HasSpilledSGPRs = false;
390   bool HasSpilledVGPRs = false;
391   bool HasNonSpillStackObjects = false;
392   bool IsStackRealigned = false;
393 
394   unsigned NumSpilledSGPRs = 0;
395   unsigned NumSpilledVGPRs = 0;
396 
397   // Feature bits required for inputs passed in user SGPRs.
398   bool PrivateSegmentBuffer : 1;
399   bool DispatchPtr : 1;
400   bool QueuePtr : 1;
401   bool KernargSegmentPtr : 1;
402   bool DispatchID : 1;
403   bool FlatScratchInit : 1;
404 
405   // Feature bits required for inputs passed in system SGPRs.
406   bool WorkGroupIDX : 1; // Always initialized.
407   bool WorkGroupIDY : 1;
408   bool WorkGroupIDZ : 1;
409   bool WorkGroupInfo : 1;
410   bool PrivateSegmentWaveByteOffset : 1;
411 
412   bool WorkItemIDX : 1; // Always initialized.
413   bool WorkItemIDY : 1;
414   bool WorkItemIDZ : 1;
415 
416   // Private memory buffer
417   // Compute directly in sgpr[0:1]
418   // Other shaders indirect 64-bits at sgpr[0:1]
419   bool ImplicitBufferPtr : 1;
420 
421   // Pointer to where the ABI inserts special kernel arguments separate from the
422   // user arguments. This is an offset from the KernargSegmentPtr.
423   bool ImplicitArgPtr : 1;
424   bool HostcallPtr : 1;
425 
426   bool MayNeedAGPRs : 1;
427 
428   // The hard-wired high half of the address of the global information table
429   // for AMDPAL OS type. 0xffffffff represents no hard-wired high half, since
430   // current hardware only allows a 16 bit value.
431   unsigned GITPtrHigh;
432 
433   unsigned HighBitsOf32BitAddress;
434   unsigned GDSSize;
435 
436   // Current recorded maximum possible occupancy.
437   unsigned Occupancy;
438 
439   mutable Optional<bool> UsesAGPRs;
440 
441   MCPhysReg getNextUserSGPR() const;
442 
443   MCPhysReg getNextSystemSGPR() const;
444 
445 public:
446   struct SpilledReg {
447     Register VGPR;
448     int Lane = -1;
449 
450     SpilledReg() = default;
451     SpilledReg(Register R, int L) : VGPR (R), Lane (L) {}
452 
453     bool hasLane() { return Lane != -1;}
454     bool hasReg() { return VGPR != 0;}
455   };
456 
457   struct SGPRSpillVGPR {
458     // VGPR used for SGPR spills
459     Register VGPR;
460 
461     // If the VGPR is is used for SGPR spills in a non-entrypoint function, the
462     // stack slot used to save/restore it in the prolog/epilog.
463     Optional<int> FI;
464 
465     SGPRSpillVGPR(Register V, Optional<int> F) : VGPR(V), FI(F) {}
466   };
467 
468   struct VGPRSpillToAGPR {
469     SmallVector<MCPhysReg, 32> Lanes;
470     bool FullyAllocated = false;
471     bool IsDead = false;
472   };
473 
474   // Map WWM VGPR to a stack slot that is used to save/restore it in the
475   // prolog/epilog.
476   MapVector<Register, Optional<int>> WWMReservedRegs;
477 
478 private:
479   // Track VGPR + wave index for each subregister of the SGPR spilled to
480   // frameindex key.
481   DenseMap<int, std::vector<SpilledReg>> SGPRToVGPRSpills;
482   unsigned NumVGPRSpillLanes = 0;
483   SmallVector<SGPRSpillVGPR, 2> SpillVGPRs;
484 
485   DenseMap<int, VGPRSpillToAGPR> VGPRToAGPRSpills;
486 
487   // AGPRs used for VGPR spills.
488   SmallVector<MCPhysReg, 32> SpillAGPR;
489 
490   // VGPRs used for AGPR spills.
491   SmallVector<MCPhysReg, 32> SpillVGPR;
492 
493   // Emergency stack slot. Sometimes, we create this before finalizing the stack
494   // frame, so save it here and add it to the RegScavenger later.
495   Optional<int> ScavengeFI;
496 
497 public: // FIXME
498   /// If this is set, an SGPR used for save/restore of the register used for the
499   /// frame pointer.
500   Register SGPRForFPSaveRestoreCopy;
501   Optional<int> FramePointerSaveIndex;
502 
503   /// If this is set, an SGPR used for save/restore of the register used for the
504   /// base pointer.
505   Register SGPRForBPSaveRestoreCopy;
506   Optional<int> BasePointerSaveIndex;
507 
508   bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg);
509 
510 public:
511   SIMachineFunctionInfo(const MachineFunction &MF);
512 
513   bool initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI,
514                                 const MachineFunction &MF,
515                                 PerFunctionMIParsingState &PFS,
516                                 SMDiagnostic &Error, SMRange &SourceRange);
517 
518   void reserveWWMRegister(Register Reg, Optional<int> FI) {
519     WWMReservedRegs.insert(std::make_pair(Reg, FI));
520   }
521 
522   ArrayRef<SpilledReg> getSGPRToVGPRSpills(int FrameIndex) const {
523     auto I = SGPRToVGPRSpills.find(FrameIndex);
524     return (I == SGPRToVGPRSpills.end()) ?
525       ArrayRef<SpilledReg>() : makeArrayRef(I->second);
526   }
527 
528   ArrayRef<SGPRSpillVGPR> getSGPRSpillVGPRs() const { return SpillVGPRs; }
529 
530   void setSGPRSpillVGPRs(Register NewVGPR, Optional<int> newFI, int Index) {
531     SpillVGPRs[Index].VGPR = NewVGPR;
532     SpillVGPRs[Index].FI = newFI;
533   }
534 
535   bool removeVGPRForSGPRSpill(Register ReservedVGPR, MachineFunction &MF);
536 
537   ArrayRef<MCPhysReg> getAGPRSpillVGPRs() const {
538     return SpillAGPR;
539   }
540 
541   ArrayRef<MCPhysReg> getVGPRSpillAGPRs() const {
542     return SpillVGPR;
543   }
544 
545   MCPhysReg getVGPRToAGPRSpill(int FrameIndex, unsigned Lane) const {
546     auto I = VGPRToAGPRSpills.find(FrameIndex);
547     return (I == VGPRToAGPRSpills.end()) ? (MCPhysReg)AMDGPU::NoRegister
548                                          : I->second.Lanes[Lane];
549   }
550 
551   void setVGPRToAGPRSpillDead(int FrameIndex) {
552     auto I = VGPRToAGPRSpills.find(FrameIndex);
553     if (I != VGPRToAGPRSpills.end())
554       I->second.IsDead = true;
555   }
556 
557   bool haveFreeLanesForSGPRSpill(const MachineFunction &MF,
558                                  unsigned NumLane) const;
559   bool allocateSGPRSpillToVGPR(MachineFunction &MF, int FI);
560   bool allocateVGPRSpillToAGPR(MachineFunction &MF, int FI, bool isAGPRtoVGPR);
561 
562   /// If \p ResetSGPRSpillStackIDs is true, reset the stack ID from sgpr-spill
563   /// to the default stack.
564   bool removeDeadFrameIndices(MachineFrameInfo &MFI,
565                               bool ResetSGPRSpillStackIDs);
566 
567   int getScavengeFI(MachineFrameInfo &MFI, const SIRegisterInfo &TRI);
568   Optional<int> getOptionalScavengeFI() const { return ScavengeFI; }
569 
570   bool hasCalculatedTID() const { return TIDReg != 0; };
571   Register getTIDReg() const { return TIDReg; };
572   void setTIDReg(Register Reg) { TIDReg = Reg; }
573 
574   unsigned getBytesInStackArgArea() const {
575     return BytesInStackArgArea;
576   }
577 
578   void setBytesInStackArgArea(unsigned Bytes) {
579     BytesInStackArgArea = Bytes;
580   }
581 
582   // Add user SGPRs.
583   Register addPrivateSegmentBuffer(const SIRegisterInfo &TRI);
584   Register addDispatchPtr(const SIRegisterInfo &TRI);
585   Register addQueuePtr(const SIRegisterInfo &TRI);
586   Register addKernargSegmentPtr(const SIRegisterInfo &TRI);
587   Register addDispatchID(const SIRegisterInfo &TRI);
588   Register addFlatScratchInit(const SIRegisterInfo &TRI);
589   Register addImplicitBufferPtr(const SIRegisterInfo &TRI);
590 
591   // Add system SGPRs.
592   Register addWorkGroupIDX() {
593     ArgInfo.WorkGroupIDX = ArgDescriptor::createRegister(getNextSystemSGPR());
594     NumSystemSGPRs += 1;
595     return ArgInfo.WorkGroupIDX.getRegister();
596   }
597 
598   Register addWorkGroupIDY() {
599     ArgInfo.WorkGroupIDY = ArgDescriptor::createRegister(getNextSystemSGPR());
600     NumSystemSGPRs += 1;
601     return ArgInfo.WorkGroupIDY.getRegister();
602   }
603 
604   Register addWorkGroupIDZ() {
605     ArgInfo.WorkGroupIDZ = ArgDescriptor::createRegister(getNextSystemSGPR());
606     NumSystemSGPRs += 1;
607     return ArgInfo.WorkGroupIDZ.getRegister();
608   }
609 
610   Register addWorkGroupInfo() {
611     ArgInfo.WorkGroupInfo = ArgDescriptor::createRegister(getNextSystemSGPR());
612     NumSystemSGPRs += 1;
613     return ArgInfo.WorkGroupInfo.getRegister();
614   }
615 
616   // Add special VGPR inputs
617   void setWorkItemIDX(ArgDescriptor Arg) {
618     ArgInfo.WorkItemIDX = Arg;
619   }
620 
621   void setWorkItemIDY(ArgDescriptor Arg) {
622     ArgInfo.WorkItemIDY = Arg;
623   }
624 
625   void setWorkItemIDZ(ArgDescriptor Arg) {
626     ArgInfo.WorkItemIDZ = Arg;
627   }
628 
629   Register addPrivateSegmentWaveByteOffset() {
630     ArgInfo.PrivateSegmentWaveByteOffset
631       = ArgDescriptor::createRegister(getNextSystemSGPR());
632     NumSystemSGPRs += 1;
633     return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
634   }
635 
636   void setPrivateSegmentWaveByteOffset(Register Reg) {
637     ArgInfo.PrivateSegmentWaveByteOffset = ArgDescriptor::createRegister(Reg);
638   }
639 
640   bool hasPrivateSegmentBuffer() const {
641     return PrivateSegmentBuffer;
642   }
643 
644   bool hasDispatchPtr() const {
645     return DispatchPtr;
646   }
647 
648   bool hasQueuePtr() const {
649     return QueuePtr;
650   }
651 
652   bool hasKernargSegmentPtr() const {
653     return KernargSegmentPtr;
654   }
655 
656   bool hasDispatchID() const {
657     return DispatchID;
658   }
659 
660   bool hasFlatScratchInit() const {
661     return FlatScratchInit;
662   }
663 
664   bool hasWorkGroupIDX() const {
665     return WorkGroupIDX;
666   }
667 
668   bool hasWorkGroupIDY() const {
669     return WorkGroupIDY;
670   }
671 
672   bool hasWorkGroupIDZ() const {
673     return WorkGroupIDZ;
674   }
675 
676   bool hasWorkGroupInfo() const {
677     return WorkGroupInfo;
678   }
679 
680   bool hasPrivateSegmentWaveByteOffset() const {
681     return PrivateSegmentWaveByteOffset;
682   }
683 
684   bool hasWorkItemIDX() const {
685     return WorkItemIDX;
686   }
687 
688   bool hasWorkItemIDY() const {
689     return WorkItemIDY;
690   }
691 
692   bool hasWorkItemIDZ() const {
693     return WorkItemIDZ;
694   }
695 
696   bool hasImplicitArgPtr() const {
697     return ImplicitArgPtr;
698   }
699 
700   bool hasHostcallPtr() const {
701     return HostcallPtr;
702   }
703 
704   bool hasImplicitBufferPtr() const {
705     return ImplicitBufferPtr;
706   }
707 
708   AMDGPUFunctionArgInfo &getArgInfo() {
709     return ArgInfo;
710   }
711 
712   const AMDGPUFunctionArgInfo &getArgInfo() const {
713     return ArgInfo;
714   }
715 
716   std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
717   getPreloadedValue(AMDGPUFunctionArgInfo::PreloadedValue Value) const {
718     return ArgInfo.getPreloadedValue(Value);
719   }
720 
721   MCRegister getPreloadedReg(AMDGPUFunctionArgInfo::PreloadedValue Value) const {
722     auto Arg = std::get<0>(ArgInfo.getPreloadedValue(Value));
723     return Arg ? Arg->getRegister() : MCRegister();
724   }
725 
726   unsigned getGITPtrHigh() const {
727     return GITPtrHigh;
728   }
729 
730   Register getGITPtrLoReg(const MachineFunction &MF) const;
731 
732   uint32_t get32BitAddressHighBits() const {
733     return HighBitsOf32BitAddress;
734   }
735 
736   unsigned getGDSSize() const {
737     return GDSSize;
738   }
739 
740   unsigned getNumUserSGPRs() const {
741     return NumUserSGPRs;
742   }
743 
744   unsigned getNumPreloadedSGPRs() const {
745     return NumUserSGPRs + NumSystemSGPRs;
746   }
747 
748   Register getPrivateSegmentWaveByteOffsetSystemSGPR() const {
749     return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
750   }
751 
752   /// Returns the physical register reserved for use as the resource
753   /// descriptor for scratch accesses.
754   Register getScratchRSrcReg() const {
755     return ScratchRSrcReg;
756   }
757 
758   void setScratchRSrcReg(Register Reg) {
759     assert(Reg != 0 && "Should never be unset");
760     ScratchRSrcReg = Reg;
761   }
762 
763   Register getFrameOffsetReg() const {
764     return FrameOffsetReg;
765   }
766 
767   void setFrameOffsetReg(Register Reg) {
768     assert(Reg != 0 && "Should never be unset");
769     FrameOffsetReg = Reg;
770   }
771 
772   void setStackPtrOffsetReg(Register Reg) {
773     assert(Reg != 0 && "Should never be unset");
774     StackPtrOffsetReg = Reg;
775   }
776 
777   // Note the unset value for this is AMDGPU::SP_REG rather than
778   // NoRegister. This is mostly a workaround for MIR tests where state that
779   // can't be directly computed from the function is not preserved in serialized
780   // MIR.
781   Register getStackPtrOffsetReg() const {
782     return StackPtrOffsetReg;
783   }
784 
785   Register getQueuePtrUserSGPR() const {
786     return ArgInfo.QueuePtr.getRegister();
787   }
788 
789   Register getImplicitBufferPtrUserSGPR() const {
790     return ArgInfo.ImplicitBufferPtr.getRegister();
791   }
792 
793   bool hasSpilledSGPRs() const {
794     return HasSpilledSGPRs;
795   }
796 
797   void setHasSpilledSGPRs(bool Spill = true) {
798     HasSpilledSGPRs = Spill;
799   }
800 
801   bool hasSpilledVGPRs() const {
802     return HasSpilledVGPRs;
803   }
804 
805   void setHasSpilledVGPRs(bool Spill = true) {
806     HasSpilledVGPRs = Spill;
807   }
808 
809   bool hasNonSpillStackObjects() const {
810     return HasNonSpillStackObjects;
811   }
812 
813   void setHasNonSpillStackObjects(bool StackObject = true) {
814     HasNonSpillStackObjects = StackObject;
815   }
816 
817   bool isStackRealigned() const {
818     return IsStackRealigned;
819   }
820 
821   void setIsStackRealigned(bool Realigned = true) {
822     IsStackRealigned = Realigned;
823   }
824 
825   unsigned getNumSpilledSGPRs() const {
826     return NumSpilledSGPRs;
827   }
828 
829   unsigned getNumSpilledVGPRs() const {
830     return NumSpilledVGPRs;
831   }
832 
833   void addToSpilledSGPRs(unsigned num) {
834     NumSpilledSGPRs += num;
835   }
836 
837   void addToSpilledVGPRs(unsigned num) {
838     NumSpilledVGPRs += num;
839   }
840 
841   unsigned getPSInputAddr() const {
842     return PSInputAddr;
843   }
844 
845   unsigned getPSInputEnable() const {
846     return PSInputEnable;
847   }
848 
849   bool isPSInputAllocated(unsigned Index) const {
850     return PSInputAddr & (1 << Index);
851   }
852 
853   void markPSInputAllocated(unsigned Index) {
854     PSInputAddr |= 1 << Index;
855   }
856 
857   void markPSInputEnabled(unsigned Index) {
858     PSInputEnable |= 1 << Index;
859   }
860 
861   bool returnsVoid() const {
862     return ReturnsVoid;
863   }
864 
865   void setIfReturnsVoid(bool Value) {
866     ReturnsVoid = Value;
867   }
868 
869   /// \returns A pair of default/requested minimum/maximum flat work group sizes
870   /// for this function.
871   std::pair<unsigned, unsigned> getFlatWorkGroupSizes() const {
872     return FlatWorkGroupSizes;
873   }
874 
875   /// \returns Default/requested minimum flat work group size for this function.
876   unsigned getMinFlatWorkGroupSize() const {
877     return FlatWorkGroupSizes.first;
878   }
879 
880   /// \returns Default/requested maximum flat work group size for this function.
881   unsigned getMaxFlatWorkGroupSize() const {
882     return FlatWorkGroupSizes.second;
883   }
884 
885   /// \returns A pair of default/requested minimum/maximum number of waves per
886   /// execution unit.
887   std::pair<unsigned, unsigned> getWavesPerEU() const {
888     return WavesPerEU;
889   }
890 
891   /// \returns Default/requested minimum number of waves per execution unit.
892   unsigned getMinWavesPerEU() const {
893     return WavesPerEU.first;
894   }
895 
896   /// \returns Default/requested maximum number of waves per execution unit.
897   unsigned getMaxWavesPerEU() const {
898     return WavesPerEU.second;
899   }
900 
901   /// \returns SGPR used for \p Dim's work group ID.
902   Register getWorkGroupIDSGPR(unsigned Dim) const {
903     switch (Dim) {
904     case 0:
905       assert(hasWorkGroupIDX());
906       return ArgInfo.WorkGroupIDX.getRegister();
907     case 1:
908       assert(hasWorkGroupIDY());
909       return ArgInfo.WorkGroupIDY.getRegister();
910     case 2:
911       assert(hasWorkGroupIDZ());
912       return ArgInfo.WorkGroupIDZ.getRegister();
913     }
914     llvm_unreachable("unexpected dimension");
915   }
916 
917   unsigned getLDSWaveSpillSize() const {
918     return LDSWaveSpillSize;
919   }
920 
921   const AMDGPUBufferPseudoSourceValue *getBufferPSV(const SIInstrInfo &TII) {
922     if (!BufferPSV)
923       BufferPSV = std::make_unique<AMDGPUBufferPseudoSourceValue>(TII);
924 
925     return BufferPSV.get();
926   }
927 
928   const AMDGPUImagePseudoSourceValue *getImagePSV(const SIInstrInfo &TII) {
929     if (!ImagePSV)
930       ImagePSV = std::make_unique<AMDGPUImagePseudoSourceValue>(TII);
931 
932     return ImagePSV.get();
933   }
934 
935   const AMDGPUGWSResourcePseudoSourceValue *getGWSPSV(const SIInstrInfo &TII) {
936     if (!GWSResourcePSV) {
937       GWSResourcePSV =
938           std::make_unique<AMDGPUGWSResourcePseudoSourceValue>(TII);
939     }
940 
941     return GWSResourcePSV.get();
942   }
943 
944   unsigned getOccupancy() const {
945     return Occupancy;
946   }
947 
948   unsigned getMinAllowedOccupancy() const {
949     if (!isMemoryBound() && !needsWaveLimiter())
950       return Occupancy;
951     return (Occupancy < 4) ? Occupancy : 4;
952   }
953 
954   void limitOccupancy(const MachineFunction &MF);
955 
956   void limitOccupancy(unsigned Limit) {
957     if (Occupancy > Limit)
958       Occupancy = Limit;
959   }
960 
961   void increaseOccupancy(const MachineFunction &MF, unsigned Limit) {
962     if (Occupancy < Limit)
963       Occupancy = Limit;
964     limitOccupancy(MF);
965   }
966 
967   bool mayNeedAGPRs() const {
968     return MayNeedAGPRs;
969   }
970 
971   // \returns true if a function has a use of AGPRs via inline asm or
972   // has a call which may use it.
973   bool mayUseAGPRs(const MachineFunction &MF) const;
974 
975   // \returns true if a function needs or may need AGPRs.
976   bool usesAGPRs(const MachineFunction &MF) const;
977 };
978 
979 } // end namespace llvm
980 
981 #endif // LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
982