xref: /llvm-project/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h (revision b7f44f7cf92b75f0dd4fb5e372990a25acfe908d) 
1 //==- SIMachineFunctionInfo.h - SIMachineFunctionInfo interface --*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
14 #define LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
15 
16 #include "AMDGPUArgumentUsageInfo.h"
17 #include "AMDGPUMachineFunction.h"
18 #include "AMDGPUTargetMachine.h"
19 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
20 #include "SIInstrInfo.h"
21 #include "llvm/ADT/SetVector.h"
22 #include "llvm/CodeGen/MIRYamlMapping.h"
23 #include "llvm/CodeGen/PseudoSourceValue.h"
24 #include "llvm/Support/raw_ostream.h"
25 
26 namespace llvm {
27 
28 class MachineFrameInfo;
29 class MachineFunction;
30 class SIMachineFunctionInfo;
31 class SIRegisterInfo;
32 class TargetRegisterClass;
33 
34 class AMDGPUPseudoSourceValue : public PseudoSourceValue {
35 public:
36   enum AMDGPUPSVKind : unsigned {
37     PSVImage = PseudoSourceValue::TargetCustom,
38     GWSResource
39   };
40 
41 protected:
42   AMDGPUPseudoSourceValue(unsigned Kind, const AMDGPUTargetMachine &TM)
43       : PseudoSourceValue(Kind, TM) {}
44 
45 public:
46   bool isConstant(const MachineFrameInfo *) const override {
47     // This should probably be true for most images, but we will start by being
48     // conservative.
49     return false;
50   }
51 
52   bool isAliased(const MachineFrameInfo *) const override {
53     return true;
54   }
55 
56   bool mayAlias(const MachineFrameInfo *) const override {
57     return true;
58   }
59 };
60 
61 class AMDGPUGWSResourcePseudoSourceValue final : public AMDGPUPseudoSourceValue {
62 public:
63   explicit AMDGPUGWSResourcePseudoSourceValue(const AMDGPUTargetMachine &TM)
64       : AMDGPUPseudoSourceValue(GWSResource, TM) {}
65 
66   static bool classof(const PseudoSourceValue *V) {
67     return V->kind() == GWSResource;
68   }
69 
70   // These are inaccessible memory from IR.
71   bool isAliased(const MachineFrameInfo *) const override {
72     return false;
73   }
74 
75   // These are inaccessible memory from IR.
76   bool mayAlias(const MachineFrameInfo *) const override {
77     return false;
78   }
79 
80   void printCustom(raw_ostream &OS) const override {
81     OS << "GWSResource";
82   }
83 };
84 
85 namespace yaml {
86 
87 struct SIArgument {
88   bool IsRegister;
89   union {
90     StringValue RegisterName;
91     unsigned StackOffset;
92   };
93   Optional<unsigned> Mask;
94 
95   // Default constructor, which creates a stack argument.
96   SIArgument() : IsRegister(false), StackOffset(0) {}
97   SIArgument(const SIArgument &Other) {
98     IsRegister = Other.IsRegister;
99     if (IsRegister) {
100       ::new ((void *)std::addressof(RegisterName))
101           StringValue(Other.RegisterName);
102     } else
103       StackOffset = Other.StackOffset;
104     Mask = Other.Mask;
105   }
106   SIArgument &operator=(const SIArgument &Other) {
107     IsRegister = Other.IsRegister;
108     if (IsRegister) {
109       ::new ((void *)std::addressof(RegisterName))
110           StringValue(Other.RegisterName);
111     } else
112       StackOffset = Other.StackOffset;
113     Mask = Other.Mask;
114     return *this;
115   }
116   ~SIArgument() {
117     if (IsRegister)
118       RegisterName.~StringValue();
119   }
120 
121   // Helper to create a register or stack argument.
122   static inline SIArgument createArgument(bool IsReg) {
123     if (IsReg)
124       return SIArgument(IsReg);
125     return SIArgument();
126   }
127 
128 private:
129   // Construct a register argument.
130   SIArgument(bool) : IsRegister(true), RegisterName() {}
131 };
132 
133 template <> struct MappingTraits<SIArgument> {
134   static void mapping(IO &YamlIO, SIArgument &A) {
135     if (YamlIO.outputting()) {
136       if (A.IsRegister)
137         YamlIO.mapRequired("reg", A.RegisterName);
138       else
139         YamlIO.mapRequired("offset", A.StackOffset);
140     } else {
141       auto Keys = YamlIO.keys();
142       if (is_contained(Keys, "reg")) {
143         A = SIArgument::createArgument(true);
144         YamlIO.mapRequired("reg", A.RegisterName);
145       } else if (is_contained(Keys, "offset"))
146         YamlIO.mapRequired("offset", A.StackOffset);
147       else
148         YamlIO.setError("missing required key 'reg' or 'offset'");
149     }
150     YamlIO.mapOptional("mask", A.Mask);
151   }
152   static const bool flow = true;
153 };
154 
155 struct SIArgumentInfo {
156   Optional<SIArgument> PrivateSegmentBuffer;
157   Optional<SIArgument> DispatchPtr;
158   Optional<SIArgument> QueuePtr;
159   Optional<SIArgument> KernargSegmentPtr;
160   Optional<SIArgument> DispatchID;
161   Optional<SIArgument> FlatScratchInit;
162   Optional<SIArgument> PrivateSegmentSize;
163 
164   Optional<SIArgument> WorkGroupIDX;
165   Optional<SIArgument> WorkGroupIDY;
166   Optional<SIArgument> WorkGroupIDZ;
167   Optional<SIArgument> WorkGroupInfo;
168   Optional<SIArgument> LDSKernelId;
169   Optional<SIArgument> PrivateSegmentWaveByteOffset;
170 
171   Optional<SIArgument> ImplicitArgPtr;
172   Optional<SIArgument> ImplicitBufferPtr;
173 
174   Optional<SIArgument> WorkItemIDX;
175   Optional<SIArgument> WorkItemIDY;
176   Optional<SIArgument> WorkItemIDZ;
177 };
178 
179 template <> struct MappingTraits<SIArgumentInfo> {
180   static void mapping(IO &YamlIO, SIArgumentInfo &AI) {
181     YamlIO.mapOptional("privateSegmentBuffer", AI.PrivateSegmentBuffer);
182     YamlIO.mapOptional("dispatchPtr", AI.DispatchPtr);
183     YamlIO.mapOptional("queuePtr", AI.QueuePtr);
184     YamlIO.mapOptional("kernargSegmentPtr", AI.KernargSegmentPtr);
185     YamlIO.mapOptional("dispatchID", AI.DispatchID);
186     YamlIO.mapOptional("flatScratchInit", AI.FlatScratchInit);
187     YamlIO.mapOptional("privateSegmentSize", AI.PrivateSegmentSize);
188 
189     YamlIO.mapOptional("workGroupIDX", AI.WorkGroupIDX);
190     YamlIO.mapOptional("workGroupIDY", AI.WorkGroupIDY);
191     YamlIO.mapOptional("workGroupIDZ", AI.WorkGroupIDZ);
192     YamlIO.mapOptional("workGroupInfo", AI.WorkGroupInfo);
193     YamlIO.mapOptional("LDSKernelId", AI.LDSKernelId);
194     YamlIO.mapOptional("privateSegmentWaveByteOffset",
195                        AI.PrivateSegmentWaveByteOffset);
196 
197     YamlIO.mapOptional("implicitArgPtr", AI.ImplicitArgPtr);
198     YamlIO.mapOptional("implicitBufferPtr", AI.ImplicitBufferPtr);
199 
200     YamlIO.mapOptional("workItemIDX", AI.WorkItemIDX);
201     YamlIO.mapOptional("workItemIDY", AI.WorkItemIDY);
202     YamlIO.mapOptional("workItemIDZ", AI.WorkItemIDZ);
203   }
204 };
205 
206 // Default to default mode for default calling convention.
207 struct SIMode {
208   bool IEEE = true;
209   bool DX10Clamp = true;
210   bool FP32InputDenormals = true;
211   bool FP32OutputDenormals = true;
212   bool FP64FP16InputDenormals = true;
213   bool FP64FP16OutputDenormals = true;
214 
215   SIMode() = default;
216 
217   SIMode(const AMDGPU::SIModeRegisterDefaults &Mode) {
218     IEEE = Mode.IEEE;
219     DX10Clamp = Mode.DX10Clamp;
220     FP32InputDenormals = Mode.FP32InputDenormals;
221     FP32OutputDenormals = Mode.FP32OutputDenormals;
222     FP64FP16InputDenormals = Mode.FP64FP16InputDenormals;
223     FP64FP16OutputDenormals = Mode.FP64FP16OutputDenormals;
224   }
225 
226   bool operator ==(const SIMode Other) const {
227     return IEEE == Other.IEEE &&
228            DX10Clamp == Other.DX10Clamp &&
229            FP32InputDenormals == Other.FP32InputDenormals &&
230            FP32OutputDenormals == Other.FP32OutputDenormals &&
231            FP64FP16InputDenormals == Other.FP64FP16InputDenormals &&
232            FP64FP16OutputDenormals == Other.FP64FP16OutputDenormals;
233   }
234 };
235 
236 template <> struct MappingTraits<SIMode> {
237   static void mapping(IO &YamlIO, SIMode &Mode) {
238     YamlIO.mapOptional("ieee", Mode.IEEE, true);
239     YamlIO.mapOptional("dx10-clamp", Mode.DX10Clamp, true);
240     YamlIO.mapOptional("fp32-input-denormals", Mode.FP32InputDenormals, true);
241     YamlIO.mapOptional("fp32-output-denormals", Mode.FP32OutputDenormals, true);
242     YamlIO.mapOptional("fp64-fp16-input-denormals", Mode.FP64FP16InputDenormals, true);
243     YamlIO.mapOptional("fp64-fp16-output-denormals", Mode.FP64FP16OutputDenormals, true);
244   }
245 };
246 
247 struct SIMachineFunctionInfo final : public yaml::MachineFunctionInfo {
248   uint64_t ExplicitKernArgSize = 0;
249   Align MaxKernArgAlign;
250   uint32_t LDSSize = 0;
251   uint32_t GDSSize = 0;
252   Align DynLDSAlign;
253   bool IsEntryFunction = false;
254   bool NoSignedZerosFPMath = false;
255   bool MemoryBound = false;
256   bool WaveLimiter = false;
257   bool HasSpilledSGPRs = false;
258   bool HasSpilledVGPRs = false;
259   uint32_t HighBitsOf32BitAddress = 0;
260 
261   // TODO: 10 may be a better default since it's the maximum.
262   unsigned Occupancy = 0;
263 
264   SmallVector<StringValue> WWMReservedRegs;
265 
266   StringValue ScratchRSrcReg = "$private_rsrc_reg";
267   StringValue FrameOffsetReg = "$fp_reg";
268   StringValue StackPtrOffsetReg = "$sp_reg";
269 
270   unsigned BytesInStackArgArea = 0;
271   bool ReturnsVoid = true;
272 
273   Optional<SIArgumentInfo> ArgInfo;
274   SIMode Mode;
275   Optional<FrameIndex> ScavengeFI;
276   StringValue VGPRForAGPRCopy;
277 
278   SIMachineFunctionInfo() = default;
279   SIMachineFunctionInfo(const llvm::SIMachineFunctionInfo &,
280                         const TargetRegisterInfo &TRI,
281                         const llvm::MachineFunction &MF);
282 
283   void mappingImpl(yaml::IO &YamlIO) override;
284   ~SIMachineFunctionInfo() = default;
285 };
286 
287 template <> struct MappingTraits<SIMachineFunctionInfo> {
288   static void mapping(IO &YamlIO, SIMachineFunctionInfo &MFI) {
289     YamlIO.mapOptional("explicitKernArgSize", MFI.ExplicitKernArgSize,
290                        UINT64_C(0));
291     YamlIO.mapOptional("maxKernArgAlign", MFI.MaxKernArgAlign);
292     YamlIO.mapOptional("ldsSize", MFI.LDSSize, 0u);
293     YamlIO.mapOptional("gdsSize", MFI.GDSSize, 0u);
294     YamlIO.mapOptional("dynLDSAlign", MFI.DynLDSAlign, Align());
295     YamlIO.mapOptional("isEntryFunction", MFI.IsEntryFunction, false);
296     YamlIO.mapOptional("noSignedZerosFPMath", MFI.NoSignedZerosFPMath, false);
297     YamlIO.mapOptional("memoryBound", MFI.MemoryBound, false);
298     YamlIO.mapOptional("waveLimiter", MFI.WaveLimiter, false);
299     YamlIO.mapOptional("hasSpilledSGPRs", MFI.HasSpilledSGPRs, false);
300     YamlIO.mapOptional("hasSpilledVGPRs", MFI.HasSpilledVGPRs, false);
301     YamlIO.mapOptional("scratchRSrcReg", MFI.ScratchRSrcReg,
302                        StringValue("$private_rsrc_reg"));
303     YamlIO.mapOptional("frameOffsetReg", MFI.FrameOffsetReg,
304                        StringValue("$fp_reg"));
305     YamlIO.mapOptional("stackPtrOffsetReg", MFI.StackPtrOffsetReg,
306                        StringValue("$sp_reg"));
307     YamlIO.mapOptional("bytesInStackArgArea", MFI.BytesInStackArgArea, 0u);
308     YamlIO.mapOptional("returnsVoid", MFI.ReturnsVoid, true);
309     YamlIO.mapOptional("argumentInfo", MFI.ArgInfo);
310     YamlIO.mapOptional("mode", MFI.Mode, SIMode());
311     YamlIO.mapOptional("highBitsOf32BitAddress",
312                        MFI.HighBitsOf32BitAddress, 0u);
313     YamlIO.mapOptional("occupancy", MFI.Occupancy, 0);
314     YamlIO.mapOptional("wwmReservedRegs", MFI.WWMReservedRegs);
315     YamlIO.mapOptional("scavengeFI", MFI.ScavengeFI);
316     YamlIO.mapOptional("vgprForAGPRCopy", MFI.VGPRForAGPRCopy,
317                        StringValue()); // Don't print out when it's empty.
318   }
319 };
320 
321 } // end namespace yaml
322 
323 /// This class keeps track of the SPI_SP_INPUT_ADDR config register, which
324 /// tells the hardware which interpolation parameters to load.
325 class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
326   friend class GCNTargetMachine;
327 
328   // State of MODE register, assumed FP mode.
329   AMDGPU::SIModeRegisterDefaults Mode;
330 
331   // Registers that may be reserved for spilling purposes. These may be the same
332   // as the input registers.
333   Register ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG;
334 
335   // This is the unswizzled offset from the current dispatch's scratch wave
336   // base to the beginning of the current function's frame.
337   Register FrameOffsetReg = AMDGPU::FP_REG;
338 
339   // This is an ABI register used in the non-entry calling convention to
340   // communicate the unswizzled offset from the current dispatch's scratch wave
341   // base to the beginning of the new function's frame.
342   Register StackPtrOffsetReg = AMDGPU::SP_REG;
343 
344   AMDGPUFunctionArgInfo ArgInfo;
345 
346   // Graphics info.
347   unsigned PSInputAddr = 0;
348   unsigned PSInputEnable = 0;
349 
350   /// Number of bytes of arguments this function has on the stack. If the callee
351   /// is expected to restore the argument stack this should be a multiple of 16,
352   /// all usable during a tail call.
353   ///
354   /// The alternative would forbid tail call optimisation in some cases: if we
355   /// want to transfer control from a function with 8-bytes of stack-argument
356   /// space to a function with 16-bytes then misalignment of this value would
357   /// make a stack adjustment necessary, which could not be undone by the
358   /// callee.
359   unsigned BytesInStackArgArea = 0;
360 
361   bool ReturnsVoid = true;
362 
363   // A pair of default/requested minimum/maximum flat work group sizes.
364   // Minimum - first, maximum - second.
365   std::pair<unsigned, unsigned> FlatWorkGroupSizes = {0, 0};
366 
367   // A pair of default/requested minimum/maximum number of waves per execution
368   // unit. Minimum - first, maximum - second.
369   std::pair<unsigned, unsigned> WavesPerEU = {0, 0};
370 
371   const AMDGPUGWSResourcePseudoSourceValue GWSResourcePSV;
372 
373 private:
374   unsigned NumUserSGPRs = 0;
375   unsigned NumSystemSGPRs = 0;
376 
377   bool HasSpilledSGPRs = false;
378   bool HasSpilledVGPRs = false;
379   bool HasNonSpillStackObjects = false;
380   bool IsStackRealigned = false;
381 
382   unsigned NumSpilledSGPRs = 0;
383   unsigned NumSpilledVGPRs = 0;
384 
385   // Feature bits required for inputs passed in user SGPRs.
386   bool PrivateSegmentBuffer : 1;
387   bool DispatchPtr : 1;
388   bool QueuePtr : 1;
389   bool KernargSegmentPtr : 1;
390   bool DispatchID : 1;
391   bool FlatScratchInit : 1;
392 
393   // Feature bits required for inputs passed in system SGPRs.
394   bool WorkGroupIDX : 1; // Always initialized.
395   bool WorkGroupIDY : 1;
396   bool WorkGroupIDZ : 1;
397   bool WorkGroupInfo : 1;
398   bool LDSKernelId : 1;
399   bool PrivateSegmentWaveByteOffset : 1;
400 
401   bool WorkItemIDX : 1; // Always initialized.
402   bool WorkItemIDY : 1;
403   bool WorkItemIDZ : 1;
404 
405   // Private memory buffer
406   // Compute directly in sgpr[0:1]
407   // Other shaders indirect 64-bits at sgpr[0:1]
408   bool ImplicitBufferPtr : 1;
409 
410   // Pointer to where the ABI inserts special kernel arguments separate from the
411   // user arguments. This is an offset from the KernargSegmentPtr.
412   bool ImplicitArgPtr : 1;
413 
414   bool MayNeedAGPRs : 1;
415 
416   // The hard-wired high half of the address of the global information table
417   // for AMDPAL OS type. 0xffffffff represents no hard-wired high half, since
418   // current hardware only allows a 16 bit value.
419   unsigned GITPtrHigh;
420 
421   unsigned HighBitsOf32BitAddress;
422 
423   // Current recorded maximum possible occupancy.
424   unsigned Occupancy;
425 
426   mutable Optional<bool> UsesAGPRs;
427 
428   MCPhysReg getNextUserSGPR() const;
429 
430   MCPhysReg getNextSystemSGPR() const;
431 
432 public:
433   struct SGPRSpillVGPR {
434     // VGPR used for SGPR spills
435     Register VGPR;
436 
437     // If the VGPR is used for SGPR spills in a non-entrypoint function, the
438     // stack slot used to save/restore it in the prolog/epilog.
439     Optional<int> FI;
440 
441     SGPRSpillVGPR(Register V, Optional<int> F) : VGPR(V), FI(F) {}
442   };
443 
444   struct VGPRSpillToAGPR {
445     SmallVector<MCPhysReg, 32> Lanes;
446     bool FullyAllocated = false;
447     bool IsDead = false;
448   };
449 
450   // Track VGPRs reserved for WWM.
451   SmallSetVector<Register, 8> WWMReservedRegs;
452 
453   /// Track stack slots used for save/restore of reserved WWM VGPRs in the
454   /// prolog/epilog.
455 
456   /// FIXME: This is temporary state only needed in PrologEpilogInserter, and
457   /// doesn't really belong here. It does not require serialization
458   SmallVector<int, 8> WWMReservedFrameIndexes;
459 
460   void allocateWWMReservedSpillSlots(MachineFrameInfo &MFI,
461                                      const SIRegisterInfo &TRI);
462 
463   auto wwmAllocation() const {
464     assert(WWMReservedRegs.size() == WWMReservedFrameIndexes.size());
465     return zip(WWMReservedRegs, WWMReservedFrameIndexes);
466   }
467 
468 private:
469   // Track VGPR + wave index for each subregister of the SGPR spilled to
470   // frameindex key.
471   DenseMap<int, std::vector<SIRegisterInfo::SpilledReg>> SGPRToVGPRSpills;
472   unsigned NumVGPRSpillLanes = 0;
473   SmallVector<SGPRSpillVGPR, 2> SpillVGPRs;
474 
475   DenseMap<int, VGPRSpillToAGPR> VGPRToAGPRSpills;
476 
477   // AGPRs used for VGPR spills.
478   SmallVector<MCPhysReg, 32> SpillAGPR;
479 
480   // VGPRs used for AGPR spills.
481   SmallVector<MCPhysReg, 32> SpillVGPR;
482 
483   // Emergency stack slot. Sometimes, we create this before finalizing the stack
484   // frame, so save it here and add it to the RegScavenger later.
485   Optional<int> ScavengeFI;
486 
487 private:
488   Register VGPRForAGPRCopy;
489 
490 public:
491   Register getVGPRForAGPRCopy() const {
492     return VGPRForAGPRCopy;
493   }
494 
495   void setVGPRForAGPRCopy(Register NewVGPRForAGPRCopy) {
496     VGPRForAGPRCopy = NewVGPRForAGPRCopy;
497   }
498 
499 public: // FIXME
500   /// If this is set, an SGPR used for save/restore of the register used for the
501   /// frame pointer.
502   Register SGPRForFPSaveRestoreCopy;
503   Optional<int> FramePointerSaveIndex;
504 
505   /// If this is set, an SGPR used for save/restore of the register used for the
506   /// base pointer.
507   Register SGPRForBPSaveRestoreCopy;
508   Optional<int> BasePointerSaveIndex;
509 
510   bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg);
511 
512 public:
513   SIMachineFunctionInfo(const MachineFunction &MF);
514   SIMachineFunctionInfo(const SIMachineFunctionInfo &MFI) = default;
515 
516   MachineFunctionInfo *
517   clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
518         const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
519       const override;
520 
521   bool initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI,
522                                 const MachineFunction &MF,
523                                 PerFunctionMIParsingState &PFS,
524                                 SMDiagnostic &Error, SMRange &SourceRange);
525 
526   void reserveWWMRegister(Register Reg) {
527     WWMReservedRegs.insert(Reg);
528   }
529 
530   AMDGPU::SIModeRegisterDefaults getMode() const {
531     return Mode;
532   }
533 
534   ArrayRef<SIRegisterInfo::SpilledReg>
535   getSGPRToVGPRSpills(int FrameIndex) const {
536     auto I = SGPRToVGPRSpills.find(FrameIndex);
537     return (I == SGPRToVGPRSpills.end())
538                ? ArrayRef<SIRegisterInfo::SpilledReg>()
539                : makeArrayRef(I->second);
540   }
541 
542   ArrayRef<SGPRSpillVGPR> getSGPRSpillVGPRs() const { return SpillVGPRs; }
543 
544   ArrayRef<MCPhysReg> getAGPRSpillVGPRs() const {
545     return SpillAGPR;
546   }
547 
548   ArrayRef<MCPhysReg> getVGPRSpillAGPRs() const {
549     return SpillVGPR;
550   }
551 
552   MCPhysReg getVGPRToAGPRSpill(int FrameIndex, unsigned Lane) const {
553     auto I = VGPRToAGPRSpills.find(FrameIndex);
554     return (I == VGPRToAGPRSpills.end()) ? (MCPhysReg)AMDGPU::NoRegister
555                                          : I->second.Lanes[Lane];
556   }
557 
558   void setVGPRToAGPRSpillDead(int FrameIndex) {
559     auto I = VGPRToAGPRSpills.find(FrameIndex);
560     if (I != VGPRToAGPRSpills.end())
561       I->second.IsDead = true;
562   }
563 
564   bool haveFreeLanesForSGPRSpill(const MachineFunction &MF,
565                                  unsigned NumLane) const;
566   bool allocateSGPRSpillToVGPR(MachineFunction &MF, int FI);
567   bool allocateVGPRSpillToAGPR(MachineFunction &MF, int FI, bool isAGPRtoVGPR);
568 
569   /// If \p ResetSGPRSpillStackIDs is true, reset the stack ID from sgpr-spill
570   /// to the default stack.
571   bool removeDeadFrameIndices(MachineFrameInfo &MFI,
572                               bool ResetSGPRSpillStackIDs);
573 
574   int getScavengeFI(MachineFrameInfo &MFI, const SIRegisterInfo &TRI);
575   Optional<int> getOptionalScavengeFI() const { return ScavengeFI; }
576 
577   unsigned getBytesInStackArgArea() const {
578     return BytesInStackArgArea;
579   }
580 
581   void setBytesInStackArgArea(unsigned Bytes) {
582     BytesInStackArgArea = Bytes;
583   }
584 
585   // Add user SGPRs.
586   Register addPrivateSegmentBuffer(const SIRegisterInfo &TRI);
587   Register addDispatchPtr(const SIRegisterInfo &TRI);
588   Register addQueuePtr(const SIRegisterInfo &TRI);
589   Register addKernargSegmentPtr(const SIRegisterInfo &TRI);
590   Register addDispatchID(const SIRegisterInfo &TRI);
591   Register addFlatScratchInit(const SIRegisterInfo &TRI);
592   Register addImplicitBufferPtr(const SIRegisterInfo &TRI);
593   Register addLDSKernelId();
594 
595   /// Increment user SGPRs used for padding the argument list only.
596   Register addReservedUserSGPR() {
597     Register Next = getNextUserSGPR();
598     ++NumUserSGPRs;
599     return Next;
600   }
601 
602   // Add system SGPRs.
603   Register addWorkGroupIDX() {
604     ArgInfo.WorkGroupIDX = ArgDescriptor::createRegister(getNextSystemSGPR());
605     NumSystemSGPRs += 1;
606     return ArgInfo.WorkGroupIDX.getRegister();
607   }
608 
609   Register addWorkGroupIDY() {
610     ArgInfo.WorkGroupIDY = ArgDescriptor::createRegister(getNextSystemSGPR());
611     NumSystemSGPRs += 1;
612     return ArgInfo.WorkGroupIDY.getRegister();
613   }
614 
615   Register addWorkGroupIDZ() {
616     ArgInfo.WorkGroupIDZ = ArgDescriptor::createRegister(getNextSystemSGPR());
617     NumSystemSGPRs += 1;
618     return ArgInfo.WorkGroupIDZ.getRegister();
619   }
620 
621   Register addWorkGroupInfo() {
622     ArgInfo.WorkGroupInfo = ArgDescriptor::createRegister(getNextSystemSGPR());
623     NumSystemSGPRs += 1;
624     return ArgInfo.WorkGroupInfo.getRegister();
625   }
626 
627   // Add special VGPR inputs
628   void setWorkItemIDX(ArgDescriptor Arg) {
629     ArgInfo.WorkItemIDX = Arg;
630   }
631 
632   void setWorkItemIDY(ArgDescriptor Arg) {
633     ArgInfo.WorkItemIDY = Arg;
634   }
635 
636   void setWorkItemIDZ(ArgDescriptor Arg) {
637     ArgInfo.WorkItemIDZ = Arg;
638   }
639 
640   Register addPrivateSegmentWaveByteOffset() {
641     ArgInfo.PrivateSegmentWaveByteOffset
642       = ArgDescriptor::createRegister(getNextSystemSGPR());
643     NumSystemSGPRs += 1;
644     return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
645   }
646 
647   void setPrivateSegmentWaveByteOffset(Register Reg) {
648     ArgInfo.PrivateSegmentWaveByteOffset = ArgDescriptor::createRegister(Reg);
649   }
650 
651   bool hasPrivateSegmentBuffer() const {
652     return PrivateSegmentBuffer;
653   }
654 
655   bool hasDispatchPtr() const {
656     return DispatchPtr;
657   }
658 
659   bool hasQueuePtr() const {
660     return QueuePtr;
661   }
662 
663   bool hasKernargSegmentPtr() const {
664     return KernargSegmentPtr;
665   }
666 
667   bool hasDispatchID() const {
668     return DispatchID;
669   }
670 
671   bool hasFlatScratchInit() const {
672     return FlatScratchInit;
673   }
674 
675   bool hasWorkGroupIDX() const {
676     return WorkGroupIDX;
677   }
678 
679   bool hasWorkGroupIDY() const {
680     return WorkGroupIDY;
681   }
682 
683   bool hasWorkGroupIDZ() const {
684     return WorkGroupIDZ;
685   }
686 
687   bool hasWorkGroupInfo() const {
688     return WorkGroupInfo;
689   }
690 
691   bool hasLDSKernelId() const { return LDSKernelId; }
692 
693   bool hasPrivateSegmentWaveByteOffset() const {
694     return PrivateSegmentWaveByteOffset;
695   }
696 
697   bool hasWorkItemIDX() const {
698     return WorkItemIDX;
699   }
700 
701   bool hasWorkItemIDY() const {
702     return WorkItemIDY;
703   }
704 
705   bool hasWorkItemIDZ() const {
706     return WorkItemIDZ;
707   }
708 
709   bool hasImplicitArgPtr() const {
710     return ImplicitArgPtr;
711   }
712 
713   bool hasImplicitBufferPtr() const {
714     return ImplicitBufferPtr;
715   }
716 
717   AMDGPUFunctionArgInfo &getArgInfo() {
718     return ArgInfo;
719   }
720 
721   const AMDGPUFunctionArgInfo &getArgInfo() const {
722     return ArgInfo;
723   }
724 
725   std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
726   getPreloadedValue(AMDGPUFunctionArgInfo::PreloadedValue Value) const {
727     return ArgInfo.getPreloadedValue(Value);
728   }
729 
730   MCRegister getPreloadedReg(AMDGPUFunctionArgInfo::PreloadedValue Value) const {
731     auto Arg = std::get<0>(ArgInfo.getPreloadedValue(Value));
732     return Arg ? Arg->getRegister() : MCRegister();
733   }
734 
735   unsigned getGITPtrHigh() const {
736     return GITPtrHigh;
737   }
738 
739   Register getGITPtrLoReg(const MachineFunction &MF) const;
740 
741   uint32_t get32BitAddressHighBits() const {
742     return HighBitsOf32BitAddress;
743   }
744 
745   unsigned getNumUserSGPRs() const {
746     return NumUserSGPRs;
747   }
748 
749   unsigned getNumPreloadedSGPRs() const {
750     return NumUserSGPRs + NumSystemSGPRs;
751   }
752 
753   Register getPrivateSegmentWaveByteOffsetSystemSGPR() const {
754     return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
755   }
756 
757   /// Returns the physical register reserved for use as the resource
758   /// descriptor for scratch accesses.
759   Register getScratchRSrcReg() const {
760     return ScratchRSrcReg;
761   }
762 
763   void setScratchRSrcReg(Register Reg) {
764     assert(Reg != 0 && "Should never be unset");
765     ScratchRSrcReg = Reg;
766   }
767 
768   Register getFrameOffsetReg() const {
769     return FrameOffsetReg;
770   }
771 
772   void setFrameOffsetReg(Register Reg) {
773     assert(Reg != 0 && "Should never be unset");
774     FrameOffsetReg = Reg;
775   }
776 
777   void setStackPtrOffsetReg(Register Reg) {
778     assert(Reg != 0 && "Should never be unset");
779     StackPtrOffsetReg = Reg;
780   }
781 
782   // Note the unset value for this is AMDGPU::SP_REG rather than
783   // NoRegister. This is mostly a workaround for MIR tests where state that
784   // can't be directly computed from the function is not preserved in serialized
785   // MIR.
786   Register getStackPtrOffsetReg() const {
787     return StackPtrOffsetReg;
788   }
789 
790   Register getQueuePtrUserSGPR() const {
791     return ArgInfo.QueuePtr.getRegister();
792   }
793 
794   Register getImplicitBufferPtrUserSGPR() const {
795     return ArgInfo.ImplicitBufferPtr.getRegister();
796   }
797 
798   bool hasSpilledSGPRs() const {
799     return HasSpilledSGPRs;
800   }
801 
802   void setHasSpilledSGPRs(bool Spill = true) {
803     HasSpilledSGPRs = Spill;
804   }
805 
806   bool hasSpilledVGPRs() const {
807     return HasSpilledVGPRs;
808   }
809 
810   void setHasSpilledVGPRs(bool Spill = true) {
811     HasSpilledVGPRs = Spill;
812   }
813 
814   bool hasNonSpillStackObjects() const {
815     return HasNonSpillStackObjects;
816   }
817 
818   void setHasNonSpillStackObjects(bool StackObject = true) {
819     HasNonSpillStackObjects = StackObject;
820   }
821 
822   bool isStackRealigned() const {
823     return IsStackRealigned;
824   }
825 
826   void setIsStackRealigned(bool Realigned = true) {
827     IsStackRealigned = Realigned;
828   }
829 
830   unsigned getNumSpilledSGPRs() const {
831     return NumSpilledSGPRs;
832   }
833 
834   unsigned getNumSpilledVGPRs() const {
835     return NumSpilledVGPRs;
836   }
837 
838   void addToSpilledSGPRs(unsigned num) {
839     NumSpilledSGPRs += num;
840   }
841 
842   void addToSpilledVGPRs(unsigned num) {
843     NumSpilledVGPRs += num;
844   }
845 
846   unsigned getPSInputAddr() const {
847     return PSInputAddr;
848   }
849 
850   unsigned getPSInputEnable() const {
851     return PSInputEnable;
852   }
853 
854   bool isPSInputAllocated(unsigned Index) const {
855     return PSInputAddr & (1 << Index);
856   }
857 
858   void markPSInputAllocated(unsigned Index) {
859     PSInputAddr |= 1 << Index;
860   }
861 
862   void markPSInputEnabled(unsigned Index) {
863     PSInputEnable |= 1 << Index;
864   }
865 
866   bool returnsVoid() const {
867     return ReturnsVoid;
868   }
869 
870   void setIfReturnsVoid(bool Value) {
871     ReturnsVoid = Value;
872   }
873 
874   /// \returns A pair of default/requested minimum/maximum flat work group sizes
875   /// for this function.
876   std::pair<unsigned, unsigned> getFlatWorkGroupSizes() const {
877     return FlatWorkGroupSizes;
878   }
879 
880   /// \returns Default/requested minimum flat work group size for this function.
881   unsigned getMinFlatWorkGroupSize() const {
882     return FlatWorkGroupSizes.first;
883   }
884 
885   /// \returns Default/requested maximum flat work group size for this function.
886   unsigned getMaxFlatWorkGroupSize() const {
887     return FlatWorkGroupSizes.second;
888   }
889 
890   /// \returns A pair of default/requested minimum/maximum number of waves per
891   /// execution unit.
892   std::pair<unsigned, unsigned> getWavesPerEU() const {
893     return WavesPerEU;
894   }
895 
896   /// \returns Default/requested minimum number of waves per execution unit.
897   unsigned getMinWavesPerEU() const {
898     return WavesPerEU.first;
899   }
900 
901   /// \returns Default/requested maximum number of waves per execution unit.
902   unsigned getMaxWavesPerEU() const {
903     return WavesPerEU.second;
904   }
905 
906   /// \returns SGPR used for \p Dim's work group ID.
907   Register getWorkGroupIDSGPR(unsigned Dim) const {
908     switch (Dim) {
909     case 0:
910       assert(hasWorkGroupIDX());
911       return ArgInfo.WorkGroupIDX.getRegister();
912     case 1:
913       assert(hasWorkGroupIDY());
914       return ArgInfo.WorkGroupIDY.getRegister();
915     case 2:
916       assert(hasWorkGroupIDZ());
917       return ArgInfo.WorkGroupIDZ.getRegister();
918     }
919     llvm_unreachable("unexpected dimension");
920   }
921 
922   const AMDGPUGWSResourcePseudoSourceValue *
923   getGWSPSV(const AMDGPUTargetMachine &TM) {
924     return &GWSResourcePSV;
925   }
926 
927   unsigned getOccupancy() const {
928     return Occupancy;
929   }
930 
931   unsigned getMinAllowedOccupancy() const {
932     if (!isMemoryBound() && !needsWaveLimiter())
933       return Occupancy;
934     return (Occupancy < 4) ? Occupancy : 4;
935   }
936 
937   void limitOccupancy(const MachineFunction &MF);
938 
939   void limitOccupancy(unsigned Limit) {
940     if (Occupancy > Limit)
941       Occupancy = Limit;
942   }
943 
944   void increaseOccupancy(const MachineFunction &MF, unsigned Limit) {
945     if (Occupancy < Limit)
946       Occupancy = Limit;
947     limitOccupancy(MF);
948   }
949 
950   bool mayNeedAGPRs() const {
951     return MayNeedAGPRs;
952   }
953 
954   // \returns true if a function has a use of AGPRs via inline asm or
955   // has a call which may use it.
956   bool mayUseAGPRs(const Function &F) const;
957 
958   // \returns true if a function needs or may need AGPRs.
959   bool usesAGPRs(const MachineFunction &MF) const;
960 };
961 
962 } // end namespace llvm
963 
964 #endif // LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
965