xref: /llvm-project/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h (revision 80177ca5a9b0731b62943e30c7d8f39e7664bb82) 
1 //==- SIMachineFunctionInfo.h - SIMachineFunctionInfo interface --*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
14 #define LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
15 
16 #include "AMDGPUArgumentUsageInfo.h"
17 #include "AMDGPUMachineFunction.h"
18 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
19 #include "SIInstrInfo.h"
20 #include "SIRegisterInfo.h"
21 #include "llvm/ADT/ArrayRef.h"
22 #include "llvm/ADT/DenseMap.h"
23 #include "llvm/ADT/Optional.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/SmallVector.h"
26 #include "llvm/ADT/SparseBitVector.h"
27 #include "llvm/CodeGen/MIRYamlMapping.h"
28 #include "llvm/CodeGen/PseudoSourceValue.h"
29 #include "llvm/CodeGen/TargetInstrInfo.h"
30 #include "llvm/MC/MCRegisterInfo.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include <array>
33 #include <cassert>
34 #include <utility>
35 #include <vector>
36 
37 namespace llvm {
38 
39 class MachineFrameInfo;
40 class MachineFunction;
41 class TargetRegisterClass;
42 
43 class AMDGPUPseudoSourceValue : public PseudoSourceValue {
44 public:
45   enum AMDGPUPSVKind : unsigned {
46     PSVBuffer = PseudoSourceValue::TargetCustom,
47     PSVImage,
48     GWSResource
49   };
50 
51 protected:
52   AMDGPUPseudoSourceValue(unsigned Kind, const TargetInstrInfo &TII)
53       : PseudoSourceValue(Kind, TII) {}
54 
55 public:
56   bool isConstant(const MachineFrameInfo *) const override {
57     // This should probably be true for most images, but we will start by being
58     // conservative.
59     return false;
60   }
61 
62   bool isAliased(const MachineFrameInfo *) const override {
63     return true;
64   }
65 
66   bool mayAlias(const MachineFrameInfo *) const override {
67     return true;
68   }
69 };
70 
71 class AMDGPUBufferPseudoSourceValue final : public AMDGPUPseudoSourceValue {
72 public:
73   explicit AMDGPUBufferPseudoSourceValue(const TargetInstrInfo &TII)
74       : AMDGPUPseudoSourceValue(PSVBuffer, TII) {}
75 
76   static bool classof(const PseudoSourceValue *V) {
77     return V->kind() == PSVBuffer;
78   }
79 };
80 
81 class AMDGPUImagePseudoSourceValue final : public AMDGPUPseudoSourceValue {
82 public:
83   // TODO: Is the img rsrc useful?
84   explicit AMDGPUImagePseudoSourceValue(const TargetInstrInfo &TII)
85       : AMDGPUPseudoSourceValue(PSVImage, TII) {}
86 
87   static bool classof(const PseudoSourceValue *V) {
88     return V->kind() == PSVImage;
89   }
90 };
91 
92 class AMDGPUGWSResourcePseudoSourceValue final : public AMDGPUPseudoSourceValue {
93 public:
94   explicit AMDGPUGWSResourcePseudoSourceValue(const TargetInstrInfo &TII)
95       : AMDGPUPseudoSourceValue(GWSResource, TII) {}
96 
97   static bool classof(const PseudoSourceValue *V) {
98     return V->kind() == GWSResource;
99   }
100 
101   // These are inaccessible memory from IR.
102   bool isAliased(const MachineFrameInfo *) const override {
103     return false;
104   }
105 
106   // These are inaccessible memory from IR.
107   bool mayAlias(const MachineFrameInfo *) const override {
108     return false;
109   }
110 
111   void printCustom(raw_ostream &OS) const override {
112     OS << "GWSResource";
113   }
114 };
115 
116 namespace yaml {
117 
118 struct SIArgument {
119   bool IsRegister;
120   union {
121     StringValue RegisterName;
122     unsigned StackOffset;
123   };
124   Optional<unsigned> Mask;
125 
126   // Default constructor, which creates a stack argument.
127   SIArgument() : IsRegister(false), StackOffset(0) {}
128   SIArgument(const SIArgument &Other) {
129     IsRegister = Other.IsRegister;
130     if (IsRegister) {
131       ::new ((void *)std::addressof(RegisterName))
132           StringValue(Other.RegisterName);
133     } else
134       StackOffset = Other.StackOffset;
135     Mask = Other.Mask;
136   }
137   SIArgument &operator=(const SIArgument &Other) {
138     IsRegister = Other.IsRegister;
139     if (IsRegister) {
140       ::new ((void *)std::addressof(RegisterName))
141           StringValue(Other.RegisterName);
142     } else
143       StackOffset = Other.StackOffset;
144     Mask = Other.Mask;
145     return *this;
146   }
147   ~SIArgument() {
148     if (IsRegister)
149       RegisterName.~StringValue();
150   }
151 
152   // Helper to create a register or stack argument.
153   static inline SIArgument createArgument(bool IsReg) {
154     if (IsReg)
155       return SIArgument(IsReg);
156     return SIArgument();
157   }
158 
159 private:
160   // Construct a register argument.
161   SIArgument(bool) : IsRegister(true), RegisterName() {}
162 };
163 
164 template <> struct MappingTraits<SIArgument> {
165   static void mapping(IO &YamlIO, SIArgument &A) {
166     if (YamlIO.outputting()) {
167       if (A.IsRegister)
168         YamlIO.mapRequired("reg", A.RegisterName);
169       else
170         YamlIO.mapRequired("offset", A.StackOffset);
171     } else {
172       auto Keys = YamlIO.keys();
173       if (is_contained(Keys, "reg")) {
174         A = SIArgument::createArgument(true);
175         YamlIO.mapRequired("reg", A.RegisterName);
176       } else if (is_contained(Keys, "offset"))
177         YamlIO.mapRequired("offset", A.StackOffset);
178       else
179         YamlIO.setError("missing required key 'reg' or 'offset'");
180     }
181     YamlIO.mapOptional("mask", A.Mask);
182   }
183   static const bool flow = true;
184 };
185 
186 struct SIArgumentInfo {
187   Optional<SIArgument> PrivateSegmentBuffer;
188   Optional<SIArgument> DispatchPtr;
189   Optional<SIArgument> QueuePtr;
190   Optional<SIArgument> KernargSegmentPtr;
191   Optional<SIArgument> DispatchID;
192   Optional<SIArgument> FlatScratchInit;
193   Optional<SIArgument> PrivateSegmentSize;
194 
195   Optional<SIArgument> WorkGroupIDX;
196   Optional<SIArgument> WorkGroupIDY;
197   Optional<SIArgument> WorkGroupIDZ;
198   Optional<SIArgument> WorkGroupInfo;
199   Optional<SIArgument> PrivateSegmentWaveByteOffset;
200 
201   Optional<SIArgument> ImplicitArgPtr;
202   Optional<SIArgument> ImplicitBufferPtr;
203 
204   Optional<SIArgument> WorkItemIDX;
205   Optional<SIArgument> WorkItemIDY;
206   Optional<SIArgument> WorkItemIDZ;
207 };
208 
209 template <> struct MappingTraits<SIArgumentInfo> {
210   static void mapping(IO &YamlIO, SIArgumentInfo &AI) {
211     YamlIO.mapOptional("privateSegmentBuffer", AI.PrivateSegmentBuffer);
212     YamlIO.mapOptional("dispatchPtr", AI.DispatchPtr);
213     YamlIO.mapOptional("queuePtr", AI.QueuePtr);
214     YamlIO.mapOptional("kernargSegmentPtr", AI.KernargSegmentPtr);
215     YamlIO.mapOptional("dispatchID", AI.DispatchID);
216     YamlIO.mapOptional("flatScratchInit", AI.FlatScratchInit);
217     YamlIO.mapOptional("privateSegmentSize", AI.PrivateSegmentSize);
218 
219     YamlIO.mapOptional("workGroupIDX", AI.WorkGroupIDX);
220     YamlIO.mapOptional("workGroupIDY", AI.WorkGroupIDY);
221     YamlIO.mapOptional("workGroupIDZ", AI.WorkGroupIDZ);
222     YamlIO.mapOptional("workGroupInfo", AI.WorkGroupInfo);
223     YamlIO.mapOptional("privateSegmentWaveByteOffset",
224                        AI.PrivateSegmentWaveByteOffset);
225 
226     YamlIO.mapOptional("implicitArgPtr", AI.ImplicitArgPtr);
227     YamlIO.mapOptional("implicitBufferPtr", AI.ImplicitBufferPtr);
228 
229     YamlIO.mapOptional("workItemIDX", AI.WorkItemIDX);
230     YamlIO.mapOptional("workItemIDY", AI.WorkItemIDY);
231     YamlIO.mapOptional("workItemIDZ", AI.WorkItemIDZ);
232   }
233 };
234 
235 struct SIMachineFunctionInfo final : public yaml::MachineFunctionInfo {
236   uint64_t ExplicitKernArgSize = 0;
237   unsigned MaxKernArgAlign = 0;
238   unsigned LDSSize = 0;
239   bool IsEntryFunction = false;
240   bool NoSignedZerosFPMath = false;
241   bool MemoryBound = false;
242   bool WaveLimiter = false;
243 
244   StringValue ScratchRSrcReg = "$private_rsrc_reg";
245   StringValue ScratchWaveOffsetReg = "$scratch_wave_offset_reg";
246   StringValue FrameOffsetReg = "$fp_reg";
247   StringValue StackPtrOffsetReg = "$sp_reg";
248 
249   Optional<SIArgumentInfo> ArgInfo;
250 
251   SIMachineFunctionInfo() = default;
252   SIMachineFunctionInfo(const llvm::SIMachineFunctionInfo &,
253                         const TargetRegisterInfo &TRI);
254 
255   void mappingImpl(yaml::IO &YamlIO) override;
256   ~SIMachineFunctionInfo() = default;
257 };
258 
259 template <> struct MappingTraits<SIMachineFunctionInfo> {
260   static void mapping(IO &YamlIO, SIMachineFunctionInfo &MFI) {
261     YamlIO.mapOptional("explicitKernArgSize", MFI.ExplicitKernArgSize,
262                        UINT64_C(0));
263     YamlIO.mapOptional("maxKernArgAlign", MFI.MaxKernArgAlign, 0u);
264     YamlIO.mapOptional("ldsSize", MFI.LDSSize, 0u);
265     YamlIO.mapOptional("isEntryFunction", MFI.IsEntryFunction, false);
266     YamlIO.mapOptional("noSignedZerosFPMath", MFI.NoSignedZerosFPMath, false);
267     YamlIO.mapOptional("memoryBound", MFI.MemoryBound, false);
268     YamlIO.mapOptional("waveLimiter", MFI.WaveLimiter, false);
269     YamlIO.mapOptional("scratchRSrcReg", MFI.ScratchRSrcReg,
270                        StringValue("$private_rsrc_reg"));
271     YamlIO.mapOptional("scratchWaveOffsetReg", MFI.ScratchWaveOffsetReg,
272                        StringValue("$scratch_wave_offset_reg"));
273     YamlIO.mapOptional("frameOffsetReg", MFI.FrameOffsetReg,
274                        StringValue("$fp_reg"));
275     YamlIO.mapOptional("stackPtrOffsetReg", MFI.StackPtrOffsetReg,
276                        StringValue("$sp_reg"));
277     YamlIO.mapOptional("argumentInfo", MFI.ArgInfo);
278   }
279 };
280 
281 } // end namespace yaml
282 
283 /// This class keeps track of the SPI_SP_INPUT_ADDR config register, which
284 /// tells the hardware which interpolation parameters to load.
285 class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
286   friend class GCNTargetMachine;
287 
288   unsigned TIDReg = AMDGPU::NoRegister;
289 
290   // Registers that may be reserved for spilling purposes. These may be the same
291   // as the input registers.
292   unsigned ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG;
293   unsigned ScratchWaveOffsetReg = AMDGPU::SCRATCH_WAVE_OFFSET_REG;
294 
295   // This is the current function's incremented size from the kernel's scratch
296   // wave offset register. For an entry function, this is exactly the same as
297   // the ScratchWaveOffsetReg.
298   unsigned FrameOffsetReg = AMDGPU::FP_REG;
299 
300   // Top of the stack SGPR offset derived from the ScratchWaveOffsetReg.
301   unsigned StackPtrOffsetReg = AMDGPU::SP_REG;
302 
303   AMDGPUFunctionArgInfo ArgInfo;
304 
305   // State of MODE register, assumed FP mode.
306   AMDGPU::SIModeRegisterDefaults Mode;
307 
308   // Graphics info.
309   unsigned PSInputAddr = 0;
310   unsigned PSInputEnable = 0;
311 
312   /// Number of bytes of arguments this function has on the stack. If the callee
313   /// is expected to restore the argument stack this should be a multiple of 16,
314   /// all usable during a tail call.
315   ///
316   /// The alternative would forbid tail call optimisation in some cases: if we
317   /// want to transfer control from a function with 8-bytes of stack-argument
318   /// space to a function with 16-bytes then misalignment of this value would
319   /// make a stack adjustment necessary, which could not be undone by the
320   /// callee.
321   unsigned BytesInStackArgArea = 0;
322 
323   bool ReturnsVoid = true;
324 
325   // A pair of default/requested minimum/maximum flat work group sizes.
326   // Minimum - first, maximum - second.
327   std::pair<unsigned, unsigned> FlatWorkGroupSizes = {0, 0};
328 
329   // A pair of default/requested minimum/maximum number of waves per execution
330   // unit. Minimum - first, maximum - second.
331   std::pair<unsigned, unsigned> WavesPerEU = {0, 0};
332 
333   DenseMap<const Value *,
334            std::unique_ptr<const AMDGPUBufferPseudoSourceValue>> BufferPSVs;
335   DenseMap<const Value *,
336            std::unique_ptr<const AMDGPUImagePseudoSourceValue>> ImagePSVs;
337   std::unique_ptr<const AMDGPUGWSResourcePseudoSourceValue> GWSResourcePSV;
338 
339 private:
340   unsigned LDSWaveSpillSize = 0;
341   unsigned NumUserSGPRs = 0;
342   unsigned NumSystemSGPRs = 0;
343 
344   bool HasSpilledSGPRs = false;
345   bool HasSpilledVGPRs = false;
346   bool HasNonSpillStackObjects = false;
347   bool IsStackRealigned = false;
348 
349   unsigned NumSpilledSGPRs = 0;
350   unsigned NumSpilledVGPRs = 0;
351 
352   // Feature bits required for inputs passed in user SGPRs.
353   bool PrivateSegmentBuffer : 1;
354   bool DispatchPtr : 1;
355   bool QueuePtr : 1;
356   bool KernargSegmentPtr : 1;
357   bool DispatchID : 1;
358   bool FlatScratchInit : 1;
359 
360   // Feature bits required for inputs passed in system SGPRs.
361   bool WorkGroupIDX : 1; // Always initialized.
362   bool WorkGroupIDY : 1;
363   bool WorkGroupIDZ : 1;
364   bool WorkGroupInfo : 1;
365   bool PrivateSegmentWaveByteOffset : 1;
366 
367   bool WorkItemIDX : 1; // Always initialized.
368   bool WorkItemIDY : 1;
369   bool WorkItemIDZ : 1;
370 
371   // Private memory buffer
372   // Compute directly in sgpr[0:1]
373   // Other shaders indirect 64-bits at sgpr[0:1]
374   bool ImplicitBufferPtr : 1;
375 
376   // Pointer to where the ABI inserts special kernel arguments separate from the
377   // user arguments. This is an offset from the KernargSegmentPtr.
378   bool ImplicitArgPtr : 1;
379 
380   // The hard-wired high half of the address of the global information table
381   // for AMDPAL OS type. 0xffffffff represents no hard-wired high half, since
382   // current hardware only allows a 16 bit value.
383   unsigned GITPtrHigh;
384 
385   unsigned HighBitsOf32BitAddress;
386   unsigned GDSSize;
387 
388   // Current recorded maximum possible occupancy.
389   unsigned Occupancy;
390 
391   MCPhysReg getNextUserSGPR() const;
392 
393   MCPhysReg getNextSystemSGPR() const;
394 
395 public:
396   struct SpilledReg {
397     unsigned VGPR = 0;
398     int Lane = -1;
399 
400     SpilledReg() = default;
401     SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) {}
402 
403     bool hasLane() { return Lane != -1;}
404     bool hasReg() { return VGPR != 0;}
405   };
406 
407   struct SGPRSpillVGPRCSR {
408     // VGPR used for SGPR spills
409     unsigned VGPR;
410 
411     // If the VGPR is a CSR, the stack slot used to save/restore it in the
412     // prolog/epilog.
413     Optional<int> FI;
414 
415     SGPRSpillVGPRCSR(unsigned V, Optional<int> F) : VGPR(V), FI(F) {}
416   };
417 
418   SparseBitVector<> WWMReservedRegs;
419 
420   void ReserveWWMRegister(unsigned reg) { WWMReservedRegs.set(reg); }
421 
422 private:
423   // SGPR->VGPR spilling support.
424   using SpillRegMask = std::pair<unsigned, unsigned>;
425 
426   // Track VGPR + wave index for each subregister of the SGPR spilled to
427   // frameindex key.
428   DenseMap<int, std::vector<SpilledReg>> SGPRToVGPRSpills;
429   unsigned NumVGPRSpillLanes = 0;
430   SmallVector<SGPRSpillVGPRCSR, 2> SpillVGPRs;
431 
432 public:
433   SIMachineFunctionInfo(const MachineFunction &MF);
434 
435   bool initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI);
436 
437   ArrayRef<SpilledReg> getSGPRToVGPRSpills(int FrameIndex) const {
438     auto I = SGPRToVGPRSpills.find(FrameIndex);
439     return (I == SGPRToVGPRSpills.end()) ?
440       ArrayRef<SpilledReg>() : makeArrayRef(I->second);
441   }
442 
443   ArrayRef<SGPRSpillVGPRCSR> getSGPRSpillVGPRs() const {
444     return SpillVGPRs;
445   }
446 
447   AMDGPU::SIModeRegisterDefaults getMode() const {
448     return Mode;
449   }
450 
451   bool allocateSGPRSpillToVGPR(MachineFunction &MF, int FI);
452   void removeSGPRToVGPRFrameIndices(MachineFrameInfo &MFI);
453 
454   bool hasCalculatedTID() const { return TIDReg != 0; };
455   unsigned getTIDReg() const { return TIDReg; };
456   void setTIDReg(unsigned Reg) { TIDReg = Reg; }
457 
458   unsigned getBytesInStackArgArea() const {
459     return BytesInStackArgArea;
460   }
461 
462   void setBytesInStackArgArea(unsigned Bytes) {
463     BytesInStackArgArea = Bytes;
464   }
465 
466   // Add user SGPRs.
467   unsigned addPrivateSegmentBuffer(const SIRegisterInfo &TRI);
468   unsigned addDispatchPtr(const SIRegisterInfo &TRI);
469   unsigned addQueuePtr(const SIRegisterInfo &TRI);
470   unsigned addKernargSegmentPtr(const SIRegisterInfo &TRI);
471   unsigned addDispatchID(const SIRegisterInfo &TRI);
472   unsigned addFlatScratchInit(const SIRegisterInfo &TRI);
473   unsigned addImplicitBufferPtr(const SIRegisterInfo &TRI);
474 
475   // Add system SGPRs.
476   unsigned addWorkGroupIDX() {
477     ArgInfo.WorkGroupIDX = ArgDescriptor::createRegister(getNextSystemSGPR());
478     NumSystemSGPRs += 1;
479     return ArgInfo.WorkGroupIDX.getRegister();
480   }
481 
482   unsigned addWorkGroupIDY() {
483     ArgInfo.WorkGroupIDY = ArgDescriptor::createRegister(getNextSystemSGPR());
484     NumSystemSGPRs += 1;
485     return ArgInfo.WorkGroupIDY.getRegister();
486   }
487 
488   unsigned addWorkGroupIDZ() {
489     ArgInfo.WorkGroupIDZ = ArgDescriptor::createRegister(getNextSystemSGPR());
490     NumSystemSGPRs += 1;
491     return ArgInfo.WorkGroupIDZ.getRegister();
492   }
493 
494   unsigned addWorkGroupInfo() {
495     ArgInfo.WorkGroupInfo = ArgDescriptor::createRegister(getNextSystemSGPR());
496     NumSystemSGPRs += 1;
497     return ArgInfo.WorkGroupInfo.getRegister();
498   }
499 
500   // Add special VGPR inputs
501   void setWorkItemIDX(ArgDescriptor Arg) {
502     ArgInfo.WorkItemIDX = Arg;
503   }
504 
505   void setWorkItemIDY(ArgDescriptor Arg) {
506     ArgInfo.WorkItemIDY = Arg;
507   }
508 
509   void setWorkItemIDZ(ArgDescriptor Arg) {
510     ArgInfo.WorkItemIDZ = Arg;
511   }
512 
513   unsigned addPrivateSegmentWaveByteOffset() {
514     ArgInfo.PrivateSegmentWaveByteOffset
515       = ArgDescriptor::createRegister(getNextSystemSGPR());
516     NumSystemSGPRs += 1;
517     return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
518   }
519 
520   void setPrivateSegmentWaveByteOffset(unsigned Reg) {
521     ArgInfo.PrivateSegmentWaveByteOffset = ArgDescriptor::createRegister(Reg);
522   }
523 
524   bool hasPrivateSegmentBuffer() const {
525     return PrivateSegmentBuffer;
526   }
527 
528   bool hasDispatchPtr() const {
529     return DispatchPtr;
530   }
531 
532   bool hasQueuePtr() const {
533     return QueuePtr;
534   }
535 
536   bool hasKernargSegmentPtr() const {
537     return KernargSegmentPtr;
538   }
539 
540   bool hasDispatchID() const {
541     return DispatchID;
542   }
543 
544   bool hasFlatScratchInit() const {
545     return FlatScratchInit;
546   }
547 
548   bool hasWorkGroupIDX() const {
549     return WorkGroupIDX;
550   }
551 
552   bool hasWorkGroupIDY() const {
553     return WorkGroupIDY;
554   }
555 
556   bool hasWorkGroupIDZ() const {
557     return WorkGroupIDZ;
558   }
559 
560   bool hasWorkGroupInfo() const {
561     return WorkGroupInfo;
562   }
563 
564   bool hasPrivateSegmentWaveByteOffset() const {
565     return PrivateSegmentWaveByteOffset;
566   }
567 
568   bool hasWorkItemIDX() const {
569     return WorkItemIDX;
570   }
571 
572   bool hasWorkItemIDY() const {
573     return WorkItemIDY;
574   }
575 
576   bool hasWorkItemIDZ() const {
577     return WorkItemIDZ;
578   }
579 
580   bool hasImplicitArgPtr() const {
581     return ImplicitArgPtr;
582   }
583 
584   bool hasImplicitBufferPtr() const {
585     return ImplicitBufferPtr;
586   }
587 
588   AMDGPUFunctionArgInfo &getArgInfo() {
589     return ArgInfo;
590   }
591 
592   const AMDGPUFunctionArgInfo &getArgInfo() const {
593     return ArgInfo;
594   }
595 
596   std::pair<const ArgDescriptor *, const TargetRegisterClass *>
597   getPreloadedValue(AMDGPUFunctionArgInfo::PreloadedValue Value) const {
598     return ArgInfo.getPreloadedValue(Value);
599   }
600 
601   Register getPreloadedReg(AMDGPUFunctionArgInfo::PreloadedValue Value) const {
602     auto Arg = ArgInfo.getPreloadedValue(Value).first;
603     return Arg ? Arg->getRegister() : Register();
604   }
605 
606   unsigned getGITPtrHigh() const {
607     return GITPtrHigh;
608   }
609 
610   unsigned get32BitAddressHighBits() const {
611     return HighBitsOf32BitAddress;
612   }
613 
614   unsigned getGDSSize() const {
615     return GDSSize;
616   }
617 
618   unsigned getNumUserSGPRs() const {
619     return NumUserSGPRs;
620   }
621 
622   unsigned getNumPreloadedSGPRs() const {
623     return NumUserSGPRs + NumSystemSGPRs;
624   }
625 
626   unsigned getPrivateSegmentWaveByteOffsetSystemSGPR() const {
627     return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
628   }
629 
630   /// Returns the physical register reserved for use as the resource
631   /// descriptor for scratch accesses.
632   unsigned getScratchRSrcReg() const {
633     return ScratchRSrcReg;
634   }
635 
636   void setScratchRSrcReg(unsigned Reg) {
637     assert(Reg != 0 && "Should never be unset");
638     ScratchRSrcReg = Reg;
639   }
640 
641   unsigned getScratchWaveOffsetReg() const {
642     return ScratchWaveOffsetReg;
643   }
644 
645   unsigned getFrameOffsetReg() const {
646     return FrameOffsetReg;
647   }
648 
649   void setFrameOffsetReg(unsigned Reg) {
650     assert(Reg != 0 && "Should never be unset");
651     FrameOffsetReg = Reg;
652   }
653 
654   void setStackPtrOffsetReg(unsigned Reg) {
655     assert(Reg != 0 && "Should never be unset");
656     StackPtrOffsetReg = Reg;
657   }
658 
659   // Note the unset value for this is AMDGPU::SP_REG rather than
660   // NoRegister. This is mostly a workaround for MIR tests where state that
661   // can't be directly computed from the function is not preserved in serialized
662   // MIR.
663   unsigned getStackPtrOffsetReg() const {
664     return StackPtrOffsetReg;
665   }
666 
667   void setScratchWaveOffsetReg(unsigned Reg) {
668     assert(Reg != 0 && "Should never be unset");
669     ScratchWaveOffsetReg = Reg;
670   }
671 
672   unsigned getQueuePtrUserSGPR() const {
673     return ArgInfo.QueuePtr.getRegister();
674   }
675 
676   unsigned getImplicitBufferPtrUserSGPR() const {
677     return ArgInfo.ImplicitBufferPtr.getRegister();
678   }
679 
680   bool hasSpilledSGPRs() const {
681     return HasSpilledSGPRs;
682   }
683 
684   void setHasSpilledSGPRs(bool Spill = true) {
685     HasSpilledSGPRs = Spill;
686   }
687 
688   bool hasSpilledVGPRs() const {
689     return HasSpilledVGPRs;
690   }
691 
692   void setHasSpilledVGPRs(bool Spill = true) {
693     HasSpilledVGPRs = Spill;
694   }
695 
696   bool hasNonSpillStackObjects() const {
697     return HasNonSpillStackObjects;
698   }
699 
700   void setHasNonSpillStackObjects(bool StackObject = true) {
701     HasNonSpillStackObjects = StackObject;
702   }
703 
704   bool isStackRealigned() const {
705     return IsStackRealigned;
706   }
707 
708   void setIsStackRealigned(bool Realigned = true) {
709     IsStackRealigned = Realigned;
710   }
711 
712   unsigned getNumSpilledSGPRs() const {
713     return NumSpilledSGPRs;
714   }
715 
716   unsigned getNumSpilledVGPRs() const {
717     return NumSpilledVGPRs;
718   }
719 
720   void addToSpilledSGPRs(unsigned num) {
721     NumSpilledSGPRs += num;
722   }
723 
724   void addToSpilledVGPRs(unsigned num) {
725     NumSpilledVGPRs += num;
726   }
727 
728   unsigned getPSInputAddr() const {
729     return PSInputAddr;
730   }
731 
732   unsigned getPSInputEnable() const {
733     return PSInputEnable;
734   }
735 
736   bool isPSInputAllocated(unsigned Index) const {
737     return PSInputAddr & (1 << Index);
738   }
739 
740   void markPSInputAllocated(unsigned Index) {
741     PSInputAddr |= 1 << Index;
742   }
743 
744   void markPSInputEnabled(unsigned Index) {
745     PSInputEnable |= 1 << Index;
746   }
747 
748   bool returnsVoid() const {
749     return ReturnsVoid;
750   }
751 
752   void setIfReturnsVoid(bool Value) {
753     ReturnsVoid = Value;
754   }
755 
756   /// \returns A pair of default/requested minimum/maximum flat work group sizes
757   /// for this function.
758   std::pair<unsigned, unsigned> getFlatWorkGroupSizes() const {
759     return FlatWorkGroupSizes;
760   }
761 
762   /// \returns Default/requested minimum flat work group size for this function.
763   unsigned getMinFlatWorkGroupSize() const {
764     return FlatWorkGroupSizes.first;
765   }
766 
767   /// \returns Default/requested maximum flat work group size for this function.
768   unsigned getMaxFlatWorkGroupSize() const {
769     return FlatWorkGroupSizes.second;
770   }
771 
772   /// \returns A pair of default/requested minimum/maximum number of waves per
773   /// execution unit.
774   std::pair<unsigned, unsigned> getWavesPerEU() const {
775     return WavesPerEU;
776   }
777 
778   /// \returns Default/requested minimum number of waves per execution unit.
779   unsigned getMinWavesPerEU() const {
780     return WavesPerEU.first;
781   }
782 
783   /// \returns Default/requested maximum number of waves per execution unit.
784   unsigned getMaxWavesPerEU() const {
785     return WavesPerEU.second;
786   }
787 
788   /// \returns SGPR used for \p Dim's work group ID.
789   unsigned getWorkGroupIDSGPR(unsigned Dim) const {
790     switch (Dim) {
791     case 0:
792       assert(hasWorkGroupIDX());
793       return ArgInfo.WorkGroupIDX.getRegister();
794     case 1:
795       assert(hasWorkGroupIDY());
796       return ArgInfo.WorkGroupIDY.getRegister();
797     case 2:
798       assert(hasWorkGroupIDZ());
799       return ArgInfo.WorkGroupIDZ.getRegister();
800     }
801     llvm_unreachable("unexpected dimension");
802   }
803 
804   unsigned getLDSWaveSpillSize() const {
805     return LDSWaveSpillSize;
806   }
807 
808   const AMDGPUBufferPseudoSourceValue *getBufferPSV(const SIInstrInfo &TII,
809                                                     const Value *BufferRsrc) {
810     assert(BufferRsrc);
811     auto PSV = BufferPSVs.try_emplace(
812       BufferRsrc,
813       llvm::make_unique<AMDGPUBufferPseudoSourceValue>(TII));
814     return PSV.first->second.get();
815   }
816 
817   const AMDGPUImagePseudoSourceValue *getImagePSV(const SIInstrInfo &TII,
818                                                   const Value *ImgRsrc) {
819     assert(ImgRsrc);
820     auto PSV = ImagePSVs.try_emplace(
821       ImgRsrc,
822       llvm::make_unique<AMDGPUImagePseudoSourceValue>(TII));
823     return PSV.first->second.get();
824   }
825 
826   const AMDGPUGWSResourcePseudoSourceValue *getGWSPSV(const SIInstrInfo &TII) {
827     if (!GWSResourcePSV) {
828       GWSResourcePSV =
829           llvm::make_unique<AMDGPUGWSResourcePseudoSourceValue>(TII);
830     }
831 
832     return GWSResourcePSV.get();
833   }
834 
835   unsigned getOccupancy() const {
836     return Occupancy;
837   }
838 
839   unsigned getMinAllowedOccupancy() const {
840     if (!isMemoryBound() && !needsWaveLimiter())
841       return Occupancy;
842     return (Occupancy < 4) ? Occupancy : 4;
843   }
844 
845   void limitOccupancy(const MachineFunction &MF);
846 
847   void limitOccupancy(unsigned Limit) {
848     if (Occupancy > Limit)
849       Occupancy = Limit;
850   }
851 
852   void increaseOccupancy(const MachineFunction &MF, unsigned Limit) {
853     if (Occupancy < Limit)
854       Occupancy = Limit;
855     limitOccupancy(MF);
856   }
857 };
858 
859 } // end namespace llvm
860 
861 #endif // LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
862