xref: /llvm-project/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h (revision 60b1967c3933c42f473a3f7be5f40747547b6057) 
1 //==- SIMachineFunctionInfo.h - SIMachineFunctionInfo interface --*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
14 #define LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
15 
16 #include "AMDGPUArgumentUsageInfo.h"
17 #include "AMDGPUMachineFunction.h"
18 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
19 #include "SIInstrInfo.h"
20 #include "SIRegisterInfo.h"
21 #include "llvm/ADT/ArrayRef.h"
22 #include "llvm/ADT/DenseMap.h"
23 #include "llvm/ADT/Optional.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/SmallVector.h"
26 #include "llvm/ADT/SparseBitVector.h"
27 #include "llvm/CodeGen/MIRYamlMapping.h"
28 #include "llvm/CodeGen/PseudoSourceValue.h"
29 #include "llvm/CodeGen/TargetInstrInfo.h"
30 #include "llvm/MC/MCRegisterInfo.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include <array>
33 #include <cassert>
34 #include <utility>
35 #include <vector>
36 
37 namespace llvm {
38 
39 class MachineFrameInfo;
40 class MachineFunction;
41 class TargetRegisterClass;
42 
43 class AMDGPUPseudoSourceValue : public PseudoSourceValue {
44 public:
45   enum AMDGPUPSVKind : unsigned {
46     PSVBuffer = PseudoSourceValue::TargetCustom,
47     PSVImage,
48     GWSResource
49   };
50 
51 protected:
52   AMDGPUPseudoSourceValue(unsigned Kind, const TargetInstrInfo &TII)
53       : PseudoSourceValue(Kind, TII) {}
54 
55 public:
56   bool isConstant(const MachineFrameInfo *) const override {
57     // This should probably be true for most images, but we will start by being
58     // conservative.
59     return false;
60   }
61 
62   bool isAliased(const MachineFrameInfo *) const override {
63     return true;
64   }
65 
66   bool mayAlias(const MachineFrameInfo *) const override {
67     return true;
68   }
69 };
70 
71 class AMDGPUBufferPseudoSourceValue final : public AMDGPUPseudoSourceValue {
72 public:
73   explicit AMDGPUBufferPseudoSourceValue(const TargetInstrInfo &TII)
74       : AMDGPUPseudoSourceValue(PSVBuffer, TII) {}
75 
76   static bool classof(const PseudoSourceValue *V) {
77     return V->kind() == PSVBuffer;
78   }
79 };
80 
81 class AMDGPUImagePseudoSourceValue final : public AMDGPUPseudoSourceValue {
82 public:
83   // TODO: Is the img rsrc useful?
84   explicit AMDGPUImagePseudoSourceValue(const TargetInstrInfo &TII)
85       : AMDGPUPseudoSourceValue(PSVImage, TII) {}
86 
87   static bool classof(const PseudoSourceValue *V) {
88     return V->kind() == PSVImage;
89   }
90 };
91 
92 class AMDGPUGWSResourcePseudoSourceValue final : public AMDGPUPseudoSourceValue {
93 public:
94   explicit AMDGPUGWSResourcePseudoSourceValue(const TargetInstrInfo &TII)
95       : AMDGPUPseudoSourceValue(GWSResource, TII) {}
96 
97   static bool classof(const PseudoSourceValue *V) {
98     return V->kind() == GWSResource;
99   }
100 
101   // These are inaccessible memory from IR.
102   bool isAliased(const MachineFrameInfo *) const override {
103     return false;
104   }
105 
106   // These are inaccessible memory from IR.
107   bool mayAlias(const MachineFrameInfo *) const override {
108     return false;
109   }
110 
111   void printCustom(raw_ostream &OS) const override {
112     OS << "GWSResource";
113   }
114 };
115 
116 namespace yaml {
117 
118 struct SIArgument {
119   bool IsRegister;
120   union {
121     StringValue RegisterName;
122     unsigned StackOffset;
123   };
124   Optional<unsigned> Mask;
125 
126   // Default constructor, which creates a stack argument.
127   SIArgument() : IsRegister(false), StackOffset(0) {}
128   SIArgument(const SIArgument &Other) {
129     IsRegister = Other.IsRegister;
130     if (IsRegister) {
131       ::new ((void *)std::addressof(RegisterName))
132           StringValue(Other.RegisterName);
133     } else
134       StackOffset = Other.StackOffset;
135     Mask = Other.Mask;
136   }
137   SIArgument &operator=(const SIArgument &Other) {
138     IsRegister = Other.IsRegister;
139     if (IsRegister) {
140       ::new ((void *)std::addressof(RegisterName))
141           StringValue(Other.RegisterName);
142     } else
143       StackOffset = Other.StackOffset;
144     Mask = Other.Mask;
145     return *this;
146   }
147   ~SIArgument() {
148     if (IsRegister)
149       RegisterName.~StringValue();
150   }
151 
152   // Helper to create a register or stack argument.
153   static inline SIArgument createArgument(bool IsReg) {
154     if (IsReg)
155       return SIArgument(IsReg);
156     return SIArgument();
157   }
158 
159 private:
160   // Construct a register argument.
161   SIArgument(bool) : IsRegister(true), RegisterName() {}
162 };
163 
164 template <> struct MappingTraits<SIArgument> {
165   static void mapping(IO &YamlIO, SIArgument &A) {
166     if (YamlIO.outputting()) {
167       if (A.IsRegister)
168         YamlIO.mapRequired("reg", A.RegisterName);
169       else
170         YamlIO.mapRequired("offset", A.StackOffset);
171     } else {
172       auto Keys = YamlIO.keys();
173       if (is_contained(Keys, "reg")) {
174         A = SIArgument::createArgument(true);
175         YamlIO.mapRequired("reg", A.RegisterName);
176       } else if (is_contained(Keys, "offset"))
177         YamlIO.mapRequired("offset", A.StackOffset);
178       else
179         YamlIO.setError("missing required key 'reg' or 'offset'");
180     }
181     YamlIO.mapOptional("mask", A.Mask);
182   }
183   static const bool flow = true;
184 };
185 
186 struct SIArgumentInfo {
187   Optional<SIArgument> PrivateSegmentBuffer;
188   Optional<SIArgument> DispatchPtr;
189   Optional<SIArgument> QueuePtr;
190   Optional<SIArgument> KernargSegmentPtr;
191   Optional<SIArgument> DispatchID;
192   Optional<SIArgument> FlatScratchInit;
193   Optional<SIArgument> PrivateSegmentSize;
194 
195   Optional<SIArgument> WorkGroupIDX;
196   Optional<SIArgument> WorkGroupIDY;
197   Optional<SIArgument> WorkGroupIDZ;
198   Optional<SIArgument> WorkGroupInfo;
199   Optional<SIArgument> PrivateSegmentWaveByteOffset;
200 
201   Optional<SIArgument> ImplicitArgPtr;
202   Optional<SIArgument> ImplicitBufferPtr;
203 
204   Optional<SIArgument> WorkItemIDX;
205   Optional<SIArgument> WorkItemIDY;
206   Optional<SIArgument> WorkItemIDZ;
207 };
208 
209 template <> struct MappingTraits<SIArgumentInfo> {
210   static void mapping(IO &YamlIO, SIArgumentInfo &AI) {
211     YamlIO.mapOptional("privateSegmentBuffer", AI.PrivateSegmentBuffer);
212     YamlIO.mapOptional("dispatchPtr", AI.DispatchPtr);
213     YamlIO.mapOptional("queuePtr", AI.QueuePtr);
214     YamlIO.mapOptional("kernargSegmentPtr", AI.KernargSegmentPtr);
215     YamlIO.mapOptional("dispatchID", AI.DispatchID);
216     YamlIO.mapOptional("flatScratchInit", AI.FlatScratchInit);
217     YamlIO.mapOptional("privateSegmentSize", AI.PrivateSegmentSize);
218 
219     YamlIO.mapOptional("workGroupIDX", AI.WorkGroupIDX);
220     YamlIO.mapOptional("workGroupIDY", AI.WorkGroupIDY);
221     YamlIO.mapOptional("workGroupIDZ", AI.WorkGroupIDZ);
222     YamlIO.mapOptional("workGroupInfo", AI.WorkGroupInfo);
223     YamlIO.mapOptional("privateSegmentWaveByteOffset",
224                        AI.PrivateSegmentWaveByteOffset);
225 
226     YamlIO.mapOptional("implicitArgPtr", AI.ImplicitArgPtr);
227     YamlIO.mapOptional("implicitBufferPtr", AI.ImplicitBufferPtr);
228 
229     YamlIO.mapOptional("workItemIDX", AI.WorkItemIDX);
230     YamlIO.mapOptional("workItemIDY", AI.WorkItemIDY);
231     YamlIO.mapOptional("workItemIDZ", AI.WorkItemIDZ);
232   }
233 };
234 
235 // Default to default mode for default calling convention.
236 struct SIMode {
237   bool IEEE = true;
238   bool DX10Clamp = true;
239   bool FP32InputDenormals = true;
240   bool FP32OutputDenormals = true;
241   bool FP64FP16InputDenormals = true;
242   bool FP64FP16OutputDenormals = true;
243 
244   SIMode() = default;
245 
246   SIMode(const AMDGPU::SIModeRegisterDefaults &Mode) {
247     IEEE = Mode.IEEE;
248     DX10Clamp = Mode.DX10Clamp;
249     FP32InputDenormals = Mode.FP32InputDenormals;
250     FP32OutputDenormals = Mode.FP32OutputDenormals;
251     FP64FP16InputDenormals = Mode.FP64FP16InputDenormals;
252     FP64FP16OutputDenormals = Mode.FP64FP16OutputDenormals;
253   }
254 
255   bool operator ==(const SIMode Other) const {
256     return IEEE == Other.IEEE &&
257            DX10Clamp == Other.DX10Clamp &&
258            FP32InputDenormals == Other.FP32InputDenormals &&
259            FP32OutputDenormals == Other.FP32OutputDenormals &&
260            FP64FP16InputDenormals == Other.FP64FP16InputDenormals &&
261            FP64FP16OutputDenormals == Other.FP64FP16OutputDenormals;
262   }
263 };
264 
265 template <> struct MappingTraits<SIMode> {
266   static void mapping(IO &YamlIO, SIMode &Mode) {
267     YamlIO.mapOptional("ieee", Mode.IEEE, true);
268     YamlIO.mapOptional("dx10-clamp", Mode.DX10Clamp, true);
269     YamlIO.mapOptional("fp32-input-denormals", Mode.FP32InputDenormals, true);
270     YamlIO.mapOptional("fp32-output-denormals", Mode.FP32OutputDenormals, true);
271     YamlIO.mapOptional("fp64-fp16-input-denormals", Mode.FP64FP16InputDenormals, true);
272     YamlIO.mapOptional("fp64-fp16-output-denormals", Mode.FP64FP16OutputDenormals, true);
273   }
274 };
275 
276 struct SIMachineFunctionInfo final : public yaml::MachineFunctionInfo {
277   uint64_t ExplicitKernArgSize = 0;
278   unsigned MaxKernArgAlign = 0;
279   unsigned LDSSize = 0;
280   bool IsEntryFunction = false;
281   bool NoSignedZerosFPMath = false;
282   bool MemoryBound = false;
283   bool WaveLimiter = false;
284   uint32_t HighBitsOf32BitAddress = 0;
285 
286   StringValue ScratchRSrcReg = "$private_rsrc_reg";
287   StringValue FrameOffsetReg = "$fp_reg";
288   StringValue StackPtrOffsetReg = "$sp_reg";
289 
290   Optional<SIArgumentInfo> ArgInfo;
291   SIMode Mode;
292 
293   SIMachineFunctionInfo() = default;
294   SIMachineFunctionInfo(const llvm::SIMachineFunctionInfo &,
295                         const TargetRegisterInfo &TRI);
296 
297   void mappingImpl(yaml::IO &YamlIO) override;
298   ~SIMachineFunctionInfo() = default;
299 };
300 
301 template <> struct MappingTraits<SIMachineFunctionInfo> {
302   static void mapping(IO &YamlIO, SIMachineFunctionInfo &MFI) {
303     YamlIO.mapOptional("explicitKernArgSize", MFI.ExplicitKernArgSize,
304                        UINT64_C(0));
305     YamlIO.mapOptional("maxKernArgAlign", MFI.MaxKernArgAlign, 0u);
306     YamlIO.mapOptional("ldsSize", MFI.LDSSize, 0u);
307     YamlIO.mapOptional("isEntryFunction", MFI.IsEntryFunction, false);
308     YamlIO.mapOptional("noSignedZerosFPMath", MFI.NoSignedZerosFPMath, false);
309     YamlIO.mapOptional("memoryBound", MFI.MemoryBound, false);
310     YamlIO.mapOptional("waveLimiter", MFI.WaveLimiter, false);
311     YamlIO.mapOptional("scratchRSrcReg", MFI.ScratchRSrcReg,
312                        StringValue("$private_rsrc_reg"));
313     YamlIO.mapOptional("frameOffsetReg", MFI.FrameOffsetReg,
314                        StringValue("$fp_reg"));
315     YamlIO.mapOptional("stackPtrOffsetReg", MFI.StackPtrOffsetReg,
316                        StringValue("$sp_reg"));
317     YamlIO.mapOptional("argumentInfo", MFI.ArgInfo);
318     YamlIO.mapOptional("mode", MFI.Mode, SIMode());
319     YamlIO.mapOptional("highBitsOf32BitAddress",
320                        MFI.HighBitsOf32BitAddress, 0u);
321   }
322 };
323 
324 } // end namespace yaml
325 
326 /// This class keeps track of the SPI_SP_INPUT_ADDR config register, which
327 /// tells the hardware which interpolation parameters to load.
328 class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
329   friend class GCNTargetMachine;
330 
331   Register TIDReg = AMDGPU::NoRegister;
332 
333   // Registers that may be reserved for spilling purposes. These may be the same
334   // as the input registers.
335   Register ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG;
336 
337   // This is the the unswizzled offset from the current dispatch's scratch wave
338   // base to the beginning of the current function's frame.
339   Register FrameOffsetReg = AMDGPU::FP_REG;
340 
341   // This is an ABI register used in the non-entry calling convention to
342   // communicate the unswizzled offset from the current dispatch's scratch wave
343   // base to the beginning of the new function's frame.
344   Register StackPtrOffsetReg = AMDGPU::SP_REG;
345 
346   AMDGPUFunctionArgInfo ArgInfo;
347 
348   // Graphics info.
349   unsigned PSInputAddr = 0;
350   unsigned PSInputEnable = 0;
351 
352   /// Number of bytes of arguments this function has on the stack. If the callee
353   /// is expected to restore the argument stack this should be a multiple of 16,
354   /// all usable during a tail call.
355   ///
356   /// The alternative would forbid tail call optimisation in some cases: if we
357   /// want to transfer control from a function with 8-bytes of stack-argument
358   /// space to a function with 16-bytes then misalignment of this value would
359   /// make a stack adjustment necessary, which could not be undone by the
360   /// callee.
361   unsigned BytesInStackArgArea = 0;
362 
363   bool ReturnsVoid = true;
364 
365   // A pair of default/requested minimum/maximum flat work group sizes.
366   // Minimum - first, maximum - second.
367   std::pair<unsigned, unsigned> FlatWorkGroupSizes = {0, 0};
368 
369   // A pair of default/requested minimum/maximum number of waves per execution
370   // unit. Minimum - first, maximum - second.
371   std::pair<unsigned, unsigned> WavesPerEU = {0, 0};
372 
373   DenseMap<const Value *,
374            std::unique_ptr<const AMDGPUBufferPseudoSourceValue>> BufferPSVs;
375   DenseMap<const Value *,
376            std::unique_ptr<const AMDGPUImagePseudoSourceValue>> ImagePSVs;
377   std::unique_ptr<const AMDGPUGWSResourcePseudoSourceValue> GWSResourcePSV;
378 
379 private:
380   unsigned LDSWaveSpillSize = 0;
381   unsigned NumUserSGPRs = 0;
382   unsigned NumSystemSGPRs = 0;
383 
384   bool HasSpilledSGPRs = false;
385   bool HasSpilledVGPRs = false;
386   bool HasNonSpillStackObjects = false;
387   bool IsStackRealigned = false;
388 
389   unsigned NumSpilledSGPRs = 0;
390   unsigned NumSpilledVGPRs = 0;
391 
392   // Feature bits required for inputs passed in user SGPRs.
393   bool PrivateSegmentBuffer : 1;
394   bool DispatchPtr : 1;
395   bool QueuePtr : 1;
396   bool KernargSegmentPtr : 1;
397   bool DispatchID : 1;
398   bool FlatScratchInit : 1;
399 
400   // Feature bits required for inputs passed in system SGPRs.
401   bool WorkGroupIDX : 1; // Always initialized.
402   bool WorkGroupIDY : 1;
403   bool WorkGroupIDZ : 1;
404   bool WorkGroupInfo : 1;
405   bool PrivateSegmentWaveByteOffset : 1;
406 
407   bool WorkItemIDX : 1; // Always initialized.
408   bool WorkItemIDY : 1;
409   bool WorkItemIDZ : 1;
410 
411   // Private memory buffer
412   // Compute directly in sgpr[0:1]
413   // Other shaders indirect 64-bits at sgpr[0:1]
414   bool ImplicitBufferPtr : 1;
415 
416   // Pointer to where the ABI inserts special kernel arguments separate from the
417   // user arguments. This is an offset from the KernargSegmentPtr.
418   bool ImplicitArgPtr : 1;
419 
420   // The hard-wired high half of the address of the global information table
421   // for AMDPAL OS type. 0xffffffff represents no hard-wired high half, since
422   // current hardware only allows a 16 bit value.
423   unsigned GITPtrHigh;
424 
425   unsigned HighBitsOf32BitAddress;
426   unsigned GDSSize;
427 
428   // Current recorded maximum possible occupancy.
429   unsigned Occupancy;
430 
431   MCPhysReg getNextUserSGPR() const;
432 
433   MCPhysReg getNextSystemSGPR() const;
434 
435 public:
436   struct SpilledReg {
437     Register VGPR;
438     int Lane = -1;
439 
440     SpilledReg() = default;
441     SpilledReg(Register R, int L) : VGPR (R), Lane (L) {}
442 
443     bool hasLane() { return Lane != -1;}
444     bool hasReg() { return VGPR != 0;}
445   };
446 
447   struct SGPRSpillVGPRCSR {
448     // VGPR used for SGPR spills
449     Register VGPR;
450 
451     // If the VGPR is a CSR, the stack slot used to save/restore it in the
452     // prolog/epilog.
453     Optional<int> FI;
454 
455     SGPRSpillVGPRCSR(Register V, Optional<int> F) : VGPR(V), FI(F) {}
456   };
457 
458   struct VGPRSpillToAGPR {
459     SmallVector<MCPhysReg, 32> Lanes;
460     bool FullyAllocated = false;
461   };
462 
463   SparseBitVector<> WWMReservedRegs;
464 
465   void ReserveWWMRegister(Register Reg) { WWMReservedRegs.set(Reg); }
466 
467 private:
468   // Track VGPR + wave index for each subregister of the SGPR spilled to
469   // frameindex key.
470   DenseMap<int, std::vector<SpilledReg>> SGPRToVGPRSpills;
471   unsigned NumVGPRSpillLanes = 0;
472   SmallVector<SGPRSpillVGPRCSR, 2> SpillVGPRs;
473 
474   DenseMap<int, VGPRSpillToAGPR> VGPRToAGPRSpills;
475 
476   // AGPRs used for VGPR spills.
477   SmallVector<MCPhysReg, 32> SpillAGPR;
478 
479   // VGPRs used for AGPR spills.
480   SmallVector<MCPhysReg, 32> SpillVGPR;
481 
482 public: // FIXME
483   /// If this is set, an SGPR used for save/restore of the register used for the
484   /// frame pointer.
485   Register SGPRForFPSaveRestoreCopy;
486   Optional<int> FramePointerSaveIndex;
487 
488 public:
489   SIMachineFunctionInfo(const MachineFunction &MF);
490 
491   bool initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI);
492 
493   ArrayRef<SpilledReg> getSGPRToVGPRSpills(int FrameIndex) const {
494     auto I = SGPRToVGPRSpills.find(FrameIndex);
495     return (I == SGPRToVGPRSpills.end()) ?
496       ArrayRef<SpilledReg>() : makeArrayRef(I->second);
497   }
498 
499   ArrayRef<SGPRSpillVGPRCSR> getSGPRSpillVGPRs() const {
500     return SpillVGPRs;
501   }
502 
503   ArrayRef<MCPhysReg> getAGPRSpillVGPRs() const {
504     return SpillAGPR;
505   }
506 
507   ArrayRef<MCPhysReg> getVGPRSpillAGPRs() const {
508     return SpillVGPR;
509   }
510 
511   MCPhysReg getVGPRToAGPRSpill(int FrameIndex, unsigned Lane) const {
512     auto I = VGPRToAGPRSpills.find(FrameIndex);
513     return (I == VGPRToAGPRSpills.end()) ? (MCPhysReg)AMDGPU::NoRegister
514                                          : I->second.Lanes[Lane];
515   }
516 
517   bool haveFreeLanesForSGPRSpill(const MachineFunction &MF,
518                                  unsigned NumLane) const;
519   bool allocateSGPRSpillToVGPR(MachineFunction &MF, int FI);
520   bool allocateVGPRSpillToAGPR(MachineFunction &MF, int FI, bool isAGPRtoVGPR);
521   void removeDeadFrameIndices(MachineFrameInfo &MFI);
522 
523   bool hasCalculatedTID() const { return TIDReg != 0; };
524   Register getTIDReg() const { return TIDReg; };
525   void setTIDReg(Register Reg) { TIDReg = Reg; }
526 
527   unsigned getBytesInStackArgArea() const {
528     return BytesInStackArgArea;
529   }
530 
531   void setBytesInStackArgArea(unsigned Bytes) {
532     BytesInStackArgArea = Bytes;
533   }
534 
535   // Add user SGPRs.
536   Register addPrivateSegmentBuffer(const SIRegisterInfo &TRI);
537   Register addDispatchPtr(const SIRegisterInfo &TRI);
538   Register addQueuePtr(const SIRegisterInfo &TRI);
539   Register addKernargSegmentPtr(const SIRegisterInfo &TRI);
540   Register addDispatchID(const SIRegisterInfo &TRI);
541   Register addFlatScratchInit(const SIRegisterInfo &TRI);
542   Register addImplicitBufferPtr(const SIRegisterInfo &TRI);
543 
544   // Add system SGPRs.
545   Register addWorkGroupIDX() {
546     ArgInfo.WorkGroupIDX = ArgDescriptor::createRegister(getNextSystemSGPR());
547     NumSystemSGPRs += 1;
548     return ArgInfo.WorkGroupIDX.getRegister();
549   }
550 
551   Register addWorkGroupIDY() {
552     ArgInfo.WorkGroupIDY = ArgDescriptor::createRegister(getNextSystemSGPR());
553     NumSystemSGPRs += 1;
554     return ArgInfo.WorkGroupIDY.getRegister();
555   }
556 
557   Register addWorkGroupIDZ() {
558     ArgInfo.WorkGroupIDZ = ArgDescriptor::createRegister(getNextSystemSGPR());
559     NumSystemSGPRs += 1;
560     return ArgInfo.WorkGroupIDZ.getRegister();
561   }
562 
563   Register addWorkGroupInfo() {
564     ArgInfo.WorkGroupInfo = ArgDescriptor::createRegister(getNextSystemSGPR());
565     NumSystemSGPRs += 1;
566     return ArgInfo.WorkGroupInfo.getRegister();
567   }
568 
569   // Add special VGPR inputs
570   void setWorkItemIDX(ArgDescriptor Arg) {
571     ArgInfo.WorkItemIDX = Arg;
572   }
573 
574   void setWorkItemIDY(ArgDescriptor Arg) {
575     ArgInfo.WorkItemIDY = Arg;
576   }
577 
578   void setWorkItemIDZ(ArgDescriptor Arg) {
579     ArgInfo.WorkItemIDZ = Arg;
580   }
581 
582   Register addPrivateSegmentWaveByteOffset() {
583     ArgInfo.PrivateSegmentWaveByteOffset
584       = ArgDescriptor::createRegister(getNextSystemSGPR());
585     NumSystemSGPRs += 1;
586     return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
587   }
588 
589   void setPrivateSegmentWaveByteOffset(Register Reg) {
590     ArgInfo.PrivateSegmentWaveByteOffset = ArgDescriptor::createRegister(Reg);
591   }
592 
593   bool hasPrivateSegmentBuffer() const {
594     return PrivateSegmentBuffer;
595   }
596 
597   bool hasDispatchPtr() const {
598     return DispatchPtr;
599   }
600 
601   bool hasQueuePtr() const {
602     return QueuePtr;
603   }
604 
605   bool hasKernargSegmentPtr() const {
606     return KernargSegmentPtr;
607   }
608 
609   bool hasDispatchID() const {
610     return DispatchID;
611   }
612 
613   bool hasFlatScratchInit() const {
614     return FlatScratchInit;
615   }
616 
617   bool hasWorkGroupIDX() const {
618     return WorkGroupIDX;
619   }
620 
621   bool hasWorkGroupIDY() const {
622     return WorkGroupIDY;
623   }
624 
625   bool hasWorkGroupIDZ() const {
626     return WorkGroupIDZ;
627   }
628 
629   bool hasWorkGroupInfo() const {
630     return WorkGroupInfo;
631   }
632 
633   bool hasPrivateSegmentWaveByteOffset() const {
634     return PrivateSegmentWaveByteOffset;
635   }
636 
637   bool hasWorkItemIDX() const {
638     return WorkItemIDX;
639   }
640 
641   bool hasWorkItemIDY() const {
642     return WorkItemIDY;
643   }
644 
645   bool hasWorkItemIDZ() const {
646     return WorkItemIDZ;
647   }
648 
649   bool hasImplicitArgPtr() const {
650     return ImplicitArgPtr;
651   }
652 
653   bool hasImplicitBufferPtr() const {
654     return ImplicitBufferPtr;
655   }
656 
657   AMDGPUFunctionArgInfo &getArgInfo() {
658     return ArgInfo;
659   }
660 
661   const AMDGPUFunctionArgInfo &getArgInfo() const {
662     return ArgInfo;
663   }
664 
665   std::pair<const ArgDescriptor *, const TargetRegisterClass *>
666   getPreloadedValue(AMDGPUFunctionArgInfo::PreloadedValue Value) const {
667     return ArgInfo.getPreloadedValue(Value);
668   }
669 
670   Register getPreloadedReg(AMDGPUFunctionArgInfo::PreloadedValue Value) const {
671     auto Arg = ArgInfo.getPreloadedValue(Value).first;
672     return Arg ? Arg->getRegister() : Register();
673   }
674 
675   unsigned getGITPtrHigh() const {
676     return GITPtrHigh;
677   }
678 
679   uint32_t get32BitAddressHighBits() const {
680     return HighBitsOf32BitAddress;
681   }
682 
683   unsigned getGDSSize() const {
684     return GDSSize;
685   }
686 
687   unsigned getNumUserSGPRs() const {
688     return NumUserSGPRs;
689   }
690 
691   unsigned getNumPreloadedSGPRs() const {
692     return NumUserSGPRs + NumSystemSGPRs;
693   }
694 
695   Register getPrivateSegmentWaveByteOffsetSystemSGPR() const {
696     return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
697   }
698 
699   /// Returns the physical register reserved for use as the resource
700   /// descriptor for scratch accesses.
701   Register getScratchRSrcReg() const {
702     return ScratchRSrcReg;
703   }
704 
705   void setScratchRSrcReg(Register Reg) {
706     assert(Reg != 0 && "Should never be unset");
707     ScratchRSrcReg = Reg;
708   }
709 
710   Register getFrameOffsetReg() const {
711     return FrameOffsetReg;
712   }
713 
714   void setFrameOffsetReg(Register Reg) {
715     assert(Reg != 0 && "Should never be unset");
716     FrameOffsetReg = Reg;
717   }
718 
719   void setStackPtrOffsetReg(Register Reg) {
720     assert(Reg != 0 && "Should never be unset");
721     StackPtrOffsetReg = Reg;
722   }
723 
724   // Note the unset value for this is AMDGPU::SP_REG rather than
725   // NoRegister. This is mostly a workaround for MIR tests where state that
726   // can't be directly computed from the function is not preserved in serialized
727   // MIR.
728   Register getStackPtrOffsetReg() const {
729     return StackPtrOffsetReg;
730   }
731 
732   Register getQueuePtrUserSGPR() const {
733     return ArgInfo.QueuePtr.getRegister();
734   }
735 
736   Register getImplicitBufferPtrUserSGPR() const {
737     return ArgInfo.ImplicitBufferPtr.getRegister();
738   }
739 
740   bool hasSpilledSGPRs() const {
741     return HasSpilledSGPRs;
742   }
743 
744   void setHasSpilledSGPRs(bool Spill = true) {
745     HasSpilledSGPRs = Spill;
746   }
747 
748   bool hasSpilledVGPRs() const {
749     return HasSpilledVGPRs;
750   }
751 
752   void setHasSpilledVGPRs(bool Spill = true) {
753     HasSpilledVGPRs = Spill;
754   }
755 
756   bool hasNonSpillStackObjects() const {
757     return HasNonSpillStackObjects;
758   }
759 
760   void setHasNonSpillStackObjects(bool StackObject = true) {
761     HasNonSpillStackObjects = StackObject;
762   }
763 
764   bool isStackRealigned() const {
765     return IsStackRealigned;
766   }
767 
768   void setIsStackRealigned(bool Realigned = true) {
769     IsStackRealigned = Realigned;
770   }
771 
772   unsigned getNumSpilledSGPRs() const {
773     return NumSpilledSGPRs;
774   }
775 
776   unsigned getNumSpilledVGPRs() const {
777     return NumSpilledVGPRs;
778   }
779 
780   void addToSpilledSGPRs(unsigned num) {
781     NumSpilledSGPRs += num;
782   }
783 
784   void addToSpilledVGPRs(unsigned num) {
785     NumSpilledVGPRs += num;
786   }
787 
788   unsigned getPSInputAddr() const {
789     return PSInputAddr;
790   }
791 
792   unsigned getPSInputEnable() const {
793     return PSInputEnable;
794   }
795 
796   bool isPSInputAllocated(unsigned Index) const {
797     return PSInputAddr & (1 << Index);
798   }
799 
800   void markPSInputAllocated(unsigned Index) {
801     PSInputAddr |= 1 << Index;
802   }
803 
804   void markPSInputEnabled(unsigned Index) {
805     PSInputEnable |= 1 << Index;
806   }
807 
808   bool returnsVoid() const {
809     return ReturnsVoid;
810   }
811 
812   void setIfReturnsVoid(bool Value) {
813     ReturnsVoid = Value;
814   }
815 
816   /// \returns A pair of default/requested minimum/maximum flat work group sizes
817   /// for this function.
818   std::pair<unsigned, unsigned> getFlatWorkGroupSizes() const {
819     return FlatWorkGroupSizes;
820   }
821 
822   /// \returns Default/requested minimum flat work group size for this function.
823   unsigned getMinFlatWorkGroupSize() const {
824     return FlatWorkGroupSizes.first;
825   }
826 
827   /// \returns Default/requested maximum flat work group size for this function.
828   unsigned getMaxFlatWorkGroupSize() const {
829     return FlatWorkGroupSizes.second;
830   }
831 
832   /// \returns A pair of default/requested minimum/maximum number of waves per
833   /// execution unit.
834   std::pair<unsigned, unsigned> getWavesPerEU() const {
835     return WavesPerEU;
836   }
837 
838   /// \returns Default/requested minimum number of waves per execution unit.
839   unsigned getMinWavesPerEU() const {
840     return WavesPerEU.first;
841   }
842 
843   /// \returns Default/requested maximum number of waves per execution unit.
844   unsigned getMaxWavesPerEU() const {
845     return WavesPerEU.second;
846   }
847 
848   /// \returns SGPR used for \p Dim's work group ID.
849   Register getWorkGroupIDSGPR(unsigned Dim) const {
850     switch (Dim) {
851     case 0:
852       assert(hasWorkGroupIDX());
853       return ArgInfo.WorkGroupIDX.getRegister();
854     case 1:
855       assert(hasWorkGroupIDY());
856       return ArgInfo.WorkGroupIDY.getRegister();
857     case 2:
858       assert(hasWorkGroupIDZ());
859       return ArgInfo.WorkGroupIDZ.getRegister();
860     }
861     llvm_unreachable("unexpected dimension");
862   }
863 
864   unsigned getLDSWaveSpillSize() const {
865     return LDSWaveSpillSize;
866   }
867 
868   const AMDGPUBufferPseudoSourceValue *getBufferPSV(const SIInstrInfo &TII,
869                                                     const Value *BufferRsrc) {
870     assert(BufferRsrc);
871     auto PSV = BufferPSVs.try_emplace(
872       BufferRsrc,
873       std::make_unique<AMDGPUBufferPseudoSourceValue>(TII));
874     return PSV.first->second.get();
875   }
876 
877   const AMDGPUImagePseudoSourceValue *getImagePSV(const SIInstrInfo &TII,
878                                                   const Value *ImgRsrc) {
879     assert(ImgRsrc);
880     auto PSV = ImagePSVs.try_emplace(
881       ImgRsrc,
882       std::make_unique<AMDGPUImagePseudoSourceValue>(TII));
883     return PSV.first->second.get();
884   }
885 
886   const AMDGPUGWSResourcePseudoSourceValue *getGWSPSV(const SIInstrInfo &TII) {
887     if (!GWSResourcePSV) {
888       GWSResourcePSV =
889           std::make_unique<AMDGPUGWSResourcePseudoSourceValue>(TII);
890     }
891 
892     return GWSResourcePSV.get();
893   }
894 
895   unsigned getOccupancy() const {
896     return Occupancy;
897   }
898 
899   unsigned getMinAllowedOccupancy() const {
900     if (!isMemoryBound() && !needsWaveLimiter())
901       return Occupancy;
902     return (Occupancy < 4) ? Occupancy : 4;
903   }
904 
905   void limitOccupancy(const MachineFunction &MF);
906 
907   void limitOccupancy(unsigned Limit) {
908     if (Occupancy > Limit)
909       Occupancy = Limit;
910   }
911 
912   void increaseOccupancy(const MachineFunction &MF, unsigned Limit) {
913     if (Occupancy < Limit)
914       Occupancy = Limit;
915     limitOccupancy(MF);
916   }
917 };
918 
919 } // end namespace llvm
920 
921 #endif // LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
922