xref: /llvm-project/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp (revision 0b43d573f54c16f8ccd231ae40a4704a93ab4aa1) 
1 //===- SIMachineFunctionInfo.cpp - SI Machine Function Info ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "SIMachineFunctionInfo.h"
10 #include "AMDGPUSubtarget.h"
11 #include "AMDGPUTargetMachine.h"
12 #include "GCNSubtarget.h"
13 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
14 #include "SIRegisterInfo.h"
15 #include "Utils/AMDGPUBaseInfo.h"
16 #include "llvm/CodeGen/LiveIntervals.h"
17 #include "llvm/CodeGen/MIRParser/MIParser.h"
18 #include "llvm/CodeGen/MachineBasicBlock.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/IR/DiagnosticInfo.h"
24 #include "llvm/IR/Function.h"
25 #include <cassert>
26 #include <optional>
27 #include <vector>
28 
29 enum { MAX_LANES = 64 };
30 
31 using namespace llvm;
32 
33 const GCNTargetMachine &getTM(const GCNSubtarget *STI) {
34   const SITargetLowering *TLI = STI->getTargetLowering();
35   return static_cast<const GCNTargetMachine &>(TLI->getTargetMachine());
36 }
37 
38 SIMachineFunctionInfo::SIMachineFunctionInfo(const Function &F,
39                                              const GCNSubtarget *STI)
40     : AMDGPUMachineFunction(F, *STI), Mode(F, *STI), GWSResourcePSV(getTM(STI)),
41       UserSGPRInfo(F, *STI), WorkGroupIDX(false), WorkGroupIDY(false),
42       WorkGroupIDZ(false), WorkGroupInfo(false), LDSKernelId(false),
43       PrivateSegmentWaveByteOffset(false), WorkItemIDX(false),
44       WorkItemIDY(false), WorkItemIDZ(false), ImplicitArgPtr(false),
45       GITPtrHigh(0xffffffff), HighBitsOf32BitAddress(0) {
46   const GCNSubtarget &ST = *static_cast<const GCNSubtarget *>(STI);
47   FlatWorkGroupSizes = ST.getFlatWorkGroupSizes(F);
48   WavesPerEU = ST.getWavesPerEU(F);
49   MaxNumWorkGroups = ST.getMaxNumWorkGroups(F);
50   assert(MaxNumWorkGroups.size() == 3);
51 
52   Occupancy = ST.computeOccupancy(F, getLDSSize());
53   CallingConv::ID CC = F.getCallingConv();
54 
55   VRegFlags.reserve(1024);
56 
57   const bool IsKernel = CC == CallingConv::AMDGPU_KERNEL ||
58                         CC == CallingConv::SPIR_KERNEL;
59 
60   if (IsKernel) {
61     WorkGroupIDX = true;
62     WorkItemIDX = true;
63   } else if (CC == CallingConv::AMDGPU_PS) {
64     PSInputAddr = AMDGPU::getInitialPSInputAddr(F);
65   }
66 
67   MayNeedAGPRs = ST.hasMAIInsts();
68 
69   if (AMDGPU::isChainCC(CC)) {
70     // Chain functions don't receive an SP from their caller, but are free to
71     // set one up. For now, we can use s32 to match what amdgpu_gfx functions
72     // would use if called, but this can be revisited.
73     // FIXME: Only reserve this if we actually need it.
74     StackPtrOffsetReg = AMDGPU::SGPR32;
75 
76     ScratchRSrcReg = AMDGPU::SGPR48_SGPR49_SGPR50_SGPR51;
77 
78     ArgInfo.PrivateSegmentBuffer =
79         ArgDescriptor::createRegister(ScratchRSrcReg);
80 
81     ImplicitArgPtr = false;
82   } else if (!isEntryFunction()) {
83     if (CC != CallingConv::AMDGPU_Gfx)
84       ArgInfo = AMDGPUArgumentUsageInfo::FixedABIFunctionInfo;
85 
86     FrameOffsetReg = AMDGPU::SGPR33;
87     StackPtrOffsetReg = AMDGPU::SGPR32;
88 
89     if (!ST.enableFlatScratch()) {
90       // Non-entry functions have no special inputs for now, other registers
91       // required for scratch access.
92       ScratchRSrcReg = AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3;
93 
94       ArgInfo.PrivateSegmentBuffer =
95         ArgDescriptor::createRegister(ScratchRSrcReg);
96     }
97 
98     if (!F.hasFnAttribute("amdgpu-no-implicitarg-ptr"))
99       ImplicitArgPtr = true;
100   } else {
101     ImplicitArgPtr = false;
102     MaxKernArgAlign = std::max(ST.getAlignmentForImplicitArgPtr(),
103                                MaxKernArgAlign);
104 
105     if (ST.hasGFX90AInsts() &&
106         ST.getMaxNumVGPRs(F) <= AMDGPU::VGPR_32RegClass.getNumRegs() &&
107         !mayUseAGPRs(F))
108       MayNeedAGPRs = false; // We will select all MAI with VGPR operands.
109   }
110 
111   if (!AMDGPU::isGraphics(CC) ||
112       ((CC == CallingConv::AMDGPU_CS || CC == CallingConv::AMDGPU_Gfx) &&
113        ST.hasArchitectedSGPRs())) {
114     if (IsKernel || !F.hasFnAttribute("amdgpu-no-workgroup-id-x"))
115       WorkGroupIDX = true;
116 
117     if (!F.hasFnAttribute("amdgpu-no-workgroup-id-y"))
118       WorkGroupIDY = true;
119 
120     if (!F.hasFnAttribute("amdgpu-no-workgroup-id-z"))
121       WorkGroupIDZ = true;
122   }
123 
124   if (!AMDGPU::isGraphics(CC)) {
125     if (IsKernel || !F.hasFnAttribute("amdgpu-no-workitem-id-x"))
126       WorkItemIDX = true;
127 
128     if (!F.hasFnAttribute("amdgpu-no-workitem-id-y") &&
129         ST.getMaxWorkitemID(F, 1) != 0)
130       WorkItemIDY = true;
131 
132     if (!F.hasFnAttribute("amdgpu-no-workitem-id-z") &&
133         ST.getMaxWorkitemID(F, 2) != 0)
134       WorkItemIDZ = true;
135 
136     if (!IsKernel && !F.hasFnAttribute("amdgpu-no-lds-kernel-id"))
137       LDSKernelId = true;
138   }
139 
140   if (isEntryFunction()) {
141     // X, XY, and XYZ are the only supported combinations, so make sure Y is
142     // enabled if Z is.
143     if (WorkItemIDZ)
144       WorkItemIDY = true;
145 
146     if (!ST.flatScratchIsArchitected()) {
147       PrivateSegmentWaveByteOffset = true;
148 
149       // HS and GS always have the scratch wave offset in SGPR5 on GFX9.
150       if (ST.getGeneration() >= AMDGPUSubtarget::GFX9 &&
151           (CC == CallingConv::AMDGPU_HS || CC == CallingConv::AMDGPU_GS))
152         ArgInfo.PrivateSegmentWaveByteOffset =
153             ArgDescriptor::createRegister(AMDGPU::SGPR5);
154     }
155   }
156 
157   Attribute A = F.getFnAttribute("amdgpu-git-ptr-high");
158   StringRef S = A.getValueAsString();
159   if (!S.empty())
160     S.consumeInteger(0, GITPtrHigh);
161 
162   A = F.getFnAttribute("amdgpu-32bit-address-high-bits");
163   S = A.getValueAsString();
164   if (!S.empty())
165     S.consumeInteger(0, HighBitsOf32BitAddress);
166 
167   // On GFX908, in order to guarantee copying between AGPRs, we need a scratch
168   // VGPR available at all times. For now, reserve highest available VGPR. After
169   // RA, shift it to the lowest available unused VGPR if the one exist.
170   if (ST.hasMAIInsts() && !ST.hasGFX90AInsts()) {
171     VGPRForAGPRCopy =
172         AMDGPU::VGPR_32RegClass.getRegister(ST.getMaxNumVGPRs(F) - 1);
173   }
174 }
175 
176 MachineFunctionInfo *SIMachineFunctionInfo::clone(
177     BumpPtrAllocator &Allocator, MachineFunction &DestMF,
178     const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
179     const {
180   return DestMF.cloneInfo<SIMachineFunctionInfo>(*this);
181 }
182 
183 void SIMachineFunctionInfo::limitOccupancy(const MachineFunction &MF) {
184   limitOccupancy(getMaxWavesPerEU());
185   const GCNSubtarget& ST = MF.getSubtarget<GCNSubtarget>();
186   limitOccupancy(ST.getOccupancyWithLocalMemSize(getLDSSize(),
187                  MF.getFunction()));
188 }
189 
190 Register SIMachineFunctionInfo::addPrivateSegmentBuffer(
191   const SIRegisterInfo &TRI) {
192   ArgInfo.PrivateSegmentBuffer =
193     ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
194     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SGPR_128RegClass));
195   NumUserSGPRs += 4;
196   return ArgInfo.PrivateSegmentBuffer.getRegister();
197 }
198 
199 Register SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) {
200   ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
201     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
202   NumUserSGPRs += 2;
203   return ArgInfo.DispatchPtr.getRegister();
204 }
205 
206 Register SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) {
207   ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
208     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
209   NumUserSGPRs += 2;
210   return ArgInfo.QueuePtr.getRegister();
211 }
212 
213 Register SIMachineFunctionInfo::addKernargSegmentPtr(const SIRegisterInfo &TRI) {
214   ArgInfo.KernargSegmentPtr
215     = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
216     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
217   NumUserSGPRs += 2;
218   return ArgInfo.KernargSegmentPtr.getRegister();
219 }
220 
221 Register SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) {
222   ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
223     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
224   NumUserSGPRs += 2;
225   return ArgInfo.DispatchID.getRegister();
226 }
227 
228 Register SIMachineFunctionInfo::addFlatScratchInit(const SIRegisterInfo &TRI) {
229   ArgInfo.FlatScratchInit = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
230     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
231   NumUserSGPRs += 2;
232   return ArgInfo.FlatScratchInit.getRegister();
233 }
234 
235 Register SIMachineFunctionInfo::addPrivateSegmentSize(const SIRegisterInfo &TRI) {
236   ArgInfo.PrivateSegmentSize = ArgDescriptor::createRegister(getNextUserSGPR());
237   NumUserSGPRs += 1;
238   return ArgInfo.PrivateSegmentSize.getRegister();
239 }
240 
241 Register SIMachineFunctionInfo::addImplicitBufferPtr(const SIRegisterInfo &TRI) {
242   ArgInfo.ImplicitBufferPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
243     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
244   NumUserSGPRs += 2;
245   return ArgInfo.ImplicitBufferPtr.getRegister();
246 }
247 
248 Register SIMachineFunctionInfo::addLDSKernelId() {
249   ArgInfo.LDSKernelId = ArgDescriptor::createRegister(getNextUserSGPR());
250   NumUserSGPRs += 1;
251   return ArgInfo.LDSKernelId.getRegister();
252 }
253 
254 SmallVectorImpl<MCRegister> *SIMachineFunctionInfo::addPreloadedKernArg(
255     const SIRegisterInfo &TRI, const TargetRegisterClass *RC,
256     unsigned AllocSizeDWord, int KernArgIdx, int PaddingSGPRs) {
257   assert(!ArgInfo.PreloadKernArgs.count(KernArgIdx) &&
258          "Preload kernel argument allocated twice.");
259   NumUserSGPRs += PaddingSGPRs;
260   // If the available register tuples are aligned with the kernarg to be
261   // preloaded use that register, otherwise we need to use a set of SGPRs and
262   // merge them.
263   Register PreloadReg =
264       TRI.getMatchingSuperReg(getNextUserSGPR(), AMDGPU::sub0, RC);
265   if (PreloadReg &&
266       (RC == &AMDGPU::SReg_32RegClass || RC == &AMDGPU::SReg_64RegClass)) {
267     ArgInfo.PreloadKernArgs[KernArgIdx].Regs.push_back(PreloadReg);
268     NumUserSGPRs += AllocSizeDWord;
269   } else {
270     for (unsigned I = 0; I < AllocSizeDWord; ++I) {
271       ArgInfo.PreloadKernArgs[KernArgIdx].Regs.push_back(getNextUserSGPR());
272       NumUserSGPRs++;
273     }
274   }
275 
276   // Track the actual number of SGPRs that HW will preload to.
277   UserSGPRInfo.allocKernargPreloadSGPRs(AllocSizeDWord + PaddingSGPRs);
278   return &ArgInfo.PreloadKernArgs[KernArgIdx].Regs;
279 }
280 
281 void SIMachineFunctionInfo::allocateWWMSpill(MachineFunction &MF, Register VGPR,
282                                              uint64_t Size, Align Alignment) {
283   // Skip if it is an entry function or the register is already added.
284   if (isEntryFunction() || WWMSpills.count(VGPR))
285     return;
286 
287   // Skip if this is a function with the amdgpu_cs_chain or
288   // amdgpu_cs_chain_preserve calling convention and this is a scratch register.
289   // We never need to allocate a spill for these because we don't even need to
290   // restore the inactive lanes for them (they're scratchier than the usual
291   // scratch registers).
292   if (isChainFunction() && SIRegisterInfo::isChainScratchRegister(VGPR))
293     return;
294 
295   WWMSpills.insert(std::make_pair(
296       VGPR, MF.getFrameInfo().CreateSpillStackObject(Size, Alignment)));
297 }
298 
299 // Separate out the callee-saved and scratch registers.
300 void SIMachineFunctionInfo::splitWWMSpillRegisters(
301     MachineFunction &MF,
302     SmallVectorImpl<std::pair<Register, int>> &CalleeSavedRegs,
303     SmallVectorImpl<std::pair<Register, int>> &ScratchRegs) const {
304   const MCPhysReg *CSRegs = MF.getRegInfo().getCalleeSavedRegs();
305   for (auto &Reg : WWMSpills) {
306     if (isCalleeSavedReg(CSRegs, Reg.first))
307       CalleeSavedRegs.push_back(Reg);
308     else
309       ScratchRegs.push_back(Reg);
310   }
311 }
312 
313 bool SIMachineFunctionInfo::isCalleeSavedReg(const MCPhysReg *CSRegs,
314                                              MCPhysReg Reg) const {
315   for (unsigned I = 0; CSRegs[I]; ++I) {
316     if (CSRegs[I] == Reg)
317       return true;
318   }
319 
320   return false;
321 }
322 
323 void SIMachineFunctionInfo::shiftSpillPhysVGPRsToLowestRange(
324     MachineFunction &MF) {
325   const SIRegisterInfo *TRI = MF.getSubtarget<GCNSubtarget>().getRegisterInfo();
326   MachineRegisterInfo &MRI = MF.getRegInfo();
327   for (unsigned I = 0, E = SpillPhysVGPRs.size(); I < E; ++I) {
328     Register Reg = SpillPhysVGPRs[I];
329     Register NewReg =
330         TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF);
331     if (!NewReg || NewReg >= Reg)
332       break;
333 
334     MRI.replaceRegWith(Reg, NewReg);
335 
336     // Update various tables with the new VGPR.
337     SpillPhysVGPRs[I] = NewReg;
338     WWMReservedRegs.remove(Reg);
339     WWMReservedRegs.insert(NewReg);
340     WWMSpills.insert(std::make_pair(NewReg, WWMSpills[Reg]));
341     WWMSpills.erase(Reg);
342 
343     for (MachineBasicBlock &MBB : MF) {
344       MBB.removeLiveIn(Reg);
345       MBB.sortUniqueLiveIns();
346     }
347   }
348 }
349 
350 bool SIMachineFunctionInfo::allocateVirtualVGPRForSGPRSpills(
351     MachineFunction &MF, int FI, unsigned LaneIndex) {
352   MachineRegisterInfo &MRI = MF.getRegInfo();
353   Register LaneVGPR;
354   if (!LaneIndex) {
355     LaneVGPR = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
356     SpillVGPRs.push_back(LaneVGPR);
357   } else {
358     LaneVGPR = SpillVGPRs.back();
359   }
360 
361   SGPRSpillsToVirtualVGPRLanes[FI].push_back(
362       SIRegisterInfo::SpilledReg(LaneVGPR, LaneIndex));
363   return true;
364 }
365 
366 bool SIMachineFunctionInfo::allocatePhysicalVGPRForSGPRSpills(
367     MachineFunction &MF, int FI, unsigned LaneIndex, bool IsPrologEpilog) {
368   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
369   const SIRegisterInfo *TRI = ST.getRegisterInfo();
370   MachineRegisterInfo &MRI = MF.getRegInfo();
371   Register LaneVGPR;
372   if (!LaneIndex) {
373     // Find the highest available register if called before RA to ensure the
374     // lowest registers are available for allocation. The LaneVGPR, in that
375     // case, will be shifted back to the lowest range after VGPR allocation.
376     LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF,
377                                        !IsPrologEpilog);
378     if (LaneVGPR == AMDGPU::NoRegister) {
379       // We have no VGPRs left for spilling SGPRs. Reset because we will not
380       // partially spill the SGPR to VGPRs.
381       SGPRSpillsToPhysicalVGPRLanes.erase(FI);
382       return false;
383     }
384 
385     allocateWWMSpill(MF, LaneVGPR);
386     reserveWWMRegister(LaneVGPR);
387     for (MachineBasicBlock &MBB : MF) {
388       MBB.addLiveIn(LaneVGPR);
389       MBB.sortUniqueLiveIns();
390     }
391     SpillPhysVGPRs.push_back(LaneVGPR);
392   } else {
393     LaneVGPR = SpillPhysVGPRs.back();
394   }
395 
396   SGPRSpillsToPhysicalVGPRLanes[FI].push_back(
397       SIRegisterInfo::SpilledReg(LaneVGPR, LaneIndex));
398   return true;
399 }
400 
401 bool SIMachineFunctionInfo::allocateSGPRSpillToVGPRLane(
402     MachineFunction &MF, int FI, bool SpillToPhysVGPRLane,
403     bool IsPrologEpilog) {
404   std::vector<SIRegisterInfo::SpilledReg> &SpillLanes =
405       SpillToPhysVGPRLane ? SGPRSpillsToPhysicalVGPRLanes[FI]
406                           : SGPRSpillsToVirtualVGPRLanes[FI];
407 
408   // This has already been allocated.
409   if (!SpillLanes.empty())
410     return true;
411 
412   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
413   MachineFrameInfo &FrameInfo = MF.getFrameInfo();
414   unsigned WaveSize = ST.getWavefrontSize();
415 
416   unsigned Size = FrameInfo.getObjectSize(FI);
417   unsigned NumLanes = Size / 4;
418 
419   if (NumLanes > WaveSize)
420     return false;
421 
422   assert(Size >= 4 && "invalid sgpr spill size");
423   assert(ST.getRegisterInfo()->spillSGPRToVGPR() &&
424          "not spilling SGPRs to VGPRs");
425 
426   unsigned &NumSpillLanes = SpillToPhysVGPRLane ? NumPhysicalVGPRSpillLanes
427                                                 : NumVirtualVGPRSpillLanes;
428 
429   for (unsigned I = 0; I < NumLanes; ++I, ++NumSpillLanes) {
430     unsigned LaneIndex = (NumSpillLanes % WaveSize);
431 
432     bool Allocated = SpillToPhysVGPRLane
433                          ? allocatePhysicalVGPRForSGPRSpills(MF, FI, LaneIndex,
434                                                              IsPrologEpilog)
435                          : allocateVirtualVGPRForSGPRSpills(MF, FI, LaneIndex);
436     if (!Allocated) {
437       NumSpillLanes -= I;
438       return false;
439     }
440   }
441 
442   return true;
443 }
444 
445 /// Reserve AGPRs or VGPRs to support spilling for FrameIndex \p FI.
446 /// Either AGPR is spilled to VGPR to vice versa.
447 /// Returns true if a \p FI can be eliminated completely.
448 bool SIMachineFunctionInfo::allocateVGPRSpillToAGPR(MachineFunction &MF,
449                                                     int FI,
450                                                     bool isAGPRtoVGPR) {
451   MachineRegisterInfo &MRI = MF.getRegInfo();
452   MachineFrameInfo &FrameInfo = MF.getFrameInfo();
453   const GCNSubtarget &ST =  MF.getSubtarget<GCNSubtarget>();
454 
455   assert(ST.hasMAIInsts() && FrameInfo.isSpillSlotObjectIndex(FI));
456 
457   auto &Spill = VGPRToAGPRSpills[FI];
458 
459   // This has already been allocated.
460   if (!Spill.Lanes.empty())
461     return Spill.FullyAllocated;
462 
463   unsigned Size = FrameInfo.getObjectSize(FI);
464   unsigned NumLanes = Size / 4;
465   Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister);
466 
467   const TargetRegisterClass &RC =
468       isAGPRtoVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::AGPR_32RegClass;
469   auto Regs = RC.getRegisters();
470 
471   auto &SpillRegs = isAGPRtoVGPR ? SpillAGPR : SpillVGPR;
472   const SIRegisterInfo *TRI = ST.getRegisterInfo();
473   Spill.FullyAllocated = true;
474 
475   // FIXME: Move allocation logic out of MachineFunctionInfo and initialize
476   // once.
477   BitVector OtherUsedRegs;
478   OtherUsedRegs.resize(TRI->getNumRegs());
479 
480   const uint32_t *CSRMask =
481       TRI->getCallPreservedMask(MF, MF.getFunction().getCallingConv());
482   if (CSRMask)
483     OtherUsedRegs.setBitsInMask(CSRMask);
484 
485   // TODO: Should include register tuples, but doesn't matter with current
486   // usage.
487   for (MCPhysReg Reg : SpillAGPR)
488     OtherUsedRegs.set(Reg);
489   for (MCPhysReg Reg : SpillVGPR)
490     OtherUsedRegs.set(Reg);
491 
492   SmallVectorImpl<MCPhysReg>::const_iterator NextSpillReg = Regs.begin();
493   for (int I = NumLanes - 1; I >= 0; --I) {
494     NextSpillReg = std::find_if(
495         NextSpillReg, Regs.end(), [&MRI, &OtherUsedRegs](MCPhysReg Reg) {
496           return MRI.isAllocatable(Reg) && !MRI.isPhysRegUsed(Reg) &&
497                  !OtherUsedRegs[Reg];
498         });
499 
500     if (NextSpillReg == Regs.end()) { // Registers exhausted
501       Spill.FullyAllocated = false;
502       break;
503     }
504 
505     OtherUsedRegs.set(*NextSpillReg);
506     SpillRegs.push_back(*NextSpillReg);
507     MRI.reserveReg(*NextSpillReg, TRI);
508     Spill.Lanes[I] = *NextSpillReg++;
509   }
510 
511   return Spill.FullyAllocated;
512 }
513 
514 bool SIMachineFunctionInfo::removeDeadFrameIndices(
515     MachineFrameInfo &MFI, bool ResetSGPRSpillStackIDs) {
516   // Remove dead frame indices from function frame, however keep FP & BP since
517   // spills for them haven't been inserted yet. And also make sure to remove the
518   // frame indices from `SGPRSpillsToVirtualVGPRLanes` data structure,
519   // otherwise, it could result in an unexpected side effect and bug, in case of
520   // any re-mapping of freed frame indices by later pass(es) like "stack slot
521   // coloring".
522   for (auto &R : make_early_inc_range(SGPRSpillsToVirtualVGPRLanes)) {
523     MFI.RemoveStackObject(R.first);
524     SGPRSpillsToVirtualVGPRLanes.erase(R.first);
525   }
526 
527   // Remove the dead frame indices of CSR SGPRs which are spilled to physical
528   // VGPR lanes during SILowerSGPRSpills pass.
529   if (!ResetSGPRSpillStackIDs) {
530     for (auto &R : make_early_inc_range(SGPRSpillsToPhysicalVGPRLanes)) {
531       MFI.RemoveStackObject(R.first);
532       SGPRSpillsToPhysicalVGPRLanes.erase(R.first);
533     }
534   }
535   bool HaveSGPRToMemory = false;
536 
537   if (ResetSGPRSpillStackIDs) {
538     // All other SGPRs must be allocated on the default stack, so reset the
539     // stack ID.
540     for (int I = MFI.getObjectIndexBegin(), E = MFI.getObjectIndexEnd(); I != E;
541          ++I) {
542       if (!checkIndexInPrologEpilogSGPRSpills(I)) {
543         if (MFI.getStackID(I) == TargetStackID::SGPRSpill) {
544           MFI.setStackID(I, TargetStackID::Default);
545           HaveSGPRToMemory = true;
546         }
547       }
548     }
549   }
550 
551   for (auto &R : VGPRToAGPRSpills) {
552     if (R.second.IsDead)
553       MFI.RemoveStackObject(R.first);
554   }
555 
556   return HaveSGPRToMemory;
557 }
558 
559 int SIMachineFunctionInfo::getScavengeFI(MachineFrameInfo &MFI,
560                                          const SIRegisterInfo &TRI) {
561   if (ScavengeFI)
562     return *ScavengeFI;
563 
564   ScavengeFI =
565       MFI.CreateStackObject(TRI.getSpillSize(AMDGPU::SGPR_32RegClass),
566                             TRI.getSpillAlign(AMDGPU::SGPR_32RegClass), false);
567   return *ScavengeFI;
568 }
569 
570 MCPhysReg SIMachineFunctionInfo::getNextUserSGPR() const {
571   assert(NumSystemSGPRs == 0 && "System SGPRs must be added after user SGPRs");
572   return AMDGPU::SGPR0 + NumUserSGPRs;
573 }
574 
575 MCPhysReg SIMachineFunctionInfo::getNextSystemSGPR() const {
576   return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs;
577 }
578 
579 void SIMachineFunctionInfo::MRI_NoteNewVirtualRegister(Register Reg) {
580   VRegFlags.grow(Reg);
581 }
582 
583 void SIMachineFunctionInfo::MRI_NoteCloneVirtualRegister(Register NewReg,
584                                                          Register SrcReg) {
585   VRegFlags.grow(NewReg);
586   VRegFlags[NewReg] = VRegFlags[SrcReg];
587 }
588 
589 Register
590 SIMachineFunctionInfo::getGITPtrLoReg(const MachineFunction &MF) const {
591   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
592   if (!ST.isAmdPalOS())
593     return Register();
594   Register GitPtrLo = AMDGPU::SGPR0; // Low GIT address passed in
595   if (ST.hasMergedShaders()) {
596     switch (MF.getFunction().getCallingConv()) {
597     case CallingConv::AMDGPU_HS:
598     case CallingConv::AMDGPU_GS:
599       // Low GIT address is passed in s8 rather than s0 for an LS+HS or
600       // ES+GS merged shader on gfx9+.
601       GitPtrLo = AMDGPU::SGPR8;
602       return GitPtrLo;
603     default:
604       return GitPtrLo;
605     }
606   }
607   return GitPtrLo;
608 }
609 
610 static yaml::StringValue regToString(Register Reg,
611                                      const TargetRegisterInfo &TRI) {
612   yaml::StringValue Dest;
613   {
614     raw_string_ostream OS(Dest.Value);
615     OS << printReg(Reg, &TRI);
616   }
617   return Dest;
618 }
619 
620 static std::optional<yaml::SIArgumentInfo>
621 convertArgumentInfo(const AMDGPUFunctionArgInfo &ArgInfo,
622                     const TargetRegisterInfo &TRI) {
623   yaml::SIArgumentInfo AI;
624 
625   auto convertArg = [&](std::optional<yaml::SIArgument> &A,
626                         const ArgDescriptor &Arg) {
627     if (!Arg)
628       return false;
629 
630     // Create a register or stack argument.
631     yaml::SIArgument SA = yaml::SIArgument::createArgument(Arg.isRegister());
632     if (Arg.isRegister()) {
633       raw_string_ostream OS(SA.RegisterName.Value);
634       OS << printReg(Arg.getRegister(), &TRI);
635     } else
636       SA.StackOffset = Arg.getStackOffset();
637     // Check and update the optional mask.
638     if (Arg.isMasked())
639       SA.Mask = Arg.getMask();
640 
641     A = SA;
642     return true;
643   };
644 
645   // TODO: Need to serialize kernarg preloads.
646   bool Any = false;
647   Any |= convertArg(AI.PrivateSegmentBuffer, ArgInfo.PrivateSegmentBuffer);
648   Any |= convertArg(AI.DispatchPtr, ArgInfo.DispatchPtr);
649   Any |= convertArg(AI.QueuePtr, ArgInfo.QueuePtr);
650   Any |= convertArg(AI.KernargSegmentPtr, ArgInfo.KernargSegmentPtr);
651   Any |= convertArg(AI.DispatchID, ArgInfo.DispatchID);
652   Any |= convertArg(AI.FlatScratchInit, ArgInfo.FlatScratchInit);
653   Any |= convertArg(AI.LDSKernelId, ArgInfo.LDSKernelId);
654   Any |= convertArg(AI.PrivateSegmentSize, ArgInfo.PrivateSegmentSize);
655   Any |= convertArg(AI.WorkGroupIDX, ArgInfo.WorkGroupIDX);
656   Any |= convertArg(AI.WorkGroupIDY, ArgInfo.WorkGroupIDY);
657   Any |= convertArg(AI.WorkGroupIDZ, ArgInfo.WorkGroupIDZ);
658   Any |= convertArg(AI.WorkGroupInfo, ArgInfo.WorkGroupInfo);
659   Any |= convertArg(AI.PrivateSegmentWaveByteOffset,
660                     ArgInfo.PrivateSegmentWaveByteOffset);
661   Any |= convertArg(AI.ImplicitArgPtr, ArgInfo.ImplicitArgPtr);
662   Any |= convertArg(AI.ImplicitBufferPtr, ArgInfo.ImplicitBufferPtr);
663   Any |= convertArg(AI.WorkItemIDX, ArgInfo.WorkItemIDX);
664   Any |= convertArg(AI.WorkItemIDY, ArgInfo.WorkItemIDY);
665   Any |= convertArg(AI.WorkItemIDZ, ArgInfo.WorkItemIDZ);
666 
667   if (Any)
668     return AI;
669 
670   return std::nullopt;
671 }
672 
673 yaml::SIMachineFunctionInfo::SIMachineFunctionInfo(
674     const llvm::SIMachineFunctionInfo &MFI, const TargetRegisterInfo &TRI,
675     const llvm::MachineFunction &MF)
676     : ExplicitKernArgSize(MFI.getExplicitKernArgSize()),
677       MaxKernArgAlign(MFI.getMaxKernArgAlign()), LDSSize(MFI.getLDSSize()),
678       GDSSize(MFI.getGDSSize()),
679       DynLDSAlign(MFI.getDynLDSAlign()), IsEntryFunction(MFI.isEntryFunction()),
680       NoSignedZerosFPMath(MFI.hasNoSignedZerosFPMath()),
681       MemoryBound(MFI.isMemoryBound()), WaveLimiter(MFI.needsWaveLimiter()),
682       HasSpilledSGPRs(MFI.hasSpilledSGPRs()),
683       HasSpilledVGPRs(MFI.hasSpilledVGPRs()),
684       HighBitsOf32BitAddress(MFI.get32BitAddressHighBits()),
685       Occupancy(MFI.getOccupancy()),
686       ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)),
687       FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)),
688       StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)),
689       BytesInStackArgArea(MFI.getBytesInStackArgArea()),
690       ReturnsVoid(MFI.returnsVoid()),
691       ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)),
692       PSInputAddr(MFI.getPSInputAddr()),
693       PSInputEnable(MFI.getPSInputEnable()),
694       Mode(MFI.getMode()) {
695   for (Register Reg : MFI.getWWMReservedRegs())
696     WWMReservedRegs.push_back(regToString(Reg, TRI));
697 
698   if (MFI.getLongBranchReservedReg())
699     LongBranchReservedReg = regToString(MFI.getLongBranchReservedReg(), TRI);
700   if (MFI.getVGPRForAGPRCopy())
701     VGPRForAGPRCopy = regToString(MFI.getVGPRForAGPRCopy(), TRI);
702 
703   if (MFI.getSGPRForEXECCopy())
704     SGPRForEXECCopy = regToString(MFI.getSGPRForEXECCopy(), TRI);
705 
706   auto SFI = MFI.getOptionalScavengeFI();
707   if (SFI)
708     ScavengeFI = yaml::FrameIndex(*SFI, MF.getFrameInfo());
709 }
710 
711 void yaml::SIMachineFunctionInfo::mappingImpl(yaml::IO &YamlIO) {
712   MappingTraits<SIMachineFunctionInfo>::mapping(YamlIO, *this);
713 }
714 
715 bool SIMachineFunctionInfo::initializeBaseYamlFields(
716     const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF,
717     PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) {
718   ExplicitKernArgSize = YamlMFI.ExplicitKernArgSize;
719   MaxKernArgAlign = YamlMFI.MaxKernArgAlign;
720   LDSSize = YamlMFI.LDSSize;
721   GDSSize = YamlMFI.GDSSize;
722   DynLDSAlign = YamlMFI.DynLDSAlign;
723   PSInputAddr = YamlMFI.PSInputAddr;
724   PSInputEnable = YamlMFI.PSInputEnable;
725   HighBitsOf32BitAddress = YamlMFI.HighBitsOf32BitAddress;
726   Occupancy = YamlMFI.Occupancy;
727   IsEntryFunction = YamlMFI.IsEntryFunction;
728   NoSignedZerosFPMath = YamlMFI.NoSignedZerosFPMath;
729   MemoryBound = YamlMFI.MemoryBound;
730   WaveLimiter = YamlMFI.WaveLimiter;
731   HasSpilledSGPRs = YamlMFI.HasSpilledSGPRs;
732   HasSpilledVGPRs = YamlMFI.HasSpilledVGPRs;
733   BytesInStackArgArea = YamlMFI.BytesInStackArgArea;
734   ReturnsVoid = YamlMFI.ReturnsVoid;
735 
736   if (YamlMFI.ScavengeFI) {
737     auto FIOrErr = YamlMFI.ScavengeFI->getFI(MF.getFrameInfo());
738     if (!FIOrErr) {
739       // Create a diagnostic for a the frame index.
740       const MemoryBuffer &Buffer =
741           *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
742 
743       Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1, 1,
744                            SourceMgr::DK_Error, toString(FIOrErr.takeError()),
745                            "", std::nullopt, std::nullopt);
746       SourceRange = YamlMFI.ScavengeFI->SourceRange;
747       return true;
748     }
749     ScavengeFI = *FIOrErr;
750   } else {
751     ScavengeFI = std::nullopt;
752   }
753   return false;
754 }
755 
756 bool SIMachineFunctionInfo::mayUseAGPRs(const Function &F) const {
757   return !F.hasFnAttribute("amdgpu-no-agpr");
758 }
759 
760 bool SIMachineFunctionInfo::usesAGPRs(const MachineFunction &MF) const {
761   if (UsesAGPRs)
762     return *UsesAGPRs;
763 
764   if (!mayNeedAGPRs()) {
765     UsesAGPRs = false;
766     return false;
767   }
768 
769   if (!AMDGPU::isEntryFunctionCC(MF.getFunction().getCallingConv()) ||
770       MF.getFrameInfo().hasCalls()) {
771     UsesAGPRs = true;
772     return true;
773   }
774 
775   const MachineRegisterInfo &MRI = MF.getRegInfo();
776 
777   for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
778     const Register Reg = Register::index2VirtReg(I);
779     const TargetRegisterClass *RC = MRI.getRegClassOrNull(Reg);
780     if (RC && SIRegisterInfo::isAGPRClass(RC)) {
781       UsesAGPRs = true;
782       return true;
783     } else if (!RC && !MRI.use_empty(Reg) && MRI.getType(Reg).isValid()) {
784       // Defer caching UsesAGPRs, function might not yet been regbank selected.
785       return true;
786     }
787   }
788 
789   for (MCRegister Reg : AMDGPU::AGPR_32RegClass) {
790     if (MRI.isPhysRegUsed(Reg)) {
791       UsesAGPRs = true;
792       return true;
793     }
794   }
795 
796   UsesAGPRs = false;
797   return false;
798 }
799