1 //===-- SILowerControlFlow.cpp - Use predicates for control flow ----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// \brief This pass lowers the pseudo control flow instructions to real 12 /// machine instructions. 13 /// 14 /// All control flow is handled using predicated instructions and 15 /// a predicate stack. Each Scalar ALU controls the operations of 64 Vector 16 /// ALUs. The Scalar ALU can update the predicate for any of the Vector ALUs 17 /// by writting to the 64-bit EXEC register (each bit corresponds to a 18 /// single vector ALU). Typically, for predicates, a vector ALU will write 19 /// to its bit of the VCC register (like EXEC VCC is 64-bits, one for each 20 /// Vector ALU) and then the ScalarALU will AND the VCC register with the 21 /// EXEC to update the predicates. 22 /// 23 /// For example: 24 /// %VCC = V_CMP_GT_F32 %VGPR1, %VGPR2 25 /// %SGPR0 = SI_IF %VCC 26 /// %VGPR0 = V_ADD_F32 %VGPR0, %VGPR0 27 /// %SGPR0 = SI_ELSE %SGPR0 28 /// %VGPR0 = V_SUB_F32 %VGPR0, %VGPR0 29 /// SI_END_CF %SGPR0 30 /// 31 /// becomes: 32 /// 33 /// %SGPR0 = S_AND_SAVEEXEC_B64 %VCC // Save and update the exec mask 34 /// %SGPR0 = S_XOR_B64 %SGPR0, %EXEC // Clear live bits from saved exec mask 35 /// S_CBRANCH_EXECZ label0 // This instruction is an optional 36 /// // optimization which allows us to 37 /// // branch if all the bits of 38 /// // EXEC are zero. 39 /// %VGPR0 = V_ADD_F32 %VGPR0, %VGPR0 // Do the IF block of the branch 40 /// 41 /// label0: 42 /// %SGPR0 = S_OR_SAVEEXEC_B64 %EXEC // Restore the exec mask for the Then block 43 /// %EXEC = S_XOR_B64 %SGPR0, %EXEC // Clear live bits from saved exec mask 44 /// S_BRANCH_EXECZ label1 // Use our branch optimization 45 /// // instruction again. 46 /// %VGPR0 = V_SUB_F32 %VGPR0, %VGPR // Do the THEN block 47 /// label1: 48 /// %EXEC = S_OR_B64 %EXEC, %SGPR0 // Re-enable saved exec mask bits 49 //===----------------------------------------------------------------------===// 50 51 #include "AMDGPU.h" 52 #include "AMDGPUSubtarget.h" 53 #include "SIInstrInfo.h" 54 #include "SIMachineFunctionInfo.h" 55 #include "llvm/CodeGen/MachineFrameInfo.h" 56 #include "llvm/CodeGen/MachineFunction.h" 57 #include "llvm/CodeGen/MachineFunctionPass.h" 58 #include "llvm/CodeGen/MachineInstrBuilder.h" 59 #include "llvm/CodeGen/MachineRegisterInfo.h" 60 #include "llvm/IR/Constants.h" 61 62 using namespace llvm; 63 64 #define DEBUG_TYPE "si-lower-control-flow" 65 66 namespace { 67 68 class SILowerControlFlow : public MachineFunctionPass { 69 private: 70 static const unsigned SkipThreshold = 12; 71 72 const SIRegisterInfo *TRI; 73 const SIInstrInfo *TII; 74 75 bool shouldSkip(MachineBasicBlock *From, MachineBasicBlock *To); 76 77 void Skip(MachineInstr &From, MachineOperand &To); 78 void SkipIfDead(MachineInstr &MI); 79 80 void If(MachineInstr &MI); 81 void Else(MachineInstr &MI); 82 void Break(MachineInstr &MI); 83 void IfBreak(MachineInstr &MI); 84 void ElseBreak(MachineInstr &MI); 85 void Loop(MachineInstr &MI); 86 void EndCf(MachineInstr &MI); 87 88 void Kill(MachineInstr &MI); 89 void Branch(MachineInstr &MI); 90 91 void LoadM0(MachineInstr &MI, MachineInstr *MovRel, int Offset = 0); 92 void computeIndirectRegAndOffset(unsigned VecReg, unsigned &Reg, int &Offset); 93 void IndirectSrc(MachineInstr &MI); 94 void IndirectDst(MachineInstr &MI); 95 96 public: 97 static char ID; 98 99 SILowerControlFlow() : 100 MachineFunctionPass(ID), TRI(nullptr), TII(nullptr) { } 101 102 bool runOnMachineFunction(MachineFunction &MF) override; 103 104 const char *getPassName() const override { 105 return "SI Lower control flow pseudo instructions"; 106 } 107 108 void getAnalysisUsage(AnalysisUsage &AU) const override { 109 AU.setPreservesCFG(); 110 MachineFunctionPass::getAnalysisUsage(AU); 111 } 112 }; 113 114 } // End anonymous namespace 115 116 char SILowerControlFlow::ID = 0; 117 118 INITIALIZE_PASS(SILowerControlFlow, DEBUG_TYPE, 119 "SI lower control flow", false, false) 120 121 char &llvm::SILowerControlFlowPassID = SILowerControlFlow::ID; 122 123 124 FunctionPass *llvm::createSILowerControlFlowPass() { 125 return new SILowerControlFlow(); 126 } 127 128 bool SILowerControlFlow::shouldSkip(MachineBasicBlock *From, 129 MachineBasicBlock *To) { 130 131 unsigned NumInstr = 0; 132 133 for (MachineBasicBlock *MBB = From; MBB != To && !MBB->succ_empty(); 134 MBB = *MBB->succ_begin()) { 135 136 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); 137 NumInstr < SkipThreshold && I != E; ++I) { 138 139 if (I->isBundle() || !I->isBundled()) 140 if (++NumInstr >= SkipThreshold) 141 return true; 142 } 143 } 144 145 return false; 146 } 147 148 void SILowerControlFlow::Skip(MachineInstr &From, MachineOperand &To) { 149 150 if (!shouldSkip(*From.getParent()->succ_begin(), To.getMBB())) 151 return; 152 153 DebugLoc DL = From.getDebugLoc(); 154 BuildMI(*From.getParent(), &From, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ)) 155 .addOperand(To); 156 } 157 158 void SILowerControlFlow::SkipIfDead(MachineInstr &MI) { 159 160 MachineBasicBlock &MBB = *MI.getParent(); 161 DebugLoc DL = MI.getDebugLoc(); 162 163 if (MBB.getParent()->getInfo<SIMachineFunctionInfo>()->getShaderType() != 164 ShaderType::PIXEL || 165 !shouldSkip(&MBB, &MBB.getParent()->back())) 166 return; 167 168 MachineBasicBlock::iterator Insert = &MI; 169 ++Insert; 170 171 // If the exec mask is non-zero, skip the next two instructions 172 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ)) 173 .addImm(3); 174 175 // Exec mask is zero: Export to NULL target... 176 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::EXP)) 177 .addImm(0) 178 .addImm(0x09) // V_008DFC_SQ_EXP_NULL 179 .addImm(0) 180 .addImm(1) 181 .addImm(1) 182 .addReg(AMDGPU::VGPR0) 183 .addReg(AMDGPU::VGPR0) 184 .addReg(AMDGPU::VGPR0) 185 .addReg(AMDGPU::VGPR0); 186 187 // ... and terminate wavefront 188 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM)); 189 } 190 191 void SILowerControlFlow::If(MachineInstr &MI) { 192 MachineBasicBlock &MBB = *MI.getParent(); 193 DebugLoc DL = MI.getDebugLoc(); 194 unsigned Reg = MI.getOperand(0).getReg(); 195 unsigned Vcc = MI.getOperand(1).getReg(); 196 197 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg) 198 .addReg(Vcc); 199 200 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg) 201 .addReg(AMDGPU::EXEC) 202 .addReg(Reg); 203 204 Skip(MI, MI.getOperand(2)); 205 206 MI.eraseFromParent(); 207 } 208 209 void SILowerControlFlow::Else(MachineInstr &MI) { 210 MachineBasicBlock &MBB = *MI.getParent(); 211 DebugLoc DL = MI.getDebugLoc(); 212 unsigned Dst = MI.getOperand(0).getReg(); 213 unsigned Src = MI.getOperand(1).getReg(); 214 215 BuildMI(MBB, MBB.getFirstNonPHI(), DL, 216 TII->get(AMDGPU::S_OR_SAVEEXEC_B64), Dst) 217 .addReg(Src); // Saved EXEC 218 219 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC) 220 .addReg(AMDGPU::EXEC) 221 .addReg(Dst); 222 223 Skip(MI, MI.getOperand(2)); 224 225 MI.eraseFromParent(); 226 } 227 228 void SILowerControlFlow::Break(MachineInstr &MI) { 229 MachineBasicBlock &MBB = *MI.getParent(); 230 DebugLoc DL = MI.getDebugLoc(); 231 232 unsigned Dst = MI.getOperand(0).getReg(); 233 unsigned Src = MI.getOperand(1).getReg(); 234 235 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst) 236 .addReg(AMDGPU::EXEC) 237 .addReg(Src); 238 239 MI.eraseFromParent(); 240 } 241 242 void SILowerControlFlow::IfBreak(MachineInstr &MI) { 243 MachineBasicBlock &MBB = *MI.getParent(); 244 DebugLoc DL = MI.getDebugLoc(); 245 246 unsigned Dst = MI.getOperand(0).getReg(); 247 unsigned Vcc = MI.getOperand(1).getReg(); 248 unsigned Src = MI.getOperand(2).getReg(); 249 250 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst) 251 .addReg(Vcc) 252 .addReg(Src); 253 254 MI.eraseFromParent(); 255 } 256 257 void SILowerControlFlow::ElseBreak(MachineInstr &MI) { 258 MachineBasicBlock &MBB = *MI.getParent(); 259 DebugLoc DL = MI.getDebugLoc(); 260 261 unsigned Dst = MI.getOperand(0).getReg(); 262 unsigned Saved = MI.getOperand(1).getReg(); 263 unsigned Src = MI.getOperand(2).getReg(); 264 265 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst) 266 .addReg(Saved) 267 .addReg(Src); 268 269 MI.eraseFromParent(); 270 } 271 272 void SILowerControlFlow::Loop(MachineInstr &MI) { 273 MachineBasicBlock &MBB = *MI.getParent(); 274 DebugLoc DL = MI.getDebugLoc(); 275 unsigned Src = MI.getOperand(0).getReg(); 276 277 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_ANDN2_B64), AMDGPU::EXEC) 278 .addReg(AMDGPU::EXEC) 279 .addReg(Src); 280 281 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ)) 282 .addOperand(MI.getOperand(1)); 283 284 MI.eraseFromParent(); 285 } 286 287 void SILowerControlFlow::EndCf(MachineInstr &MI) { 288 MachineBasicBlock &MBB = *MI.getParent(); 289 DebugLoc DL = MI.getDebugLoc(); 290 unsigned Reg = MI.getOperand(0).getReg(); 291 292 BuildMI(MBB, MBB.getFirstNonPHI(), DL, 293 TII->get(AMDGPU::S_OR_B64), AMDGPU::EXEC) 294 .addReg(AMDGPU::EXEC) 295 .addReg(Reg); 296 297 MI.eraseFromParent(); 298 } 299 300 void SILowerControlFlow::Branch(MachineInstr &MI) { 301 if (MI.getOperand(0).getMBB() == MI.getParent()->getNextNode()) 302 MI.eraseFromParent(); 303 304 // If these aren't equal, this is probably an infinite loop. 305 } 306 307 void SILowerControlFlow::Kill(MachineInstr &MI) { 308 MachineBasicBlock &MBB = *MI.getParent(); 309 DebugLoc DL = MI.getDebugLoc(); 310 const MachineOperand &Op = MI.getOperand(0); 311 312 #ifndef NDEBUG 313 const SIMachineFunctionInfo *MFI 314 = MBB.getParent()->getInfo<SIMachineFunctionInfo>(); 315 // Kill is only allowed in pixel / geometry shaders. 316 assert(MFI->getShaderType() == ShaderType::PIXEL || 317 MFI->getShaderType() == ShaderType::GEOMETRY); 318 #endif 319 320 // Clear this thread from the exec mask if the operand is negative 321 if ((Op.isImm())) { 322 // Constant operand: Set exec mask to 0 or do nothing 323 if (Op.getImm() & 0x80000000) { 324 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), AMDGPU::EXEC) 325 .addImm(0); 326 } 327 } else { 328 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMPX_LE_F32_e32)) 329 .addImm(0) 330 .addOperand(Op); 331 } 332 333 MI.eraseFromParent(); 334 } 335 336 void SILowerControlFlow::LoadM0(MachineInstr &MI, MachineInstr *MovRel, int Offset) { 337 338 MachineBasicBlock &MBB = *MI.getParent(); 339 DebugLoc DL = MI.getDebugLoc(); 340 MachineBasicBlock::iterator I = MI; 341 342 unsigned Save = MI.getOperand(1).getReg(); 343 unsigned Idx = MI.getOperand(3).getReg(); 344 345 if (AMDGPU::SReg_32RegClass.contains(Idx)) { 346 if (Offset) { 347 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0) 348 .addReg(Idx) 349 .addImm(Offset); 350 } else { 351 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0) 352 .addReg(Idx); 353 } 354 MBB.insert(I, MovRel); 355 } else { 356 357 assert(AMDGPU::SReg_64RegClass.contains(Save)); 358 assert(AMDGPU::VGPR_32RegClass.contains(Idx)); 359 360 // Save the EXEC mask 361 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), Save) 362 .addReg(AMDGPU::EXEC); 363 364 // Read the next variant into VCC (lower 32 bits) <- also loop target 365 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), 366 AMDGPU::VCC_LO) 367 .addReg(Idx); 368 369 // Move index from VCC into M0 370 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0) 371 .addReg(AMDGPU::VCC_LO); 372 373 // Compare the just read M0 value to all possible Idx values 374 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMP_EQ_U32_e32)) 375 .addReg(AMDGPU::M0) 376 .addReg(Idx); 377 378 // Update EXEC, save the original EXEC value to VCC 379 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), AMDGPU::VCC) 380 .addReg(AMDGPU::VCC); 381 382 if (Offset) { 383 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0) 384 .addReg(AMDGPU::M0) 385 .addImm(Offset); 386 } 387 // Do the actual move 388 MBB.insert(I, MovRel); 389 390 // Update EXEC, switch all done bits to 0 and all todo bits to 1 391 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC) 392 .addReg(AMDGPU::EXEC) 393 .addReg(AMDGPU::VCC); 394 395 // Loop back to V_READFIRSTLANE_B32 if there are still variants to cover 396 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ)) 397 .addImm(-7); 398 399 // Restore EXEC 400 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), AMDGPU::EXEC) 401 .addReg(Save); 402 403 } 404 MI.eraseFromParent(); 405 } 406 407 /// \param @VecReg The register which holds element zero of the vector 408 /// being addressed into. 409 /// \param[out] @Reg The base register to use in the indirect addressing instruction. 410 /// \param[in,out] @Offset As an input, this is the constant offset part of the 411 // indirect Index. e.g. v0 = v[VecReg + Offset] 412 // As an output, this is a constant value that needs 413 // to be added to the value stored in M0. 414 void SILowerControlFlow::computeIndirectRegAndOffset(unsigned VecReg, 415 unsigned &Reg, 416 int &Offset) { 417 unsigned SubReg = TRI->getSubReg(VecReg, AMDGPU::sub0); 418 if (!SubReg) 419 SubReg = VecReg; 420 421 const TargetRegisterClass *RC = TRI->getPhysRegClass(SubReg); 422 int RegIdx = TRI->getHWRegIndex(SubReg) + Offset; 423 424 if (RegIdx < 0) { 425 Offset = RegIdx; 426 RegIdx = 0; 427 } else { 428 Offset = 0; 429 } 430 431 Reg = RC->getRegister(RegIdx); 432 } 433 434 void SILowerControlFlow::IndirectSrc(MachineInstr &MI) { 435 436 MachineBasicBlock &MBB = *MI.getParent(); 437 DebugLoc DL = MI.getDebugLoc(); 438 439 unsigned Dst = MI.getOperand(0).getReg(); 440 unsigned Vec = MI.getOperand(2).getReg(); 441 int Off = MI.getOperand(4).getImm(); 442 unsigned Reg; 443 444 computeIndirectRegAndOffset(Vec, Reg, Off); 445 446 MachineInstr *MovRel = 447 BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst) 448 .addReg(Reg) 449 .addReg(Vec, RegState::Implicit); 450 451 LoadM0(MI, MovRel, Off); 452 } 453 454 void SILowerControlFlow::IndirectDst(MachineInstr &MI) { 455 456 MachineBasicBlock &MBB = *MI.getParent(); 457 DebugLoc DL = MI.getDebugLoc(); 458 459 unsigned Dst = MI.getOperand(0).getReg(); 460 int Off = MI.getOperand(4).getImm(); 461 unsigned Val = MI.getOperand(5).getReg(); 462 unsigned Reg; 463 464 computeIndirectRegAndOffset(Dst, Reg, Off); 465 466 MachineInstr *MovRel = 467 BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELD_B32_e32)) 468 .addReg(Reg, RegState::Define) 469 .addReg(Val) 470 .addReg(Dst, RegState::Implicit); 471 472 LoadM0(MI, MovRel, Off); 473 } 474 475 bool SILowerControlFlow::runOnMachineFunction(MachineFunction &MF) { 476 TII = static_cast<const SIInstrInfo *>(MF.getSubtarget().getInstrInfo()); 477 TRI = 478 static_cast<const SIRegisterInfo *>(MF.getSubtarget().getRegisterInfo()); 479 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); 480 481 bool HaveKill = false; 482 bool NeedWQM = false; 483 bool NeedFlat = false; 484 unsigned Depth = 0; 485 486 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); 487 BI != BE; ++BI) { 488 489 MachineBasicBlock &MBB = *BI; 490 MachineBasicBlock::iterator I, Next; 491 for (I = MBB.begin(); I != MBB.end(); I = Next) { 492 Next = std::next(I); 493 494 MachineInstr &MI = *I; 495 if (TII->isWQM(MI) || TII->isDS(MI)) 496 NeedWQM = true; 497 498 // Flat uses m0 in case it needs to access LDS. 499 if (TII->isFLAT(MI)) 500 NeedFlat = true; 501 502 switch (MI.getOpcode()) { 503 default: break; 504 case AMDGPU::SI_IF: 505 ++Depth; 506 If(MI); 507 break; 508 509 case AMDGPU::SI_ELSE: 510 Else(MI); 511 break; 512 513 case AMDGPU::SI_BREAK: 514 Break(MI); 515 break; 516 517 case AMDGPU::SI_IF_BREAK: 518 IfBreak(MI); 519 break; 520 521 case AMDGPU::SI_ELSE_BREAK: 522 ElseBreak(MI); 523 break; 524 525 case AMDGPU::SI_LOOP: 526 ++Depth; 527 Loop(MI); 528 break; 529 530 case AMDGPU::SI_END_CF: 531 if (--Depth == 0 && HaveKill) { 532 SkipIfDead(MI); 533 HaveKill = false; 534 } 535 EndCf(MI); 536 break; 537 538 case AMDGPU::SI_KILL: 539 if (Depth == 0) 540 SkipIfDead(MI); 541 else 542 HaveKill = true; 543 Kill(MI); 544 break; 545 546 case AMDGPU::S_BRANCH: 547 Branch(MI); 548 break; 549 550 case AMDGPU::SI_INDIRECT_SRC_V1: 551 case AMDGPU::SI_INDIRECT_SRC_V2: 552 case AMDGPU::SI_INDIRECT_SRC_V4: 553 case AMDGPU::SI_INDIRECT_SRC_V8: 554 case AMDGPU::SI_INDIRECT_SRC_V16: 555 IndirectSrc(MI); 556 break; 557 558 case AMDGPU::SI_INDIRECT_DST_V1: 559 case AMDGPU::SI_INDIRECT_DST_V2: 560 case AMDGPU::SI_INDIRECT_DST_V4: 561 case AMDGPU::SI_INDIRECT_DST_V8: 562 case AMDGPU::SI_INDIRECT_DST_V16: 563 IndirectDst(MI); 564 break; 565 } 566 } 567 } 568 569 if (NeedWQM && MFI->getShaderType() == ShaderType::PIXEL) { 570 MachineBasicBlock &MBB = MF.front(); 571 BuildMI(MBB, MBB.getFirstNonPHI(), DebugLoc(), TII->get(AMDGPU::S_WQM_B64), 572 AMDGPU::EXEC).addReg(AMDGPU::EXEC); 573 } 574 575 // FIXME: This seems inappropriate to do here. 576 if (NeedFlat && MFI->IsKernel) { 577 // Insert the prologue initializing the SGPRs pointing to the scratch space 578 // for flat accesses. 579 const MachineFrameInfo *FrameInfo = MF.getFrameInfo(); 580 581 // TODO: What to use with function calls? 582 583 // FIXME: This is reporting stack size that is used in a scratch buffer 584 // rather than registers as well. 585 uint64_t StackSizeBytes = FrameInfo->getStackSize(); 586 587 int IndirectBegin 588 = static_cast<const AMDGPUInstrInfo*>(TII)->getIndirectIndexBegin(MF); 589 // Convert register index to 256-byte unit. 590 uint64_t StackOffset = IndirectBegin < 0 ? 0 : (4 * IndirectBegin / 256); 591 592 assert((StackSizeBytes < 0xffff) && StackOffset < 0xffff && 593 "Stack limits should be smaller than 16-bits"); 594 595 // Initialize the flat scratch register pair. 596 // TODO: Can we use one s_mov_b64 here? 597 598 // Offset is in units of 256-bytes. 599 MachineBasicBlock &MBB = MF.front(); 600 DebugLoc NoDL; 601 MachineBasicBlock::iterator Start = MBB.getFirstNonPHI(); 602 const MCInstrDesc &SMovK = TII->get(AMDGPU::S_MOVK_I32); 603 604 assert(isInt<16>(StackOffset) && isInt<16>(StackSizeBytes)); 605 606 BuildMI(MBB, Start, NoDL, SMovK, AMDGPU::FLAT_SCR_LO) 607 .addImm(StackOffset); 608 609 // Documentation says size is "per-thread scratch size in bytes" 610 BuildMI(MBB, Start, NoDL, SMovK, AMDGPU::FLAT_SCR_HI) 611 .addImm(StackSizeBytes); 612 } 613 614 return true; 615 } 616