145bb48eaSTom Stellard//===-- R700Instructions.td - R700 Instruction defs -------*- tablegen -*-===// 245bb48eaSTom Stellard// 3*2946cd70SChandler Carruth// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*2946cd70SChandler Carruth// See https://llvm.org/LICENSE.txt for license information. 5*2946cd70SChandler Carruth// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 645bb48eaSTom Stellard// 745bb48eaSTom Stellard//===----------------------------------------------------------------------===// 845bb48eaSTom Stellard// 945bb48eaSTom Stellard// TableGen definitions for instructions which are: 1045bb48eaSTom Stellard// - Available to R700 and newer VLIW4/VLIW5 GPUs 1145bb48eaSTom Stellard// - Available only on R700 family GPUs. 1245bb48eaSTom Stellard// 1345bb48eaSTom Stellard//===----------------------------------------------------------------------===// 1445bb48eaSTom Stellard 155bfbae5cSTom Stellarddef isR700 : Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::R700">; 1645bb48eaSTom Stellard 1745bb48eaSTom Stellardlet Predicates = [isR700] in { 1845bb48eaSTom Stellard def SIN_r700 : SIN_Common<0x6E>; 1945bb48eaSTom Stellard def COS_r700 : COS_Common<0x6F>; 2045bb48eaSTom Stellard} 21