1 //===-- R600RegisterInfo.cpp - R600 Register Information ------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// R600 implementation of the TargetRegisterInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "R600RegisterInfo.h" 15 #include "AMDGPUSubtarget.h" 16 #include "R600Defines.h" 17 18 using namespace llvm; 19 20 #define GET_REGINFO_TARGET_DESC 21 #include "R600GenRegisterInfo.inc" 22 23 unsigned R600RegisterInfo::getSubRegFromChannel(unsigned Channel) { 24 static const uint16_t SubRegFromChannelTable[] = { 25 R600::sub0, R600::sub1, R600::sub2, R600::sub3, 26 R600::sub4, R600::sub5, R600::sub6, R600::sub7, 27 R600::sub8, R600::sub9, R600::sub10, R600::sub11, 28 R600::sub12, R600::sub13, R600::sub14, R600::sub15 29 }; 30 31 assert(Channel < array_lengthof(SubRegFromChannelTable)); 32 return SubRegFromChannelTable[Channel]; 33 } 34 35 BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const { 36 BitVector Reserved(getNumRegs()); 37 38 const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>(); 39 const R600InstrInfo *TII = ST.getInstrInfo(); 40 41 reserveRegisterTuples(Reserved, R600::ZERO); 42 reserveRegisterTuples(Reserved, R600::HALF); 43 reserveRegisterTuples(Reserved, R600::ONE); 44 reserveRegisterTuples(Reserved, R600::ONE_INT); 45 reserveRegisterTuples(Reserved, R600::NEG_HALF); 46 reserveRegisterTuples(Reserved, R600::NEG_ONE); 47 reserveRegisterTuples(Reserved, R600::PV_X); 48 reserveRegisterTuples(Reserved, R600::ALU_LITERAL_X); 49 reserveRegisterTuples(Reserved, R600::ALU_CONST); 50 reserveRegisterTuples(Reserved, R600::PREDICATE_BIT); 51 reserveRegisterTuples(Reserved, R600::PRED_SEL_OFF); 52 reserveRegisterTuples(Reserved, R600::PRED_SEL_ZERO); 53 reserveRegisterTuples(Reserved, R600::PRED_SEL_ONE); 54 reserveRegisterTuples(Reserved, R600::INDIRECT_BASE_ADDR); 55 56 for (TargetRegisterClass::iterator I = R600::R600_AddrRegClass.begin(), 57 E = R600::R600_AddrRegClass.end(); I != E; ++I) { 58 reserveRegisterTuples(Reserved, *I); 59 } 60 61 TII->reserveIndirectRegisters(Reserved, MF, *this); 62 63 return Reserved; 64 } 65 66 // Dummy to not crash RegisterClassInfo. 67 static const MCPhysReg CalleeSavedReg = R600::NoRegister; 68 69 const MCPhysReg *R600RegisterInfo::getCalleeSavedRegs( 70 const MachineFunction *) const { 71 return &CalleeSavedReg; 72 } 73 74 Register R600RegisterInfo::getFrameRegister(const MachineFunction &MF) const { 75 return R600::NoRegister; 76 } 77 78 unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const { 79 return this->getEncodingValue(reg) >> HW_CHAN_SHIFT; 80 } 81 82 unsigned R600RegisterInfo::getHWRegIndex(unsigned Reg) const { 83 return GET_REG_INDEX(getEncodingValue(Reg)); 84 } 85 86 const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass( 87 MVT VT) const { 88 switch(VT.SimpleTy) { 89 default: 90 case MVT::i32: return &R600::R600_TReg32RegClass; 91 } 92 } 93 94 bool R600RegisterInfo::isPhysRegLiveAcrossClauses(Register Reg) const { 95 assert(!Reg.isVirtual()); 96 97 switch (Reg) { 98 case R600::OQAP: 99 case R600::OQBP: 100 case R600::AR_X: 101 return false; 102 default: 103 return true; 104 } 105 } 106 107 void R600RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, 108 int SPAdj, 109 unsigned FIOperandNum, 110 RegScavenger *RS) const { 111 llvm_unreachable("Subroutines not supported yet"); 112 } 113 114 void R600RegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const { 115 MCRegAliasIterator R(Reg, this, true); 116 117 for (; R.isValid(); ++R) 118 Reserved.set(*R); 119 } 120