1 //===-- R600RegisterInfo.cpp - R600 Register Information ------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// R600 implementation of the TargetRegisterInfo class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "R600RegisterInfo.h" 16 #include "AMDGPUTargetMachine.h" 17 #include "R600Defines.h" 18 #include "R600InstrInfo.h" 19 #include "R600MachineFunctionInfo.h" 20 21 using namespace llvm; 22 23 R600RegisterInfo::R600RegisterInfo() : AMDGPURegisterInfo() { 24 RCW.RegWeight = 0; 25 RCW.WeightLimit = 0; 26 } 27 28 BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const { 29 BitVector Reserved(getNumRegs()); 30 31 const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>(); 32 const R600InstrInfo *TII = ST.getInstrInfo(); 33 34 reserveRegisterTuples(Reserved, AMDGPU::ZERO); 35 reserveRegisterTuples(Reserved, AMDGPU::HALF); 36 reserveRegisterTuples(Reserved, AMDGPU::ONE); 37 reserveRegisterTuples(Reserved, AMDGPU::ONE_INT); 38 reserveRegisterTuples(Reserved, AMDGPU::NEG_HALF); 39 reserveRegisterTuples(Reserved, AMDGPU::NEG_ONE); 40 reserveRegisterTuples(Reserved, AMDGPU::PV_X); 41 reserveRegisterTuples(Reserved, AMDGPU::ALU_LITERAL_X); 42 reserveRegisterTuples(Reserved, AMDGPU::ALU_CONST); 43 reserveRegisterTuples(Reserved, AMDGPU::PREDICATE_BIT); 44 reserveRegisterTuples(Reserved, AMDGPU::PRED_SEL_OFF); 45 reserveRegisterTuples(Reserved, AMDGPU::PRED_SEL_ZERO); 46 reserveRegisterTuples(Reserved, AMDGPU::PRED_SEL_ONE); 47 reserveRegisterTuples(Reserved, AMDGPU::INDIRECT_BASE_ADDR); 48 49 for (TargetRegisterClass::iterator I = AMDGPU::R600_AddrRegClass.begin(), 50 E = AMDGPU::R600_AddrRegClass.end(); I != E; ++I) { 51 reserveRegisterTuples(Reserved, *I); 52 } 53 54 TII->reserveIndirectRegisters(Reserved, MF, *this); 55 56 return Reserved; 57 } 58 59 // Dummy to not crash RegisterClassInfo. 60 static const MCPhysReg CalleeSavedReg = AMDGPU::NoRegister; 61 62 const MCPhysReg *R600RegisterInfo::getCalleeSavedRegs( 63 const MachineFunction *) const { 64 return &CalleeSavedReg; 65 } 66 67 unsigned R600RegisterInfo::getFrameRegister(const MachineFunction &MF) const { 68 return AMDGPU::NoRegister; 69 } 70 71 unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const { 72 return this->getEncodingValue(reg) >> HW_CHAN_SHIFT; 73 } 74 75 unsigned R600RegisterInfo::getHWRegIndex(unsigned Reg) const { 76 return GET_REG_INDEX(getEncodingValue(Reg)); 77 } 78 79 const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass( 80 MVT VT) const { 81 switch(VT.SimpleTy) { 82 default: 83 case MVT::i32: return &AMDGPU::R600_TReg32RegClass; 84 } 85 } 86 87 const RegClassWeight &R600RegisterInfo::getRegClassWeight( 88 const TargetRegisterClass *RC) const { 89 return RCW; 90 } 91 92 bool R600RegisterInfo::isPhysRegLiveAcrossClauses(unsigned Reg) const { 93 assert(!TargetRegisterInfo::isVirtualRegister(Reg)); 94 95 switch (Reg) { 96 case AMDGPU::OQAP: 97 case AMDGPU::OQBP: 98 case AMDGPU::AR_X: 99 return false; 100 default: 101 return true; 102 } 103 } 104 105 void R600RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, 106 int SPAdj, 107 unsigned FIOperandNum, 108 RegScavenger *RS) const { 109 llvm_unreachable("Subroutines not supported yet"); 110 } 111