1 //===-- GCNHazardRecognizers.h - GCN Hazard Recognizers ---------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines hazard recognizers for scheduling on GCN processors. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H 14 #define LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H 15 16 #include "llvm/ADT/BitVector.h" 17 #include "llvm/ADT/STLExtras.h" 18 #include "llvm/CodeGen/ScheduleHazardRecognizer.h" 19 #include <list> 20 21 namespace llvm { 22 23 class MachineFunction; 24 class MachineInstr; 25 class MachineOperand; 26 class MachineRegisterInfo; 27 class ScheduleDAG; 28 class SIInstrInfo; 29 class SIRegisterInfo; 30 class GCNSubtarget; 31 32 class GCNHazardRecognizer final : public ScheduleHazardRecognizer { 33 public: 34 typedef function_ref<bool(MachineInstr *)> IsHazardFn; 35 36 private: 37 // Distinguish if we are called from scheduler or hazard recognizer 38 bool IsHazardRecognizerMode; 39 40 // This variable stores the instruction that has been emitted this cycle. It 41 // will be added to EmittedInstrs, when AdvanceCycle() or RecedeCycle() is 42 // called. 43 MachineInstr *CurrCycleInstr; 44 std::list<MachineInstr*> EmittedInstrs; 45 const MachineFunction &MF; 46 const GCNSubtarget &ST; 47 const SIInstrInfo &TII; 48 const SIRegisterInfo &TRI; 49 50 /// RegUnits of uses in the current soft memory clause. 51 BitVector ClauseUses; 52 53 /// RegUnits of defs in the current soft memory clause. 54 BitVector ClauseDefs; 55 56 void resetClause() { 57 ClauseUses.reset(); 58 ClauseDefs.reset(); 59 } 60 61 void addClauseInst(const MachineInstr &MI); 62 63 // Advance over a MachineInstr bundle. Look for hazards in the bundled 64 // instructions. 65 void processBundle(); 66 67 int getWaitStatesSince(IsHazardFn IsHazard, int Limit); 68 int getWaitStatesSinceDef(unsigned Reg, IsHazardFn IsHazardDef, int Limit); 69 int getWaitStatesSinceSetReg(IsHazardFn IsHazard, int Limit); 70 71 int checkSoftClauseHazards(MachineInstr *SMEM); 72 int checkSMRDHazards(MachineInstr *SMRD); 73 int checkVMEMHazards(MachineInstr* VMEM); 74 int checkDPPHazards(MachineInstr *DPP); 75 int checkDivFMasHazards(MachineInstr *DivFMas); 76 int checkGetRegHazards(MachineInstr *GetRegInstr); 77 int checkSetRegHazards(MachineInstr *SetRegInstr); 78 int createsVALUHazard(const MachineInstr &MI); 79 int checkVALUHazards(MachineInstr *VALU); 80 int checkVALUHazardsHelper(const MachineOperand &Def, const MachineRegisterInfo &MRI); 81 int checkRWLaneHazards(MachineInstr *RWLane); 82 int checkRFEHazards(MachineInstr *RFE); 83 int checkInlineAsmHazards(MachineInstr *IA); 84 int checkAnyInstHazards(MachineInstr *MI); 85 int checkReadM0Hazards(MachineInstr *SMovRel); 86 int checkNSAtoVMEMHazard(MachineInstr *MI); 87 88 void fixHazards(MachineInstr *MI); 89 bool fixVMEMtoScalarWriteHazards(MachineInstr *MI); 90 bool fixSMEMtoVectorWriteHazards(MachineInstr *MI); 91 bool fixVcmpxExecWARHazard(MachineInstr *MI); 92 bool fixLdsBranchVmemWARHazard(MachineInstr *MI); 93 94 public: 95 GCNHazardRecognizer(const MachineFunction &MF); 96 // We can only issue one instruction per cycle. 97 bool atIssueLimit() const override { return true; } 98 void EmitInstruction(SUnit *SU) override; 99 void EmitInstruction(MachineInstr *MI) override; 100 HazardType getHazardType(SUnit *SU, int Stalls) override; 101 void EmitNoop() override; 102 unsigned PreEmitNoops(SUnit *SU) override; 103 unsigned PreEmitNoops(MachineInstr *) override; 104 unsigned PreEmitNoopsCommon(MachineInstr *); 105 void AdvanceCycle() override; 106 void RecedeCycle() override; 107 }; 108 109 } // end namespace llvm 110 111 #endif //LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H 112