1 //===-- GCNHazardRecognizers.h - GCN Hazard Recognizers ---------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines hazard recognizers for scheduling on GCN processors. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H 14 #define LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H 15 16 #include "llvm/ADT/BitVector.h" 17 #include "llvm/ADT/STLExtras.h" 18 #include "llvm/CodeGen/ScheduleHazardRecognizer.h" 19 #include <list> 20 21 namespace llvm { 22 23 class MachineFunction; 24 class MachineInstr; 25 class MachineOperand; 26 class MachineRegisterInfo; 27 class ScheduleDAG; 28 class SIInstrInfo; 29 class SIRegisterInfo; 30 class GCNSubtarget; 31 32 class GCNHazardRecognizer final : public ScheduleHazardRecognizer { 33 // This variable stores the instruction that has been emitted this cycle. It 34 // will be added to EmittedInstrs, when AdvanceCycle() or RecedeCycle() is 35 // called. 36 MachineInstr *CurrCycleInstr; 37 std::list<MachineInstr*> EmittedInstrs; 38 const MachineFunction &MF; 39 const GCNSubtarget &ST; 40 const SIInstrInfo &TII; 41 const SIRegisterInfo &TRI; 42 43 /// RegUnits of uses in the current soft memory clause. 44 BitVector ClauseUses; 45 46 /// RegUnits of defs in the current soft memory clause. 47 BitVector ClauseDefs; 48 49 void resetClause() { 50 ClauseUses.reset(); 51 ClauseDefs.reset(); 52 } 53 54 void addClauseInst(const MachineInstr &MI); 55 56 int getWaitStatesSince(function_ref<bool(MachineInstr *)> IsHazard); 57 int getWaitStatesSinceDef(unsigned Reg, 58 function_ref<bool(MachineInstr *)> IsHazardDef = 59 [](MachineInstr *) { return true; }); 60 int getWaitStatesSinceSetReg(function_ref<bool(MachineInstr *)> IsHazard); 61 62 int checkSoftClauseHazards(MachineInstr *SMEM); 63 int checkSMRDHazards(MachineInstr *SMRD); 64 int checkVMEMHazards(MachineInstr* VMEM); 65 int checkDPPHazards(MachineInstr *DPP); 66 int checkDivFMasHazards(MachineInstr *DivFMas); 67 int checkGetRegHazards(MachineInstr *GetRegInstr); 68 int checkSetRegHazards(MachineInstr *SetRegInstr); 69 int createsVALUHazard(const MachineInstr &MI); 70 int checkVALUHazards(MachineInstr *VALU); 71 int checkVALUHazardsHelper(const MachineOperand &Def, const MachineRegisterInfo &MRI); 72 int checkRWLaneHazards(MachineInstr *RWLane); 73 int checkRFEHazards(MachineInstr *RFE); 74 int checkInlineAsmHazards(MachineInstr *IA); 75 int checkAnyInstHazards(MachineInstr *MI); 76 int checkReadM0Hazards(MachineInstr *SMovRel); 77 public: 78 GCNHazardRecognizer(const MachineFunction &MF); 79 // We can only issue one instruction per cycle. 80 bool atIssueLimit() const override { return true; } 81 void EmitInstruction(SUnit *SU) override; 82 void EmitInstruction(MachineInstr *MI) override; 83 HazardType getHazardType(SUnit *SU, int Stalls) override; 84 void EmitNoop() override; 85 unsigned PreEmitNoops(SUnit *SU) override; 86 unsigned PreEmitNoops(MachineInstr *) override; 87 void AdvanceCycle() override; 88 void RecedeCycle() override; 89 }; 90 91 } // end namespace llvm 92 93 #endif //LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H 94