1 //===-- GCNHazardRecognizers.cpp - GCN Hazard Recognizer Impls ------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements hazard recognizers for scheduling on GCN processors. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "GCNHazardRecognizer.h" 14 #include "GCNSubtarget.h" 15 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 16 #include "SIMachineFunctionInfo.h" 17 #include "llvm/CodeGen/MachineFunction.h" 18 #include "llvm/CodeGen/ScheduleDAG.h" 19 #include "llvm/Support/TargetParser.h" 20 21 using namespace llvm; 22 23 namespace { 24 25 struct MFMAPaddingRatioParser : public cl::parser<unsigned> { 26 MFMAPaddingRatioParser(cl::Option &O) : cl::parser<unsigned>(O) {} 27 28 bool parse(cl::Option &O, StringRef ArgName, StringRef Arg, unsigned &Value) { 29 if (Arg.getAsInteger(0, Value)) 30 return O.error("'" + Arg + "' value invalid for uint argument!"); 31 32 if (Value > 100) 33 return O.error("'" + Arg + "' value must be in the range [0, 100]!"); 34 35 return false; 36 } 37 }; 38 39 } // end anonymous namespace 40 41 static cl::opt<unsigned, false, MFMAPaddingRatioParser> 42 MFMAPaddingRatio("amdgpu-mfma-padding-ratio", cl::init(0), cl::Hidden, 43 cl::desc("Fill a percentage of the latency between " 44 "neighboring MFMA with s_nops.")); 45 46 //===----------------------------------------------------------------------===// 47 // Hazard Recognizer Implementation 48 //===----------------------------------------------------------------------===// 49 50 static bool shouldRunLdsBranchVmemWARHazardFixup(const MachineFunction &MF, 51 const GCNSubtarget &ST); 52 53 GCNHazardRecognizer::GCNHazardRecognizer(const MachineFunction &MF) : 54 IsHazardRecognizerMode(false), 55 CurrCycleInstr(nullptr), 56 MF(MF), 57 ST(MF.getSubtarget<GCNSubtarget>()), 58 TII(*ST.getInstrInfo()), 59 TRI(TII.getRegisterInfo()), 60 ClauseUses(TRI.getNumRegUnits()), 61 ClauseDefs(TRI.getNumRegUnits()) { 62 MaxLookAhead = MF.getRegInfo().isPhysRegUsed(AMDGPU::AGPR0) ? 19 : 5; 63 TSchedModel.init(&ST); 64 RunLdsBranchVmemWARHazardFixup = shouldRunLdsBranchVmemWARHazardFixup(MF, ST); 65 } 66 67 void GCNHazardRecognizer::Reset() { 68 EmittedInstrs.clear(); 69 } 70 71 void GCNHazardRecognizer::EmitInstruction(SUnit *SU) { 72 EmitInstruction(SU->getInstr()); 73 } 74 75 void GCNHazardRecognizer::EmitInstruction(MachineInstr *MI) { 76 CurrCycleInstr = MI; 77 } 78 79 static bool isDivFMas(unsigned Opcode) { 80 return Opcode == AMDGPU::V_DIV_FMAS_F32_e64 || Opcode == AMDGPU::V_DIV_FMAS_F64_e64; 81 } 82 83 static bool isSGetReg(unsigned Opcode) { 84 return Opcode == AMDGPU::S_GETREG_B32; 85 } 86 87 static bool isSSetReg(unsigned Opcode) { 88 switch (Opcode) { 89 case AMDGPU::S_SETREG_B32: 90 case AMDGPU::S_SETREG_B32_mode: 91 case AMDGPU::S_SETREG_IMM32_B32: 92 case AMDGPU::S_SETREG_IMM32_B32_mode: 93 return true; 94 } 95 return false; 96 } 97 98 static bool isRWLane(unsigned Opcode) { 99 return Opcode == AMDGPU::V_READLANE_B32 || Opcode == AMDGPU::V_WRITELANE_B32; 100 } 101 102 static bool isRFE(unsigned Opcode) { 103 return Opcode == AMDGPU::S_RFE_B64; 104 } 105 106 static bool isSMovRel(unsigned Opcode) { 107 switch (Opcode) { 108 case AMDGPU::S_MOVRELS_B32: 109 case AMDGPU::S_MOVRELS_B64: 110 case AMDGPU::S_MOVRELD_B32: 111 case AMDGPU::S_MOVRELD_B64: 112 return true; 113 default: 114 return false; 115 } 116 } 117 118 static bool isDGEMM(unsigned Opcode) { 119 return Opcode == AMDGPU::V_MFMA_F64_4X4X4F64_e64 || 120 Opcode == AMDGPU::V_MFMA_F64_4X4X4F64_vgprcd_e64 || 121 Opcode == AMDGPU::V_MFMA_F64_16X16X4F64_e64 || 122 Opcode == AMDGPU::V_MFMA_F64_16X16X4F64_vgprcd_e64 || 123 Opcode == AMDGPU::V_MFMA_F64_16X16X4F64_mac_e64 || 124 Opcode == AMDGPU::V_MFMA_F64_16X16X4F64_mac_vgprcd_e64; 125 } 126 127 static bool isXDL(const GCNSubtarget &ST, const MachineInstr &MI) { 128 unsigned Opcode = MI.getOpcode(); 129 130 if (!SIInstrInfo::isMAI(MI) || 131 isDGEMM(Opcode) || 132 Opcode == AMDGPU::V_ACCVGPR_WRITE_B32_e64 || 133 Opcode == AMDGPU::V_ACCVGPR_READ_B32_e64) 134 return false; 135 136 if (!ST.hasGFX940Insts()) 137 return true; 138 139 return AMDGPU::getMAIIsGFX940XDL(Opcode); 140 } 141 142 static bool isSendMsgTraceDataOrGDS(const SIInstrInfo &TII, 143 const MachineInstr &MI) { 144 if (TII.isAlwaysGDS(MI.getOpcode())) 145 return true; 146 147 switch (MI.getOpcode()) { 148 case AMDGPU::S_SENDMSG: 149 case AMDGPU::S_SENDMSGHALT: 150 case AMDGPU::S_TTRACEDATA: 151 return true; 152 // These DS opcodes don't support GDS. 153 case AMDGPU::DS_NOP: 154 case AMDGPU::DS_PERMUTE_B32: 155 case AMDGPU::DS_BPERMUTE_B32: 156 return false; 157 default: 158 if (TII.isDS(MI.getOpcode())) { 159 int GDS = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 160 AMDGPU::OpName::gds); 161 if (MI.getOperand(GDS).getImm()) 162 return true; 163 } 164 return false; 165 } 166 } 167 168 static bool isPermlane(const MachineInstr &MI) { 169 unsigned Opcode = MI.getOpcode(); 170 return Opcode == AMDGPU::V_PERMLANE16_B32_e64 || 171 Opcode == AMDGPU::V_PERMLANEX16_B32_e64; 172 } 173 174 static unsigned getHWReg(const SIInstrInfo *TII, const MachineInstr &RegInstr) { 175 const MachineOperand *RegOp = TII->getNamedOperand(RegInstr, 176 AMDGPU::OpName::simm16); 177 return RegOp->getImm() & AMDGPU::Hwreg::ID_MASK_; 178 } 179 180 ScheduleHazardRecognizer::HazardType 181 GCNHazardRecognizer::getHazardType(SUnit *SU, int Stalls) { 182 MachineInstr *MI = SU->getInstr(); 183 // If we are not in "HazardRecognizerMode" and therefore not being run from 184 // the scheduler, track possible stalls from hazards but don't insert noops. 185 auto HazardType = IsHazardRecognizerMode ? NoopHazard : Hazard; 186 187 if (MI->isBundle()) 188 return NoHazard; 189 190 if (SIInstrInfo::isSMRD(*MI) && checkSMRDHazards(MI) > 0) 191 return HazardType; 192 193 if (ST.hasNSAtoVMEMBug() && checkNSAtoVMEMHazard(MI) > 0) 194 return HazardType; 195 196 if (checkFPAtomicToDenormModeHazard(MI) > 0) 197 return HazardType; 198 199 if (ST.hasNoDataDepHazard()) 200 return NoHazard; 201 202 // FIXME: Should flat be considered vmem? 203 if ((SIInstrInfo::isVMEM(*MI) || 204 SIInstrInfo::isFLAT(*MI)) 205 && checkVMEMHazards(MI) > 0) 206 return HazardType; 207 208 if (SIInstrInfo::isVALU(*MI) && checkVALUHazards(MI) > 0) 209 return HazardType; 210 211 if (SIInstrInfo::isDPP(*MI) && checkDPPHazards(MI) > 0) 212 return HazardType; 213 214 if (isDivFMas(MI->getOpcode()) && checkDivFMasHazards(MI) > 0) 215 return HazardType; 216 217 if (isRWLane(MI->getOpcode()) && checkRWLaneHazards(MI) > 0) 218 return HazardType; 219 220 if ((SIInstrInfo::isVALU(*MI) || SIInstrInfo::isVMEM(*MI) || 221 SIInstrInfo::isFLAT(*MI) || SIInstrInfo::isDS(*MI) || 222 SIInstrInfo::isEXP(*MI)) && checkMAIVALUHazards(MI) > 0) 223 return HazardType; 224 225 if (isSGetReg(MI->getOpcode()) && checkGetRegHazards(MI) > 0) 226 return HazardType; 227 228 if (isSSetReg(MI->getOpcode()) && checkSetRegHazards(MI) > 0) 229 return HazardType; 230 231 if (isRFE(MI->getOpcode()) && checkRFEHazards(MI) > 0) 232 return HazardType; 233 234 if (ST.hasReadM0MovRelInterpHazard() && 235 (TII.isVINTRP(*MI) || isSMovRel(MI->getOpcode())) && 236 checkReadM0Hazards(MI) > 0) 237 return HazardType; 238 239 if (ST.hasReadM0SendMsgHazard() && isSendMsgTraceDataOrGDS(TII, *MI) && 240 checkReadM0Hazards(MI) > 0) 241 return HazardType; 242 243 if (SIInstrInfo::isMAI(*MI) && checkMAIHazards(MI) > 0) 244 return HazardType; 245 246 if ((SIInstrInfo::isVMEM(*MI) || 247 SIInstrInfo::isFLAT(*MI) || 248 SIInstrInfo::isDS(*MI)) && checkMAILdStHazards(MI) > 0) 249 return HazardType; 250 251 if (MI->isInlineAsm() && checkInlineAsmHazards(MI) > 0) 252 return HazardType; 253 254 return NoHazard; 255 } 256 257 static void insertNoopsInBundle(MachineInstr *MI, const SIInstrInfo &TII, 258 unsigned Quantity) { 259 while (Quantity > 0) { 260 unsigned Arg = std::min(Quantity, 8u); 261 Quantity -= Arg; 262 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII.get(AMDGPU::S_NOP)) 263 .addImm(Arg - 1); 264 } 265 } 266 267 unsigned 268 GCNHazardRecognizer::getMFMAPipelineWaitStates(const MachineInstr &MI) const { 269 const MCSchedClassDesc *SC = TSchedModel.resolveSchedClass(&MI); 270 assert(TSchedModel.getWriteProcResBegin(SC) != 271 TSchedModel.getWriteProcResEnd(SC)); 272 return TSchedModel.getWriteProcResBegin(SC)->Cycles; 273 } 274 275 void GCNHazardRecognizer::processBundle() { 276 MachineBasicBlock::instr_iterator MI = std::next(CurrCycleInstr->getIterator()); 277 MachineBasicBlock::instr_iterator E = CurrCycleInstr->getParent()->instr_end(); 278 // Check bundled MachineInstr's for hazards. 279 for (; MI != E && MI->isInsideBundle(); ++MI) { 280 CurrCycleInstr = &*MI; 281 unsigned WaitStates = PreEmitNoopsCommon(CurrCycleInstr); 282 283 if (IsHazardRecognizerMode) { 284 fixHazards(CurrCycleInstr); 285 286 insertNoopsInBundle(CurrCycleInstr, TII, WaitStates); 287 } 288 289 // It’s unnecessary to track more than MaxLookAhead instructions. Since we 290 // include the bundled MI directly after, only add a maximum of 291 // (MaxLookAhead - 1) noops to EmittedInstrs. 292 for (unsigned i = 0, e = std::min(WaitStates, MaxLookAhead - 1); i < e; ++i) 293 EmittedInstrs.push_front(nullptr); 294 295 EmittedInstrs.push_front(CurrCycleInstr); 296 EmittedInstrs.resize(MaxLookAhead); 297 } 298 CurrCycleInstr = nullptr; 299 } 300 301 unsigned GCNHazardRecognizer::PreEmitNoops(MachineInstr *MI) { 302 IsHazardRecognizerMode = true; 303 CurrCycleInstr = MI; 304 unsigned W = PreEmitNoopsCommon(MI); 305 fixHazards(MI); 306 CurrCycleInstr = nullptr; 307 return W; 308 } 309 310 unsigned GCNHazardRecognizer::PreEmitNoopsCommon(MachineInstr *MI) { 311 if (MI->isBundle()) 312 return 0; 313 314 int WaitStates = 0; 315 316 if (SIInstrInfo::isSMRD(*MI)) 317 return std::max(WaitStates, checkSMRDHazards(MI)); 318 319 if (ST.hasNSAtoVMEMBug()) 320 WaitStates = std::max(WaitStates, checkNSAtoVMEMHazard(MI)); 321 322 WaitStates = std::max(WaitStates, checkFPAtomicToDenormModeHazard(MI)); 323 324 if (ST.hasNoDataDepHazard()) 325 return WaitStates; 326 327 if (SIInstrInfo::isVMEM(*MI) || SIInstrInfo::isFLAT(*MI)) 328 WaitStates = std::max(WaitStates, checkVMEMHazards(MI)); 329 330 if (SIInstrInfo::isVALU(*MI)) 331 WaitStates = std::max(WaitStates, checkVALUHazards(MI)); 332 333 if (SIInstrInfo::isDPP(*MI)) 334 WaitStates = std::max(WaitStates, checkDPPHazards(MI)); 335 336 if (isDivFMas(MI->getOpcode())) 337 WaitStates = std::max(WaitStates, checkDivFMasHazards(MI)); 338 339 if (isRWLane(MI->getOpcode())) 340 WaitStates = std::max(WaitStates, checkRWLaneHazards(MI)); 341 342 if ((SIInstrInfo::isVALU(*MI) || SIInstrInfo::isVMEM(*MI) || 343 SIInstrInfo::isFLAT(*MI) || SIInstrInfo::isDS(*MI) || 344 SIInstrInfo::isEXP(*MI)) && checkMAIVALUHazards(MI) > 0) 345 WaitStates = std::max(WaitStates, checkMAIVALUHazards(MI)); 346 347 if (MI->isInlineAsm()) 348 return std::max(WaitStates, checkInlineAsmHazards(MI)); 349 350 if (isSGetReg(MI->getOpcode())) 351 return std::max(WaitStates, checkGetRegHazards(MI)); 352 353 if (isSSetReg(MI->getOpcode())) 354 return std::max(WaitStates, checkSetRegHazards(MI)); 355 356 if (isRFE(MI->getOpcode())) 357 return std::max(WaitStates, checkRFEHazards(MI)); 358 359 if (ST.hasReadM0MovRelInterpHazard() && (TII.isVINTRP(*MI) || 360 isSMovRel(MI->getOpcode()))) 361 return std::max(WaitStates, checkReadM0Hazards(MI)); 362 363 if (ST.hasReadM0SendMsgHazard() && isSendMsgTraceDataOrGDS(TII, *MI)) 364 return std::max(WaitStates, checkReadM0Hazards(MI)); 365 366 if (SIInstrInfo::isMAI(*MI)) 367 return std::max(WaitStates, checkMAIHazards(MI)); 368 369 if (SIInstrInfo::isVMEM(*MI) || 370 SIInstrInfo::isFLAT(*MI) || 371 SIInstrInfo::isDS(*MI)) 372 return std::max(WaitStates, checkMAILdStHazards(MI)); 373 374 return WaitStates; 375 } 376 377 void GCNHazardRecognizer::EmitNoop() { 378 EmittedInstrs.push_front(nullptr); 379 } 380 381 void GCNHazardRecognizer::AdvanceCycle() { 382 // When the scheduler detects a stall, it will call AdvanceCycle() without 383 // emitting any instructions. 384 if (!CurrCycleInstr) { 385 EmittedInstrs.push_front(nullptr); 386 return; 387 } 388 389 if (CurrCycleInstr->isBundle()) { 390 processBundle(); 391 return; 392 } 393 394 unsigned NumWaitStates = TII.getNumWaitStates(*CurrCycleInstr); 395 if (!NumWaitStates) { 396 CurrCycleInstr = nullptr; 397 return; 398 } 399 400 // Keep track of emitted instructions 401 EmittedInstrs.push_front(CurrCycleInstr); 402 403 // Add a nullptr for each additional wait state after the first. Make sure 404 // not to add more than getMaxLookAhead() items to the list, since we 405 // truncate the list to that size right after this loop. 406 for (unsigned i = 1, e = std::min(NumWaitStates, getMaxLookAhead()); 407 i < e; ++i) { 408 EmittedInstrs.push_front(nullptr); 409 } 410 411 // getMaxLookahead() is the largest number of wait states we will ever need 412 // to insert, so there is no point in keeping track of more than that many 413 // wait states. 414 EmittedInstrs.resize(getMaxLookAhead()); 415 416 CurrCycleInstr = nullptr; 417 } 418 419 void GCNHazardRecognizer::RecedeCycle() { 420 llvm_unreachable("hazard recognizer does not support bottom-up scheduling."); 421 } 422 423 //===----------------------------------------------------------------------===// 424 // Helper Functions 425 //===----------------------------------------------------------------------===// 426 427 typedef function_ref<bool(const MachineInstr &, int WaitStates)> IsExpiredFn; 428 429 // Returns a minimum wait states since \p I walking all predecessors. 430 // Only scans until \p IsExpired does not return true. 431 // Can only be run in a hazard recognizer mode. 432 static int getWaitStatesSince(GCNHazardRecognizer::IsHazardFn IsHazard, 433 const MachineBasicBlock *MBB, 434 MachineBasicBlock::const_reverse_instr_iterator I, 435 int WaitStates, IsExpiredFn IsExpired, 436 DenseSet<const MachineBasicBlock *> &Visited) { 437 for (auto E = MBB->instr_rend(); I != E; ++I) { 438 // Don't add WaitStates for parent BUNDLE instructions. 439 if (I->isBundle()) 440 continue; 441 442 if (IsHazard(*I)) 443 return WaitStates; 444 445 if (I->isInlineAsm()) 446 continue; 447 448 WaitStates += SIInstrInfo::getNumWaitStates(*I); 449 450 if (IsExpired(*I, WaitStates)) 451 return std::numeric_limits<int>::max(); 452 } 453 454 int MinWaitStates = std::numeric_limits<int>::max(); 455 for (MachineBasicBlock *Pred : MBB->predecessors()) { 456 if (!Visited.insert(Pred).second) 457 continue; 458 459 int W = getWaitStatesSince(IsHazard, Pred, Pred->instr_rbegin(), 460 WaitStates, IsExpired, Visited); 461 462 MinWaitStates = std::min(MinWaitStates, W); 463 } 464 465 return MinWaitStates; 466 } 467 468 static int getWaitStatesSince(GCNHazardRecognizer::IsHazardFn IsHazard, 469 const MachineInstr *MI, IsExpiredFn IsExpired) { 470 DenseSet<const MachineBasicBlock *> Visited; 471 return getWaitStatesSince(IsHazard, MI->getParent(), 472 std::next(MI->getReverseIterator()), 473 0, IsExpired, Visited); 474 } 475 476 int GCNHazardRecognizer::getWaitStatesSince(IsHazardFn IsHazard, int Limit) { 477 if (IsHazardRecognizerMode) { 478 auto IsExpiredFn = [Limit](const MachineInstr &, int WaitStates) { 479 return WaitStates >= Limit; 480 }; 481 return ::getWaitStatesSince(IsHazard, CurrCycleInstr, IsExpiredFn); 482 } 483 484 int WaitStates = 0; 485 for (MachineInstr *MI : EmittedInstrs) { 486 if (MI) { 487 if (IsHazard(*MI)) 488 return WaitStates; 489 490 if (MI->isInlineAsm()) 491 continue; 492 } 493 ++WaitStates; 494 495 if (WaitStates >= Limit) 496 break; 497 } 498 return std::numeric_limits<int>::max(); 499 } 500 501 int GCNHazardRecognizer::getWaitStatesSinceDef(unsigned Reg, 502 IsHazardFn IsHazardDef, 503 int Limit) { 504 const SIRegisterInfo *TRI = ST.getRegisterInfo(); 505 506 auto IsHazardFn = [IsHazardDef, TRI, Reg](const MachineInstr &MI) { 507 return IsHazardDef(MI) && MI.modifiesRegister(Reg, TRI); 508 }; 509 510 return getWaitStatesSince(IsHazardFn, Limit); 511 } 512 513 int GCNHazardRecognizer::getWaitStatesSinceSetReg(IsHazardFn IsHazard, 514 int Limit) { 515 auto IsHazardFn = [IsHazard](const MachineInstr &MI) { 516 return isSSetReg(MI.getOpcode()) && IsHazard(MI); 517 }; 518 519 return getWaitStatesSince(IsHazardFn, Limit); 520 } 521 522 //===----------------------------------------------------------------------===// 523 // No-op Hazard Detection 524 //===----------------------------------------------------------------------===// 525 526 static void addRegUnits(const SIRegisterInfo &TRI, BitVector &BV, 527 MCRegister Reg) { 528 for (MCRegUnitIterator RUI(Reg, &TRI); RUI.isValid(); ++RUI) 529 BV.set(*RUI); 530 } 531 532 static void addRegsToSet(const SIRegisterInfo &TRI, 533 iterator_range<MachineInstr::const_mop_iterator> Ops, 534 BitVector &Set) { 535 for (const MachineOperand &Op : Ops) { 536 if (Op.isReg()) 537 addRegUnits(TRI, Set, Op.getReg().asMCReg()); 538 } 539 } 540 541 void GCNHazardRecognizer::addClauseInst(const MachineInstr &MI) { 542 // XXX: Do we need to worry about implicit operands 543 addRegsToSet(TRI, MI.defs(), ClauseDefs); 544 addRegsToSet(TRI, MI.uses(), ClauseUses); 545 } 546 547 static bool breaksSMEMSoftClause(MachineInstr *MI) { 548 return !SIInstrInfo::isSMRD(*MI); 549 } 550 551 static bool breaksVMEMSoftClause(MachineInstr *MI) { 552 return !SIInstrInfo::isVMEM(*MI) && !SIInstrInfo::isFLAT(*MI); 553 } 554 555 int GCNHazardRecognizer::checkSoftClauseHazards(MachineInstr *MEM) { 556 // SMEM soft clause are only present on VI+, and only matter if xnack is 557 // enabled. 558 if (!ST.isXNACKEnabled()) 559 return 0; 560 561 bool IsSMRD = TII.isSMRD(*MEM); 562 563 resetClause(); 564 565 // A soft-clause is any group of consecutive SMEM instructions. The 566 // instructions in this group may return out of order and/or may be 567 // replayed (i.e. the same instruction issued more than once). 568 // 569 // In order to handle these situations correctly we need to make sure that 570 // when a clause has more than one instruction, no instruction in the clause 571 // writes to a register that is read by another instruction in the clause 572 // (including itself). If we encounter this situation, we need to break the 573 // clause by inserting a non SMEM instruction. 574 575 for (MachineInstr *MI : EmittedInstrs) { 576 // When we hit a non-SMEM instruction then we have passed the start of the 577 // clause and we can stop. 578 if (!MI) 579 break; 580 581 if (IsSMRD ? breaksSMEMSoftClause(MI) : breaksVMEMSoftClause(MI)) 582 break; 583 584 addClauseInst(*MI); 585 } 586 587 if (ClauseDefs.none()) 588 return 0; 589 590 // We need to make sure not to put loads and stores in the same clause if they 591 // use the same address. For now, just start a new clause whenever we see a 592 // store. 593 if (MEM->mayStore()) 594 return 1; 595 596 addClauseInst(*MEM); 597 598 // If the set of defs and uses intersect then we cannot add this instruction 599 // to the clause, so we have a hazard. 600 return ClauseDefs.anyCommon(ClauseUses) ? 1 : 0; 601 } 602 603 int GCNHazardRecognizer::checkSMRDHazards(MachineInstr *SMRD) { 604 int WaitStatesNeeded = 0; 605 606 WaitStatesNeeded = checkSoftClauseHazards(SMRD); 607 608 // This SMRD hazard only affects SI. 609 if (!ST.hasSMRDReadVALUDefHazard()) 610 return WaitStatesNeeded; 611 612 // A read of an SGPR by SMRD instruction requires 4 wait states when the 613 // SGPR was written by a VALU instruction. 614 int SmrdSgprWaitStates = 4; 615 auto IsHazardDefFn = [this](const MachineInstr &MI) { 616 return TII.isVALU(MI); 617 }; 618 auto IsBufferHazardDefFn = [this](const MachineInstr &MI) { 619 return TII.isSALU(MI); 620 }; 621 622 bool IsBufferSMRD = TII.isBufferSMRD(*SMRD); 623 624 for (const MachineOperand &Use : SMRD->uses()) { 625 if (!Use.isReg()) 626 continue; 627 int WaitStatesNeededForUse = 628 SmrdSgprWaitStates - getWaitStatesSinceDef(Use.getReg(), IsHazardDefFn, 629 SmrdSgprWaitStates); 630 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse); 631 632 // This fixes what appears to be undocumented hardware behavior in SI where 633 // s_mov writing a descriptor and s_buffer_load_dword reading the descriptor 634 // needs some number of nops in between. We don't know how many we need, but 635 // let's use 4. This wasn't discovered before probably because the only 636 // case when this happens is when we expand a 64-bit pointer into a full 637 // descriptor and use s_buffer_load_dword instead of s_load_dword, which was 638 // probably never encountered in the closed-source land. 639 if (IsBufferSMRD) { 640 int WaitStatesNeededForUse = 641 SmrdSgprWaitStates - getWaitStatesSinceDef(Use.getReg(), 642 IsBufferHazardDefFn, 643 SmrdSgprWaitStates); 644 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse); 645 } 646 } 647 648 return WaitStatesNeeded; 649 } 650 651 int GCNHazardRecognizer::checkVMEMHazards(MachineInstr* VMEM) { 652 if (!ST.hasVMEMReadSGPRVALUDefHazard()) 653 return 0; 654 655 int WaitStatesNeeded = checkSoftClauseHazards(VMEM); 656 657 // A read of an SGPR by a VMEM instruction requires 5 wait states when the 658 // SGPR was written by a VALU Instruction. 659 const int VmemSgprWaitStates = 5; 660 auto IsHazardDefFn = [this](const MachineInstr &MI) { 661 return TII.isVALU(MI); 662 }; 663 for (const MachineOperand &Use : VMEM->uses()) { 664 if (!Use.isReg() || TRI.isVectorRegister(MF.getRegInfo(), Use.getReg())) 665 continue; 666 667 int WaitStatesNeededForUse = 668 VmemSgprWaitStates - getWaitStatesSinceDef(Use.getReg(), IsHazardDefFn, 669 VmemSgprWaitStates); 670 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse); 671 } 672 return WaitStatesNeeded; 673 } 674 675 int GCNHazardRecognizer::checkDPPHazards(MachineInstr *DPP) { 676 const SIRegisterInfo *TRI = ST.getRegisterInfo(); 677 const SIInstrInfo *TII = ST.getInstrInfo(); 678 679 // Check for DPP VGPR read after VALU VGPR write and EXEC write. 680 int DppVgprWaitStates = 2; 681 int DppExecWaitStates = 5; 682 int WaitStatesNeeded = 0; 683 auto IsHazardDefFn = [TII](const MachineInstr &MI) { 684 return TII->isVALU(MI); 685 }; 686 687 for (const MachineOperand &Use : DPP->uses()) { 688 if (!Use.isReg() || !TRI->isVGPR(MF.getRegInfo(), Use.getReg())) 689 continue; 690 int WaitStatesNeededForUse = 691 DppVgprWaitStates - getWaitStatesSinceDef( 692 Use.getReg(), 693 [](const MachineInstr &) { return true; }, 694 DppVgprWaitStates); 695 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse); 696 } 697 698 WaitStatesNeeded = std::max( 699 WaitStatesNeeded, 700 DppExecWaitStates - getWaitStatesSinceDef(AMDGPU::EXEC, IsHazardDefFn, 701 DppExecWaitStates)); 702 703 return WaitStatesNeeded; 704 } 705 706 int GCNHazardRecognizer::checkDivFMasHazards(MachineInstr *DivFMas) { 707 const SIInstrInfo *TII = ST.getInstrInfo(); 708 709 // v_div_fmas requires 4 wait states after a write to vcc from a VALU 710 // instruction. 711 const int DivFMasWaitStates = 4; 712 auto IsHazardDefFn = [TII](const MachineInstr &MI) { 713 return TII->isVALU(MI); 714 }; 715 int WaitStatesNeeded = getWaitStatesSinceDef(AMDGPU::VCC, IsHazardDefFn, 716 DivFMasWaitStates); 717 718 return DivFMasWaitStates - WaitStatesNeeded; 719 } 720 721 int GCNHazardRecognizer::checkGetRegHazards(MachineInstr *GetRegInstr) { 722 const SIInstrInfo *TII = ST.getInstrInfo(); 723 unsigned GetRegHWReg = getHWReg(TII, *GetRegInstr); 724 725 const int GetRegWaitStates = 2; 726 auto IsHazardFn = [TII, GetRegHWReg](const MachineInstr &MI) { 727 return GetRegHWReg == getHWReg(TII, MI); 728 }; 729 int WaitStatesNeeded = getWaitStatesSinceSetReg(IsHazardFn, GetRegWaitStates); 730 731 return GetRegWaitStates - WaitStatesNeeded; 732 } 733 734 int GCNHazardRecognizer::checkSetRegHazards(MachineInstr *SetRegInstr) { 735 const SIInstrInfo *TII = ST.getInstrInfo(); 736 unsigned HWReg = getHWReg(TII, *SetRegInstr); 737 738 const int SetRegWaitStates = ST.getSetRegWaitStates(); 739 auto IsHazardFn = [TII, HWReg](const MachineInstr &MI) { 740 return HWReg == getHWReg(TII, MI); 741 }; 742 int WaitStatesNeeded = getWaitStatesSinceSetReg(IsHazardFn, SetRegWaitStates); 743 return SetRegWaitStates - WaitStatesNeeded; 744 } 745 746 int GCNHazardRecognizer::createsVALUHazard(const MachineInstr &MI) { 747 if (!MI.mayStore()) 748 return -1; 749 750 const SIInstrInfo *TII = ST.getInstrInfo(); 751 unsigned Opcode = MI.getOpcode(); 752 const MCInstrDesc &Desc = MI.getDesc(); 753 754 int VDataIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdata); 755 int VDataRCID = -1; 756 if (VDataIdx != -1) 757 VDataRCID = Desc.OpInfo[VDataIdx].RegClass; 758 759 if (TII->isMUBUF(MI) || TII->isMTBUF(MI)) { 760 // There is no hazard if the instruction does not use vector regs 761 // (like wbinvl1) 762 if (VDataIdx == -1) 763 return -1; 764 // For MUBUF/MTBUF instructions this hazard only exists if the 765 // instruction is not using a register in the soffset field. 766 const MachineOperand *SOffset = 767 TII->getNamedOperand(MI, AMDGPU::OpName::soffset); 768 // If we have no soffset operand, then assume this field has been 769 // hardcoded to zero. 770 if (AMDGPU::getRegBitWidth(VDataRCID) > 64 && 771 (!SOffset || !SOffset->isReg())) 772 return VDataIdx; 773 } 774 775 // MIMG instructions create a hazard if they don't use a 256-bit T# and 776 // the store size is greater than 8 bytes and they have more than two bits 777 // of their dmask set. 778 // All our MIMG definitions use a 256-bit T#, so we can skip checking for them. 779 if (TII->isMIMG(MI)) { 780 int SRsrcIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::srsrc); 781 assert(SRsrcIdx != -1 && 782 AMDGPU::getRegBitWidth(Desc.OpInfo[SRsrcIdx].RegClass) == 256); 783 (void)SRsrcIdx; 784 } 785 786 if (TII->isFLAT(MI)) { 787 int DataIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdata); 788 if (AMDGPU::getRegBitWidth(Desc.OpInfo[DataIdx].RegClass) > 64) 789 return DataIdx; 790 } 791 792 return -1; 793 } 794 795 int 796 GCNHazardRecognizer::checkVALUHazardsHelper(const MachineOperand &Def, 797 const MachineRegisterInfo &MRI) { 798 // Helper to check for the hazard where VMEM instructions that store more than 799 // 8 bytes can have there store data over written by the next instruction. 800 const SIRegisterInfo *TRI = ST.getRegisterInfo(); 801 802 const int VALUWaitStates = 1; 803 int WaitStatesNeeded = 0; 804 805 if (!TRI->isVectorRegister(MRI, Def.getReg())) 806 return WaitStatesNeeded; 807 Register Reg = Def.getReg(); 808 auto IsHazardFn = [this, Reg, TRI](const MachineInstr &MI) { 809 int DataIdx = createsVALUHazard(MI); 810 return DataIdx >= 0 && 811 TRI->regsOverlap(MI.getOperand(DataIdx).getReg(), Reg); 812 }; 813 int WaitStatesNeededForDef = 814 VALUWaitStates - getWaitStatesSince(IsHazardFn, VALUWaitStates); 815 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForDef); 816 817 return WaitStatesNeeded; 818 } 819 820 int GCNHazardRecognizer::checkVALUHazards(MachineInstr *VALU) { 821 // This checks for the hazard where VMEM instructions that store more than 822 // 8 bytes can have there store data over written by the next instruction. 823 if (!ST.has12DWordStoreHazard()) 824 return 0; 825 826 const MachineRegisterInfo &MRI = MF.getRegInfo(); 827 int WaitStatesNeeded = 0; 828 829 for (const MachineOperand &Def : VALU->defs()) { 830 WaitStatesNeeded = std::max(WaitStatesNeeded, checkVALUHazardsHelper(Def, MRI)); 831 } 832 833 return WaitStatesNeeded; 834 } 835 836 int GCNHazardRecognizer::checkInlineAsmHazards(MachineInstr *IA) { 837 // This checks for hazards associated with inline asm statements. 838 // Since inline asms can contain just about anything, we use this 839 // to call/leverage other check*Hazard routines. Note that 840 // this function doesn't attempt to address all possible inline asm 841 // hazards (good luck), but is a collection of what has been 842 // problematic thus far. 843 844 // see checkVALUHazards() 845 if (!ST.has12DWordStoreHazard()) 846 return 0; 847 848 const MachineRegisterInfo &MRI = MF.getRegInfo(); 849 int WaitStatesNeeded = 0; 850 851 for (unsigned I = InlineAsm::MIOp_FirstOperand, E = IA->getNumOperands(); 852 I != E; ++I) { 853 const MachineOperand &Op = IA->getOperand(I); 854 if (Op.isReg() && Op.isDef()) { 855 WaitStatesNeeded = std::max(WaitStatesNeeded, checkVALUHazardsHelper(Op, MRI)); 856 } 857 } 858 859 return WaitStatesNeeded; 860 } 861 862 int GCNHazardRecognizer::checkRWLaneHazards(MachineInstr *RWLane) { 863 const SIInstrInfo *TII = ST.getInstrInfo(); 864 const SIRegisterInfo *TRI = ST.getRegisterInfo(); 865 const MachineRegisterInfo &MRI = MF.getRegInfo(); 866 867 const MachineOperand *LaneSelectOp = 868 TII->getNamedOperand(*RWLane, AMDGPU::OpName::src1); 869 870 if (!LaneSelectOp->isReg() || !TRI->isSGPRReg(MRI, LaneSelectOp->getReg())) 871 return 0; 872 873 Register LaneSelectReg = LaneSelectOp->getReg(); 874 auto IsHazardFn = [TII](const MachineInstr &MI) { return TII->isVALU(MI); }; 875 876 const int RWLaneWaitStates = 4; 877 int WaitStatesSince = getWaitStatesSinceDef(LaneSelectReg, IsHazardFn, 878 RWLaneWaitStates); 879 return RWLaneWaitStates - WaitStatesSince; 880 } 881 882 int GCNHazardRecognizer::checkRFEHazards(MachineInstr *RFE) { 883 if (!ST.hasRFEHazards()) 884 return 0; 885 886 const SIInstrInfo *TII = ST.getInstrInfo(); 887 888 const int RFEWaitStates = 1; 889 890 auto IsHazardFn = [TII](const MachineInstr &MI) { 891 return getHWReg(TII, MI) == AMDGPU::Hwreg::ID_TRAPSTS; 892 }; 893 int WaitStatesNeeded = getWaitStatesSinceSetReg(IsHazardFn, RFEWaitStates); 894 return RFEWaitStates - WaitStatesNeeded; 895 } 896 897 int GCNHazardRecognizer::checkReadM0Hazards(MachineInstr *MI) { 898 const SIInstrInfo *TII = ST.getInstrInfo(); 899 const int SMovRelWaitStates = 1; 900 auto IsHazardFn = [TII](const MachineInstr &MI) { return TII->isSALU(MI); }; 901 return SMovRelWaitStates - getWaitStatesSinceDef(AMDGPU::M0, IsHazardFn, 902 SMovRelWaitStates); 903 } 904 905 void GCNHazardRecognizer::fixHazards(MachineInstr *MI) { 906 fixVMEMtoScalarWriteHazards(MI); 907 fixVcmpxPermlaneHazards(MI); 908 fixSMEMtoVectorWriteHazards(MI); 909 fixVcmpxExecWARHazard(MI); 910 fixLdsBranchVmemWARHazard(MI); 911 } 912 913 bool GCNHazardRecognizer::fixVcmpxPermlaneHazards(MachineInstr *MI) { 914 if (!ST.hasVcmpxPermlaneHazard() || !isPermlane(*MI)) 915 return false; 916 917 const SIInstrInfo *TII = ST.getInstrInfo(); 918 auto IsHazardFn = [TII](const MachineInstr &MI) { return TII->isVOPC(MI); }; 919 920 auto IsExpiredFn = [](const MachineInstr &MI, int) { 921 unsigned Opc = MI.getOpcode(); 922 return SIInstrInfo::isVALU(MI) && Opc != AMDGPU::V_NOP_e32 && 923 Opc != AMDGPU::V_NOP_e64 && Opc != AMDGPU::V_NOP_sdwa; 924 }; 925 926 if (::getWaitStatesSince(IsHazardFn, MI, IsExpiredFn) == 927 std::numeric_limits<int>::max()) 928 return false; 929 930 // V_NOP will be discarded by SQ. 931 // Use V_MOV_B32 v?, v?. Register must be alive so use src0 of V_PERMLANE* 932 // which is always a VGPR and available. 933 auto *Src0 = TII->getNamedOperand(*MI, AMDGPU::OpName::src0); 934 Register Reg = Src0->getReg(); 935 bool IsUndef = Src0->isUndef(); 936 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), 937 TII->get(AMDGPU::V_MOV_B32_e32)) 938 .addReg(Reg, RegState::Define | (IsUndef ? RegState::Dead : 0)) 939 .addReg(Reg, IsUndef ? RegState::Undef : RegState::Kill); 940 941 return true; 942 } 943 944 bool GCNHazardRecognizer::fixVMEMtoScalarWriteHazards(MachineInstr *MI) { 945 if (!ST.hasVMEMtoScalarWriteHazard()) 946 return false; 947 948 if (!SIInstrInfo::isSALU(*MI) && !SIInstrInfo::isSMRD(*MI)) 949 return false; 950 951 if (MI->getNumDefs() == 0) 952 return false; 953 954 const SIRegisterInfo *TRI = ST.getRegisterInfo(); 955 956 auto IsHazardFn = [TRI, MI](const MachineInstr &I) { 957 if (!SIInstrInfo::isVMEM(I) && !SIInstrInfo::isDS(I) && 958 !SIInstrInfo::isFLAT(I)) 959 return false; 960 961 for (const MachineOperand &Def : MI->defs()) { 962 const MachineOperand *Op = 963 I.findRegisterUseOperand(Def.getReg(), false, TRI); 964 if (!Op) 965 continue; 966 return true; 967 } 968 return false; 969 }; 970 971 auto IsExpiredFn = [](const MachineInstr &MI, int) { 972 return SIInstrInfo::isVALU(MI) || 973 (MI.getOpcode() == AMDGPU::S_WAITCNT && 974 !MI.getOperand(0).getImm()) || 975 (MI.getOpcode() == AMDGPU::S_WAITCNT_DEPCTR && 976 MI.getOperand(0).getImm() == 0xffe3); 977 }; 978 979 if (::getWaitStatesSince(IsHazardFn, MI, IsExpiredFn) == 980 std::numeric_limits<int>::max()) 981 return false; 982 983 const SIInstrInfo *TII = ST.getInstrInfo(); 984 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), 985 TII->get(AMDGPU::S_WAITCNT_DEPCTR)) 986 .addImm(0xffe3); 987 return true; 988 } 989 990 bool GCNHazardRecognizer::fixSMEMtoVectorWriteHazards(MachineInstr *MI) { 991 if (!ST.hasSMEMtoVectorWriteHazard()) 992 return false; 993 994 if (!SIInstrInfo::isVALU(*MI)) 995 return false; 996 997 unsigned SDSTName; 998 switch (MI->getOpcode()) { 999 case AMDGPU::V_READLANE_B32: 1000 case AMDGPU::V_READFIRSTLANE_B32: 1001 SDSTName = AMDGPU::OpName::vdst; 1002 break; 1003 default: 1004 SDSTName = AMDGPU::OpName::sdst; 1005 break; 1006 } 1007 1008 const SIInstrInfo *TII = ST.getInstrInfo(); 1009 const SIRegisterInfo *TRI = ST.getRegisterInfo(); 1010 const AMDGPU::IsaVersion IV = AMDGPU::getIsaVersion(ST.getCPU()); 1011 const MachineOperand *SDST = TII->getNamedOperand(*MI, SDSTName); 1012 if (!SDST) { 1013 for (const auto &MO : MI->implicit_operands()) { 1014 if (MO.isDef() && TRI->isSGPRClass(TRI->getPhysRegClass(MO.getReg()))) { 1015 SDST = &MO; 1016 break; 1017 } 1018 } 1019 } 1020 1021 if (!SDST) 1022 return false; 1023 1024 const Register SDSTReg = SDST->getReg(); 1025 auto IsHazardFn = [SDSTReg, TRI](const MachineInstr &I) { 1026 return SIInstrInfo::isSMRD(I) && I.readsRegister(SDSTReg, TRI); 1027 }; 1028 1029 auto IsExpiredFn = [TII, IV](const MachineInstr &MI, int) { 1030 if (TII->isSALU(MI)) { 1031 switch (MI.getOpcode()) { 1032 case AMDGPU::S_SETVSKIP: 1033 case AMDGPU::S_VERSION: 1034 case AMDGPU::S_WAITCNT_VSCNT: 1035 case AMDGPU::S_WAITCNT_VMCNT: 1036 case AMDGPU::S_WAITCNT_EXPCNT: 1037 // These instructions cannot not mitigate the hazard. 1038 return false; 1039 case AMDGPU::S_WAITCNT_LGKMCNT: 1040 // Reducing lgkmcnt count to 0 always mitigates the hazard. 1041 return (MI.getOperand(1).getImm() == 0) && 1042 (MI.getOperand(0).getReg() == AMDGPU::SGPR_NULL); 1043 case AMDGPU::S_WAITCNT: { 1044 const int64_t Imm = MI.getOperand(0).getImm(); 1045 AMDGPU::Waitcnt Decoded = AMDGPU::decodeWaitcnt(IV, Imm); 1046 return (Decoded.LgkmCnt == 0); 1047 } 1048 default: 1049 // SOPP instructions cannot mitigate the hazard. 1050 if (TII->isSOPP(MI)) 1051 return false; 1052 // At this point the SALU can be assumed to mitigate the hazard 1053 // because either: 1054 // (a) it is independent of the at risk SMEM (breaking chain), 1055 // or 1056 // (b) it is dependent on the SMEM, in which case an appropriate 1057 // s_waitcnt lgkmcnt _must_ exist between it and the at risk 1058 // SMEM instruction. 1059 return true; 1060 } 1061 } 1062 return false; 1063 }; 1064 1065 if (::getWaitStatesSince(IsHazardFn, MI, IsExpiredFn) == 1066 std::numeric_limits<int>::max()) 1067 return false; 1068 1069 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), 1070 TII->get(AMDGPU::S_MOV_B32), AMDGPU::SGPR_NULL) 1071 .addImm(0); 1072 return true; 1073 } 1074 1075 bool GCNHazardRecognizer::fixVcmpxExecWARHazard(MachineInstr *MI) { 1076 if (!ST.hasVcmpxExecWARHazard() || !SIInstrInfo::isVALU(*MI)) 1077 return false; 1078 1079 const SIRegisterInfo *TRI = ST.getRegisterInfo(); 1080 if (!MI->modifiesRegister(AMDGPU::EXEC, TRI)) 1081 return false; 1082 1083 auto IsHazardFn = [TRI](const MachineInstr &I) { 1084 if (SIInstrInfo::isVALU(I)) 1085 return false; 1086 return I.readsRegister(AMDGPU::EXEC, TRI); 1087 }; 1088 1089 const SIInstrInfo *TII = ST.getInstrInfo(); 1090 auto IsExpiredFn = [TII, TRI](const MachineInstr &MI, int) { 1091 if (SIInstrInfo::isVALU(MI)) { 1092 if (TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) 1093 return true; 1094 for (auto MO : MI.implicit_operands()) 1095 if (MO.isDef() && TRI->isSGPRClass(TRI->getPhysRegClass(MO.getReg()))) 1096 return true; 1097 } 1098 if (MI.getOpcode() == AMDGPU::S_WAITCNT_DEPCTR && 1099 (MI.getOperand(0).getImm() & 0xfffe) == 0xfffe) 1100 return true; 1101 return false; 1102 }; 1103 1104 if (::getWaitStatesSince(IsHazardFn, MI, IsExpiredFn) == 1105 std::numeric_limits<int>::max()) 1106 return false; 1107 1108 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), 1109 TII->get(AMDGPU::S_WAITCNT_DEPCTR)) 1110 .addImm(0xfffe); 1111 return true; 1112 } 1113 1114 static bool shouldRunLdsBranchVmemWARHazardFixup(const MachineFunction &MF, 1115 const GCNSubtarget &ST) { 1116 if (!ST.hasLdsBranchVmemWARHazard()) 1117 return false; 1118 1119 // Check if the necessary condition for the hazard is met: both LDS and VMEM 1120 // instructions need to appear in the same function. 1121 bool HasLds = false; 1122 bool HasVmem = false; 1123 for (auto &MBB : MF) { 1124 for (auto &MI : MBB) { 1125 HasLds |= SIInstrInfo::isDS(MI); 1126 HasVmem |= 1127 SIInstrInfo::isVMEM(MI) || SIInstrInfo::isSegmentSpecificFLAT(MI); 1128 if (HasLds && HasVmem) 1129 return true; 1130 } 1131 } 1132 return false; 1133 } 1134 1135 bool GCNHazardRecognizer::fixLdsBranchVmemWARHazard(MachineInstr *MI) { 1136 if (!RunLdsBranchVmemWARHazardFixup) 1137 return false; 1138 1139 assert(ST.hasLdsBranchVmemWARHazard()); 1140 1141 auto IsHazardInst = [](const MachineInstr &MI) { 1142 if (SIInstrInfo::isDS(MI)) 1143 return 1; 1144 if (SIInstrInfo::isVMEM(MI) || SIInstrInfo::isSegmentSpecificFLAT(MI)) 1145 return 2; 1146 return 0; 1147 }; 1148 1149 auto InstType = IsHazardInst(*MI); 1150 if (!InstType) 1151 return false; 1152 1153 auto IsExpiredFn = [&IsHazardInst](const MachineInstr &I, int) { 1154 return IsHazardInst(I) || (I.getOpcode() == AMDGPU::S_WAITCNT_VSCNT && 1155 I.getOperand(0).getReg() == AMDGPU::SGPR_NULL && 1156 !I.getOperand(1).getImm()); 1157 }; 1158 1159 auto IsHazardFn = [InstType, &IsHazardInst](const MachineInstr &I) { 1160 if (!I.isBranch()) 1161 return false; 1162 1163 auto IsHazardFn = [InstType, IsHazardInst](const MachineInstr &I) { 1164 auto InstType2 = IsHazardInst(I); 1165 return InstType2 && InstType != InstType2; 1166 }; 1167 1168 auto IsExpiredFn = [InstType, &IsHazardInst](const MachineInstr &I, int) { 1169 auto InstType2 = IsHazardInst(I); 1170 if (InstType == InstType2) 1171 return true; 1172 1173 return I.getOpcode() == AMDGPU::S_WAITCNT_VSCNT && 1174 I.getOperand(0).getReg() == AMDGPU::SGPR_NULL && 1175 !I.getOperand(1).getImm(); 1176 }; 1177 1178 return ::getWaitStatesSince(IsHazardFn, &I, IsExpiredFn) != 1179 std::numeric_limits<int>::max(); 1180 }; 1181 1182 if (::getWaitStatesSince(IsHazardFn, MI, IsExpiredFn) == 1183 std::numeric_limits<int>::max()) 1184 return false; 1185 1186 const SIInstrInfo *TII = ST.getInstrInfo(); 1187 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), 1188 TII->get(AMDGPU::S_WAITCNT_VSCNT)) 1189 .addReg(AMDGPU::SGPR_NULL, RegState::Undef) 1190 .addImm(0); 1191 1192 return true; 1193 } 1194 1195 int GCNHazardRecognizer::checkNSAtoVMEMHazard(MachineInstr *MI) { 1196 int NSAtoVMEMWaitStates = 1; 1197 1198 if (!ST.hasNSAtoVMEMBug()) 1199 return 0; 1200 1201 if (!SIInstrInfo::isMUBUF(*MI) && !SIInstrInfo::isMTBUF(*MI)) 1202 return 0; 1203 1204 const SIInstrInfo *TII = ST.getInstrInfo(); 1205 const auto *Offset = TII->getNamedOperand(*MI, AMDGPU::OpName::offset); 1206 if (!Offset || (Offset->getImm() & 6) == 0) 1207 return 0; 1208 1209 auto IsHazardFn = [TII](const MachineInstr &I) { 1210 if (!SIInstrInfo::isMIMG(I)) 1211 return false; 1212 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(I.getOpcode()); 1213 return Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA && 1214 TII->getInstSizeInBytes(I) >= 16; 1215 }; 1216 1217 return NSAtoVMEMWaitStates - getWaitStatesSince(IsHazardFn, 1); 1218 } 1219 1220 int GCNHazardRecognizer::checkFPAtomicToDenormModeHazard(MachineInstr *MI) { 1221 int FPAtomicToDenormModeWaitStates = 3; 1222 1223 if (MI->getOpcode() != AMDGPU::S_DENORM_MODE) 1224 return 0; 1225 1226 auto IsHazardFn = [](const MachineInstr &I) { 1227 if (!SIInstrInfo::isVMEM(I) && !SIInstrInfo::isFLAT(I)) 1228 return false; 1229 return SIInstrInfo::isFPAtomic(I); 1230 }; 1231 1232 auto IsExpiredFn = [](const MachineInstr &MI, int WaitStates) { 1233 if (WaitStates >= 3 || SIInstrInfo::isVALU(MI)) 1234 return true; 1235 1236 switch (MI.getOpcode()) { 1237 case AMDGPU::S_WAITCNT: 1238 case AMDGPU::S_WAITCNT_VSCNT: 1239 case AMDGPU::S_WAITCNT_VMCNT: 1240 case AMDGPU::S_WAITCNT_EXPCNT: 1241 case AMDGPU::S_WAITCNT_LGKMCNT: 1242 case AMDGPU::S_WAIT_IDLE: 1243 return true; 1244 default: 1245 break; 1246 } 1247 1248 return false; 1249 }; 1250 1251 return FPAtomicToDenormModeWaitStates - 1252 ::getWaitStatesSince(IsHazardFn, MI, IsExpiredFn); 1253 } 1254 1255 int GCNHazardRecognizer::checkMAIHazards(MachineInstr *MI) { 1256 assert(SIInstrInfo::isMAI(*MI)); 1257 1258 return ST.hasGFX90AInsts() ? checkMAIHazards90A(MI) : checkMAIHazards908(MI); 1259 } 1260 1261 int GCNHazardRecognizer::checkMFMAPadding(MachineInstr *MI) { 1262 // Early exit if no padding is requested. 1263 if (MFMAPaddingRatio == 0) 1264 return 0; 1265 1266 auto IsMFMAFn = [](const MachineInstr &MI) { 1267 return SIInstrInfo::isMAI(MI) && 1268 MI.getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32_e64 && 1269 MI.getOpcode() != AMDGPU::V_ACCVGPR_READ_B32_e64; 1270 }; 1271 1272 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); 1273 if (!IsMFMAFn(*MI) || MFI->getOccupancy() < 2) 1274 return 0; 1275 1276 int NeighborMFMALatency = 0; 1277 auto IsNeighboringMFMA = [&IsMFMAFn, &NeighborMFMALatency, 1278 this](const MachineInstr &MI) { 1279 if (!IsMFMAFn(MI)) 1280 return false; 1281 1282 NeighborMFMALatency = this->getMFMAPipelineWaitStates(MI); 1283 return true; 1284 }; 1285 1286 const int MaxMFMAPipelineWaitStates = 16; 1287 int WaitStatesSinceNeighborMFMA = 1288 getWaitStatesSince(IsNeighboringMFMA, MaxMFMAPipelineWaitStates); 1289 1290 int NeighborMFMAPaddingNeeded = 1291 (NeighborMFMALatency * MFMAPaddingRatio / 100) - 1292 WaitStatesSinceNeighborMFMA; 1293 1294 return std::max(0, NeighborMFMAPaddingNeeded); 1295 } 1296 1297 int GCNHazardRecognizer::checkMAIHazards908(MachineInstr *MI) { 1298 int WaitStatesNeeded = 0; 1299 unsigned Opc = MI->getOpcode(); 1300 1301 auto IsVALUFn = [](const MachineInstr &MI) { 1302 return SIInstrInfo::isVALU(MI); 1303 }; 1304 1305 if (Opc != AMDGPU::V_ACCVGPR_READ_B32_e64) { // MFMA or v_accvgpr_write 1306 const int LegacyVALUWritesVGPRWaitStates = 2; 1307 const int VALUWritesExecWaitStates = 4; 1308 const int MaxWaitStates = 4; 1309 1310 int WaitStatesNeededForUse = VALUWritesExecWaitStates - 1311 getWaitStatesSinceDef(AMDGPU::EXEC, IsVALUFn, MaxWaitStates); 1312 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse); 1313 1314 if (WaitStatesNeeded < MaxWaitStates) { 1315 for (const MachineOperand &Use : MI->explicit_uses()) { 1316 const int MaxWaitStates = 2; 1317 1318 if (!Use.isReg() || !TRI.isVGPR(MF.getRegInfo(), Use.getReg())) 1319 continue; 1320 1321 int WaitStatesNeededForUse = LegacyVALUWritesVGPRWaitStates - 1322 getWaitStatesSinceDef(Use.getReg(), IsVALUFn, MaxWaitStates); 1323 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse); 1324 1325 if (WaitStatesNeeded == MaxWaitStates) 1326 break; 1327 } 1328 } 1329 } 1330 1331 auto IsMFMAFn = [](const MachineInstr &MI) { 1332 return SIInstrInfo::isMAI(MI) && 1333 MI.getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32_e64 && 1334 MI.getOpcode() != AMDGPU::V_ACCVGPR_READ_B32_e64; 1335 }; 1336 1337 for (const MachineOperand &Op : MI->explicit_operands()) { 1338 if (!Op.isReg() || !TRI.isAGPR(MF.getRegInfo(), Op.getReg())) 1339 continue; 1340 1341 if (Op.isDef() && Opc != AMDGPU::V_ACCVGPR_WRITE_B32_e64) 1342 continue; 1343 1344 const int MFMAWritesAGPROverlappedSrcABWaitStates = 4; 1345 const int MFMAWritesAGPROverlappedSrcCWaitStates = 2; 1346 const int MFMA4x4WritesAGPRAccVgprReadWaitStates = 4; 1347 const int MFMA16x16WritesAGPRAccVgprReadWaitStates = 10; 1348 const int MFMA32x32WritesAGPRAccVgprReadWaitStates = 18; 1349 const int MFMA4x4WritesAGPRAccVgprWriteWaitStates = 1; 1350 const int MFMA16x16WritesAGPRAccVgprWriteWaitStates = 7; 1351 const int MFMA32x32WritesAGPRAccVgprWriteWaitStates = 15; 1352 const int MaxWaitStates = 18; 1353 Register Reg = Op.getReg(); 1354 unsigned HazardDefLatency = 0; 1355 1356 auto IsOverlappedMFMAFn = [Reg, &IsMFMAFn, &HazardDefLatency, 1357 this](const MachineInstr &MI) { 1358 if (!IsMFMAFn(MI)) 1359 return false; 1360 Register DstReg = MI.getOperand(0).getReg(); 1361 if (DstReg == Reg) 1362 return false; 1363 HazardDefLatency = 1364 std::max(HazardDefLatency, TSchedModel.computeInstrLatency(&MI)); 1365 return TRI.regsOverlap(DstReg, Reg); 1366 }; 1367 1368 int WaitStatesSinceDef = getWaitStatesSinceDef(Reg, IsOverlappedMFMAFn, 1369 MaxWaitStates); 1370 int NeedWaitStates = MFMAWritesAGPROverlappedSrcABWaitStates; 1371 int SrcCIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2); 1372 int OpNo = MI->getOperandNo(&Op); 1373 if (OpNo == SrcCIdx) { 1374 NeedWaitStates = MFMAWritesAGPROverlappedSrcCWaitStates; 1375 } else if (Opc == AMDGPU::V_ACCVGPR_READ_B32_e64) { 1376 switch (HazardDefLatency) { 1377 case 2: NeedWaitStates = MFMA4x4WritesAGPRAccVgprReadWaitStates; 1378 break; 1379 case 8: NeedWaitStates = MFMA16x16WritesAGPRAccVgprReadWaitStates; 1380 break; 1381 case 16: LLVM_FALLTHROUGH; 1382 default: NeedWaitStates = MFMA32x32WritesAGPRAccVgprReadWaitStates; 1383 break; 1384 } 1385 } else if (Opc == AMDGPU::V_ACCVGPR_WRITE_B32_e64) { 1386 switch (HazardDefLatency) { 1387 case 2: NeedWaitStates = MFMA4x4WritesAGPRAccVgprWriteWaitStates; 1388 break; 1389 case 8: NeedWaitStates = MFMA16x16WritesAGPRAccVgprWriteWaitStates; 1390 break; 1391 case 16: LLVM_FALLTHROUGH; 1392 default: NeedWaitStates = MFMA32x32WritesAGPRAccVgprWriteWaitStates; 1393 break; 1394 } 1395 } 1396 1397 int WaitStatesNeededForUse = NeedWaitStates - WaitStatesSinceDef; 1398 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse); 1399 1400 if (WaitStatesNeeded == MaxWaitStates) 1401 return WaitStatesNeeded; // Early exit. 1402 1403 auto IsAccVgprWriteFn = [Reg, this](const MachineInstr &MI) { 1404 if (MI.getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32_e64) 1405 return false; 1406 Register DstReg = MI.getOperand(0).getReg(); 1407 return TRI.regsOverlap(Reg, DstReg); 1408 }; 1409 1410 const int AccVGPRWriteMFMAReadSrcCWaitStates = 1; 1411 const int AccVGPRWriteMFMAReadSrcABWaitStates = 3; 1412 const int AccVGPRWriteAccVgprReadWaitStates = 3; 1413 NeedWaitStates = AccVGPRWriteMFMAReadSrcABWaitStates; 1414 if (OpNo == SrcCIdx) 1415 NeedWaitStates = AccVGPRWriteMFMAReadSrcCWaitStates; 1416 else if (Opc == AMDGPU::V_ACCVGPR_READ_B32_e64) 1417 NeedWaitStates = AccVGPRWriteAccVgprReadWaitStates; 1418 1419 WaitStatesNeededForUse = NeedWaitStates - 1420 getWaitStatesSinceDef(Reg, IsAccVgprWriteFn, MaxWaitStates); 1421 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse); 1422 1423 if (WaitStatesNeeded == MaxWaitStates) 1424 return WaitStatesNeeded; // Early exit. 1425 } 1426 1427 if (Opc == AMDGPU::V_ACCVGPR_WRITE_B32_e64) { 1428 const int MFMA4x4ReadSrcCAccVgprWriteWaitStates = 0; 1429 const int MFMA16x16ReadSrcCAccVgprWriteWaitStates = 5; 1430 const int MFMA32x32ReadSrcCAccVgprWriteWaitStates = 13; 1431 const int MaxWaitStates = 13; 1432 Register DstReg = MI->getOperand(0).getReg(); 1433 unsigned HazardDefLatency = 0; 1434 1435 auto IsSrcCMFMAFn = [DstReg, &IsMFMAFn, &HazardDefLatency, 1436 this](const MachineInstr &MI) { 1437 if (!IsMFMAFn(MI)) 1438 return false; 1439 Register Reg = TII.getNamedOperand(MI, AMDGPU::OpName::src2)->getReg(); 1440 HazardDefLatency = 1441 std::max(HazardDefLatency, TSchedModel.computeInstrLatency(&MI)); 1442 return TRI.regsOverlap(Reg, DstReg); 1443 }; 1444 1445 int WaitStatesSince = getWaitStatesSince(IsSrcCMFMAFn, MaxWaitStates); 1446 int NeedWaitStates; 1447 switch (HazardDefLatency) { 1448 case 2: NeedWaitStates = MFMA4x4ReadSrcCAccVgprWriteWaitStates; 1449 break; 1450 case 8: NeedWaitStates = MFMA16x16ReadSrcCAccVgprWriteWaitStates; 1451 break; 1452 case 16: LLVM_FALLTHROUGH; 1453 default: NeedWaitStates = MFMA32x32ReadSrcCAccVgprWriteWaitStates; 1454 break; 1455 } 1456 1457 int WaitStatesNeededForUse = NeedWaitStates - WaitStatesSince; 1458 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse); 1459 } 1460 1461 // Pad neighboring MFMA with noops for better inter-wave performance. 1462 WaitStatesNeeded = std::max(WaitStatesNeeded, checkMFMAPadding(MI)); 1463 1464 return WaitStatesNeeded; 1465 } 1466 1467 int GCNHazardRecognizer::checkMAIHazards90A(MachineInstr *MI) { 1468 int WaitStatesNeeded = 0; 1469 unsigned Opc = MI->getOpcode(); 1470 1471 auto IsMFMAFn = [](const MachineInstr &MI) { 1472 return SIInstrInfo::isMAI(MI) && 1473 MI.getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32_e64 && 1474 MI.getOpcode() != AMDGPU::V_ACCVGPR_READ_B32_e64; 1475 }; 1476 1477 auto IsLegacyVALUFn = [&IsMFMAFn](const MachineInstr &MI) { 1478 return SIInstrInfo::isVALU(MI) && !IsMFMAFn(MI); 1479 }; 1480 1481 auto IsLegacyVALUNotDotFn = [&IsMFMAFn](const MachineInstr &MI) { 1482 return SIInstrInfo::isVALU(MI) && !IsMFMAFn(MI) && !SIInstrInfo::isDOT(MI); 1483 }; 1484 1485 if (!IsMFMAFn(*MI)) 1486 return WaitStatesNeeded; 1487 1488 const int VALUWritesExecWaitStates = 4; 1489 int WaitStatesNeededForUse = VALUWritesExecWaitStates - 1490 getWaitStatesSinceDef(AMDGPU::EXEC, IsLegacyVALUFn, 1491 VALUWritesExecWaitStates); 1492 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse); 1493 1494 int SrcCIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2); 1495 1496 // Loop for both DGEMM and S/HGEMM 2nd instruction. 1497 for (const MachineOperand &Use : MI->explicit_uses()) { 1498 const int LegacyVALUNotDotWritesVGPRWaitStates = 2; 1499 const int SMFMA4x4WritesVGPROverlappedSMFMASrcCWaitStates = 2; 1500 const int GFX940_XDL2PassWritesVGPROverlappedSMFMASrcCWaitStates = 3; 1501 const int GFX940_XDL4PassWritesVGPROverlappedSMFMASrcCWaitStates = 5; 1502 const int GFX940_SMFMA4PassWritesVGPROverlappedSMFMASrcCWaitStates = 4; 1503 const int GFX940_XDL8PassWritesVGPROverlappedSMFMASrcCWaitStates = 9; 1504 const int GFX940_SMFMA8PassWritesVGPROverlappedSMFMASrcCWaitStates = 8; 1505 const int GFX940_XDL16PassWritesVGPROverlappedSMFMASrcCWaitStates = 17; 1506 const int GFX940_SMFMA16PassWritesVGPROverlappedSMFMASrcCWaitStates = 16; 1507 const int SMFMA16x16WritesVGPROverlappedSMFMASrcCWaitStates = 8; 1508 const int SMFMA32x32WritesVGPROverlappedSMFMASrcCWaitStates = 16; 1509 const int SMFMA4x4WritesVGPROverlappedDMFMASrcCWaitStates = 3; 1510 const int SMFMA16x16WritesVGPROverlappedDMFMASrcCWaitStates = 9; 1511 const int SMFMA32x32WritesVGPROverlappedDMFMASrcCWaitStates = 17; 1512 const int DMFMA16x16WritesVGPROverlappedSrcCWaitStates = 9; 1513 const int DMFMA4x4WritesVGPROverlappedSrcCWaitStates = 4; 1514 const int SMFMA4x4WritesVGPROverlappedSrcABWaitStates = 5; 1515 const int SMFMA16x16WritesVGPROverlappedSrcABWaitStates = 11; 1516 const int SMFMA32x32WritesVGPROverlappedSrcABWaitStates = 19; 1517 const int GFX940_SMFMA2PassWritesVGPROverlappedSrcABWaitStates = 4; 1518 const int GFX940_SMFMA4PassWritesVGPROverlappedSrcABWaitStates = 6; 1519 const int GFX940_SMFMA8PassWritesVGPROverlappedSrcABWaitStates = 10; 1520 const int GFX940_SMFMA16PassWritesVGPROverlappedSrcABWaitStates = 18; 1521 const int GFX940_XDL2PassWritesVGPROverlappedSrcABWaitStates = 5; 1522 const int GFX940_XDL4PassWritesVGPROverlappedSrcABWaitStates = 7; 1523 const int GFX940_XDL8PassWritesVGPROverlappedSrcABWaitStates = 11; 1524 const int GFX940_XDL16PassWritesVGPROverlappedSrcABWaitStates = 19; 1525 const int DMFMA4x4WritesVGPROverlappedMFMASrcABWaitStates = 6; 1526 const int DMFMA16x16WritesVGPROverlappedMFMASrcABWaitStates = 11; 1527 const int DMFMA4x4WritesVGPRFullSrcCWaitStates = 4; 1528 const int GFX940_SMFMA4x4WritesVGPRFullSrcCWaitStates = 2; 1529 const int MaxWaitStates = 19; 1530 1531 if (!Use.isReg()) 1532 continue; 1533 Register Reg = Use.getReg(); 1534 bool FullReg; 1535 const MachineInstr *MI1; 1536 1537 auto IsOverlappedMFMAFn = [Reg, &IsMFMAFn, &FullReg, &MI1, 1538 this](const MachineInstr &MI) { 1539 if (!IsMFMAFn(MI)) 1540 return false; 1541 Register DstReg = MI.getOperand(0).getReg(); 1542 FullReg = (DstReg == Reg); 1543 MI1 = &MI; 1544 return TRI.regsOverlap(DstReg, Reg); 1545 }; 1546 1547 WaitStatesNeededForUse = LegacyVALUNotDotWritesVGPRWaitStates - 1548 getWaitStatesSinceDef(Reg, IsLegacyVALUNotDotFn, MaxWaitStates); 1549 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse); 1550 1551 int NumWaitStates = 1552 getWaitStatesSinceDef(Reg, IsOverlappedMFMAFn, MaxWaitStates); 1553 if (NumWaitStates == std::numeric_limits<int>::max()) 1554 continue; 1555 1556 int OpNo = MI->getOperandNo(&Use); 1557 unsigned Opc1 = MI1->getOpcode(); 1558 int NeedWaitStates = 0; 1559 if (OpNo == SrcCIdx) { 1560 if (!isDGEMM(Opc) && (!ST.hasGFX940Insts() && isDGEMM(Opc1))) { 1561 NeedWaitStates = 0; 1562 } else if (FullReg) { 1563 if ((Opc == AMDGPU::V_MFMA_F64_4X4X4F64_e64 || 1564 Opc == AMDGPU::V_MFMA_F64_4X4X4F64_vgprcd_e64) && 1565 (Opc1 == AMDGPU::V_MFMA_F64_4X4X4F64_e64 || 1566 Opc1 == AMDGPU::V_MFMA_F64_4X4X4F64_vgprcd_e64)) 1567 NeedWaitStates = DMFMA4x4WritesVGPRFullSrcCWaitStates; 1568 else if (ST.hasGFX940Insts() && 1569 TSchedModel.computeInstrLatency(MI1) == 2) 1570 NeedWaitStates = GFX940_SMFMA4x4WritesVGPRFullSrcCWaitStates; 1571 } else { 1572 switch (Opc1) { 1573 case AMDGPU::V_MFMA_F64_16X16X4F64_e64: 1574 case AMDGPU::V_MFMA_F64_16X16X4F64_vgprcd_e64: 1575 case AMDGPU::V_MFMA_F64_16X16X4F64_mac_e64: 1576 case AMDGPU::V_MFMA_F64_16X16X4F64_mac_vgprcd_e64: 1577 if (!isXDL(ST, *MI)) 1578 NeedWaitStates = DMFMA16x16WritesVGPROverlappedSrcCWaitStates; 1579 break; 1580 case AMDGPU::V_MFMA_F64_4X4X4F64_e64: 1581 case AMDGPU::V_MFMA_F64_4X4X4F64_vgprcd_e64: 1582 if (!isXDL(ST, *MI)) 1583 NeedWaitStates = DMFMA4x4WritesVGPROverlappedSrcCWaitStates; 1584 break; 1585 default: 1586 if (ST.hasGFX940Insts() && isXDL(ST, *MI) && !isXDL(ST, *MI1)) 1587 break; 1588 switch (TSchedModel.computeInstrLatency(MI1)) { 1589 case 2: 1590 NeedWaitStates = ST.hasGFX940Insts() 1591 ? isXDL(ST, *MI1) 1592 ? GFX940_XDL2PassWritesVGPROverlappedSMFMASrcCWaitStates 1593 : SMFMA4x4WritesVGPROverlappedSMFMASrcCWaitStates 1594 : isDGEMM(Opc) 1595 ? SMFMA4x4WritesVGPROverlappedDMFMASrcCWaitStates 1596 : SMFMA4x4WritesVGPROverlappedSMFMASrcCWaitStates; 1597 break; 1598 case 4: 1599 assert(ST.hasGFX940Insts()); 1600 NeedWaitStates = isXDL(ST, *MI1) 1601 ? GFX940_XDL4PassWritesVGPROverlappedSMFMASrcCWaitStates 1602 : GFX940_SMFMA4PassWritesVGPROverlappedSMFMASrcCWaitStates; 1603 break; 1604 case 8: 1605 NeedWaitStates = ST.hasGFX940Insts() 1606 ? isXDL(ST, *MI1) 1607 ? GFX940_XDL8PassWritesVGPROverlappedSMFMASrcCWaitStates 1608 : GFX940_SMFMA8PassWritesVGPROverlappedSMFMASrcCWaitStates 1609 : isDGEMM(Opc) 1610 ? SMFMA16x16WritesVGPROverlappedDMFMASrcCWaitStates 1611 : SMFMA16x16WritesVGPROverlappedSMFMASrcCWaitStates; 1612 break; 1613 case 16: LLVM_FALLTHROUGH; 1614 default: 1615 NeedWaitStates = ST.hasGFX940Insts() 1616 ? isXDL(ST, *MI1) 1617 ? GFX940_XDL16PassWritesVGPROverlappedSMFMASrcCWaitStates 1618 : GFX940_SMFMA16PassWritesVGPROverlappedSMFMASrcCWaitStates 1619 : isDGEMM(Opc) 1620 ? SMFMA32x32WritesVGPROverlappedDMFMASrcCWaitStates 1621 : SMFMA32x32WritesVGPROverlappedSMFMASrcCWaitStates; 1622 } 1623 } 1624 } 1625 } else { 1626 switch (Opc1) { 1627 case AMDGPU::V_MFMA_F64_16X16X4F64_e64: 1628 case AMDGPU::V_MFMA_F64_16X16X4F64_vgprcd_e64: 1629 case AMDGPU::V_MFMA_F64_16X16X4F64_mac_e64: 1630 case AMDGPU::V_MFMA_F64_16X16X4F64_mac_vgprcd_e64: 1631 NeedWaitStates = DMFMA16x16WritesVGPROverlappedMFMASrcABWaitStates; 1632 break; 1633 case AMDGPU::V_MFMA_F64_4X4X4F64_e64: 1634 case AMDGPU::V_MFMA_F64_4X4X4F64_vgprcd_e64: 1635 NeedWaitStates = DMFMA4x4WritesVGPROverlappedMFMASrcABWaitStates; 1636 break; 1637 default: 1638 switch (TSchedModel.computeInstrLatency(MI1)) { 1639 case 2: 1640 NeedWaitStates = ST.hasGFX940Insts() 1641 ? isXDL(ST, *MI1) 1642 ? GFX940_XDL2PassWritesVGPROverlappedSrcABWaitStates 1643 : GFX940_SMFMA2PassWritesVGPROverlappedSrcABWaitStates 1644 : SMFMA4x4WritesVGPROverlappedSrcABWaitStates; 1645 break; 1646 case 4: 1647 assert(ST.hasGFX940Insts()); 1648 NeedWaitStates = isXDL(ST, *MI1) 1649 ? GFX940_XDL4PassWritesVGPROverlappedSrcABWaitStates 1650 : GFX940_SMFMA4PassWritesVGPROverlappedSrcABWaitStates; 1651 break; 1652 case 8: 1653 NeedWaitStates = ST.hasGFX940Insts() 1654 ? isXDL(ST, *MI1) 1655 ? GFX940_XDL8PassWritesVGPROverlappedSrcABWaitStates 1656 : GFX940_SMFMA8PassWritesVGPROverlappedSrcABWaitStates 1657 : SMFMA16x16WritesVGPROverlappedSrcABWaitStates; 1658 break; 1659 case 16: LLVM_FALLTHROUGH; 1660 default: 1661 NeedWaitStates = ST.hasGFX940Insts() 1662 ? isXDL(ST, *MI1) 1663 ? GFX940_XDL16PassWritesVGPROverlappedSrcABWaitStates 1664 : GFX940_SMFMA16PassWritesVGPROverlappedSrcABWaitStates 1665 : SMFMA32x32WritesVGPROverlappedSrcABWaitStates; 1666 } 1667 } 1668 } 1669 if (WaitStatesNeeded >= NeedWaitStates) 1670 continue; 1671 1672 WaitStatesNeededForUse = NeedWaitStates - NumWaitStates; 1673 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse); 1674 1675 if (WaitStatesNeeded == MaxWaitStates) 1676 break; 1677 } 1678 1679 return WaitStatesNeeded; 1680 } 1681 1682 int GCNHazardRecognizer::checkMAILdStHazards(MachineInstr *MI) { 1683 // On gfx90a+ relevant hazards are checked in checkMAIVALUHazards() 1684 if (!ST.hasMAIInsts() || ST.hasGFX90AInsts()) 1685 return 0; 1686 1687 int WaitStatesNeeded = 0; 1688 1689 auto IsAccVgprReadFn = [](const MachineInstr &MI) { 1690 return MI.getOpcode() == AMDGPU::V_ACCVGPR_READ_B32_e64; 1691 }; 1692 1693 for (const MachineOperand &Op : MI->explicit_uses()) { 1694 if (!Op.isReg() || !TRI.isVGPR(MF.getRegInfo(), Op.getReg())) 1695 continue; 1696 1697 Register Reg = Op.getReg(); 1698 1699 const int AccVgprReadLdStWaitStates = 2; 1700 const int VALUWriteAccVgprRdWrLdStDepVALUWaitStates = 1; 1701 const int MaxWaitStates = 2; 1702 1703 int WaitStatesNeededForUse = AccVgprReadLdStWaitStates - 1704 getWaitStatesSinceDef(Reg, IsAccVgprReadFn, MaxWaitStates); 1705 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse); 1706 1707 if (WaitStatesNeeded == MaxWaitStates) 1708 return WaitStatesNeeded; // Early exit. 1709 1710 auto IsVALUAccVgprRdWrCheckFn = [Reg, this](const MachineInstr &MI) { 1711 if (MI.getOpcode() != AMDGPU::V_ACCVGPR_READ_B32_e64 && 1712 MI.getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32_e64) 1713 return false; 1714 auto IsVALUFn = [](const MachineInstr &MI) { 1715 return SIInstrInfo::isVALU(MI) && !SIInstrInfo::isMAI(MI); 1716 }; 1717 return getWaitStatesSinceDef(Reg, IsVALUFn, 2 /*MaxWaitStates*/) < 1718 std::numeric_limits<int>::max(); 1719 }; 1720 1721 WaitStatesNeededForUse = VALUWriteAccVgprRdWrLdStDepVALUWaitStates - 1722 getWaitStatesSince(IsVALUAccVgprRdWrCheckFn, MaxWaitStates); 1723 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse); 1724 } 1725 1726 return WaitStatesNeeded; 1727 } 1728 1729 int GCNHazardRecognizer::checkMAIVALUHazards(MachineInstr *MI) { 1730 if (!ST.hasGFX90AInsts()) 1731 return 0; 1732 1733 auto IsMFMAFn = [](const MachineInstr &MI) -> bool { 1734 return SIInstrInfo::isMAI(MI) && 1735 MI.getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32_e64 && 1736 MI.getOpcode() != AMDGPU::V_ACCVGPR_READ_B32_e64; 1737 }; 1738 1739 auto IsDGEMMFn = [](const MachineInstr &MI) -> bool { 1740 return isDGEMM(MI.getOpcode()); 1741 }; 1742 1743 // This is checked in checkMAIHazards90A() 1744 if (IsMFMAFn(*MI)) 1745 return 0; 1746 1747 int WaitStatesNeeded = 0; 1748 1749 bool IsMemOrExport = SIInstrInfo::isVMEM(*MI) || 1750 SIInstrInfo::isFLAT(*MI) || 1751 SIInstrInfo::isDS(*MI) || 1752 SIInstrInfo::isEXP(*MI); 1753 bool IsVALU = SIInstrInfo::isVALU(*MI); 1754 1755 const MachineInstr *MFMA = nullptr; 1756 unsigned Reg; 1757 auto IsMFMAWriteFn = [&Reg, &IsMFMAFn, &MFMA, this](const MachineInstr &MI) { 1758 if (!IsMFMAFn(MI) || !TRI.regsOverlap(MI.getOperand(0).getReg(), Reg)) 1759 return false; 1760 MFMA = &MI; 1761 return true; 1762 }; 1763 1764 const MachineInstr *DOT = nullptr; 1765 auto IsDotWriteFn = [&Reg, &DOT, this](const MachineInstr &MI) { 1766 if (!SIInstrInfo::isDOT(MI) || 1767 !TRI.regsOverlap(MI.getOperand(0).getReg(), Reg)) 1768 return false; 1769 DOT = &MI; 1770 return true; 1771 }; 1772 1773 int SrcCIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(), 1774 AMDGPU::OpName::src2); 1775 1776 if (IsMemOrExport || IsVALU) { 1777 const int SMFMA4x4WriteVgprVALUMemExpReadWaitStates = 5; 1778 const int SMFMA16x16WriteVgprVALUMemExpReadWaitStates = 11; 1779 const int SMFMA32x32WriteVgprVALUMemExpReadWaitStates = 19; 1780 const int GFX940_SMFMA2PassWriteVgprVALUMemExpReadWaitStates = 4; 1781 const int GFX940_SMFMA4PassWriteVgprVALUMemExpReadWaitStates = 6; 1782 const int GFX940_SMFMA8PassWriteVgprVALUMemExpReadWaitStates = 10; 1783 const int GFX940_SMFMA16PassWriteVgprVALUMemExpReadWaitStates = 18; 1784 const int GFX940_XDL2PassWriteVgprVALUMemExpReadWaitStates = 5; 1785 const int GFX940_XDL4PassWriteVgprVALUMemExpReadWaitStates = 7; 1786 const int GFX940_XDL8PassWriteVgprVALUMemExpReadWaitStates = 11; 1787 const int GFX940_XDL16PassWriteVgprVALUMemExpReadWaitStates = 19; 1788 const int DMFMA4x4WriteVgprMemExpReadWaitStates = 9; 1789 const int DMFMA16x16WriteVgprMemExpReadWaitStates = 18; 1790 const int DMFMA4x4WriteVgprVALUReadWaitStates = 6; 1791 const int DMFMA16x16WriteVgprVALUReadWaitStates = 11; 1792 const int DotWriteSameDotReadSrcAB = 3; 1793 const int DotWriteDifferentVALURead = 3; 1794 const int MaxWaitStates = 19; 1795 1796 for (const MachineOperand &Use : MI->explicit_uses()) { 1797 if (!Use.isReg()) 1798 continue; 1799 Reg = Use.getReg(); 1800 1801 DOT = nullptr; 1802 int WaitStatesSinceDef = getWaitStatesSinceDef(Reg, IsDotWriteFn, 1803 MaxWaitStates); 1804 if (DOT) { 1805 int NeedWaitStates = 0; 1806 if (DOT->getOpcode() == MI->getOpcode()) { 1807 if (&Use - &MI->getOperand(0) != SrcCIdx) 1808 NeedWaitStates = DotWriteSameDotReadSrcAB; 1809 } else { 1810 NeedWaitStates = DotWriteDifferentVALURead; 1811 } 1812 1813 int WaitStatesNeededForUse = NeedWaitStates - WaitStatesSinceDef; 1814 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse); 1815 } 1816 1817 MFMA = nullptr; 1818 WaitStatesSinceDef = 1819 getWaitStatesSinceDef(Reg, IsMFMAWriteFn, MaxWaitStates); 1820 if (!MFMA) 1821 continue; 1822 1823 unsigned HazardDefLatency = TSchedModel.computeInstrLatency(MFMA); 1824 int NeedWaitStates = MaxWaitStates; 1825 switch (HazardDefLatency) { 1826 case 2: 1827 NeedWaitStates = 1828 ST.hasGFX940Insts() 1829 ? isXDL(ST, *MFMA) 1830 ? GFX940_XDL2PassWriteVgprVALUMemExpReadWaitStates 1831 : GFX940_SMFMA2PassWriteVgprVALUMemExpReadWaitStates 1832 : SMFMA4x4WriteVgprVALUMemExpReadWaitStates; 1833 break; 1834 case 4: 1835 assert(isDGEMM(MFMA->getOpcode()) || ST.hasGFX940Insts()); 1836 NeedWaitStates = 1837 isDGEMM(MFMA->getOpcode()) 1838 ? IsMemOrExport ? DMFMA4x4WriteVgprMemExpReadWaitStates 1839 : DMFMA4x4WriteVgprVALUReadWaitStates 1840 : isXDL(ST, *MFMA) 1841 ? GFX940_XDL4PassWriteVgprVALUMemExpReadWaitStates 1842 : GFX940_SMFMA4PassWriteVgprVALUMemExpReadWaitStates; 1843 break; 1844 case 8: 1845 NeedWaitStates = 1846 ST.hasGFX940Insts() 1847 ? isXDL(ST, *MFMA) 1848 ? GFX940_XDL8PassWriteVgprVALUMemExpReadWaitStates 1849 : GFX940_SMFMA8PassWriteVgprVALUMemExpReadWaitStates 1850 : SMFMA16x16WriteVgprVALUMemExpReadWaitStates; 1851 break; 1852 case 16: LLVM_FALLTHROUGH; 1853 default: 1854 NeedWaitStates = 1855 isDGEMM(MFMA->getOpcode()) 1856 ? IsMemOrExport ? DMFMA16x16WriteVgprMemExpReadWaitStates 1857 : DMFMA16x16WriteVgprVALUReadWaitStates 1858 : ST.hasGFX940Insts() 1859 ? isXDL(ST, *MFMA) 1860 ? GFX940_XDL16PassWriteVgprVALUMemExpReadWaitStates 1861 : GFX940_SMFMA16PassWriteVgprVALUMemExpReadWaitStates 1862 : SMFMA32x32WriteVgprVALUMemExpReadWaitStates; 1863 break; 1864 } 1865 1866 int WaitStatesNeededForUse = NeedWaitStates - WaitStatesSinceDef; 1867 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse); 1868 1869 if (WaitStatesNeeded == MaxWaitStates) 1870 break; 1871 } 1872 } 1873 1874 unsigned Opc = MI->getOpcode(); 1875 const int DMFMAToFMA64WaitStates = 2; 1876 if ((Opc == AMDGPU::V_FMA_F64_e64 || 1877 Opc == AMDGPU::V_FMAC_F64_e32 || Opc == AMDGPU::V_FMAC_F64_e64 || 1878 Opc == AMDGPU::V_FMAC_F64_dpp) && 1879 WaitStatesNeeded < DMFMAToFMA64WaitStates) { 1880 int WaitStatesNeededForUse = DMFMAToFMA64WaitStates - 1881 getWaitStatesSince(IsDGEMMFn, DMFMAToFMA64WaitStates); 1882 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse); 1883 } 1884 1885 if (!IsVALU && !IsMemOrExport) 1886 return WaitStatesNeeded; 1887 1888 for (const MachineOperand &Def : MI->defs()) { 1889 const int SMFMA4x4WriteVgprVALUWawWaitStates = 5; 1890 const int SMFMA16x16WriteVgprVALUWawWaitStates = 11; 1891 const int SMFMA32x32WriteVgprVALUWawWaitStates = 19; 1892 const int GFX940_SMFMA2PassWriteVgprVALUWawWaitStates = 4; 1893 const int GFX940_SMFMA4PassWriteVgprVALUWawWaitStates = 6; 1894 const int GFX940_SMFMA8PassWriteVgprVALUWawWaitStates = 10; 1895 const int GFX940_SMFMA16PassWriteVgprVALUWawWaitStates = 18; 1896 const int GFX940_XDL2PassWriteVgprVALUWawWaitStates = 5; 1897 const int GFX940_XDL4PassWriteVgprVALUWawWaitStates = 7; 1898 const int GFX940_XDL8PassWriteVgprVALUWawWaitStates = 11; 1899 const int GFX940_XDL16PassWriteVgprVALUWawWaitStates = 19; 1900 const int SMFMA4x4ReadVgprVALUWarWaitStates = 1; 1901 const int GFX940_XDL4PassReadVgprVALUWarWaitStates = 3; 1902 const int SMFMA16x16ReadVgprVALUWarWaitStates = 7; 1903 const int SMFMA32x32ReadVgprVALUWarWaitStates = 15; 1904 const int DMFMA4x4WriteVgprVALUWriteWaitStates = 6; 1905 const int DMFMA16x16WriteVgprVALUWriteWaitStates = 11; 1906 const int DotWriteDifferentVALUWrite = 3; 1907 const int MaxWaitStates = 19; 1908 const int MaxWarWaitStates = 15; 1909 1910 Reg = Def.getReg(); 1911 1912 DOT = nullptr; 1913 int WaitStatesSinceDef = getWaitStatesSinceDef(Reg, IsDotWriteFn, 1914 MaxWaitStates); 1915 if (DOT && DOT->getOpcode() != MI->getOpcode()) 1916 WaitStatesNeeded = std::max(WaitStatesNeeded, DotWriteDifferentVALUWrite - 1917 WaitStatesSinceDef); 1918 1919 MFMA = nullptr; 1920 WaitStatesSinceDef = 1921 getWaitStatesSinceDef(Reg, IsMFMAWriteFn, MaxWaitStates); 1922 if (MFMA) { 1923 int NeedWaitStates = MaxWaitStates; 1924 switch (TSchedModel.computeInstrLatency(MFMA)) { 1925 case 2: 1926 NeedWaitStates = ST.hasGFX940Insts() 1927 ? isXDL(ST, *MFMA) 1928 ? GFX940_XDL2PassWriteVgprVALUWawWaitStates 1929 : GFX940_SMFMA2PassWriteVgprVALUWawWaitStates 1930 : SMFMA4x4WriteVgprVALUWawWaitStates; 1931 break; 1932 case 4: 1933 assert(isDGEMM(MFMA->getOpcode()) || ST.hasGFX940Insts()); 1934 NeedWaitStates = isDGEMM(MFMA->getOpcode()) 1935 ? DMFMA4x4WriteVgprVALUWriteWaitStates 1936 : isXDL(ST, *MFMA) 1937 ? GFX940_XDL4PassWriteVgprVALUWawWaitStates 1938 : GFX940_SMFMA4PassWriteVgprVALUWawWaitStates; 1939 break; 1940 case 8: 1941 NeedWaitStates = ST.hasGFX940Insts() 1942 ? isXDL(ST, *MFMA) 1943 ? GFX940_XDL8PassWriteVgprVALUWawWaitStates 1944 : GFX940_SMFMA8PassWriteVgprVALUWawWaitStates 1945 : SMFMA16x16WriteVgprVALUWawWaitStates; 1946 break; 1947 case 16: LLVM_FALLTHROUGH; 1948 default: 1949 NeedWaitStates = isDGEMM(MFMA->getOpcode()) 1950 ? DMFMA16x16WriteVgprVALUWriteWaitStates 1951 : ST.hasGFX940Insts() 1952 ? isXDL(ST, *MFMA) 1953 ? GFX940_XDL16PassWriteVgprVALUWawWaitStates 1954 : GFX940_SMFMA16PassWriteVgprVALUWawWaitStates 1955 : SMFMA32x32WriteVgprVALUWawWaitStates; 1956 break; 1957 } 1958 1959 int WaitStatesNeededForUse = NeedWaitStates - WaitStatesSinceDef; 1960 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse); 1961 1962 if (WaitStatesNeeded == MaxWaitStates) 1963 break; 1964 } 1965 1966 auto IsSMFMAReadAsCFn = [&Reg, &IsMFMAFn, &MFMA, 1967 this](const MachineInstr &MI) { 1968 if (!IsMFMAFn(MI) || isDGEMM(MI.getOpcode()) || 1969 !MI.readsRegister(Reg, &TRI)) 1970 return false; 1971 1972 if (ST.hasGFX940Insts() && !isXDL(ST, MI)) 1973 return false; 1974 1975 const MachineOperand *SrcC = 1976 TII.getNamedOperand(MI, AMDGPU::OpName::src2); 1977 assert(SrcC); 1978 if (!SrcC->isReg() || !TRI.regsOverlap(SrcC->getReg(), Reg)) 1979 return false; 1980 1981 MFMA = &MI; 1982 return true; 1983 }; 1984 1985 MFMA = nullptr; 1986 int WaitStatesSinceUse = getWaitStatesSince(IsSMFMAReadAsCFn, 1987 MaxWarWaitStates); 1988 if (!MFMA) 1989 continue; 1990 1991 unsigned HazardDefLatency = TSchedModel.computeInstrLatency(MFMA); 1992 int NeedWaitStates = MaxWaitStates; 1993 switch (HazardDefLatency) { 1994 case 2: NeedWaitStates = SMFMA4x4ReadVgprVALUWarWaitStates; 1995 break; 1996 case 4: assert(ST.hasGFX940Insts()); 1997 NeedWaitStates = GFX940_XDL4PassReadVgprVALUWarWaitStates; 1998 break; 1999 case 8: NeedWaitStates = SMFMA16x16ReadVgprVALUWarWaitStates; 2000 break; 2001 case 16: LLVM_FALLTHROUGH; 2002 default: NeedWaitStates = SMFMA32x32ReadVgprVALUWarWaitStates; 2003 break; 2004 } 2005 2006 int WaitStatesNeededForUse = NeedWaitStates - WaitStatesSinceUse; 2007 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse); 2008 } 2009 2010 return WaitStatesNeeded; 2011 } 2012 2013 bool GCNHazardRecognizer::ShouldPreferAnother(SUnit *SU) { 2014 if (!SU->isInstr()) 2015 return false; 2016 2017 const MachineInstr *MAI = nullptr; 2018 auto IsMFMAFn = [&MAI](const MachineInstr &MI) { 2019 MAI = nullptr; 2020 if (SIInstrInfo::isMAI(MI) && 2021 MI.getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32_e64 && 2022 MI.getOpcode() != AMDGPU::V_ACCVGPR_READ_B32_e64) 2023 MAI = &MI; 2024 return MAI != nullptr; 2025 }; 2026 2027 MachineInstr *MI = SU->getInstr(); 2028 if (IsMFMAFn(*MI)) { 2029 int W = getWaitStatesSince(IsMFMAFn, 16); 2030 if (MAI) 2031 return W < (int)TSchedModel.computeInstrLatency(MAI); 2032 } 2033 2034 return false; 2035 } 2036