1 //===-- GCNHazardRecognizers.cpp - GCN Hazard Recognizer Impls ------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements hazard recognizers for scheduling on GCN processors. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "GCNHazardRecognizer.h" 14 #include "GCNSubtarget.h" 15 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 16 #include "SIMachineFunctionInfo.h" 17 #include "llvm/CodeGen/MachineFunction.h" 18 #include "llvm/CodeGen/ScheduleDAG.h" 19 #include "llvm/Support/TargetParser.h" 20 21 using namespace llvm; 22 23 namespace { 24 25 struct MFMAPaddingRatioParser : public cl::parser<unsigned> { 26 MFMAPaddingRatioParser(cl::Option &O) : cl::parser<unsigned>(O) {} 27 28 bool parse(cl::Option &O, StringRef ArgName, StringRef Arg, unsigned &Value) { 29 if (Arg.getAsInteger(0, Value)) 30 return O.error("'" + Arg + "' value invalid for uint argument!"); 31 32 if (Value > 100) 33 return O.error("'" + Arg + "' value must be in the range [0, 100]!"); 34 35 return false; 36 } 37 }; 38 39 } // end anonymous namespace 40 41 static cl::opt<unsigned, false, MFMAPaddingRatioParser> 42 MFMAPaddingRatio("amdgpu-mfma-padding-ratio", cl::init(0), cl::Hidden, 43 cl::desc("Fill a percentage of the latency between " 44 "neighboring MFMA with s_nops.")); 45 46 //===----------------------------------------------------------------------===// 47 // Hazard Recognizer Implementation 48 //===----------------------------------------------------------------------===// 49 50 static bool shouldRunLdsBranchVmemWARHazardFixup(const MachineFunction &MF, 51 const GCNSubtarget &ST); 52 53 GCNHazardRecognizer::GCNHazardRecognizer(const MachineFunction &MF) : 54 IsHazardRecognizerMode(false), 55 CurrCycleInstr(nullptr), 56 MF(MF), 57 ST(MF.getSubtarget<GCNSubtarget>()), 58 TII(*ST.getInstrInfo()), 59 TRI(TII.getRegisterInfo()), 60 ClauseUses(TRI.getNumRegUnits()), 61 ClauseDefs(TRI.getNumRegUnits()) { 62 MaxLookAhead = MF.getRegInfo().isPhysRegUsed(AMDGPU::AGPR0) ? 19 : 5; 63 TSchedModel.init(&ST); 64 RunLdsBranchVmemWARHazardFixup = shouldRunLdsBranchVmemWARHazardFixup(MF, ST); 65 } 66 67 void GCNHazardRecognizer::Reset() { 68 EmittedInstrs.clear(); 69 } 70 71 void GCNHazardRecognizer::EmitInstruction(SUnit *SU) { 72 EmitInstruction(SU->getInstr()); 73 } 74 75 void GCNHazardRecognizer::EmitInstruction(MachineInstr *MI) { 76 CurrCycleInstr = MI; 77 } 78 79 static bool isDivFMas(unsigned Opcode) { 80 return Opcode == AMDGPU::V_DIV_FMAS_F32_e64 || Opcode == AMDGPU::V_DIV_FMAS_F64_e64; 81 } 82 83 static bool isSGetReg(unsigned Opcode) { 84 return Opcode == AMDGPU::S_GETREG_B32; 85 } 86 87 static bool isSSetReg(unsigned Opcode) { 88 switch (Opcode) { 89 case AMDGPU::S_SETREG_B32: 90 case AMDGPU::S_SETREG_B32_mode: 91 case AMDGPU::S_SETREG_IMM32_B32: 92 case AMDGPU::S_SETREG_IMM32_B32_mode: 93 return true; 94 } 95 return false; 96 } 97 98 static bool isRWLane(unsigned Opcode) { 99 return Opcode == AMDGPU::V_READLANE_B32 || Opcode == AMDGPU::V_WRITELANE_B32; 100 } 101 102 static bool isRFE(unsigned Opcode) { 103 return Opcode == AMDGPU::S_RFE_B64; 104 } 105 106 static bool isSMovRel(unsigned Opcode) { 107 switch (Opcode) { 108 case AMDGPU::S_MOVRELS_B32: 109 case AMDGPU::S_MOVRELS_B64: 110 case AMDGPU::S_MOVRELD_B32: 111 case AMDGPU::S_MOVRELD_B64: 112 return true; 113 default: 114 return false; 115 } 116 } 117 118 static bool isDGEMM(unsigned Opcode) { 119 return AMDGPU::getMAIIsDGEMM(Opcode); 120 } 121 122 static bool isXDL(const GCNSubtarget &ST, const MachineInstr &MI) { 123 unsigned Opcode = MI.getOpcode(); 124 125 if (!SIInstrInfo::isMAI(MI) || 126 isDGEMM(Opcode) || 127 Opcode == AMDGPU::V_ACCVGPR_WRITE_B32_e64 || 128 Opcode == AMDGPU::V_ACCVGPR_READ_B32_e64) 129 return false; 130 131 if (!ST.hasGFX940Insts()) 132 return true; 133 134 return AMDGPU::getMAIIsGFX940XDL(Opcode); 135 } 136 137 static bool isSendMsgTraceDataOrGDS(const SIInstrInfo &TII, 138 const MachineInstr &MI) { 139 if (TII.isAlwaysGDS(MI.getOpcode())) 140 return true; 141 142 switch (MI.getOpcode()) { 143 case AMDGPU::S_SENDMSG: 144 case AMDGPU::S_SENDMSGHALT: 145 case AMDGPU::S_TTRACEDATA: 146 return true; 147 // These DS opcodes don't support GDS. 148 case AMDGPU::DS_NOP: 149 case AMDGPU::DS_PERMUTE_B32: 150 case AMDGPU::DS_BPERMUTE_B32: 151 return false; 152 default: 153 if (TII.isDS(MI.getOpcode())) { 154 int GDS = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 155 AMDGPU::OpName::gds); 156 if (MI.getOperand(GDS).getImm()) 157 return true; 158 } 159 return false; 160 } 161 } 162 163 static bool isPermlane(const MachineInstr &MI) { 164 unsigned Opcode = MI.getOpcode(); 165 return Opcode == AMDGPU::V_PERMLANE16_B32_e64 || 166 Opcode == AMDGPU::V_PERMLANEX16_B32_e64; 167 } 168 169 static unsigned getHWReg(const SIInstrInfo *TII, const MachineInstr &RegInstr) { 170 const MachineOperand *RegOp = TII->getNamedOperand(RegInstr, 171 AMDGPU::OpName::simm16); 172 return RegOp->getImm() & AMDGPU::Hwreg::ID_MASK_; 173 } 174 175 ScheduleHazardRecognizer::HazardType 176 GCNHazardRecognizer::getHazardType(SUnit *SU, int Stalls) { 177 MachineInstr *MI = SU->getInstr(); 178 // If we are not in "HazardRecognizerMode" and therefore not being run from 179 // the scheduler, track possible stalls from hazards but don't insert noops. 180 auto HazardType = IsHazardRecognizerMode ? NoopHazard : Hazard; 181 182 if (MI->isBundle()) 183 return NoHazard; 184 185 if (SIInstrInfo::isSMRD(*MI) && checkSMRDHazards(MI) > 0) 186 return HazardType; 187 188 if (ST.hasNSAtoVMEMBug() && checkNSAtoVMEMHazard(MI) > 0) 189 return HazardType; 190 191 if (checkFPAtomicToDenormModeHazard(MI) > 0) 192 return HazardType; 193 194 if (ST.hasNoDataDepHazard()) 195 return NoHazard; 196 197 // FIXME: Should flat be considered vmem? 198 if ((SIInstrInfo::isVMEM(*MI) || 199 SIInstrInfo::isFLAT(*MI)) 200 && checkVMEMHazards(MI) > 0) 201 return HazardType; 202 203 if (SIInstrInfo::isVALU(*MI) && checkVALUHazards(MI) > 0) 204 return HazardType; 205 206 if (SIInstrInfo::isDPP(*MI) && checkDPPHazards(MI) > 0) 207 return HazardType; 208 209 if (isDivFMas(MI->getOpcode()) && checkDivFMasHazards(MI) > 0) 210 return HazardType; 211 212 if (isRWLane(MI->getOpcode()) && checkRWLaneHazards(MI) > 0) 213 return HazardType; 214 215 if ((SIInstrInfo::isVALU(*MI) || SIInstrInfo::isVMEM(*MI) || 216 SIInstrInfo::isFLAT(*MI) || SIInstrInfo::isDS(*MI) || 217 SIInstrInfo::isEXP(*MI)) && checkMAIVALUHazards(MI) > 0) 218 return HazardType; 219 220 if (isSGetReg(MI->getOpcode()) && checkGetRegHazards(MI) > 0) 221 return HazardType; 222 223 if (isSSetReg(MI->getOpcode()) && checkSetRegHazards(MI) > 0) 224 return HazardType; 225 226 if (isRFE(MI->getOpcode()) && checkRFEHazards(MI) > 0) 227 return HazardType; 228 229 if (ST.hasReadM0MovRelInterpHazard() && 230 (TII.isVINTRP(*MI) || isSMovRel(MI->getOpcode())) && 231 checkReadM0Hazards(MI) > 0) 232 return HazardType; 233 234 if (ST.hasReadM0SendMsgHazard() && isSendMsgTraceDataOrGDS(TII, *MI) && 235 checkReadM0Hazards(MI) > 0) 236 return HazardType; 237 238 if (SIInstrInfo::isMAI(*MI) && checkMAIHazards(MI) > 0) 239 return HazardType; 240 241 if ((SIInstrInfo::isVMEM(*MI) || 242 SIInstrInfo::isFLAT(*MI) || 243 SIInstrInfo::isDS(*MI)) && checkMAILdStHazards(MI) > 0) 244 return HazardType; 245 246 if (MI->isInlineAsm() && checkInlineAsmHazards(MI) > 0) 247 return HazardType; 248 249 return NoHazard; 250 } 251 252 static void insertNoopsInBundle(MachineInstr *MI, const SIInstrInfo &TII, 253 unsigned Quantity) { 254 while (Quantity > 0) { 255 unsigned Arg = std::min(Quantity, 8u); 256 Quantity -= Arg; 257 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII.get(AMDGPU::S_NOP)) 258 .addImm(Arg - 1); 259 } 260 } 261 262 unsigned 263 GCNHazardRecognizer::getMFMAPipelineWaitStates(const MachineInstr &MI) const { 264 const MCSchedClassDesc *SC = TSchedModel.resolveSchedClass(&MI); 265 assert(TSchedModel.getWriteProcResBegin(SC) != 266 TSchedModel.getWriteProcResEnd(SC)); 267 return TSchedModel.getWriteProcResBegin(SC)->Cycles; 268 } 269 270 void GCNHazardRecognizer::processBundle() { 271 MachineBasicBlock::instr_iterator MI = std::next(CurrCycleInstr->getIterator()); 272 MachineBasicBlock::instr_iterator E = CurrCycleInstr->getParent()->instr_end(); 273 // Check bundled MachineInstr's for hazards. 274 for (; MI != E && MI->isInsideBundle(); ++MI) { 275 CurrCycleInstr = &*MI; 276 unsigned WaitStates = PreEmitNoopsCommon(CurrCycleInstr); 277 278 if (IsHazardRecognizerMode) { 279 fixHazards(CurrCycleInstr); 280 281 insertNoopsInBundle(CurrCycleInstr, TII, WaitStates); 282 } 283 284 // It’s unnecessary to track more than MaxLookAhead instructions. Since we 285 // include the bundled MI directly after, only add a maximum of 286 // (MaxLookAhead - 1) noops to EmittedInstrs. 287 for (unsigned i = 0, e = std::min(WaitStates, MaxLookAhead - 1); i < e; ++i) 288 EmittedInstrs.push_front(nullptr); 289 290 EmittedInstrs.push_front(CurrCycleInstr); 291 EmittedInstrs.resize(MaxLookAhead); 292 } 293 CurrCycleInstr = nullptr; 294 } 295 296 unsigned GCNHazardRecognizer::PreEmitNoops(MachineInstr *MI) { 297 IsHazardRecognizerMode = true; 298 CurrCycleInstr = MI; 299 unsigned W = PreEmitNoopsCommon(MI); 300 fixHazards(MI); 301 CurrCycleInstr = nullptr; 302 return W; 303 } 304 305 unsigned GCNHazardRecognizer::PreEmitNoopsCommon(MachineInstr *MI) { 306 if (MI->isBundle()) 307 return 0; 308 309 int WaitStates = 0; 310 311 if (SIInstrInfo::isSMRD(*MI)) 312 return std::max(WaitStates, checkSMRDHazards(MI)); 313 314 if (ST.hasNSAtoVMEMBug()) 315 WaitStates = std::max(WaitStates, checkNSAtoVMEMHazard(MI)); 316 317 WaitStates = std::max(WaitStates, checkFPAtomicToDenormModeHazard(MI)); 318 319 if (ST.hasNoDataDepHazard()) 320 return WaitStates; 321 322 if (SIInstrInfo::isVMEM(*MI) || SIInstrInfo::isFLAT(*MI)) 323 WaitStates = std::max(WaitStates, checkVMEMHazards(MI)); 324 325 if (SIInstrInfo::isVALU(*MI)) 326 WaitStates = std::max(WaitStates, checkVALUHazards(MI)); 327 328 if (SIInstrInfo::isDPP(*MI)) 329 WaitStates = std::max(WaitStates, checkDPPHazards(MI)); 330 331 if (isDivFMas(MI->getOpcode())) 332 WaitStates = std::max(WaitStates, checkDivFMasHazards(MI)); 333 334 if (isRWLane(MI->getOpcode())) 335 WaitStates = std::max(WaitStates, checkRWLaneHazards(MI)); 336 337 if ((SIInstrInfo::isVALU(*MI) || SIInstrInfo::isVMEM(*MI) || 338 SIInstrInfo::isFLAT(*MI) || SIInstrInfo::isDS(*MI) || 339 SIInstrInfo::isEXP(*MI)) && checkMAIVALUHazards(MI) > 0) 340 WaitStates = std::max(WaitStates, checkMAIVALUHazards(MI)); 341 342 if (MI->isInlineAsm()) 343 return std::max(WaitStates, checkInlineAsmHazards(MI)); 344 345 if (isSGetReg(MI->getOpcode())) 346 return std::max(WaitStates, checkGetRegHazards(MI)); 347 348 if (isSSetReg(MI->getOpcode())) 349 return std::max(WaitStates, checkSetRegHazards(MI)); 350 351 if (isRFE(MI->getOpcode())) 352 return std::max(WaitStates, checkRFEHazards(MI)); 353 354 if (ST.hasReadM0MovRelInterpHazard() && (TII.isVINTRP(*MI) || 355 isSMovRel(MI->getOpcode()))) 356 return std::max(WaitStates, checkReadM0Hazards(MI)); 357 358 if (ST.hasReadM0SendMsgHazard() && isSendMsgTraceDataOrGDS(TII, *MI)) 359 return std::max(WaitStates, checkReadM0Hazards(MI)); 360 361 if (SIInstrInfo::isMAI(*MI)) 362 return std::max(WaitStates, checkMAIHazards(MI)); 363 364 if (SIInstrInfo::isVMEM(*MI) || 365 SIInstrInfo::isFLAT(*MI) || 366 SIInstrInfo::isDS(*MI)) 367 return std::max(WaitStates, checkMAILdStHazards(MI)); 368 369 return WaitStates; 370 } 371 372 void GCNHazardRecognizer::EmitNoop() { 373 EmittedInstrs.push_front(nullptr); 374 } 375 376 void GCNHazardRecognizer::AdvanceCycle() { 377 // When the scheduler detects a stall, it will call AdvanceCycle() without 378 // emitting any instructions. 379 if (!CurrCycleInstr) { 380 EmittedInstrs.push_front(nullptr); 381 return; 382 } 383 384 if (CurrCycleInstr->isBundle()) { 385 processBundle(); 386 return; 387 } 388 389 unsigned NumWaitStates = TII.getNumWaitStates(*CurrCycleInstr); 390 if (!NumWaitStates) { 391 CurrCycleInstr = nullptr; 392 return; 393 } 394 395 // Keep track of emitted instructions 396 EmittedInstrs.push_front(CurrCycleInstr); 397 398 // Add a nullptr for each additional wait state after the first. Make sure 399 // not to add more than getMaxLookAhead() items to the list, since we 400 // truncate the list to that size right after this loop. 401 for (unsigned i = 1, e = std::min(NumWaitStates, getMaxLookAhead()); 402 i < e; ++i) { 403 EmittedInstrs.push_front(nullptr); 404 } 405 406 // getMaxLookahead() is the largest number of wait states we will ever need 407 // to insert, so there is no point in keeping track of more than that many 408 // wait states. 409 EmittedInstrs.resize(getMaxLookAhead()); 410 411 CurrCycleInstr = nullptr; 412 } 413 414 void GCNHazardRecognizer::RecedeCycle() { 415 llvm_unreachable("hazard recognizer does not support bottom-up scheduling."); 416 } 417 418 //===----------------------------------------------------------------------===// 419 // Helper Functions 420 //===----------------------------------------------------------------------===// 421 422 typedef function_ref<bool(const MachineInstr &, int WaitStates)> IsExpiredFn; 423 424 // Returns a minimum wait states since \p I walking all predecessors. 425 // Only scans until \p IsExpired does not return true. 426 // Can only be run in a hazard recognizer mode. 427 static int getWaitStatesSince(GCNHazardRecognizer::IsHazardFn IsHazard, 428 const MachineBasicBlock *MBB, 429 MachineBasicBlock::const_reverse_instr_iterator I, 430 int WaitStates, IsExpiredFn IsExpired, 431 DenseSet<const MachineBasicBlock *> &Visited) { 432 for (auto E = MBB->instr_rend(); I != E; ++I) { 433 // Don't add WaitStates for parent BUNDLE instructions. 434 if (I->isBundle()) 435 continue; 436 437 if (IsHazard(*I)) 438 return WaitStates; 439 440 if (I->isInlineAsm()) 441 continue; 442 443 WaitStates += SIInstrInfo::getNumWaitStates(*I); 444 445 if (IsExpired(*I, WaitStates)) 446 return std::numeric_limits<int>::max(); 447 } 448 449 int MinWaitStates = std::numeric_limits<int>::max(); 450 for (MachineBasicBlock *Pred : MBB->predecessors()) { 451 if (!Visited.insert(Pred).second) 452 continue; 453 454 int W = getWaitStatesSince(IsHazard, Pred, Pred->instr_rbegin(), 455 WaitStates, IsExpired, Visited); 456 457 MinWaitStates = std::min(MinWaitStates, W); 458 } 459 460 return MinWaitStates; 461 } 462 463 static int getWaitStatesSince(GCNHazardRecognizer::IsHazardFn IsHazard, 464 const MachineInstr *MI, IsExpiredFn IsExpired) { 465 DenseSet<const MachineBasicBlock *> Visited; 466 return getWaitStatesSince(IsHazard, MI->getParent(), 467 std::next(MI->getReverseIterator()), 468 0, IsExpired, Visited); 469 } 470 471 int GCNHazardRecognizer::getWaitStatesSince(IsHazardFn IsHazard, int Limit) { 472 if (IsHazardRecognizerMode) { 473 auto IsExpiredFn = [Limit](const MachineInstr &, int WaitStates) { 474 return WaitStates >= Limit; 475 }; 476 return ::getWaitStatesSince(IsHazard, CurrCycleInstr, IsExpiredFn); 477 } 478 479 int WaitStates = 0; 480 for (MachineInstr *MI : EmittedInstrs) { 481 if (MI) { 482 if (IsHazard(*MI)) 483 return WaitStates; 484 485 if (MI->isInlineAsm()) 486 continue; 487 } 488 ++WaitStates; 489 490 if (WaitStates >= Limit) 491 break; 492 } 493 return std::numeric_limits<int>::max(); 494 } 495 496 int GCNHazardRecognizer::getWaitStatesSinceDef(unsigned Reg, 497 IsHazardFn IsHazardDef, 498 int Limit) { 499 const SIRegisterInfo *TRI = ST.getRegisterInfo(); 500 501 auto IsHazardFn = [IsHazardDef, TRI, Reg](const MachineInstr &MI) { 502 return IsHazardDef(MI) && MI.modifiesRegister(Reg, TRI); 503 }; 504 505 return getWaitStatesSince(IsHazardFn, Limit); 506 } 507 508 int GCNHazardRecognizer::getWaitStatesSinceSetReg(IsHazardFn IsHazard, 509 int Limit) { 510 auto IsHazardFn = [IsHazard](const MachineInstr &MI) { 511 return isSSetReg(MI.getOpcode()) && IsHazard(MI); 512 }; 513 514 return getWaitStatesSince(IsHazardFn, Limit); 515 } 516 517 //===----------------------------------------------------------------------===// 518 // No-op Hazard Detection 519 //===----------------------------------------------------------------------===// 520 521 static void addRegUnits(const SIRegisterInfo &TRI, BitVector &BV, 522 MCRegister Reg) { 523 for (MCRegUnitIterator RUI(Reg, &TRI); RUI.isValid(); ++RUI) 524 BV.set(*RUI); 525 } 526 527 static void addRegsToSet(const SIRegisterInfo &TRI, 528 iterator_range<MachineInstr::const_mop_iterator> Ops, 529 BitVector &Set) { 530 for (const MachineOperand &Op : Ops) { 531 if (Op.isReg()) 532 addRegUnits(TRI, Set, Op.getReg().asMCReg()); 533 } 534 } 535 536 void GCNHazardRecognizer::addClauseInst(const MachineInstr &MI) { 537 // XXX: Do we need to worry about implicit operands 538 addRegsToSet(TRI, MI.defs(), ClauseDefs); 539 addRegsToSet(TRI, MI.uses(), ClauseUses); 540 } 541 542 static bool breaksSMEMSoftClause(MachineInstr *MI) { 543 return !SIInstrInfo::isSMRD(*MI); 544 } 545 546 static bool breaksVMEMSoftClause(MachineInstr *MI) { 547 return !SIInstrInfo::isVMEM(*MI) && !SIInstrInfo::isFLAT(*MI); 548 } 549 550 int GCNHazardRecognizer::checkSoftClauseHazards(MachineInstr *MEM) { 551 // SMEM soft clause are only present on VI+, and only matter if xnack is 552 // enabled. 553 if (!ST.isXNACKEnabled()) 554 return 0; 555 556 bool IsSMRD = TII.isSMRD(*MEM); 557 558 resetClause(); 559 560 // A soft-clause is any group of consecutive SMEM instructions. The 561 // instructions in this group may return out of order and/or may be 562 // replayed (i.e. the same instruction issued more than once). 563 // 564 // In order to handle these situations correctly we need to make sure that 565 // when a clause has more than one instruction, no instruction in the clause 566 // writes to a register that is read by another instruction in the clause 567 // (including itself). If we encounter this situation, we need to break the 568 // clause by inserting a non SMEM instruction. 569 570 for (MachineInstr *MI : EmittedInstrs) { 571 // When we hit a non-SMEM instruction then we have passed the start of the 572 // clause and we can stop. 573 if (!MI) 574 break; 575 576 if (IsSMRD ? breaksSMEMSoftClause(MI) : breaksVMEMSoftClause(MI)) 577 break; 578 579 addClauseInst(*MI); 580 } 581 582 if (ClauseDefs.none()) 583 return 0; 584 585 // We need to make sure not to put loads and stores in the same clause if they 586 // use the same address. For now, just start a new clause whenever we see a 587 // store. 588 if (MEM->mayStore()) 589 return 1; 590 591 addClauseInst(*MEM); 592 593 // If the set of defs and uses intersect then we cannot add this instruction 594 // to the clause, so we have a hazard. 595 return ClauseDefs.anyCommon(ClauseUses) ? 1 : 0; 596 } 597 598 int GCNHazardRecognizer::checkSMRDHazards(MachineInstr *SMRD) { 599 int WaitStatesNeeded = 0; 600 601 WaitStatesNeeded = checkSoftClauseHazards(SMRD); 602 603 // This SMRD hazard only affects SI. 604 if (!ST.hasSMRDReadVALUDefHazard()) 605 return WaitStatesNeeded; 606 607 // A read of an SGPR by SMRD instruction requires 4 wait states when the 608 // SGPR was written by a VALU instruction. 609 int SmrdSgprWaitStates = 4; 610 auto IsHazardDefFn = [this](const MachineInstr &MI) { 611 return TII.isVALU(MI); 612 }; 613 auto IsBufferHazardDefFn = [this](const MachineInstr &MI) { 614 return TII.isSALU(MI); 615 }; 616 617 bool IsBufferSMRD = TII.isBufferSMRD(*SMRD); 618 619 for (const MachineOperand &Use : SMRD->uses()) { 620 if (!Use.isReg()) 621 continue; 622 int WaitStatesNeededForUse = 623 SmrdSgprWaitStates - getWaitStatesSinceDef(Use.getReg(), IsHazardDefFn, 624 SmrdSgprWaitStates); 625 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse); 626 627 // This fixes what appears to be undocumented hardware behavior in SI where 628 // s_mov writing a descriptor and s_buffer_load_dword reading the descriptor 629 // needs some number of nops in between. We don't know how many we need, but 630 // let's use 4. This wasn't discovered before probably because the only 631 // case when this happens is when we expand a 64-bit pointer into a full 632 // descriptor and use s_buffer_load_dword instead of s_load_dword, which was 633 // probably never encountered in the closed-source land. 634 if (IsBufferSMRD) { 635 int WaitStatesNeededForUse = 636 SmrdSgprWaitStates - getWaitStatesSinceDef(Use.getReg(), 637 IsBufferHazardDefFn, 638 SmrdSgprWaitStates); 639 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse); 640 } 641 } 642 643 return WaitStatesNeeded; 644 } 645 646 int GCNHazardRecognizer::checkVMEMHazards(MachineInstr* VMEM) { 647 if (!ST.hasVMEMReadSGPRVALUDefHazard()) 648 return 0; 649 650 int WaitStatesNeeded = checkSoftClauseHazards(VMEM); 651 652 // A read of an SGPR by a VMEM instruction requires 5 wait states when the 653 // SGPR was written by a VALU Instruction. 654 const int VmemSgprWaitStates = 5; 655 auto IsHazardDefFn = [this](const MachineInstr &MI) { 656 return TII.isVALU(MI); 657 }; 658 for (const MachineOperand &Use : VMEM->uses()) { 659 if (!Use.isReg() || TRI.isVectorRegister(MF.getRegInfo(), Use.getReg())) 660 continue; 661 662 int WaitStatesNeededForUse = 663 VmemSgprWaitStates - getWaitStatesSinceDef(Use.getReg(), IsHazardDefFn, 664 VmemSgprWaitStates); 665 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse); 666 } 667 return WaitStatesNeeded; 668 } 669 670 int GCNHazardRecognizer::checkDPPHazards(MachineInstr *DPP) { 671 const SIRegisterInfo *TRI = ST.getRegisterInfo(); 672 const SIInstrInfo *TII = ST.getInstrInfo(); 673 674 // Check for DPP VGPR read after VALU VGPR write and EXEC write. 675 int DppVgprWaitStates = 2; 676 int DppExecWaitStates = 5; 677 int WaitStatesNeeded = 0; 678 auto IsHazardDefFn = [TII](const MachineInstr &MI) { 679 return TII->isVALU(MI); 680 }; 681 682 for (const MachineOperand &Use : DPP->uses()) { 683 if (!Use.isReg() || !TRI->isVGPR(MF.getRegInfo(), Use.getReg())) 684 continue; 685 int WaitStatesNeededForUse = 686 DppVgprWaitStates - getWaitStatesSinceDef( 687 Use.getReg(), 688 [](const MachineInstr &) { return true; }, 689 DppVgprWaitStates); 690 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse); 691 } 692 693 WaitStatesNeeded = std::max( 694 WaitStatesNeeded, 695 DppExecWaitStates - getWaitStatesSinceDef(AMDGPU::EXEC, IsHazardDefFn, 696 DppExecWaitStates)); 697 698 return WaitStatesNeeded; 699 } 700 701 int GCNHazardRecognizer::checkDivFMasHazards(MachineInstr *DivFMas) { 702 const SIInstrInfo *TII = ST.getInstrInfo(); 703 704 // v_div_fmas requires 4 wait states after a write to vcc from a VALU 705 // instruction. 706 const int DivFMasWaitStates = 4; 707 auto IsHazardDefFn = [TII](const MachineInstr &MI) { 708 return TII->isVALU(MI); 709 }; 710 int WaitStatesNeeded = getWaitStatesSinceDef(AMDGPU::VCC, IsHazardDefFn, 711 DivFMasWaitStates); 712 713 return DivFMasWaitStates - WaitStatesNeeded; 714 } 715 716 int GCNHazardRecognizer::checkGetRegHazards(MachineInstr *GetRegInstr) { 717 const SIInstrInfo *TII = ST.getInstrInfo(); 718 unsigned GetRegHWReg = getHWReg(TII, *GetRegInstr); 719 720 const int GetRegWaitStates = 2; 721 auto IsHazardFn = [TII, GetRegHWReg](const MachineInstr &MI) { 722 return GetRegHWReg == getHWReg(TII, MI); 723 }; 724 int WaitStatesNeeded = getWaitStatesSinceSetReg(IsHazardFn, GetRegWaitStates); 725 726 return GetRegWaitStates - WaitStatesNeeded; 727 } 728 729 int GCNHazardRecognizer::checkSetRegHazards(MachineInstr *SetRegInstr) { 730 const SIInstrInfo *TII = ST.getInstrInfo(); 731 unsigned HWReg = getHWReg(TII, *SetRegInstr); 732 733 const int SetRegWaitStates = ST.getSetRegWaitStates(); 734 auto IsHazardFn = [TII, HWReg](const MachineInstr &MI) { 735 return HWReg == getHWReg(TII, MI); 736 }; 737 int WaitStatesNeeded = getWaitStatesSinceSetReg(IsHazardFn, SetRegWaitStates); 738 return SetRegWaitStates - WaitStatesNeeded; 739 } 740 741 int GCNHazardRecognizer::createsVALUHazard(const MachineInstr &MI) { 742 if (!MI.mayStore()) 743 return -1; 744 745 const SIInstrInfo *TII = ST.getInstrInfo(); 746 unsigned Opcode = MI.getOpcode(); 747 const MCInstrDesc &Desc = MI.getDesc(); 748 749 int VDataIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdata); 750 int VDataRCID = -1; 751 if (VDataIdx != -1) 752 VDataRCID = Desc.OpInfo[VDataIdx].RegClass; 753 754 if (TII->isMUBUF(MI) || TII->isMTBUF(MI)) { 755 // There is no hazard if the instruction does not use vector regs 756 // (like wbinvl1) 757 if (VDataIdx == -1) 758 return -1; 759 // For MUBUF/MTBUF instructions this hazard only exists if the 760 // instruction is not using a register in the soffset field. 761 const MachineOperand *SOffset = 762 TII->getNamedOperand(MI, AMDGPU::OpName::soffset); 763 // If we have no soffset operand, then assume this field has been 764 // hardcoded to zero. 765 if (AMDGPU::getRegBitWidth(VDataRCID) > 64 && 766 (!SOffset || !SOffset->isReg())) 767 return VDataIdx; 768 } 769 770 // MIMG instructions create a hazard if they don't use a 256-bit T# and 771 // the store size is greater than 8 bytes and they have more than two bits 772 // of their dmask set. 773 // All our MIMG definitions use a 256-bit T#, so we can skip checking for them. 774 if (TII->isMIMG(MI)) { 775 int SRsrcIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::srsrc); 776 assert(SRsrcIdx != -1 && 777 AMDGPU::getRegBitWidth(Desc.OpInfo[SRsrcIdx].RegClass) == 256); 778 (void)SRsrcIdx; 779 } 780 781 if (TII->isFLAT(MI)) { 782 int DataIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdata); 783 if (AMDGPU::getRegBitWidth(Desc.OpInfo[DataIdx].RegClass) > 64) 784 return DataIdx; 785 } 786 787 return -1; 788 } 789 790 int 791 GCNHazardRecognizer::checkVALUHazardsHelper(const MachineOperand &Def, 792 const MachineRegisterInfo &MRI) { 793 // Helper to check for the hazard where VMEM instructions that store more than 794 // 8 bytes can have there store data over written by the next instruction. 795 const SIRegisterInfo *TRI = ST.getRegisterInfo(); 796 797 const int VALUWaitStates = 1; 798 int WaitStatesNeeded = 0; 799 800 if (!TRI->isVectorRegister(MRI, Def.getReg())) 801 return WaitStatesNeeded; 802 Register Reg = Def.getReg(); 803 auto IsHazardFn = [this, Reg, TRI](const MachineInstr &MI) { 804 int DataIdx = createsVALUHazard(MI); 805 return DataIdx >= 0 && 806 TRI->regsOverlap(MI.getOperand(DataIdx).getReg(), Reg); 807 }; 808 int WaitStatesNeededForDef = 809 VALUWaitStates - getWaitStatesSince(IsHazardFn, VALUWaitStates); 810 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForDef); 811 812 return WaitStatesNeeded; 813 } 814 815 int GCNHazardRecognizer::checkVALUHazards(MachineInstr *VALU) { 816 // This checks for the hazard where VMEM instructions that store more than 817 // 8 bytes can have there store data over written by the next instruction. 818 if (!ST.has12DWordStoreHazard()) 819 return 0; 820 821 const MachineRegisterInfo &MRI = MF.getRegInfo(); 822 int WaitStatesNeeded = 0; 823 824 for (const MachineOperand &Def : VALU->defs()) { 825 WaitStatesNeeded = std::max(WaitStatesNeeded, checkVALUHazardsHelper(Def, MRI)); 826 } 827 828 return WaitStatesNeeded; 829 } 830 831 int GCNHazardRecognizer::checkInlineAsmHazards(MachineInstr *IA) { 832 // This checks for hazards associated with inline asm statements. 833 // Since inline asms can contain just about anything, we use this 834 // to call/leverage other check*Hazard routines. Note that 835 // this function doesn't attempt to address all possible inline asm 836 // hazards (good luck), but is a collection of what has been 837 // problematic thus far. 838 839 // see checkVALUHazards() 840 if (!ST.has12DWordStoreHazard()) 841 return 0; 842 843 const MachineRegisterInfo &MRI = MF.getRegInfo(); 844 int WaitStatesNeeded = 0; 845 846 for (unsigned I = InlineAsm::MIOp_FirstOperand, E = IA->getNumOperands(); 847 I != E; ++I) { 848 const MachineOperand &Op = IA->getOperand(I); 849 if (Op.isReg() && Op.isDef()) { 850 WaitStatesNeeded = std::max(WaitStatesNeeded, checkVALUHazardsHelper(Op, MRI)); 851 } 852 } 853 854 return WaitStatesNeeded; 855 } 856 857 int GCNHazardRecognizer::checkRWLaneHazards(MachineInstr *RWLane) { 858 const SIInstrInfo *TII = ST.getInstrInfo(); 859 const SIRegisterInfo *TRI = ST.getRegisterInfo(); 860 const MachineRegisterInfo &MRI = MF.getRegInfo(); 861 862 const MachineOperand *LaneSelectOp = 863 TII->getNamedOperand(*RWLane, AMDGPU::OpName::src1); 864 865 if (!LaneSelectOp->isReg() || !TRI->isSGPRReg(MRI, LaneSelectOp->getReg())) 866 return 0; 867 868 Register LaneSelectReg = LaneSelectOp->getReg(); 869 auto IsHazardFn = [TII](const MachineInstr &MI) { return TII->isVALU(MI); }; 870 871 const int RWLaneWaitStates = 4; 872 int WaitStatesSince = getWaitStatesSinceDef(LaneSelectReg, IsHazardFn, 873 RWLaneWaitStates); 874 return RWLaneWaitStates - WaitStatesSince; 875 } 876 877 int GCNHazardRecognizer::checkRFEHazards(MachineInstr *RFE) { 878 if (!ST.hasRFEHazards()) 879 return 0; 880 881 const SIInstrInfo *TII = ST.getInstrInfo(); 882 883 const int RFEWaitStates = 1; 884 885 auto IsHazardFn = [TII](const MachineInstr &MI) { 886 return getHWReg(TII, MI) == AMDGPU::Hwreg::ID_TRAPSTS; 887 }; 888 int WaitStatesNeeded = getWaitStatesSinceSetReg(IsHazardFn, RFEWaitStates); 889 return RFEWaitStates - WaitStatesNeeded; 890 } 891 892 int GCNHazardRecognizer::checkReadM0Hazards(MachineInstr *MI) { 893 const SIInstrInfo *TII = ST.getInstrInfo(); 894 const int SMovRelWaitStates = 1; 895 auto IsHazardFn = [TII](const MachineInstr &MI) { return TII->isSALU(MI); }; 896 return SMovRelWaitStates - getWaitStatesSinceDef(AMDGPU::M0, IsHazardFn, 897 SMovRelWaitStates); 898 } 899 900 void GCNHazardRecognizer::fixHazards(MachineInstr *MI) { 901 fixVMEMtoScalarWriteHazards(MI); 902 fixVcmpxPermlaneHazards(MI); 903 fixSMEMtoVectorWriteHazards(MI); 904 fixVcmpxExecWARHazard(MI); 905 fixLdsBranchVmemWARHazard(MI); 906 } 907 908 bool GCNHazardRecognizer::fixVcmpxPermlaneHazards(MachineInstr *MI) { 909 if (!ST.hasVcmpxPermlaneHazard() || !isPermlane(*MI)) 910 return false; 911 912 const SIInstrInfo *TII = ST.getInstrInfo(); 913 auto IsHazardFn = [TII](const MachineInstr &MI) { return TII->isVOPC(MI); }; 914 915 auto IsExpiredFn = [](const MachineInstr &MI, int) { 916 unsigned Opc = MI.getOpcode(); 917 return SIInstrInfo::isVALU(MI) && Opc != AMDGPU::V_NOP_e32 && 918 Opc != AMDGPU::V_NOP_e64 && Opc != AMDGPU::V_NOP_sdwa; 919 }; 920 921 if (::getWaitStatesSince(IsHazardFn, MI, IsExpiredFn) == 922 std::numeric_limits<int>::max()) 923 return false; 924 925 // V_NOP will be discarded by SQ. 926 // Use V_MOV_B32 v?, v?. Register must be alive so use src0 of V_PERMLANE* 927 // which is always a VGPR and available. 928 auto *Src0 = TII->getNamedOperand(*MI, AMDGPU::OpName::src0); 929 Register Reg = Src0->getReg(); 930 bool IsUndef = Src0->isUndef(); 931 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), 932 TII->get(AMDGPU::V_MOV_B32_e32)) 933 .addReg(Reg, RegState::Define | (IsUndef ? RegState::Dead : 0)) 934 .addReg(Reg, IsUndef ? RegState::Undef : RegState::Kill); 935 936 return true; 937 } 938 939 bool GCNHazardRecognizer::fixVMEMtoScalarWriteHazards(MachineInstr *MI) { 940 if (!ST.hasVMEMtoScalarWriteHazard()) 941 return false; 942 943 if (!SIInstrInfo::isSALU(*MI) && !SIInstrInfo::isSMRD(*MI)) 944 return false; 945 946 if (MI->getNumDefs() == 0) 947 return false; 948 949 const SIRegisterInfo *TRI = ST.getRegisterInfo(); 950 951 auto IsHazardFn = [TRI, MI](const MachineInstr &I) { 952 if (!SIInstrInfo::isVMEM(I) && !SIInstrInfo::isDS(I) && 953 !SIInstrInfo::isFLAT(I)) 954 return false; 955 956 for (const MachineOperand &Def : MI->defs()) { 957 const MachineOperand *Op = 958 I.findRegisterUseOperand(Def.getReg(), false, TRI); 959 if (!Op) 960 continue; 961 return true; 962 } 963 return false; 964 }; 965 966 auto IsExpiredFn = [](const MachineInstr &MI, int) { 967 return SIInstrInfo::isVALU(MI) || 968 (MI.getOpcode() == AMDGPU::S_WAITCNT && 969 !MI.getOperand(0).getImm()) || 970 (MI.getOpcode() == AMDGPU::S_WAITCNT_DEPCTR && 971 MI.getOperand(0).getImm() == 0xffe3); 972 }; 973 974 if (::getWaitStatesSince(IsHazardFn, MI, IsExpiredFn) == 975 std::numeric_limits<int>::max()) 976 return false; 977 978 const SIInstrInfo *TII = ST.getInstrInfo(); 979 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), 980 TII->get(AMDGPU::S_WAITCNT_DEPCTR)) 981 .addImm(0xffe3); 982 return true; 983 } 984 985 bool GCNHazardRecognizer::fixSMEMtoVectorWriteHazards(MachineInstr *MI) { 986 if (!ST.hasSMEMtoVectorWriteHazard()) 987 return false; 988 989 if (!SIInstrInfo::isVALU(*MI)) 990 return false; 991 992 unsigned SDSTName; 993 switch (MI->getOpcode()) { 994 case AMDGPU::V_READLANE_B32: 995 case AMDGPU::V_READFIRSTLANE_B32: 996 SDSTName = AMDGPU::OpName::vdst; 997 break; 998 default: 999 SDSTName = AMDGPU::OpName::sdst; 1000 break; 1001 } 1002 1003 const SIInstrInfo *TII = ST.getInstrInfo(); 1004 const SIRegisterInfo *TRI = ST.getRegisterInfo(); 1005 const AMDGPU::IsaVersion IV = AMDGPU::getIsaVersion(ST.getCPU()); 1006 const MachineOperand *SDST = TII->getNamedOperand(*MI, SDSTName); 1007 if (!SDST) { 1008 for (const auto &MO : MI->implicit_operands()) { 1009 if (MO.isDef() && TRI->isSGPRClass(TRI->getPhysRegClass(MO.getReg()))) { 1010 SDST = &MO; 1011 break; 1012 } 1013 } 1014 } 1015 1016 if (!SDST) 1017 return false; 1018 1019 const Register SDSTReg = SDST->getReg(); 1020 auto IsHazardFn = [SDSTReg, TRI](const MachineInstr &I) { 1021 return SIInstrInfo::isSMRD(I) && I.readsRegister(SDSTReg, TRI); 1022 }; 1023 1024 auto IsExpiredFn = [TII, IV](const MachineInstr &MI, int) { 1025 if (TII->isSALU(MI)) { 1026 switch (MI.getOpcode()) { 1027 case AMDGPU::S_SETVSKIP: 1028 case AMDGPU::S_VERSION: 1029 case AMDGPU::S_WAITCNT_VSCNT: 1030 case AMDGPU::S_WAITCNT_VMCNT: 1031 case AMDGPU::S_WAITCNT_EXPCNT: 1032 // These instructions cannot not mitigate the hazard. 1033 return false; 1034 case AMDGPU::S_WAITCNT_LGKMCNT: 1035 // Reducing lgkmcnt count to 0 always mitigates the hazard. 1036 return (MI.getOperand(1).getImm() == 0) && 1037 (MI.getOperand(0).getReg() == AMDGPU::SGPR_NULL); 1038 case AMDGPU::S_WAITCNT: { 1039 const int64_t Imm = MI.getOperand(0).getImm(); 1040 AMDGPU::Waitcnt Decoded = AMDGPU::decodeWaitcnt(IV, Imm); 1041 return (Decoded.LgkmCnt == 0); 1042 } 1043 default: 1044 // SOPP instructions cannot mitigate the hazard. 1045 if (TII->isSOPP(MI)) 1046 return false; 1047 // At this point the SALU can be assumed to mitigate the hazard 1048 // because either: 1049 // (a) it is independent of the at risk SMEM (breaking chain), 1050 // or 1051 // (b) it is dependent on the SMEM, in which case an appropriate 1052 // s_waitcnt lgkmcnt _must_ exist between it and the at risk 1053 // SMEM instruction. 1054 return true; 1055 } 1056 } 1057 return false; 1058 }; 1059 1060 if (::getWaitStatesSince(IsHazardFn, MI, IsExpiredFn) == 1061 std::numeric_limits<int>::max()) 1062 return false; 1063 1064 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), 1065 TII->get(AMDGPU::S_MOV_B32), AMDGPU::SGPR_NULL) 1066 .addImm(0); 1067 return true; 1068 } 1069 1070 bool GCNHazardRecognizer::fixVcmpxExecWARHazard(MachineInstr *MI) { 1071 if (!ST.hasVcmpxExecWARHazard() || !SIInstrInfo::isVALU(*MI)) 1072 return false; 1073 1074 const SIRegisterInfo *TRI = ST.getRegisterInfo(); 1075 if (!MI->modifiesRegister(AMDGPU::EXEC, TRI)) 1076 return false; 1077 1078 auto IsHazardFn = [TRI](const MachineInstr &I) { 1079 if (SIInstrInfo::isVALU(I)) 1080 return false; 1081 return I.readsRegister(AMDGPU::EXEC, TRI); 1082 }; 1083 1084 const SIInstrInfo *TII = ST.getInstrInfo(); 1085 auto IsExpiredFn = [TII, TRI](const MachineInstr &MI, int) { 1086 if (SIInstrInfo::isVALU(MI)) { 1087 if (TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) 1088 return true; 1089 for (auto MO : MI.implicit_operands()) 1090 if (MO.isDef() && TRI->isSGPRClass(TRI->getPhysRegClass(MO.getReg()))) 1091 return true; 1092 } 1093 if (MI.getOpcode() == AMDGPU::S_WAITCNT_DEPCTR && 1094 (MI.getOperand(0).getImm() & 0xfffe) == 0xfffe) 1095 return true; 1096 return false; 1097 }; 1098 1099 if (::getWaitStatesSince(IsHazardFn, MI, IsExpiredFn) == 1100 std::numeric_limits<int>::max()) 1101 return false; 1102 1103 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), 1104 TII->get(AMDGPU::S_WAITCNT_DEPCTR)) 1105 .addImm(0xfffe); 1106 return true; 1107 } 1108 1109 static bool shouldRunLdsBranchVmemWARHazardFixup(const MachineFunction &MF, 1110 const GCNSubtarget &ST) { 1111 if (!ST.hasLdsBranchVmemWARHazard()) 1112 return false; 1113 1114 // Check if the necessary condition for the hazard is met: both LDS and VMEM 1115 // instructions need to appear in the same function. 1116 bool HasLds = false; 1117 bool HasVmem = false; 1118 for (auto &MBB : MF) { 1119 for (auto &MI : MBB) { 1120 HasLds |= SIInstrInfo::isDS(MI); 1121 HasVmem |= 1122 SIInstrInfo::isVMEM(MI) || SIInstrInfo::isSegmentSpecificFLAT(MI); 1123 if (HasLds && HasVmem) 1124 return true; 1125 } 1126 } 1127 return false; 1128 } 1129 1130 bool GCNHazardRecognizer::fixLdsBranchVmemWARHazard(MachineInstr *MI) { 1131 if (!RunLdsBranchVmemWARHazardFixup) 1132 return false; 1133 1134 assert(ST.hasLdsBranchVmemWARHazard()); 1135 1136 auto IsHazardInst = [](const MachineInstr &MI) { 1137 if (SIInstrInfo::isDS(MI)) 1138 return 1; 1139 if (SIInstrInfo::isVMEM(MI) || SIInstrInfo::isSegmentSpecificFLAT(MI)) 1140 return 2; 1141 return 0; 1142 }; 1143 1144 auto InstType = IsHazardInst(*MI); 1145 if (!InstType) 1146 return false; 1147 1148 auto IsExpiredFn = [&IsHazardInst](const MachineInstr &I, int) { 1149 return IsHazardInst(I) || (I.getOpcode() == AMDGPU::S_WAITCNT_VSCNT && 1150 I.getOperand(0).getReg() == AMDGPU::SGPR_NULL && 1151 !I.getOperand(1).getImm()); 1152 }; 1153 1154 auto IsHazardFn = [InstType, &IsHazardInst](const MachineInstr &I) { 1155 if (!I.isBranch()) 1156 return false; 1157 1158 auto IsHazardFn = [InstType, IsHazardInst](const MachineInstr &I) { 1159 auto InstType2 = IsHazardInst(I); 1160 return InstType2 && InstType != InstType2; 1161 }; 1162 1163 auto IsExpiredFn = [InstType, &IsHazardInst](const MachineInstr &I, int) { 1164 auto InstType2 = IsHazardInst(I); 1165 if (InstType == InstType2) 1166 return true; 1167 1168 return I.getOpcode() == AMDGPU::S_WAITCNT_VSCNT && 1169 I.getOperand(0).getReg() == AMDGPU::SGPR_NULL && 1170 !I.getOperand(1).getImm(); 1171 }; 1172 1173 return ::getWaitStatesSince(IsHazardFn, &I, IsExpiredFn) != 1174 std::numeric_limits<int>::max(); 1175 }; 1176 1177 if (::getWaitStatesSince(IsHazardFn, MI, IsExpiredFn) == 1178 std::numeric_limits<int>::max()) 1179 return false; 1180 1181 const SIInstrInfo *TII = ST.getInstrInfo(); 1182 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), 1183 TII->get(AMDGPU::S_WAITCNT_VSCNT)) 1184 .addReg(AMDGPU::SGPR_NULL, RegState::Undef) 1185 .addImm(0); 1186 1187 return true; 1188 } 1189 1190 int GCNHazardRecognizer::checkNSAtoVMEMHazard(MachineInstr *MI) { 1191 int NSAtoVMEMWaitStates = 1; 1192 1193 if (!ST.hasNSAtoVMEMBug()) 1194 return 0; 1195 1196 if (!SIInstrInfo::isMUBUF(*MI) && !SIInstrInfo::isMTBUF(*MI)) 1197 return 0; 1198 1199 const SIInstrInfo *TII = ST.getInstrInfo(); 1200 const auto *Offset = TII->getNamedOperand(*MI, AMDGPU::OpName::offset); 1201 if (!Offset || (Offset->getImm() & 6) == 0) 1202 return 0; 1203 1204 auto IsHazardFn = [TII](const MachineInstr &I) { 1205 if (!SIInstrInfo::isMIMG(I)) 1206 return false; 1207 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(I.getOpcode()); 1208 return Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA && 1209 TII->getInstSizeInBytes(I) >= 16; 1210 }; 1211 1212 return NSAtoVMEMWaitStates - getWaitStatesSince(IsHazardFn, 1); 1213 } 1214 1215 int GCNHazardRecognizer::checkFPAtomicToDenormModeHazard(MachineInstr *MI) { 1216 int FPAtomicToDenormModeWaitStates = 3; 1217 1218 if (MI->getOpcode() != AMDGPU::S_DENORM_MODE) 1219 return 0; 1220 1221 auto IsHazardFn = [](const MachineInstr &I) { 1222 if (!SIInstrInfo::isVMEM(I) && !SIInstrInfo::isFLAT(I)) 1223 return false; 1224 return SIInstrInfo::isFPAtomic(I); 1225 }; 1226 1227 auto IsExpiredFn = [](const MachineInstr &MI, int WaitStates) { 1228 if (WaitStates >= 3 || SIInstrInfo::isVALU(MI)) 1229 return true; 1230 1231 switch (MI.getOpcode()) { 1232 case AMDGPU::S_WAITCNT: 1233 case AMDGPU::S_WAITCNT_VSCNT: 1234 case AMDGPU::S_WAITCNT_VMCNT: 1235 case AMDGPU::S_WAITCNT_EXPCNT: 1236 case AMDGPU::S_WAITCNT_LGKMCNT: 1237 case AMDGPU::S_WAIT_IDLE: 1238 return true; 1239 default: 1240 break; 1241 } 1242 1243 return false; 1244 }; 1245 1246 return FPAtomicToDenormModeWaitStates - 1247 ::getWaitStatesSince(IsHazardFn, MI, IsExpiredFn); 1248 } 1249 1250 int GCNHazardRecognizer::checkMAIHazards(MachineInstr *MI) { 1251 assert(SIInstrInfo::isMAI(*MI)); 1252 1253 return ST.hasGFX90AInsts() ? checkMAIHazards90A(MI) : checkMAIHazards908(MI); 1254 } 1255 1256 int GCNHazardRecognizer::checkMFMAPadding(MachineInstr *MI) { 1257 // Early exit if no padding is requested. 1258 if (MFMAPaddingRatio == 0) 1259 return 0; 1260 1261 auto IsMFMAFn = [](const MachineInstr &MI) { 1262 return SIInstrInfo::isMAI(MI) && 1263 MI.getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32_e64 && 1264 MI.getOpcode() != AMDGPU::V_ACCVGPR_READ_B32_e64; 1265 }; 1266 1267 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); 1268 if (!IsMFMAFn(*MI) || MFI->getOccupancy() < 2) 1269 return 0; 1270 1271 int NeighborMFMALatency = 0; 1272 auto IsNeighboringMFMA = [&IsMFMAFn, &NeighborMFMALatency, 1273 this](const MachineInstr &MI) { 1274 if (!IsMFMAFn(MI)) 1275 return false; 1276 1277 NeighborMFMALatency = this->getMFMAPipelineWaitStates(MI); 1278 return true; 1279 }; 1280 1281 const int MaxMFMAPipelineWaitStates = 16; 1282 int WaitStatesSinceNeighborMFMA = 1283 getWaitStatesSince(IsNeighboringMFMA, MaxMFMAPipelineWaitStates); 1284 1285 int NeighborMFMAPaddingNeeded = 1286 (NeighborMFMALatency * MFMAPaddingRatio / 100) - 1287 WaitStatesSinceNeighborMFMA; 1288 1289 return std::max(0, NeighborMFMAPaddingNeeded); 1290 } 1291 1292 int GCNHazardRecognizer::checkMAIHazards908(MachineInstr *MI) { 1293 int WaitStatesNeeded = 0; 1294 unsigned Opc = MI->getOpcode(); 1295 1296 auto IsVALUFn = [](const MachineInstr &MI) { 1297 return SIInstrInfo::isVALU(MI); 1298 }; 1299 1300 if (Opc != AMDGPU::V_ACCVGPR_READ_B32_e64) { // MFMA or v_accvgpr_write 1301 const int LegacyVALUWritesVGPRWaitStates = 2; 1302 const int VALUWritesExecWaitStates = 4; 1303 const int MaxWaitStates = 4; 1304 1305 int WaitStatesNeededForUse = VALUWritesExecWaitStates - 1306 getWaitStatesSinceDef(AMDGPU::EXEC, IsVALUFn, MaxWaitStates); 1307 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse); 1308 1309 if (WaitStatesNeeded < MaxWaitStates) { 1310 for (const MachineOperand &Use : MI->explicit_uses()) { 1311 const int MaxWaitStates = 2; 1312 1313 if (!Use.isReg() || !TRI.isVGPR(MF.getRegInfo(), Use.getReg())) 1314 continue; 1315 1316 int WaitStatesNeededForUse = LegacyVALUWritesVGPRWaitStates - 1317 getWaitStatesSinceDef(Use.getReg(), IsVALUFn, MaxWaitStates); 1318 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse); 1319 1320 if (WaitStatesNeeded == MaxWaitStates) 1321 break; 1322 } 1323 } 1324 } 1325 1326 auto IsMFMAFn = [](const MachineInstr &MI) { 1327 return SIInstrInfo::isMAI(MI) && 1328 MI.getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32_e64 && 1329 MI.getOpcode() != AMDGPU::V_ACCVGPR_READ_B32_e64; 1330 }; 1331 1332 for (const MachineOperand &Op : MI->explicit_operands()) { 1333 if (!Op.isReg() || !TRI.isAGPR(MF.getRegInfo(), Op.getReg())) 1334 continue; 1335 1336 if (Op.isDef() && Opc != AMDGPU::V_ACCVGPR_WRITE_B32_e64) 1337 continue; 1338 1339 const int MFMAWritesAGPROverlappedSrcABWaitStates = 4; 1340 const int MFMAWritesAGPROverlappedSrcCWaitStates = 2; 1341 const int MFMA4x4WritesAGPRAccVgprReadWaitStates = 4; 1342 const int MFMA16x16WritesAGPRAccVgprReadWaitStates = 10; 1343 const int MFMA32x32WritesAGPRAccVgprReadWaitStates = 18; 1344 const int MFMA4x4WritesAGPRAccVgprWriteWaitStates = 1; 1345 const int MFMA16x16WritesAGPRAccVgprWriteWaitStates = 7; 1346 const int MFMA32x32WritesAGPRAccVgprWriteWaitStates = 15; 1347 const int MaxWaitStates = 18; 1348 Register Reg = Op.getReg(); 1349 unsigned HazardDefLatency = 0; 1350 1351 auto IsOverlappedMFMAFn = [Reg, &IsMFMAFn, &HazardDefLatency, 1352 this](const MachineInstr &MI) { 1353 if (!IsMFMAFn(MI)) 1354 return false; 1355 Register DstReg = MI.getOperand(0).getReg(); 1356 if (DstReg == Reg) 1357 return false; 1358 HazardDefLatency = 1359 std::max(HazardDefLatency, TSchedModel.computeInstrLatency(&MI)); 1360 return TRI.regsOverlap(DstReg, Reg); 1361 }; 1362 1363 int WaitStatesSinceDef = getWaitStatesSinceDef(Reg, IsOverlappedMFMAFn, 1364 MaxWaitStates); 1365 int NeedWaitStates = MFMAWritesAGPROverlappedSrcABWaitStates; 1366 int SrcCIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2); 1367 int OpNo = MI->getOperandNo(&Op); 1368 if (OpNo == SrcCIdx) { 1369 NeedWaitStates = MFMAWritesAGPROverlappedSrcCWaitStates; 1370 } else if (Opc == AMDGPU::V_ACCVGPR_READ_B32_e64) { 1371 switch (HazardDefLatency) { 1372 case 2: NeedWaitStates = MFMA4x4WritesAGPRAccVgprReadWaitStates; 1373 break; 1374 case 8: NeedWaitStates = MFMA16x16WritesAGPRAccVgprReadWaitStates; 1375 break; 1376 case 16: LLVM_FALLTHROUGH; 1377 default: NeedWaitStates = MFMA32x32WritesAGPRAccVgprReadWaitStates; 1378 break; 1379 } 1380 } else if (Opc == AMDGPU::V_ACCVGPR_WRITE_B32_e64) { 1381 switch (HazardDefLatency) { 1382 case 2: NeedWaitStates = MFMA4x4WritesAGPRAccVgprWriteWaitStates; 1383 break; 1384 case 8: NeedWaitStates = MFMA16x16WritesAGPRAccVgprWriteWaitStates; 1385 break; 1386 case 16: LLVM_FALLTHROUGH; 1387 default: NeedWaitStates = MFMA32x32WritesAGPRAccVgprWriteWaitStates; 1388 break; 1389 } 1390 } 1391 1392 int WaitStatesNeededForUse = NeedWaitStates - WaitStatesSinceDef; 1393 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse); 1394 1395 if (WaitStatesNeeded == MaxWaitStates) 1396 return WaitStatesNeeded; // Early exit. 1397 1398 auto IsAccVgprWriteFn = [Reg, this](const MachineInstr &MI) { 1399 if (MI.getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32_e64) 1400 return false; 1401 Register DstReg = MI.getOperand(0).getReg(); 1402 return TRI.regsOverlap(Reg, DstReg); 1403 }; 1404 1405 const int AccVGPRWriteMFMAReadSrcCWaitStates = 1; 1406 const int AccVGPRWriteMFMAReadSrcABWaitStates = 3; 1407 const int AccVGPRWriteAccVgprReadWaitStates = 3; 1408 NeedWaitStates = AccVGPRWriteMFMAReadSrcABWaitStates; 1409 if (OpNo == SrcCIdx) 1410 NeedWaitStates = AccVGPRWriteMFMAReadSrcCWaitStates; 1411 else if (Opc == AMDGPU::V_ACCVGPR_READ_B32_e64) 1412 NeedWaitStates = AccVGPRWriteAccVgprReadWaitStates; 1413 1414 WaitStatesNeededForUse = NeedWaitStates - 1415 getWaitStatesSinceDef(Reg, IsAccVgprWriteFn, MaxWaitStates); 1416 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse); 1417 1418 if (WaitStatesNeeded == MaxWaitStates) 1419 return WaitStatesNeeded; // Early exit. 1420 } 1421 1422 if (Opc == AMDGPU::V_ACCVGPR_WRITE_B32_e64) { 1423 const int MFMA4x4ReadSrcCAccVgprWriteWaitStates = 0; 1424 const int MFMA16x16ReadSrcCAccVgprWriteWaitStates = 5; 1425 const int MFMA32x32ReadSrcCAccVgprWriteWaitStates = 13; 1426 const int MaxWaitStates = 13; 1427 Register DstReg = MI->getOperand(0).getReg(); 1428 unsigned HazardDefLatency = 0; 1429 1430 auto IsSrcCMFMAFn = [DstReg, &IsMFMAFn, &HazardDefLatency, 1431 this](const MachineInstr &MI) { 1432 if (!IsMFMAFn(MI)) 1433 return false; 1434 Register Reg = TII.getNamedOperand(MI, AMDGPU::OpName::src2)->getReg(); 1435 HazardDefLatency = 1436 std::max(HazardDefLatency, TSchedModel.computeInstrLatency(&MI)); 1437 return TRI.regsOverlap(Reg, DstReg); 1438 }; 1439 1440 int WaitStatesSince = getWaitStatesSince(IsSrcCMFMAFn, MaxWaitStates); 1441 int NeedWaitStates; 1442 switch (HazardDefLatency) { 1443 case 2: NeedWaitStates = MFMA4x4ReadSrcCAccVgprWriteWaitStates; 1444 break; 1445 case 8: NeedWaitStates = MFMA16x16ReadSrcCAccVgprWriteWaitStates; 1446 break; 1447 case 16: LLVM_FALLTHROUGH; 1448 default: NeedWaitStates = MFMA32x32ReadSrcCAccVgprWriteWaitStates; 1449 break; 1450 } 1451 1452 int WaitStatesNeededForUse = NeedWaitStates - WaitStatesSince; 1453 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse); 1454 } 1455 1456 // Pad neighboring MFMA with noops for better inter-wave performance. 1457 WaitStatesNeeded = std::max(WaitStatesNeeded, checkMFMAPadding(MI)); 1458 1459 return WaitStatesNeeded; 1460 } 1461 1462 int GCNHazardRecognizer::checkMAIHazards90A(MachineInstr *MI) { 1463 int WaitStatesNeeded = 0; 1464 unsigned Opc = MI->getOpcode(); 1465 1466 auto IsMFMAFn = [](const MachineInstr &MI) { 1467 return SIInstrInfo::isMAI(MI) && 1468 MI.getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32_e64 && 1469 MI.getOpcode() != AMDGPU::V_ACCVGPR_READ_B32_e64; 1470 }; 1471 1472 auto IsLegacyVALUFn = [&IsMFMAFn](const MachineInstr &MI) { 1473 return SIInstrInfo::isVALU(MI) && !IsMFMAFn(MI); 1474 }; 1475 1476 auto IsLegacyVALUNotDotFn = [&IsMFMAFn](const MachineInstr &MI) { 1477 return SIInstrInfo::isVALU(MI) && !IsMFMAFn(MI) && !SIInstrInfo::isDOT(MI); 1478 }; 1479 1480 if (!IsMFMAFn(*MI)) 1481 return WaitStatesNeeded; 1482 1483 const int VALUWritesExecWaitStates = 4; 1484 int WaitStatesNeededForUse = VALUWritesExecWaitStates - 1485 getWaitStatesSinceDef(AMDGPU::EXEC, IsLegacyVALUFn, 1486 VALUWritesExecWaitStates); 1487 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse); 1488 1489 int SrcCIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2); 1490 1491 // Loop for both DGEMM and S/HGEMM 2nd instruction. 1492 for (const MachineOperand &Use : MI->explicit_uses()) { 1493 const int LegacyVALUNotDotWritesVGPRWaitStates = 2; 1494 const int SMFMA4x4WritesVGPROverlappedSMFMASrcCWaitStates = 2; 1495 const int GFX940_XDL2PassWritesVGPROverlappedSMFMASrcCWaitStates = 3; 1496 const int GFX940_XDL4PassWritesVGPROverlappedSMFMASrcCWaitStates = 5; 1497 const int GFX940_SMFMA4PassWritesVGPROverlappedSMFMASrcCWaitStates = 4; 1498 const int GFX940_XDL8PassWritesVGPROverlappedSMFMASrcCWaitStates = 9; 1499 const int GFX940_SMFMA8PassWritesVGPROverlappedSMFMASrcCWaitStates = 8; 1500 const int GFX940_XDL16PassWritesVGPROverlappedSMFMASrcCWaitStates = 17; 1501 const int GFX940_SMFMA16PassWritesVGPROverlappedSMFMASrcCWaitStates = 16; 1502 const int SMFMA16x16WritesVGPROverlappedSMFMASrcCWaitStates = 8; 1503 const int SMFMA32x32WritesVGPROverlappedSMFMASrcCWaitStates = 16; 1504 const int SMFMA4x4WritesVGPROverlappedDMFMASrcCWaitStates = 3; 1505 const int SMFMA16x16WritesVGPROverlappedDMFMASrcCWaitStates = 9; 1506 const int SMFMA32x32WritesVGPROverlappedDMFMASrcCWaitStates = 17; 1507 const int DMFMA16x16WritesVGPROverlappedSrcCWaitStates = 9; 1508 const int DMFMA4x4WritesVGPROverlappedSrcCWaitStates = 4; 1509 const int SMFMA4x4WritesVGPROverlappedSrcABWaitStates = 5; 1510 const int SMFMA16x16WritesVGPROverlappedSrcABWaitStates = 11; 1511 const int SMFMA32x32WritesVGPROverlappedSrcABWaitStates = 19; 1512 const int GFX940_SMFMA2PassWritesVGPROverlappedSrcABWaitStates = 4; 1513 const int GFX940_SMFMA4PassWritesVGPROverlappedSrcABWaitStates = 6; 1514 const int GFX940_SMFMA8PassWritesVGPROverlappedSrcABWaitStates = 10; 1515 const int GFX940_SMFMA16PassWritesVGPROverlappedSrcABWaitStates = 18; 1516 const int GFX940_XDL2PassWritesVGPROverlappedSrcABWaitStates = 5; 1517 const int GFX940_XDL4PassWritesVGPROverlappedSrcABWaitStates = 7; 1518 const int GFX940_XDL8PassWritesVGPROverlappedSrcABWaitStates = 11; 1519 const int GFX940_XDL16PassWritesVGPROverlappedSrcABWaitStates = 19; 1520 const int DMFMA4x4WritesVGPROverlappedMFMASrcABWaitStates = 6; 1521 const int DMFMA16x16WritesVGPROverlappedMFMASrcABWaitStates = 11; 1522 const int DMFMA4x4WritesVGPRFullSrcCWaitStates = 4; 1523 const int GFX940_SMFMA4x4WritesVGPRFullSrcCWaitStates = 2; 1524 const int MaxWaitStates = 19; 1525 1526 if (!Use.isReg()) 1527 continue; 1528 Register Reg = Use.getReg(); 1529 bool FullReg; 1530 const MachineInstr *MI1; 1531 1532 auto IsOverlappedMFMAFn = [Reg, &IsMFMAFn, &FullReg, &MI1, 1533 this](const MachineInstr &MI) { 1534 if (!IsMFMAFn(MI)) 1535 return false; 1536 Register DstReg = MI.getOperand(0).getReg(); 1537 FullReg = (DstReg == Reg); 1538 MI1 = &MI; 1539 return TRI.regsOverlap(DstReg, Reg); 1540 }; 1541 1542 WaitStatesNeededForUse = LegacyVALUNotDotWritesVGPRWaitStates - 1543 getWaitStatesSinceDef(Reg, IsLegacyVALUNotDotFn, MaxWaitStates); 1544 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse); 1545 1546 int NumWaitStates = 1547 getWaitStatesSinceDef(Reg, IsOverlappedMFMAFn, MaxWaitStates); 1548 if (NumWaitStates == std::numeric_limits<int>::max()) 1549 continue; 1550 1551 int OpNo = MI->getOperandNo(&Use); 1552 unsigned Opc1 = MI1->getOpcode(); 1553 int NeedWaitStates = 0; 1554 if (OpNo == SrcCIdx) { 1555 if (!isDGEMM(Opc) && (!ST.hasGFX940Insts() && isDGEMM(Opc1))) { 1556 NeedWaitStates = 0; 1557 } else if (FullReg) { 1558 if ((Opc == AMDGPU::V_MFMA_F64_4X4X4F64_e64 || 1559 Opc == AMDGPU::V_MFMA_F64_4X4X4F64_vgprcd_e64) && 1560 (Opc1 == AMDGPU::V_MFMA_F64_4X4X4F64_e64 || 1561 Opc1 == AMDGPU::V_MFMA_F64_4X4X4F64_vgprcd_e64)) 1562 NeedWaitStates = DMFMA4x4WritesVGPRFullSrcCWaitStates; 1563 else if (ST.hasGFX940Insts() && 1564 TSchedModel.computeInstrLatency(MI1) == 2) 1565 NeedWaitStates = GFX940_SMFMA4x4WritesVGPRFullSrcCWaitStates; 1566 } else { 1567 switch (Opc1) { 1568 case AMDGPU::V_MFMA_F64_16X16X4F64_e64: 1569 case AMDGPU::V_MFMA_F64_16X16X4F64_vgprcd_e64: 1570 case AMDGPU::V_MFMA_F64_16X16X4F64_mac_e64: 1571 case AMDGPU::V_MFMA_F64_16X16X4F64_mac_vgprcd_e64: 1572 if (!isXDL(ST, *MI)) 1573 NeedWaitStates = DMFMA16x16WritesVGPROverlappedSrcCWaitStates; 1574 break; 1575 case AMDGPU::V_MFMA_F64_4X4X4F64_e64: 1576 case AMDGPU::V_MFMA_F64_4X4X4F64_vgprcd_e64: 1577 if (!isXDL(ST, *MI)) 1578 NeedWaitStates = DMFMA4x4WritesVGPROverlappedSrcCWaitStates; 1579 break; 1580 default: 1581 if (ST.hasGFX940Insts() && isXDL(ST, *MI) && !isXDL(ST, *MI1)) 1582 break; 1583 switch (TSchedModel.computeInstrLatency(MI1)) { 1584 case 2: 1585 NeedWaitStates = ST.hasGFX940Insts() 1586 ? isXDL(ST, *MI1) 1587 ? GFX940_XDL2PassWritesVGPROverlappedSMFMASrcCWaitStates 1588 : SMFMA4x4WritesVGPROverlappedSMFMASrcCWaitStates 1589 : isDGEMM(Opc) 1590 ? SMFMA4x4WritesVGPROverlappedDMFMASrcCWaitStates 1591 : SMFMA4x4WritesVGPROverlappedSMFMASrcCWaitStates; 1592 break; 1593 case 4: 1594 assert(ST.hasGFX940Insts()); 1595 NeedWaitStates = isXDL(ST, *MI1) 1596 ? GFX940_XDL4PassWritesVGPROverlappedSMFMASrcCWaitStates 1597 : GFX940_SMFMA4PassWritesVGPROverlappedSMFMASrcCWaitStates; 1598 break; 1599 case 8: 1600 NeedWaitStates = ST.hasGFX940Insts() 1601 ? isXDL(ST, *MI1) 1602 ? GFX940_XDL8PassWritesVGPROverlappedSMFMASrcCWaitStates 1603 : GFX940_SMFMA8PassWritesVGPROverlappedSMFMASrcCWaitStates 1604 : isDGEMM(Opc) 1605 ? SMFMA16x16WritesVGPROverlappedDMFMASrcCWaitStates 1606 : SMFMA16x16WritesVGPROverlappedSMFMASrcCWaitStates; 1607 break; 1608 case 16: LLVM_FALLTHROUGH; 1609 default: 1610 NeedWaitStates = ST.hasGFX940Insts() 1611 ? isXDL(ST, *MI1) 1612 ? GFX940_XDL16PassWritesVGPROverlappedSMFMASrcCWaitStates 1613 : GFX940_SMFMA16PassWritesVGPROverlappedSMFMASrcCWaitStates 1614 : isDGEMM(Opc) 1615 ? SMFMA32x32WritesVGPROverlappedDMFMASrcCWaitStates 1616 : SMFMA32x32WritesVGPROverlappedSMFMASrcCWaitStates; 1617 } 1618 } 1619 } 1620 } else { 1621 switch (Opc1) { 1622 case AMDGPU::V_MFMA_F64_16X16X4F64_e64: 1623 case AMDGPU::V_MFMA_F64_16X16X4F64_vgprcd_e64: 1624 case AMDGPU::V_MFMA_F64_16X16X4F64_mac_e64: 1625 case AMDGPU::V_MFMA_F64_16X16X4F64_mac_vgprcd_e64: 1626 NeedWaitStates = DMFMA16x16WritesVGPROverlappedMFMASrcABWaitStates; 1627 break; 1628 case AMDGPU::V_MFMA_F64_4X4X4F64_e64: 1629 case AMDGPU::V_MFMA_F64_4X4X4F64_vgprcd_e64: 1630 NeedWaitStates = DMFMA4x4WritesVGPROverlappedMFMASrcABWaitStates; 1631 break; 1632 default: 1633 switch (TSchedModel.computeInstrLatency(MI1)) { 1634 case 2: 1635 NeedWaitStates = ST.hasGFX940Insts() 1636 ? isXDL(ST, *MI1) 1637 ? GFX940_XDL2PassWritesVGPROverlappedSrcABWaitStates 1638 : GFX940_SMFMA2PassWritesVGPROverlappedSrcABWaitStates 1639 : SMFMA4x4WritesVGPROverlappedSrcABWaitStates; 1640 break; 1641 case 4: 1642 assert(ST.hasGFX940Insts()); 1643 NeedWaitStates = isXDL(ST, *MI1) 1644 ? GFX940_XDL4PassWritesVGPROverlappedSrcABWaitStates 1645 : GFX940_SMFMA4PassWritesVGPROverlappedSrcABWaitStates; 1646 break; 1647 case 8: 1648 NeedWaitStates = ST.hasGFX940Insts() 1649 ? isXDL(ST, *MI1) 1650 ? GFX940_XDL8PassWritesVGPROverlappedSrcABWaitStates 1651 : GFX940_SMFMA8PassWritesVGPROverlappedSrcABWaitStates 1652 : SMFMA16x16WritesVGPROverlappedSrcABWaitStates; 1653 break; 1654 case 16: LLVM_FALLTHROUGH; 1655 default: 1656 NeedWaitStates = ST.hasGFX940Insts() 1657 ? isXDL(ST, *MI1) 1658 ? GFX940_XDL16PassWritesVGPROverlappedSrcABWaitStates 1659 : GFX940_SMFMA16PassWritesVGPROverlappedSrcABWaitStates 1660 : SMFMA32x32WritesVGPROverlappedSrcABWaitStates; 1661 } 1662 } 1663 } 1664 if (WaitStatesNeeded >= NeedWaitStates) 1665 continue; 1666 1667 WaitStatesNeededForUse = NeedWaitStates - NumWaitStates; 1668 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse); 1669 1670 if (WaitStatesNeeded == MaxWaitStates) 1671 break; 1672 } 1673 1674 return WaitStatesNeeded; 1675 } 1676 1677 int GCNHazardRecognizer::checkMAILdStHazards(MachineInstr *MI) { 1678 // On gfx90a+ relevant hazards are checked in checkMAIVALUHazards() 1679 if (!ST.hasMAIInsts() || ST.hasGFX90AInsts()) 1680 return 0; 1681 1682 int WaitStatesNeeded = 0; 1683 1684 auto IsAccVgprReadFn = [](const MachineInstr &MI) { 1685 return MI.getOpcode() == AMDGPU::V_ACCVGPR_READ_B32_e64; 1686 }; 1687 1688 for (const MachineOperand &Op : MI->explicit_uses()) { 1689 if (!Op.isReg() || !TRI.isVGPR(MF.getRegInfo(), Op.getReg())) 1690 continue; 1691 1692 Register Reg = Op.getReg(); 1693 1694 const int AccVgprReadLdStWaitStates = 2; 1695 const int VALUWriteAccVgprRdWrLdStDepVALUWaitStates = 1; 1696 const int MaxWaitStates = 2; 1697 1698 int WaitStatesNeededForUse = AccVgprReadLdStWaitStates - 1699 getWaitStatesSinceDef(Reg, IsAccVgprReadFn, MaxWaitStates); 1700 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse); 1701 1702 if (WaitStatesNeeded == MaxWaitStates) 1703 return WaitStatesNeeded; // Early exit. 1704 1705 auto IsVALUAccVgprRdWrCheckFn = [Reg, this](const MachineInstr &MI) { 1706 if (MI.getOpcode() != AMDGPU::V_ACCVGPR_READ_B32_e64 && 1707 MI.getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32_e64) 1708 return false; 1709 auto IsVALUFn = [](const MachineInstr &MI) { 1710 return SIInstrInfo::isVALU(MI) && !SIInstrInfo::isMAI(MI); 1711 }; 1712 return getWaitStatesSinceDef(Reg, IsVALUFn, 2 /*MaxWaitStates*/) < 1713 std::numeric_limits<int>::max(); 1714 }; 1715 1716 WaitStatesNeededForUse = VALUWriteAccVgprRdWrLdStDepVALUWaitStates - 1717 getWaitStatesSince(IsVALUAccVgprRdWrCheckFn, MaxWaitStates); 1718 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse); 1719 } 1720 1721 return WaitStatesNeeded; 1722 } 1723 1724 int GCNHazardRecognizer::checkMAIVALUHazards(MachineInstr *MI) { 1725 if (!ST.hasGFX90AInsts()) 1726 return 0; 1727 1728 auto IsMFMAFn = [](const MachineInstr &MI) -> bool { 1729 return SIInstrInfo::isMAI(MI) && 1730 MI.getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32_e64 && 1731 MI.getOpcode() != AMDGPU::V_ACCVGPR_READ_B32_e64; 1732 }; 1733 1734 auto IsDGEMMFn = [](const MachineInstr &MI) -> bool { 1735 return isDGEMM(MI.getOpcode()); 1736 }; 1737 1738 // This is checked in checkMAIHazards90A() 1739 if (IsMFMAFn(*MI)) 1740 return 0; 1741 1742 int WaitStatesNeeded = 0; 1743 1744 bool IsMemOrExport = SIInstrInfo::isVMEM(*MI) || 1745 SIInstrInfo::isFLAT(*MI) || 1746 SIInstrInfo::isDS(*MI) || 1747 SIInstrInfo::isEXP(*MI); 1748 bool IsVALU = SIInstrInfo::isVALU(*MI); 1749 1750 const MachineInstr *MFMA = nullptr; 1751 unsigned Reg; 1752 auto IsMFMAWriteFn = [&Reg, &IsMFMAFn, &MFMA, this](const MachineInstr &MI) { 1753 if (!IsMFMAFn(MI) || !TRI.regsOverlap(MI.getOperand(0).getReg(), Reg)) 1754 return false; 1755 MFMA = &MI; 1756 return true; 1757 }; 1758 1759 const MachineInstr *DOT = nullptr; 1760 auto IsDotWriteFn = [&Reg, &DOT, this](const MachineInstr &MI) { 1761 if (!SIInstrInfo::isDOT(MI) || 1762 !TRI.regsOverlap(MI.getOperand(0).getReg(), Reg)) 1763 return false; 1764 DOT = &MI; 1765 return true; 1766 }; 1767 1768 int SrcCIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(), 1769 AMDGPU::OpName::src2); 1770 1771 if (IsMemOrExport || IsVALU) { 1772 const int SMFMA4x4WriteVgprVALUMemExpReadWaitStates = 5; 1773 const int SMFMA16x16WriteVgprVALUMemExpReadWaitStates = 11; 1774 const int SMFMA32x32WriteVgprVALUMemExpReadWaitStates = 19; 1775 const int GFX940_SMFMA2PassWriteVgprVALUMemExpReadWaitStates = 4; 1776 const int GFX940_SMFMA4PassWriteVgprVALUMemExpReadWaitStates = 6; 1777 const int GFX940_SMFMA8PassWriteVgprVALUMemExpReadWaitStates = 10; 1778 const int GFX940_SMFMA16PassWriteVgprVALUMemExpReadWaitStates = 18; 1779 const int GFX940_XDL2PassWriteVgprVALUMemExpReadWaitStates = 5; 1780 const int GFX940_XDL4PassWriteVgprVALUMemExpReadWaitStates = 7; 1781 const int GFX940_XDL8PassWriteVgprVALUMemExpReadWaitStates = 11; 1782 const int GFX940_XDL16PassWriteVgprVALUMemExpReadWaitStates = 19; 1783 const int DMFMA4x4WriteVgprMemExpReadWaitStates = 9; 1784 const int DMFMA16x16WriteVgprMemExpReadWaitStates = 18; 1785 const int DMFMA4x4WriteVgprVALUReadWaitStates = 6; 1786 const int DMFMA16x16WriteVgprVALUReadWaitStates = 11; 1787 const int DotWriteSameDotReadSrcAB = 3; 1788 const int DotWriteDifferentVALURead = 3; 1789 const int MaxWaitStates = 19; 1790 1791 for (const MachineOperand &Use : MI->explicit_uses()) { 1792 if (!Use.isReg()) 1793 continue; 1794 Reg = Use.getReg(); 1795 1796 DOT = nullptr; 1797 int WaitStatesSinceDef = getWaitStatesSinceDef(Reg, IsDotWriteFn, 1798 MaxWaitStates); 1799 if (DOT) { 1800 int NeedWaitStates = 0; 1801 if (DOT->getOpcode() == MI->getOpcode()) { 1802 if (&Use - &MI->getOperand(0) != SrcCIdx) 1803 NeedWaitStates = DotWriteSameDotReadSrcAB; 1804 } else { 1805 NeedWaitStates = DotWriteDifferentVALURead; 1806 } 1807 1808 int WaitStatesNeededForUse = NeedWaitStates - WaitStatesSinceDef; 1809 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse); 1810 } 1811 1812 MFMA = nullptr; 1813 WaitStatesSinceDef = 1814 getWaitStatesSinceDef(Reg, IsMFMAWriteFn, MaxWaitStates); 1815 if (!MFMA) 1816 continue; 1817 1818 unsigned HazardDefLatency = TSchedModel.computeInstrLatency(MFMA); 1819 int NeedWaitStates = MaxWaitStates; 1820 switch (HazardDefLatency) { 1821 case 2: 1822 NeedWaitStates = 1823 ST.hasGFX940Insts() 1824 ? isXDL(ST, *MFMA) 1825 ? GFX940_XDL2PassWriteVgprVALUMemExpReadWaitStates 1826 : GFX940_SMFMA2PassWriteVgprVALUMemExpReadWaitStates 1827 : SMFMA4x4WriteVgprVALUMemExpReadWaitStates; 1828 break; 1829 case 4: 1830 assert(isDGEMM(MFMA->getOpcode()) || ST.hasGFX940Insts()); 1831 NeedWaitStates = 1832 isDGEMM(MFMA->getOpcode()) 1833 ? IsMemOrExport ? DMFMA4x4WriteVgprMemExpReadWaitStates 1834 : DMFMA4x4WriteVgprVALUReadWaitStates 1835 : isXDL(ST, *MFMA) 1836 ? GFX940_XDL4PassWriteVgprVALUMemExpReadWaitStates 1837 : GFX940_SMFMA4PassWriteVgprVALUMemExpReadWaitStates; 1838 break; 1839 case 8: 1840 NeedWaitStates = 1841 ST.hasGFX940Insts() 1842 ? isXDL(ST, *MFMA) 1843 ? GFX940_XDL8PassWriteVgprVALUMemExpReadWaitStates 1844 : GFX940_SMFMA8PassWriteVgprVALUMemExpReadWaitStates 1845 : SMFMA16x16WriteVgprVALUMemExpReadWaitStates; 1846 break; 1847 case 16: LLVM_FALLTHROUGH; 1848 default: 1849 NeedWaitStates = 1850 isDGEMM(MFMA->getOpcode()) 1851 ? IsMemOrExport ? DMFMA16x16WriteVgprMemExpReadWaitStates 1852 : DMFMA16x16WriteVgprVALUReadWaitStates 1853 : ST.hasGFX940Insts() 1854 ? isXDL(ST, *MFMA) 1855 ? GFX940_XDL16PassWriteVgprVALUMemExpReadWaitStates 1856 : GFX940_SMFMA16PassWriteVgprVALUMemExpReadWaitStates 1857 : SMFMA32x32WriteVgprVALUMemExpReadWaitStates; 1858 break; 1859 } 1860 1861 int WaitStatesNeededForUse = NeedWaitStates - WaitStatesSinceDef; 1862 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse); 1863 1864 if (WaitStatesNeeded == MaxWaitStates) 1865 break; 1866 } 1867 } 1868 1869 unsigned Opc = MI->getOpcode(); 1870 const int DMFMAToFMA64WaitStates = 2; 1871 if ((Opc == AMDGPU::V_FMA_F64_e64 || 1872 Opc == AMDGPU::V_FMAC_F64_e32 || Opc == AMDGPU::V_FMAC_F64_e64 || 1873 Opc == AMDGPU::V_FMAC_F64_dpp) && 1874 WaitStatesNeeded < DMFMAToFMA64WaitStates) { 1875 int WaitStatesNeededForUse = DMFMAToFMA64WaitStates - 1876 getWaitStatesSince(IsDGEMMFn, DMFMAToFMA64WaitStates); 1877 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse); 1878 } 1879 1880 if (!IsVALU && !IsMemOrExport) 1881 return WaitStatesNeeded; 1882 1883 for (const MachineOperand &Def : MI->defs()) { 1884 const int SMFMA4x4WriteVgprVALUWawWaitStates = 5; 1885 const int SMFMA16x16WriteVgprVALUWawWaitStates = 11; 1886 const int SMFMA32x32WriteVgprVALUWawWaitStates = 19; 1887 const int GFX940_SMFMA2PassWriteVgprVALUWawWaitStates = 4; 1888 const int GFX940_SMFMA4PassWriteVgprVALUWawWaitStates = 6; 1889 const int GFX940_SMFMA8PassWriteVgprVALUWawWaitStates = 10; 1890 const int GFX940_SMFMA16PassWriteVgprVALUWawWaitStates = 18; 1891 const int GFX940_XDL2PassWriteVgprVALUWawWaitStates = 5; 1892 const int GFX940_XDL4PassWriteVgprVALUWawWaitStates = 7; 1893 const int GFX940_XDL8PassWriteVgprVALUWawWaitStates = 11; 1894 const int GFX940_XDL16PassWriteVgprVALUWawWaitStates = 19; 1895 const int SMFMA4x4ReadVgprVALUWarWaitStates = 1; 1896 const int GFX940_XDL4PassReadVgprVALUWarWaitStates = 3; 1897 const int SMFMA16x16ReadVgprVALUWarWaitStates = 7; 1898 const int SMFMA32x32ReadVgprVALUWarWaitStates = 15; 1899 const int DMFMA4x4WriteVgprVALUWriteWaitStates = 6; 1900 const int DMFMA16x16WriteVgprVALUWriteWaitStates = 11; 1901 const int DotWriteDifferentVALUWrite = 3; 1902 const int MaxWaitStates = 19; 1903 const int MaxWarWaitStates = 15; 1904 1905 Reg = Def.getReg(); 1906 1907 DOT = nullptr; 1908 int WaitStatesSinceDef = getWaitStatesSinceDef(Reg, IsDotWriteFn, 1909 MaxWaitStates); 1910 if (DOT && DOT->getOpcode() != MI->getOpcode()) 1911 WaitStatesNeeded = std::max(WaitStatesNeeded, DotWriteDifferentVALUWrite - 1912 WaitStatesSinceDef); 1913 1914 MFMA = nullptr; 1915 WaitStatesSinceDef = 1916 getWaitStatesSinceDef(Reg, IsMFMAWriteFn, MaxWaitStates); 1917 if (MFMA) { 1918 int NeedWaitStates = MaxWaitStates; 1919 switch (TSchedModel.computeInstrLatency(MFMA)) { 1920 case 2: 1921 NeedWaitStates = ST.hasGFX940Insts() 1922 ? isXDL(ST, *MFMA) 1923 ? GFX940_XDL2PassWriteVgprVALUWawWaitStates 1924 : GFX940_SMFMA2PassWriteVgprVALUWawWaitStates 1925 : SMFMA4x4WriteVgprVALUWawWaitStates; 1926 break; 1927 case 4: 1928 assert(isDGEMM(MFMA->getOpcode()) || ST.hasGFX940Insts()); 1929 NeedWaitStates = isDGEMM(MFMA->getOpcode()) 1930 ? DMFMA4x4WriteVgprVALUWriteWaitStates 1931 : isXDL(ST, *MFMA) 1932 ? GFX940_XDL4PassWriteVgprVALUWawWaitStates 1933 : GFX940_SMFMA4PassWriteVgprVALUWawWaitStates; 1934 break; 1935 case 8: 1936 NeedWaitStates = ST.hasGFX940Insts() 1937 ? isXDL(ST, *MFMA) 1938 ? GFX940_XDL8PassWriteVgprVALUWawWaitStates 1939 : GFX940_SMFMA8PassWriteVgprVALUWawWaitStates 1940 : SMFMA16x16WriteVgprVALUWawWaitStates; 1941 break; 1942 case 16: LLVM_FALLTHROUGH; 1943 default: 1944 NeedWaitStates = isDGEMM(MFMA->getOpcode()) 1945 ? DMFMA16x16WriteVgprVALUWriteWaitStates 1946 : ST.hasGFX940Insts() 1947 ? isXDL(ST, *MFMA) 1948 ? GFX940_XDL16PassWriteVgprVALUWawWaitStates 1949 : GFX940_SMFMA16PassWriteVgprVALUWawWaitStates 1950 : SMFMA32x32WriteVgprVALUWawWaitStates; 1951 break; 1952 } 1953 1954 int WaitStatesNeededForUse = NeedWaitStates - WaitStatesSinceDef; 1955 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse); 1956 1957 if (WaitStatesNeeded == MaxWaitStates) 1958 break; 1959 } 1960 1961 auto IsSMFMAReadAsCFn = [&Reg, &IsMFMAFn, &MFMA, 1962 this](const MachineInstr &MI) { 1963 if (!IsMFMAFn(MI) || isDGEMM(MI.getOpcode()) || 1964 !MI.readsRegister(Reg, &TRI)) 1965 return false; 1966 1967 if (ST.hasGFX940Insts() && !isXDL(ST, MI)) 1968 return false; 1969 1970 const MachineOperand *SrcC = 1971 TII.getNamedOperand(MI, AMDGPU::OpName::src2); 1972 assert(SrcC); 1973 if (!SrcC->isReg() || !TRI.regsOverlap(SrcC->getReg(), Reg)) 1974 return false; 1975 1976 MFMA = &MI; 1977 return true; 1978 }; 1979 1980 MFMA = nullptr; 1981 int WaitStatesSinceUse = getWaitStatesSince(IsSMFMAReadAsCFn, 1982 MaxWarWaitStates); 1983 if (!MFMA) 1984 continue; 1985 1986 unsigned HazardDefLatency = TSchedModel.computeInstrLatency(MFMA); 1987 int NeedWaitStates = MaxWaitStates; 1988 switch (HazardDefLatency) { 1989 case 2: NeedWaitStates = SMFMA4x4ReadVgprVALUWarWaitStates; 1990 break; 1991 case 4: assert(ST.hasGFX940Insts()); 1992 NeedWaitStates = GFX940_XDL4PassReadVgprVALUWarWaitStates; 1993 break; 1994 case 8: NeedWaitStates = SMFMA16x16ReadVgprVALUWarWaitStates; 1995 break; 1996 case 16: LLVM_FALLTHROUGH; 1997 default: NeedWaitStates = SMFMA32x32ReadVgprVALUWarWaitStates; 1998 break; 1999 } 2000 2001 int WaitStatesNeededForUse = NeedWaitStates - WaitStatesSinceUse; 2002 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse); 2003 } 2004 2005 return WaitStatesNeeded; 2006 } 2007 2008 bool GCNHazardRecognizer::ShouldPreferAnother(SUnit *SU) { 2009 if (!SU->isInstr()) 2010 return false; 2011 2012 const MachineInstr *MAI = nullptr; 2013 auto IsMFMAFn = [&MAI](const MachineInstr &MI) { 2014 MAI = nullptr; 2015 if (SIInstrInfo::isMAI(MI) && 2016 MI.getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32_e64 && 2017 MI.getOpcode() != AMDGPU::V_ACCVGPR_READ_B32_e64) 2018 MAI = &MI; 2019 return MAI != nullptr; 2020 }; 2021 2022 MachineInstr *MI = SU->getInstr(); 2023 if (IsMFMAFn(*MI)) { 2024 int W = getWaitStatesSince(IsMFMAFn, 16); 2025 if (MAI) 2026 return W < (int)TSchedModel.computeInstrLatency(MAI); 2027 } 2028 2029 return false; 2030 } 2031