1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "SIDefines.h" 22 #include "SIRegisterInfo.h" 23 #include "TargetInfo/AMDGPUTargetInfo.h" 24 #include "Utils/AMDGPUBaseInfo.h" 25 #include "llvm-c/DisassemblerTypes.h" 26 #include "llvm/BinaryFormat/ELF.h" 27 #include "llvm/MC/MCAsmInfo.h" 28 #include "llvm/MC/MCContext.h" 29 #include "llvm/MC/MCDecoderOps.h" 30 #include "llvm/MC/MCExpr.h" 31 #include "llvm/MC/MCInstrDesc.h" 32 #include "llvm/MC/MCRegisterInfo.h" 33 #include "llvm/MC/MCSubtargetInfo.h" 34 #include "llvm/MC/TargetRegistry.h" 35 #include "llvm/Support/AMDHSAKernelDescriptor.h" 36 37 using namespace llvm; 38 39 #define DEBUG_TYPE "amdgpu-disassembler" 40 41 #define SGPR_MAX \ 42 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 43 : AMDGPU::EncValues::SGPR_MAX_SI) 44 45 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 46 47 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 48 MCContext &Ctx, MCInstrInfo const *MCII) 49 : MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), 50 MAI(*Ctx.getAsmInfo()), TargetMaxInstBytes(MAI.getMaxInstLength(&STI)) { 51 // ToDo: AMDGPUDisassembler supports only VI ISA. 52 if (!STI.hasFeature(AMDGPU::FeatureGCN3Encoding) && !isGFX10Plus()) 53 report_fatal_error("Disassembly not yet supported for subtarget"); 54 } 55 56 inline static MCDisassembler::DecodeStatus 57 addOperand(MCInst &Inst, const MCOperand& Opnd) { 58 Inst.addOperand(Opnd); 59 return Opnd.isValid() ? 60 MCDisassembler::Success : 61 MCDisassembler::Fail; 62 } 63 64 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 65 uint16_t NameIdx) { 66 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 67 if (OpIdx != -1) { 68 auto I = MI.begin(); 69 std::advance(I, OpIdx); 70 MI.insert(I, Op); 71 } 72 return OpIdx; 73 } 74 75 static DecodeStatus decodeSOPPBrTarget(MCInst &Inst, unsigned Imm, 76 uint64_t Addr, 77 const MCDisassembler *Decoder) { 78 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 79 80 // Our branches take a simm16, but we need two extra bits to account for the 81 // factor of 4. 82 APInt SignedOffset(18, Imm * 4, true); 83 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 84 85 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2, 0)) 86 return MCDisassembler::Success; 87 return addOperand(Inst, MCOperand::createImm(Imm)); 88 } 89 90 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, 91 const MCDisassembler *Decoder) { 92 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 93 int64_t Offset; 94 if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 95 Offset = Imm & 0xFFFFF; 96 } else { // GFX9+ supports 21-bit signed offsets. 97 Offset = SignExtend64<21>(Imm); 98 } 99 return addOperand(Inst, MCOperand::createImm(Offset)); 100 } 101 102 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, 103 const MCDisassembler *Decoder) { 104 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 105 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 106 } 107 108 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 109 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \ 110 uint64_t /*Addr*/, \ 111 const MCDisassembler *Decoder) { \ 112 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 113 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 114 } 115 116 // Decoder for registers, decode directly using RegClassID. Imm(8-bit) is 117 // number of register. Used by VGPR only and AGPR only operands. 118 #define DECODE_OPERAND_REG_8(RegClass) \ 119 static DecodeStatus Decode##RegClass##RegisterClass( \ 120 MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \ 121 const MCDisassembler *Decoder) { \ 122 assert(Imm < (1 << 8) && "8-bit encoding"); \ 123 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 124 return addOperand( \ 125 Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm)); \ 126 } 127 128 #define DECODE_SrcOp(Name, EncSize, OpWidth, EncImm, MandatoryLiteral, \ 129 ImmWidth) \ 130 static DecodeStatus Name(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \ 131 const MCDisassembler *Decoder) { \ 132 assert(Imm < (1 << EncSize) && #EncSize "-bit encoding"); \ 133 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 134 return addOperand(Inst, \ 135 DAsm->decodeSrcOp(AMDGPUDisassembler::OpWidth, EncImm, \ 136 MandatoryLiteral, ImmWidth)); \ 137 } 138 139 // Decoder for registers. Imm(7-bit) is number of register, uses decodeSrcOp to 140 // get register class. Used by SGPR only operands. 141 #define DECODE_OPERAND_REG_7(RegClass, OpWidth) \ 142 DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0) 143 144 // Decoder for registers. Imm(10-bit): Imm{7-0} is number of register, 145 // Imm{9} is acc(agpr or vgpr) Imm{8} should be 0 (see VOP3Pe_SMFMAC). 146 // Set Imm{8} to 1 (IS_VGPR) to decode using 'enum10' from decodeSrcOp. 147 // Used by AV_ register classes (AGPR or VGPR only register operands). 148 #define DECODE_OPERAND_REG_AV10(RegClass, OpWidth) \ 149 DECODE_SrcOp(Decode##RegClass##RegisterClass, 10, OpWidth, \ 150 Imm | AMDGPU::EncValues::IS_VGPR, false, 0) 151 152 // Decoder for Src(9-bit encoding) registers only. 153 #define DECODE_OPERAND_SRC_REG_9(RegClass, OpWidth) \ 154 DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm, false, 0) 155 156 // Decoder for Src(9-bit encoding) AGPR, register number encoded in 9bits, set 157 // Imm{9} to 1 (set acc) and decode using 'enum10' from decodeSrcOp, registers 158 // only. 159 #define DECODE_OPERAND_SRC_REG_A9(RegClass, OpWidth) \ 160 DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm | 512, false, 0) 161 162 // Decoder for 'enum10' from decodeSrcOp, Imm{0-8} is 9-bit Src encoding 163 // Imm{9} is acc, registers only. 164 #define DECODE_SRC_OPERAND_REG_AV10(RegClass, OpWidth) \ 165 DECODE_SrcOp(decodeOperand_##RegClass, 10, OpWidth, Imm, false, 0) 166 167 // Decoder for RegisterOperands using 9-bit Src encoding. Operand can be 168 // register from RegClass or immediate. Registers that don't belong to RegClass 169 // will be decoded and InstPrinter will report warning. Immediate will be 170 // decoded into constant of size ImmWidth, should match width of immediate used 171 // by OperandType (important for floating point types). 172 #define DECODE_OPERAND_SRC_REG_OR_IMM_9(RegClass, OpWidth, ImmWidth) \ 173 DECODE_SrcOp(decodeOperand_##RegClass##_Imm##ImmWidth, 9, OpWidth, Imm, \ 174 false, ImmWidth) 175 176 // Decoder for Src(9-bit encoding) AGPR or immediate. Set Imm{9} to 1 (set acc) 177 // and decode using 'enum10' from decodeSrcOp. 178 #define DECODE_OPERAND_SRC_REG_OR_IMM_A9(RegClass, OpWidth, ImmWidth) \ 179 DECODE_SrcOp(decodeOperand_##RegClass##_Imm##ImmWidth, 9, OpWidth, \ 180 Imm | 512, false, ImmWidth) 181 182 #define DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(RegClass, OpWidth, ImmWidth) \ 183 DECODE_SrcOp(decodeOperand_##RegClass##_Deferred##_Imm##ImmWidth, 9, \ 184 OpWidth, Imm, true, ImmWidth) 185 186 // Default decoders generated by tablegen: 'Decode<RegClass>RegisterClass' 187 // when RegisterClass is used as an operand. Most often used for destination 188 // operands. 189 190 DECODE_OPERAND_REG_8(VGPR_32) 191 DECODE_OPERAND_REG_8(VGPR_32_Lo128) 192 DECODE_OPERAND_REG_8(VReg_64) 193 DECODE_OPERAND_REG_8(VReg_96) 194 DECODE_OPERAND_REG_8(VReg_128) 195 DECODE_OPERAND_REG_8(VReg_256) 196 DECODE_OPERAND_REG_8(VReg_288) 197 DECODE_OPERAND_REG_8(VReg_352) 198 DECODE_OPERAND_REG_8(VReg_384) 199 DECODE_OPERAND_REG_8(VReg_512) 200 DECODE_OPERAND_REG_8(VReg_1024) 201 202 DECODE_OPERAND_REG_7(SReg_32, OPW32) 203 DECODE_OPERAND_REG_7(SReg_32_XM0_XEXEC, OPW32) 204 DECODE_OPERAND_REG_7(SReg_32_XEXEC_HI, OPW32) 205 DECODE_OPERAND_REG_7(SReg_64, OPW64) 206 DECODE_OPERAND_REG_7(SReg_64_XEXEC, OPW64) 207 DECODE_OPERAND_REG_7(SReg_128, OPW128) 208 DECODE_OPERAND_REG_7(SReg_256, OPW256) 209 DECODE_OPERAND_REG_7(SReg_512, OPW512) 210 211 DECODE_OPERAND_REG_8(AGPR_32) 212 DECODE_OPERAND_REG_8(AReg_64) 213 DECODE_OPERAND_REG_8(AReg_128) 214 DECODE_OPERAND_REG_8(AReg_256) 215 DECODE_OPERAND_REG_8(AReg_512) 216 DECODE_OPERAND_REG_8(AReg_1024) 217 218 DECODE_OPERAND_REG_AV10(AVDst_128, OPW128) 219 DECODE_OPERAND_REG_AV10(AVDst_512, OPW512) 220 221 // Decoders for register only source RegisterOperands that use use 9-bit Src 222 // encoding: 'decodeOperand_<RegClass>'. 223 224 DECODE_OPERAND_SRC_REG_9(VGPR_32, OPW32) 225 DECODE_OPERAND_SRC_REG_9(VReg_64, OPW64) 226 DECODE_OPERAND_SRC_REG_9(VReg_128, OPW128) 227 DECODE_OPERAND_SRC_REG_9(VReg_256, OPW256) 228 DECODE_OPERAND_SRC_REG_9(VRegOrLds_32, OPW32) 229 230 DECODE_OPERAND_SRC_REG_A9(AGPR_32, OPW32) 231 232 DECODE_SRC_OPERAND_REG_AV10(AV_32, OPW32) 233 DECODE_SRC_OPERAND_REG_AV10(AV_64, OPW64) 234 DECODE_SRC_OPERAND_REG_AV10(AV_128, OPW128) 235 236 // Decoders for register or immediate RegisterOperands that use 9-bit Src 237 // encoding: 'decodeOperand_<RegClass>_Imm<ImmWidth>'. 238 239 DECODE_OPERAND_SRC_REG_OR_IMM_9(SReg_64, OPW64, 64) 240 DECODE_OPERAND_SRC_REG_OR_IMM_9(SReg_32, OPW32, 32) 241 DECODE_OPERAND_SRC_REG_OR_IMM_9(SReg_32, OPW32, 16) 242 DECODE_OPERAND_SRC_REG_OR_IMM_9(SRegOrLds_32, OPW32, 32) 243 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32_Lo128, OPW16, 16) 244 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32, OPW32, 16) 245 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32, OPW32, 32) 246 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_64, OPW64, 64) 247 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_64, OPW64, 32) 248 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_64, OPW64, 64) 249 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_128, OPW128, 32) 250 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_256, OPW256, 64) 251 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_512, OPW512, 32) 252 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_1024, OPW1024, 32) 253 254 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_64, OPW64, 64) 255 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_128, OPW128, 32) 256 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_256, OPW256, 64) 257 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_512, OPW512, 32) 258 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_1024, OPW1024, 32) 259 260 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32_Lo128, OPW16, 16) 261 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32, OPW16, 16) 262 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32, OPW32, 32) 263 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(SReg_32, OPW32, 32) 264 265 static DecodeStatus decodeOperand_KImmFP(MCInst &Inst, unsigned Imm, 266 uint64_t Addr, 267 const MCDisassembler *Decoder) { 268 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 269 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 270 } 271 272 static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val, 273 uint64_t Addr, const void *Decoder) { 274 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 275 return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val)); 276 } 277 278 static bool IsAGPROperand(const MCInst &Inst, int OpIdx, 279 const MCRegisterInfo *MRI) { 280 if (OpIdx < 0) 281 return false; 282 283 const MCOperand &Op = Inst.getOperand(OpIdx); 284 if (!Op.isReg()) 285 return false; 286 287 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); 288 auto Reg = Sub ? Sub : Op.getReg(); 289 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; 290 } 291 292 static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, unsigned Imm, 293 AMDGPUDisassembler::OpWidthTy Opw, 294 const MCDisassembler *Decoder) { 295 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 296 if (!DAsm->isGFX90A()) { 297 Imm &= 511; 298 } else { 299 // If atomic has both vdata and vdst their register classes are tied. 300 // The bit is decoded along with the vdst, first operand. We need to 301 // change register class to AGPR if vdst was AGPR. 302 // If a DS instruction has both data0 and data1 their register classes 303 // are also tied. 304 unsigned Opc = Inst.getOpcode(); 305 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; 306 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 307 : AMDGPU::OpName::vdata; 308 const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo(); 309 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); 310 if ((int)Inst.getNumOperands() == DataIdx) { 311 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); 312 if (IsAGPROperand(Inst, DstIdx, MRI)) 313 Imm |= 512; 314 } 315 316 if (TSFlags & SIInstrFlags::DS) { 317 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); 318 if ((int)Inst.getNumOperands() == Data2Idx && 319 IsAGPROperand(Inst, DataIdx, MRI)) 320 Imm |= 512; 321 } 322 } 323 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); 324 } 325 326 static DecodeStatus 327 DecodeAVLdSt_32RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 328 const MCDisassembler *Decoder) { 329 return decodeOperand_AVLdSt_Any(Inst, Imm, 330 AMDGPUDisassembler::OPW32, Decoder); 331 } 332 333 static DecodeStatus 334 DecodeAVLdSt_64RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 335 const MCDisassembler *Decoder) { 336 return decodeOperand_AVLdSt_Any(Inst, Imm, 337 AMDGPUDisassembler::OPW64, Decoder); 338 } 339 340 static DecodeStatus 341 DecodeAVLdSt_96RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 342 const MCDisassembler *Decoder) { 343 return decodeOperand_AVLdSt_Any(Inst, Imm, 344 AMDGPUDisassembler::OPW96, Decoder); 345 } 346 347 static DecodeStatus 348 DecodeAVLdSt_128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 349 const MCDisassembler *Decoder) { 350 return decodeOperand_AVLdSt_Any(Inst, Imm, 351 AMDGPUDisassembler::OPW128, Decoder); 352 } 353 354 static DecodeStatus 355 DecodeAVLdSt_160RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 356 const MCDisassembler *Decoder) { 357 return decodeOperand_AVLdSt_Any(Inst, Imm, AMDGPUDisassembler::OPW160, 358 Decoder); 359 } 360 361 #define DECODE_SDWA(DecName) \ 362 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 363 364 DECODE_SDWA(Src32) 365 DECODE_SDWA(Src16) 366 DECODE_SDWA(VopcDst) 367 368 #include "AMDGPUGenDisassemblerTables.inc" 369 370 //===----------------------------------------------------------------------===// 371 // 372 //===----------------------------------------------------------------------===// 373 374 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 375 assert(Bytes.size() >= sizeof(T)); 376 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data()); 377 Bytes = Bytes.slice(sizeof(T)); 378 return Res; 379 } 380 381 static inline DecoderUInt128 eat12Bytes(ArrayRef<uint8_t> &Bytes) { 382 assert(Bytes.size() >= 12); 383 uint64_t Lo = support::endian::read<uint64_t, support::endianness::little>( 384 Bytes.data()); 385 Bytes = Bytes.slice(8); 386 uint64_t Hi = support::endian::read<uint32_t, support::endianness::little>( 387 Bytes.data()); 388 Bytes = Bytes.slice(4); 389 return DecoderUInt128(Lo, Hi); 390 } 391 392 // The disassembler is greedy, so we need to check FI operand value to 393 // not parse a dpp if the correct literal is not set. For dpp16 the 394 // autogenerated decoder checks the dpp literal 395 static bool isValidDPP8(const MCInst &MI) { 396 using namespace llvm::AMDGPU::DPP; 397 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi); 398 assert(FiIdx != -1); 399 if ((unsigned)FiIdx >= MI.getNumOperands()) 400 return false; 401 unsigned Fi = MI.getOperand(FiIdx).getImm(); 402 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1; 403 } 404 405 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 406 ArrayRef<uint8_t> Bytes_, 407 uint64_t Address, 408 raw_ostream &CS) const { 409 bool IsSDWA = false; 410 411 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 412 Bytes = Bytes_.slice(0, MaxInstBytesNum); 413 414 DecodeStatus Res = MCDisassembler::Fail; 415 do { 416 // ToDo: better to switch encoding length using some bit predicate 417 // but it is unknown yet, so try all we can 418 419 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 420 // encodings 421 if (isGFX11Plus() && Bytes.size() >= 12 ) { 422 DecoderUInt128 DecW = eat12Bytes(Bytes); 423 Res = 424 tryDecodeInst(DecoderTableDPP8GFX1196, DecoderTableDPP8GFX11_FAKE1696, 425 MI, DecW, Address, CS); 426 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 427 break; 428 MI = MCInst(); // clear 429 Res = tryDecodeInst(DecoderTableDPPGFX1196, DecoderTableDPPGFX11_FAKE1696, 430 MI, DecW, Address, CS); 431 if (Res) { 432 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3P) 433 convertVOP3PDPPInst(MI); 434 else if (AMDGPU::isVOPC64DPP(MI.getOpcode())) 435 convertVOPCDPPInst(MI); // Special VOP3 case 436 else { 437 assert(MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3); 438 convertVOP3DPPInst(MI); // Regular VOP3 case 439 } 440 break; 441 } 442 Res = tryDecodeInst(DecoderTableGFX1196, MI, DecW, Address, CS); 443 if (Res) 444 break; 445 } 446 // Reinitialize Bytes 447 Bytes = Bytes_.slice(0, MaxInstBytesNum); 448 449 if (Bytes.size() >= 8) { 450 const uint64_t QW = eatBytes<uint64_t>(Bytes); 451 452 if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding)) { 453 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address, CS); 454 if (Res) { 455 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) 456 == -1) 457 break; 458 if (convertDPP8Inst(MI) == MCDisassembler::Success) 459 break; 460 MI = MCInst(); // clear 461 } 462 } 463 464 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address, CS); 465 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 466 break; 467 MI = MCInst(); // clear 468 469 Res = tryDecodeInst(DecoderTableDPP8GFX1164, 470 DecoderTableDPP8GFX11_FAKE1664, MI, QW, Address, CS); 471 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 472 break; 473 MI = MCInst(); // clear 474 475 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address, CS); 476 if (Res) break; 477 478 Res = tryDecodeInst(DecoderTableDPPGFX1164, DecoderTableDPPGFX11_FAKE1664, 479 MI, QW, Address, CS); 480 if (Res) { 481 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC) 482 convertVOPCDPPInst(MI); 483 break; 484 } 485 486 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address, CS); 487 if (Res) { IsSDWA = true; break; } 488 489 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address, CS); 490 if (Res) { IsSDWA = true; break; } 491 492 Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address, CS); 493 if (Res) { IsSDWA = true; break; } 494 495 if (STI.hasFeature(AMDGPU::FeatureUnpackedD16VMem)) { 496 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address, CS); 497 if (Res) 498 break; 499 } 500 501 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 502 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 503 // table first so we print the correct name. 504 if (STI.hasFeature(AMDGPU::FeatureFmaMixInsts)) { 505 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address, CS); 506 if (Res) 507 break; 508 } 509 } 510 511 // Reinitialize Bytes as DPP64 could have eaten too much 512 Bytes = Bytes_.slice(0, MaxInstBytesNum); 513 514 // Try decode 32-bit instruction 515 if (Bytes.size() < 4) break; 516 const uint32_t DW = eatBytes<uint32_t>(Bytes); 517 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address, CS); 518 if (Res) break; 519 520 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address, CS); 521 if (Res) break; 522 523 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address, CS); 524 if (Res) break; 525 526 if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts)) { 527 Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address, CS); 528 if (Res) 529 break; 530 } 531 532 if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding)) { 533 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address, CS); 534 if (Res) break; 535 } 536 537 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address, CS); 538 if (Res) break; 539 540 Res = tryDecodeInst(DecoderTableGFX1132, DecoderTableGFX11_FAKE1632, MI, DW, 541 Address, CS); 542 if (Res) break; 543 544 if (Bytes.size() < 4) break; 545 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 546 547 if (STI.hasFeature(AMDGPU::FeatureGFX940Insts)) { 548 Res = tryDecodeInst(DecoderTableGFX94064, MI, QW, Address, CS); 549 if (Res) 550 break; 551 } 552 553 if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts)) { 554 Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address, CS); 555 if (Res) 556 break; 557 } 558 559 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address, CS); 560 if (Res) break; 561 562 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address, CS); 563 if (Res) break; 564 565 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address, CS); 566 if (Res) break; 567 568 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address, CS); 569 if (Res) break; 570 571 Res = tryDecodeInst(DecoderTableGFX1164, DecoderTableGFX11_FAKE1664, MI, QW, 572 Address, CS); 573 if (Res) 574 break; 575 576 Res = tryDecodeInst(DecoderTableWMMAGFX1164, MI, QW, Address, CS); 577 } while (false); 578 579 if (Res && AMDGPU::isMAC(MI.getOpcode())) { 580 // Insert dummy unused src2_modifiers. 581 insertNamedMCOperand(MI, MCOperand::createImm(0), 582 AMDGPU::OpName::src2_modifiers); 583 } 584 585 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 586 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT | SIInstrFlags::SMRD))) { 587 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 588 AMDGPU::OpName::cpol); 589 if (CPolPos != -1) { 590 unsigned CPol = 591 (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ? 592 AMDGPU::CPol::GLC : 0; 593 if (MI.getNumOperands() <= (unsigned)CPolPos) { 594 insertNamedMCOperand(MI, MCOperand::createImm(CPol), 595 AMDGPU::OpName::cpol); 596 } else if (CPol) { 597 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); 598 } 599 } 600 } 601 602 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 603 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) && 604 (STI.hasFeature(AMDGPU::FeatureGFX90AInsts))) { 605 // GFX90A lost TFE, its place is occupied by ACC. 606 int TFEOpIdx = 607 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); 608 if (TFEOpIdx != -1) { 609 auto TFEIter = MI.begin(); 610 std::advance(TFEIter, TFEOpIdx); 611 MI.insert(TFEIter, MCOperand::createImm(0)); 612 } 613 } 614 615 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 616 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF))) { 617 int SWZOpIdx = 618 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); 619 if (SWZOpIdx != -1) { 620 auto SWZIter = MI.begin(); 621 std::advance(SWZIter, SWZOpIdx); 622 MI.insert(SWZIter, MCOperand::createImm(0)); 623 } 624 } 625 626 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 627 int VAddr0Idx = 628 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 629 int RsrcIdx = 630 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 631 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 632 if (VAddr0Idx >= 0 && NSAArgs > 0) { 633 unsigned NSAWords = (NSAArgs + 3) / 4; 634 if (Bytes.size() < 4 * NSAWords) { 635 Res = MCDisassembler::Fail; 636 } else { 637 for (unsigned i = 0; i < NSAArgs; ++i) { 638 const unsigned VAddrIdx = VAddr0Idx + 1 + i; 639 auto VAddrRCID = 640 MCII->get(MI.getOpcode()).operands()[VAddrIdx].RegClass; 641 MI.insert(MI.begin() + VAddrIdx, 642 createRegOperand(VAddrRCID, Bytes[i])); 643 } 644 Bytes = Bytes.slice(4 * NSAWords); 645 } 646 } 647 648 if (Res) 649 Res = convertMIMGInst(MI); 650 } 651 652 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::EXP)) 653 Res = convertEXPInst(MI); 654 655 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VINTERP)) 656 Res = convertVINTERPInst(MI); 657 658 if (Res && IsSDWA) 659 Res = convertSDWAInst(MI); 660 661 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 662 AMDGPU::OpName::vdst_in); 663 if (VDstIn_Idx != -1) { 664 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 665 MCOI::OperandConstraint::TIED_TO); 666 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 667 !MI.getOperand(VDstIn_Idx).isReg() || 668 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 669 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 670 MI.erase(&MI.getOperand(VDstIn_Idx)); 671 insertNamedMCOperand(MI, 672 MCOperand::createReg(MI.getOperand(Tied).getReg()), 673 AMDGPU::OpName::vdst_in); 674 } 675 } 676 677 int ImmLitIdx = 678 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm); 679 bool IsSOPK = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::SOPK; 680 if (Res && ImmLitIdx != -1 && !IsSOPK) 681 Res = convertFMAanyK(MI, ImmLitIdx); 682 683 // if the opcode was not recognized we'll assume a Size of 4 bytes 684 // (unless there are fewer bytes left) 685 Size = Res ? (MaxInstBytesNum - Bytes.size()) 686 : std::min((size_t)4, Bytes_.size()); 687 return Res; 688 } 689 690 DecodeStatus AMDGPUDisassembler::convertEXPInst(MCInst &MI) const { 691 if (STI.hasFeature(AMDGPU::FeatureGFX11)) { 692 // The MCInst still has these fields even though they are no longer encoded 693 // in the GFX11 instruction. 694 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vm); 695 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::compr); 696 } 697 return MCDisassembler::Success; 698 } 699 700 DecodeStatus AMDGPUDisassembler::convertVINTERPInst(MCInst &MI) const { 701 if (MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx11 || 702 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx11 || 703 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx11 || 704 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx11) { 705 // The MCInst has this field that is not directly encoded in the 706 // instruction. 707 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::op_sel); 708 } 709 return MCDisassembler::Success; 710 } 711 712 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 713 if (STI.hasFeature(AMDGPU::FeatureGFX9) || 714 STI.hasFeature(AMDGPU::FeatureGFX10)) { 715 if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::sdst)) 716 // VOPC - insert clamp 717 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 718 } else if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) { 719 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 720 if (SDst != -1) { 721 // VOPC - insert VCC register as sdst 722 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 723 AMDGPU::OpName::sdst); 724 } else { 725 // VOP1/2 - insert omod if present in instruction 726 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 727 } 728 } 729 return MCDisassembler::Success; 730 } 731 732 struct VOPModifiers { 733 unsigned OpSel = 0; 734 unsigned OpSelHi = 0; 735 unsigned NegLo = 0; 736 unsigned NegHi = 0; 737 }; 738 739 // Reconstruct values of VOP3/VOP3P operands such as op_sel. 740 // Note that these values do not affect disassembler output, 741 // so this is only necessary for consistency with src_modifiers. 742 static VOPModifiers collectVOPModifiers(const MCInst &MI, 743 bool IsVOP3P = false) { 744 VOPModifiers Modifiers; 745 unsigned Opc = MI.getOpcode(); 746 const int ModOps[] = {AMDGPU::OpName::src0_modifiers, 747 AMDGPU::OpName::src1_modifiers, 748 AMDGPU::OpName::src2_modifiers}; 749 for (int J = 0; J < 3; ++J) { 750 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]); 751 if (OpIdx == -1) 752 continue; 753 754 unsigned Val = MI.getOperand(OpIdx).getImm(); 755 756 Modifiers.OpSel |= !!(Val & SISrcMods::OP_SEL_0) << J; 757 if (IsVOP3P) { 758 Modifiers.OpSelHi |= !!(Val & SISrcMods::OP_SEL_1) << J; 759 Modifiers.NegLo |= !!(Val & SISrcMods::NEG) << J; 760 Modifiers.NegHi |= !!(Val & SISrcMods::NEG_HI) << J; 761 } else if (J == 0) { 762 Modifiers.OpSel |= !!(Val & SISrcMods::DST_OP_SEL) << 3; 763 } 764 } 765 766 return Modifiers; 767 } 768 769 // MAC opcodes have special old and src2 operands. 770 // src2 is tied to dst, while old is not tied (but assumed to be). 771 bool AMDGPUDisassembler::isMacDPP(MCInst &MI) const { 772 constexpr int DST_IDX = 0; 773 auto Opcode = MI.getOpcode(); 774 const auto &Desc = MCII->get(Opcode); 775 auto OldIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::old); 776 777 if (OldIdx != -1 && Desc.getOperandConstraint( 778 OldIdx, MCOI::OperandConstraint::TIED_TO) == -1) { 779 assert(AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src2)); 780 assert(Desc.getOperandConstraint( 781 AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2), 782 MCOI::OperandConstraint::TIED_TO) == DST_IDX); 783 (void)DST_IDX; 784 return true; 785 } 786 787 return false; 788 } 789 790 // Create dummy old operand and insert dummy unused src2_modifiers 791 void AMDGPUDisassembler::convertMacDPPInst(MCInst &MI) const { 792 assert(MI.getNumOperands() + 1 < MCII->get(MI.getOpcode()).getNumOperands()); 793 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 794 insertNamedMCOperand(MI, MCOperand::createImm(0), 795 AMDGPU::OpName::src2_modifiers); 796 } 797 798 // We must check FI == literal to reject not genuine dpp8 insts, and we must 799 // first add optional MI operands to check FI 800 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 801 unsigned Opc = MI.getOpcode(); 802 if (MCII->get(Opc).TSFlags & SIInstrFlags::VOP3P) { 803 convertVOP3PDPPInst(MI); 804 } else if ((MCII->get(Opc).TSFlags & SIInstrFlags::VOPC) || 805 AMDGPU::isVOPC64DPP(Opc)) { 806 convertVOPCDPPInst(MI); 807 } else { 808 if (isMacDPP(MI)) 809 convertMacDPPInst(MI); 810 811 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 812 if (MI.getNumOperands() < DescNumOps && 813 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { 814 auto Mods = collectVOPModifiers(MI); 815 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 816 AMDGPU::OpName::op_sel); 817 } else { 818 // Insert dummy unused src modifiers. 819 if (MI.getNumOperands() < DescNumOps && 820 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) 821 insertNamedMCOperand(MI, MCOperand::createImm(0), 822 AMDGPU::OpName::src0_modifiers); 823 824 if (MI.getNumOperands() < DescNumOps && 825 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers)) 826 insertNamedMCOperand(MI, MCOperand::createImm(0), 827 AMDGPU::OpName::src1_modifiers); 828 } 829 } 830 return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail; 831 } 832 833 DecodeStatus AMDGPUDisassembler::convertVOP3DPPInst(MCInst &MI) const { 834 if (isMacDPP(MI)) 835 convertMacDPPInst(MI); 836 837 unsigned Opc = MI.getOpcode(); 838 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 839 if (MI.getNumOperands() < DescNumOps && 840 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { 841 auto Mods = collectVOPModifiers(MI); 842 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 843 AMDGPU::OpName::op_sel); 844 } 845 return MCDisassembler::Success; 846 } 847 848 // Note that before gfx10, the MIMG encoding provided no information about 849 // VADDR size. Consequently, decoded instructions always show address as if it 850 // has 1 dword, which could be not really so. 851 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 852 853 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 854 AMDGPU::OpName::vdst); 855 856 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 857 AMDGPU::OpName::vdata); 858 int VAddr0Idx = 859 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 860 int RsrcIdx = 861 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 862 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 863 AMDGPU::OpName::dmask); 864 865 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 866 AMDGPU::OpName::tfe); 867 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 868 AMDGPU::OpName::d16); 869 870 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 871 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 872 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 873 874 assert(VDataIdx != -1); 875 if (BaseOpcode->BVH) { 876 // Add A16 operand for intersect_ray instructions 877 addOperand(MI, MCOperand::createImm(BaseOpcode->A16)); 878 return MCDisassembler::Success; 879 } 880 881 bool IsAtomic = (VDstIdx != -1); 882 bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4; 883 bool IsNSA = false; 884 bool IsPartialNSA = false; 885 unsigned AddrSize = Info->VAddrDwords; 886 887 if (isGFX10Plus()) { 888 unsigned DimIdx = 889 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 890 int A16Idx = 891 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16); 892 const AMDGPU::MIMGDimInfo *Dim = 893 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 894 const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm()); 895 896 AddrSize = 897 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); 898 899 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA || 900 Info->MIMGEncoding == AMDGPU::MIMGEncGfx11NSA; 901 if (!IsNSA) { 902 if (AddrSize > 12) 903 AddrSize = 16; 904 } else { 905 if (AddrSize > Info->VAddrDwords) { 906 if (!STI.hasFeature(AMDGPU::FeaturePartialNSAEncoding)) { 907 // The NSA encoding does not contain enough operands for the 908 // combination of base opcode / dimension. Should this be an error? 909 return MCDisassembler::Success; 910 } 911 IsPartialNSA = true; 912 } 913 } 914 } 915 916 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 917 unsigned DstSize = IsGather4 ? 4 : std::max(llvm::popcount(DMask), 1); 918 919 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 920 if (D16 && AMDGPU::hasPackedD16(STI)) { 921 DstSize = (DstSize + 1) / 2; 922 } 923 924 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm()) 925 DstSize += 1; 926 927 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 928 return MCDisassembler::Success; 929 930 int NewOpcode = 931 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 932 if (NewOpcode == -1) 933 return MCDisassembler::Success; 934 935 // Widen the register to the correct number of enabled channels. 936 unsigned NewVdata = AMDGPU::NoRegister; 937 if (DstSize != Info->VDataDwords) { 938 auto DataRCID = MCII->get(NewOpcode).operands()[VDataIdx].RegClass; 939 940 // Get first subregister of VData 941 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 942 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 943 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 944 945 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 946 &MRI.getRegClass(DataRCID)); 947 if (NewVdata == AMDGPU::NoRegister) { 948 // It's possible to encode this such that the low register + enabled 949 // components exceeds the register count. 950 return MCDisassembler::Success; 951 } 952 } 953 954 // If not using NSA on GFX10+, widen vaddr0 address register to correct size. 955 // If using partial NSA on GFX11+ widen last address register. 956 int VAddrSAIdx = IsPartialNSA ? (RsrcIdx - 1) : VAddr0Idx; 957 unsigned NewVAddrSA = AMDGPU::NoRegister; 958 if (STI.hasFeature(AMDGPU::FeatureNSAEncoding) && (!IsNSA || IsPartialNSA) && 959 AddrSize != Info->VAddrDwords) { 960 unsigned VAddrSA = MI.getOperand(VAddrSAIdx).getReg(); 961 unsigned VAddrSubSA = MRI.getSubReg(VAddrSA, AMDGPU::sub0); 962 VAddrSA = VAddrSubSA ? VAddrSubSA : VAddrSA; 963 964 auto AddrRCID = MCII->get(NewOpcode).operands()[VAddrSAIdx].RegClass; 965 NewVAddrSA = MRI.getMatchingSuperReg(VAddrSA, AMDGPU::sub0, 966 &MRI.getRegClass(AddrRCID)); 967 if (!NewVAddrSA) 968 return MCDisassembler::Success; 969 } 970 971 MI.setOpcode(NewOpcode); 972 973 if (NewVdata != AMDGPU::NoRegister) { 974 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 975 976 if (IsAtomic) { 977 // Atomic operations have an additional operand (a copy of data) 978 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 979 } 980 } 981 982 if (NewVAddrSA) { 983 MI.getOperand(VAddrSAIdx) = MCOperand::createReg(NewVAddrSA); 984 } else if (IsNSA) { 985 assert(AddrSize <= Info->VAddrDwords); 986 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 987 MI.begin() + VAddr0Idx + Info->VAddrDwords); 988 } 989 990 return MCDisassembler::Success; 991 } 992 993 // Opsel and neg bits are used in src_modifiers and standalone operands. Autogen 994 // decoder only adds to src_modifiers, so manually add the bits to the other 995 // operands. 996 DecodeStatus AMDGPUDisassembler::convertVOP3PDPPInst(MCInst &MI) const { 997 unsigned Opc = MI.getOpcode(); 998 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 999 auto Mods = collectVOPModifiers(MI, true); 1000 1001 if (MI.getNumOperands() < DescNumOps && 1002 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vdst_in)) 1003 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vdst_in); 1004 1005 if (MI.getNumOperands() < DescNumOps && 1006 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) 1007 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 1008 AMDGPU::OpName::op_sel); 1009 if (MI.getNumOperands() < DescNumOps && 1010 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel_hi)) 1011 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSelHi), 1012 AMDGPU::OpName::op_sel_hi); 1013 if (MI.getNumOperands() < DescNumOps && 1014 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_lo)) 1015 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegLo), 1016 AMDGPU::OpName::neg_lo); 1017 if (MI.getNumOperands() < DescNumOps && 1018 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_hi)) 1019 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegHi), 1020 AMDGPU::OpName::neg_hi); 1021 1022 return MCDisassembler::Success; 1023 } 1024 1025 // Create dummy old operand and insert optional operands 1026 DecodeStatus AMDGPUDisassembler::convertVOPCDPPInst(MCInst &MI) const { 1027 unsigned Opc = MI.getOpcode(); 1028 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1029 1030 if (MI.getNumOperands() < DescNumOps && 1031 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::old)) 1032 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 1033 1034 if (MI.getNumOperands() < DescNumOps && 1035 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) 1036 insertNamedMCOperand(MI, MCOperand::createImm(0), 1037 AMDGPU::OpName::src0_modifiers); 1038 1039 if (MI.getNumOperands() < DescNumOps && 1040 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers)) 1041 insertNamedMCOperand(MI, MCOperand::createImm(0), 1042 AMDGPU::OpName::src1_modifiers); 1043 return MCDisassembler::Success; 1044 } 1045 1046 DecodeStatus AMDGPUDisassembler::convertFMAanyK(MCInst &MI, 1047 int ImmLitIdx) const { 1048 assert(HasLiteral && "Should have decoded a literal"); 1049 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 1050 unsigned DescNumOps = Desc.getNumOperands(); 1051 insertNamedMCOperand(MI, MCOperand::createImm(Literal), 1052 AMDGPU::OpName::immDeferred); 1053 assert(DescNumOps == MI.getNumOperands()); 1054 for (unsigned I = 0; I < DescNumOps; ++I) { 1055 auto &Op = MI.getOperand(I); 1056 auto OpType = Desc.operands()[I].OperandType; 1057 bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED || 1058 OpType == AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED); 1059 if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST && 1060 IsDeferredOp) 1061 Op.setImm(Literal); 1062 } 1063 return MCDisassembler::Success; 1064 } 1065 1066 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 1067 return getContext().getRegisterInfo()-> 1068 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 1069 } 1070 1071 inline 1072 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 1073 const Twine& ErrMsg) const { 1074 *CommentStream << "Error: " + ErrMsg; 1075 1076 // ToDo: add support for error operands to MCInst.h 1077 // return MCOperand::createError(V); 1078 return MCOperand(); 1079 } 1080 1081 inline 1082 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 1083 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 1084 } 1085 1086 inline 1087 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 1088 unsigned Val) const { 1089 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 1090 if (Val >= RegCl.getNumRegs()) 1091 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 1092 ": unknown register " + Twine(Val)); 1093 return createRegOperand(RegCl.getRegister(Val)); 1094 } 1095 1096 inline 1097 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 1098 unsigned Val) const { 1099 // ToDo: SI/CI have 104 SGPRs, VI - 102 1100 // Valery: here we accepting as much as we can, let assembler sort it out 1101 int shift = 0; 1102 switch (SRegClassID) { 1103 case AMDGPU::SGPR_32RegClassID: 1104 case AMDGPU::TTMP_32RegClassID: 1105 break; 1106 case AMDGPU::SGPR_64RegClassID: 1107 case AMDGPU::TTMP_64RegClassID: 1108 shift = 1; 1109 break; 1110 case AMDGPU::SGPR_128RegClassID: 1111 case AMDGPU::TTMP_128RegClassID: 1112 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 1113 // this bundle? 1114 case AMDGPU::SGPR_256RegClassID: 1115 case AMDGPU::TTMP_256RegClassID: 1116 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 1117 // this bundle? 1118 case AMDGPU::SGPR_288RegClassID: 1119 case AMDGPU::TTMP_288RegClassID: 1120 case AMDGPU::SGPR_320RegClassID: 1121 case AMDGPU::TTMP_320RegClassID: 1122 case AMDGPU::SGPR_352RegClassID: 1123 case AMDGPU::TTMP_352RegClassID: 1124 case AMDGPU::SGPR_384RegClassID: 1125 case AMDGPU::TTMP_384RegClassID: 1126 case AMDGPU::SGPR_512RegClassID: 1127 case AMDGPU::TTMP_512RegClassID: 1128 shift = 2; 1129 break; 1130 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 1131 // this bundle? 1132 default: 1133 llvm_unreachable("unhandled register class"); 1134 } 1135 1136 if (Val % (1 << shift)) { 1137 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 1138 << ": scalar reg isn't aligned " << Val; 1139 } 1140 1141 return createRegOperand(SRegClassID, Val >> shift); 1142 } 1143 1144 // Decode Literals for insts which always have a literal in the encoding 1145 MCOperand 1146 AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const { 1147 if (HasLiteral) { 1148 assert( 1149 AMDGPU::hasVOPD(STI) && 1150 "Should only decode multiple kimm with VOPD, check VSrc operand types"); 1151 if (Literal != Val) 1152 return errOperand(Val, "More than one unique literal is illegal"); 1153 } 1154 HasLiteral = true; 1155 Literal = Val; 1156 return MCOperand::createImm(Literal); 1157 } 1158 1159 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { 1160 // For now all literal constants are supposed to be unsigned integer 1161 // ToDo: deal with signed/unsigned 64-bit integer constants 1162 // ToDo: deal with float/double constants 1163 if (!HasLiteral) { 1164 if (Bytes.size() < 4) { 1165 return errOperand(0, "cannot read literal, inst bytes left " + 1166 Twine(Bytes.size())); 1167 } 1168 HasLiteral = true; 1169 Literal = eatBytes<uint32_t>(Bytes); 1170 } 1171 return MCOperand::createImm(Literal); 1172 } 1173 1174 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 1175 using namespace AMDGPU::EncValues; 1176 1177 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 1178 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 1179 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 1180 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 1181 // Cast prevents negative overflow. 1182 } 1183 1184 static int64_t getInlineImmVal32(unsigned Imm) { 1185 switch (Imm) { 1186 case 240: 1187 return llvm::bit_cast<uint32_t>(0.5f); 1188 case 241: 1189 return llvm::bit_cast<uint32_t>(-0.5f); 1190 case 242: 1191 return llvm::bit_cast<uint32_t>(1.0f); 1192 case 243: 1193 return llvm::bit_cast<uint32_t>(-1.0f); 1194 case 244: 1195 return llvm::bit_cast<uint32_t>(2.0f); 1196 case 245: 1197 return llvm::bit_cast<uint32_t>(-2.0f); 1198 case 246: 1199 return llvm::bit_cast<uint32_t>(4.0f); 1200 case 247: 1201 return llvm::bit_cast<uint32_t>(-4.0f); 1202 case 248: // 1 / (2 * PI) 1203 return 0x3e22f983; 1204 default: 1205 llvm_unreachable("invalid fp inline imm"); 1206 } 1207 } 1208 1209 static int64_t getInlineImmVal64(unsigned Imm) { 1210 switch (Imm) { 1211 case 240: 1212 return llvm::bit_cast<uint64_t>(0.5); 1213 case 241: 1214 return llvm::bit_cast<uint64_t>(-0.5); 1215 case 242: 1216 return llvm::bit_cast<uint64_t>(1.0); 1217 case 243: 1218 return llvm::bit_cast<uint64_t>(-1.0); 1219 case 244: 1220 return llvm::bit_cast<uint64_t>(2.0); 1221 case 245: 1222 return llvm::bit_cast<uint64_t>(-2.0); 1223 case 246: 1224 return llvm::bit_cast<uint64_t>(4.0); 1225 case 247: 1226 return llvm::bit_cast<uint64_t>(-4.0); 1227 case 248: // 1 / (2 * PI) 1228 return 0x3fc45f306dc9c882; 1229 default: 1230 llvm_unreachable("invalid fp inline imm"); 1231 } 1232 } 1233 1234 static int64_t getInlineImmVal16(unsigned Imm) { 1235 switch (Imm) { 1236 case 240: 1237 return 0x3800; 1238 case 241: 1239 return 0xB800; 1240 case 242: 1241 return 0x3C00; 1242 case 243: 1243 return 0xBC00; 1244 case 244: 1245 return 0x4000; 1246 case 245: 1247 return 0xC000; 1248 case 246: 1249 return 0x4400; 1250 case 247: 1251 return 0xC400; 1252 case 248: // 1 / (2 * PI) 1253 return 0x3118; 1254 default: 1255 llvm_unreachable("invalid fp inline imm"); 1256 } 1257 } 1258 1259 MCOperand AMDGPUDisassembler::decodeFPImmed(unsigned ImmWidth, unsigned Imm) { 1260 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 1261 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 1262 1263 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 1264 // ImmWidth 0 is a default case where operand should not allow immediates. 1265 // Imm value is still decoded into 32 bit immediate operand, inst printer will 1266 // use it to print verbose error message. 1267 switch (ImmWidth) { 1268 case 0: 1269 case 32: 1270 return MCOperand::createImm(getInlineImmVal32(Imm)); 1271 case 64: 1272 return MCOperand::createImm(getInlineImmVal64(Imm)); 1273 case 16: 1274 return MCOperand::createImm(getInlineImmVal16(Imm)); 1275 default: 1276 llvm_unreachable("implement me"); 1277 } 1278 } 1279 1280 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 1281 using namespace AMDGPU; 1282 1283 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1284 switch (Width) { 1285 default: // fall 1286 case OPW32: 1287 case OPW16: 1288 case OPWV216: 1289 return VGPR_32RegClassID; 1290 case OPW64: 1291 case OPWV232: return VReg_64RegClassID; 1292 case OPW96: return VReg_96RegClassID; 1293 case OPW128: return VReg_128RegClassID; 1294 case OPW160: return VReg_160RegClassID; 1295 case OPW256: return VReg_256RegClassID; 1296 case OPW288: return VReg_288RegClassID; 1297 case OPW320: return VReg_320RegClassID; 1298 case OPW352: return VReg_352RegClassID; 1299 case OPW384: return VReg_384RegClassID; 1300 case OPW512: return VReg_512RegClassID; 1301 case OPW1024: return VReg_1024RegClassID; 1302 } 1303 } 1304 1305 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 1306 using namespace AMDGPU; 1307 1308 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1309 switch (Width) { 1310 default: // fall 1311 case OPW32: 1312 case OPW16: 1313 case OPWV216: 1314 return AGPR_32RegClassID; 1315 case OPW64: 1316 case OPWV232: return AReg_64RegClassID; 1317 case OPW96: return AReg_96RegClassID; 1318 case OPW128: return AReg_128RegClassID; 1319 case OPW160: return AReg_160RegClassID; 1320 case OPW256: return AReg_256RegClassID; 1321 case OPW288: return AReg_288RegClassID; 1322 case OPW320: return AReg_320RegClassID; 1323 case OPW352: return AReg_352RegClassID; 1324 case OPW384: return AReg_384RegClassID; 1325 case OPW512: return AReg_512RegClassID; 1326 case OPW1024: return AReg_1024RegClassID; 1327 } 1328 } 1329 1330 1331 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 1332 using namespace AMDGPU; 1333 1334 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1335 switch (Width) { 1336 default: // fall 1337 case OPW32: 1338 case OPW16: 1339 case OPWV216: 1340 return SGPR_32RegClassID; 1341 case OPW64: 1342 case OPWV232: return SGPR_64RegClassID; 1343 case OPW96: return SGPR_96RegClassID; 1344 case OPW128: return SGPR_128RegClassID; 1345 case OPW160: return SGPR_160RegClassID; 1346 case OPW256: return SGPR_256RegClassID; 1347 case OPW288: return SGPR_288RegClassID; 1348 case OPW320: return SGPR_320RegClassID; 1349 case OPW352: return SGPR_352RegClassID; 1350 case OPW384: return SGPR_384RegClassID; 1351 case OPW512: return SGPR_512RegClassID; 1352 } 1353 } 1354 1355 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 1356 using namespace AMDGPU; 1357 1358 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1359 switch (Width) { 1360 default: // fall 1361 case OPW32: 1362 case OPW16: 1363 case OPWV216: 1364 return TTMP_32RegClassID; 1365 case OPW64: 1366 case OPWV232: return TTMP_64RegClassID; 1367 case OPW128: return TTMP_128RegClassID; 1368 case OPW256: return TTMP_256RegClassID; 1369 case OPW288: return TTMP_288RegClassID; 1370 case OPW320: return TTMP_320RegClassID; 1371 case OPW352: return TTMP_352RegClassID; 1372 case OPW384: return TTMP_384RegClassID; 1373 case OPW512: return TTMP_512RegClassID; 1374 } 1375 } 1376 1377 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 1378 using namespace AMDGPU::EncValues; 1379 1380 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN; 1381 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX; 1382 1383 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1384 } 1385 1386 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val, 1387 bool MandatoryLiteral, 1388 unsigned ImmWidth) const { 1389 using namespace AMDGPU::EncValues; 1390 1391 assert(Val < 1024); // enum10 1392 1393 bool IsAGPR = Val & 512; 1394 Val &= 511; 1395 1396 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1397 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1398 : getVgprClassId(Width), Val - VGPR_MIN); 1399 } 1400 if (Val <= SGPR_MAX) { 1401 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1402 static_assert(SGPR_MIN == 0); 1403 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1404 } 1405 1406 int TTmpIdx = getTTmpIdx(Val); 1407 if (TTmpIdx >= 0) { 1408 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1409 } 1410 1411 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1412 return decodeIntImmed(Val); 1413 1414 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1415 return decodeFPImmed(ImmWidth, Val); 1416 1417 if (Val == LITERAL_CONST) { 1418 if (MandatoryLiteral) 1419 // Keep a sentinel value for deferred setting 1420 return MCOperand::createImm(LITERAL_CONST); 1421 else 1422 return decodeLiteralConstant(); 1423 } 1424 1425 switch (Width) { 1426 case OPW32: 1427 case OPW16: 1428 case OPWV216: 1429 return decodeSpecialReg32(Val); 1430 case OPW64: 1431 case OPWV232: 1432 return decodeSpecialReg64(Val); 1433 default: 1434 llvm_unreachable("unexpected immediate type"); 1435 } 1436 } 1437 1438 // Bit 0 of DstY isn't stored in the instruction, because it's always the 1439 // opposite of bit 0 of DstX. 1440 MCOperand AMDGPUDisassembler::decodeVOPDDstYOp(MCInst &Inst, 1441 unsigned Val) const { 1442 int VDstXInd = 1443 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::vdstX); 1444 assert(VDstXInd != -1); 1445 assert(Inst.getOperand(VDstXInd).isReg()); 1446 unsigned XDstReg = MRI.getEncodingValue(Inst.getOperand(VDstXInd).getReg()); 1447 Val |= ~XDstReg & 1; 1448 auto Width = llvm::AMDGPUDisassembler::OPW32; 1449 return createRegOperand(getVgprClassId(Width), Val); 1450 } 1451 1452 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1453 using namespace AMDGPU; 1454 1455 switch (Val) { 1456 // clang-format off 1457 case 102: return createRegOperand(FLAT_SCR_LO); 1458 case 103: return createRegOperand(FLAT_SCR_HI); 1459 case 104: return createRegOperand(XNACK_MASK_LO); 1460 case 105: return createRegOperand(XNACK_MASK_HI); 1461 case 106: return createRegOperand(VCC_LO); 1462 case 107: return createRegOperand(VCC_HI); 1463 case 108: return createRegOperand(TBA_LO); 1464 case 109: return createRegOperand(TBA_HI); 1465 case 110: return createRegOperand(TMA_LO); 1466 case 111: return createRegOperand(TMA_HI); 1467 case 124: 1468 return isGFX11Plus() ? createRegOperand(SGPR_NULL) : createRegOperand(M0); 1469 case 125: 1470 return isGFX11Plus() ? createRegOperand(M0) : createRegOperand(SGPR_NULL); 1471 case 126: return createRegOperand(EXEC_LO); 1472 case 127: return createRegOperand(EXEC_HI); 1473 case 235: return createRegOperand(SRC_SHARED_BASE_LO); 1474 case 236: return createRegOperand(SRC_SHARED_LIMIT_LO); 1475 case 237: return createRegOperand(SRC_PRIVATE_BASE_LO); 1476 case 238: return createRegOperand(SRC_PRIVATE_LIMIT_LO); 1477 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1478 case 251: return createRegOperand(SRC_VCCZ); 1479 case 252: return createRegOperand(SRC_EXECZ); 1480 case 253: return createRegOperand(SRC_SCC); 1481 case 254: return createRegOperand(LDS_DIRECT); 1482 default: break; 1483 // clang-format on 1484 } 1485 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1486 } 1487 1488 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1489 using namespace AMDGPU; 1490 1491 switch (Val) { 1492 case 102: return createRegOperand(FLAT_SCR); 1493 case 104: return createRegOperand(XNACK_MASK); 1494 case 106: return createRegOperand(VCC); 1495 case 108: return createRegOperand(TBA); 1496 case 110: return createRegOperand(TMA); 1497 case 124: 1498 if (isGFX11Plus()) 1499 return createRegOperand(SGPR_NULL); 1500 break; 1501 case 125: 1502 if (!isGFX11Plus()) 1503 return createRegOperand(SGPR_NULL); 1504 break; 1505 case 126: return createRegOperand(EXEC); 1506 case 235: return createRegOperand(SRC_SHARED_BASE); 1507 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1508 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1509 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1510 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1511 case 251: return createRegOperand(SRC_VCCZ); 1512 case 252: return createRegOperand(SRC_EXECZ); 1513 case 253: return createRegOperand(SRC_SCC); 1514 default: break; 1515 } 1516 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1517 } 1518 1519 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 1520 const unsigned Val, 1521 unsigned ImmWidth) const { 1522 using namespace AMDGPU::SDWA; 1523 using namespace AMDGPU::EncValues; 1524 1525 if (STI.hasFeature(AMDGPU::FeatureGFX9) || 1526 STI.hasFeature(AMDGPU::FeatureGFX10)) { 1527 // XXX: cast to int is needed to avoid stupid warning: 1528 // compare with unsigned is always true 1529 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1530 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1531 return createRegOperand(getVgprClassId(Width), 1532 Val - SDWA9EncValues::SRC_VGPR_MIN); 1533 } 1534 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1535 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1536 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1537 return createSRegOperand(getSgprClassId(Width), 1538 Val - SDWA9EncValues::SRC_SGPR_MIN); 1539 } 1540 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1541 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1542 return createSRegOperand(getTtmpClassId(Width), 1543 Val - SDWA9EncValues::SRC_TTMP_MIN); 1544 } 1545 1546 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1547 1548 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1549 return decodeIntImmed(SVal); 1550 1551 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1552 return decodeFPImmed(ImmWidth, SVal); 1553 1554 return decodeSpecialReg32(SVal); 1555 } else if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) { 1556 return createRegOperand(getVgprClassId(Width), Val); 1557 } 1558 llvm_unreachable("unsupported target"); 1559 } 1560 1561 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1562 return decodeSDWASrc(OPW16, Val, 16); 1563 } 1564 1565 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1566 return decodeSDWASrc(OPW32, Val, 32); 1567 } 1568 1569 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1570 using namespace AMDGPU::SDWA; 1571 1572 assert((STI.hasFeature(AMDGPU::FeatureGFX9) || 1573 STI.hasFeature(AMDGPU::FeatureGFX10)) && 1574 "SDWAVopcDst should be present only on GFX9+"); 1575 1576 bool IsWave64 = STI.hasFeature(AMDGPU::FeatureWavefrontSize64); 1577 1578 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1579 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1580 1581 int TTmpIdx = getTTmpIdx(Val); 1582 if (TTmpIdx >= 0) { 1583 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1584 return createSRegOperand(TTmpClsId, TTmpIdx); 1585 } else if (Val > SGPR_MAX) { 1586 return IsWave64 ? decodeSpecialReg64(Val) 1587 : decodeSpecialReg32(Val); 1588 } else { 1589 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1590 } 1591 } else { 1592 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1593 } 1594 } 1595 1596 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1597 return STI.hasFeature(AMDGPU::FeatureWavefrontSize64) 1598 ? decodeSrcOp(OPW64, Val) 1599 : decodeSrcOp(OPW32, Val); 1600 } 1601 1602 bool AMDGPUDisassembler::isVI() const { 1603 return STI.hasFeature(AMDGPU::FeatureVolcanicIslands); 1604 } 1605 1606 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } 1607 1608 bool AMDGPUDisassembler::isGFX90A() const { 1609 return STI.hasFeature(AMDGPU::FeatureGFX90AInsts); 1610 } 1611 1612 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } 1613 1614 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } 1615 1616 bool AMDGPUDisassembler::isGFX10Plus() const { 1617 return AMDGPU::isGFX10Plus(STI); 1618 } 1619 1620 bool AMDGPUDisassembler::isGFX11() const { 1621 return STI.hasFeature(AMDGPU::FeatureGFX11); 1622 } 1623 1624 bool AMDGPUDisassembler::isGFX11Plus() const { 1625 return AMDGPU::isGFX11Plus(STI); 1626 } 1627 1628 1629 bool AMDGPUDisassembler::hasArchitectedFlatScratch() const { 1630 return STI.hasFeature(AMDGPU::FeatureArchitectedFlatScratch); 1631 } 1632 1633 bool AMDGPUDisassembler::hasKernargPreload() const { 1634 return AMDGPU::hasKernargPreload(STI); 1635 } 1636 1637 //===----------------------------------------------------------------------===// 1638 // AMDGPU specific symbol handling 1639 //===----------------------------------------------------------------------===// 1640 #define GET_FIELD(MASK) (AMDHSA_BITS_GET(FourByteBuffer, MASK)) 1641 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1642 do { \ 1643 KdStream << Indent << DIRECTIVE " " << GET_FIELD(MASK) << '\n'; \ 1644 } while (0) 1645 #define PRINT_PSEUDO_DIRECTIVE_COMMENT(DIRECTIVE, MASK) \ 1646 do { \ 1647 KdStream << Indent << MAI.getCommentString() << ' ' << DIRECTIVE " " \ 1648 << GET_FIELD(MASK) << '\n'; \ 1649 } while (0) 1650 1651 // NOLINTNEXTLINE(readability-identifier-naming) 1652 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1653 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1654 using namespace amdhsa; 1655 StringRef Indent = "\t"; 1656 1657 // We cannot accurately backward compute #VGPRs used from 1658 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1659 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1660 // simply calculate the inverse of what the assembler does. 1661 1662 uint32_t GranulatedWorkitemVGPRCount = 1663 GET_FIELD(COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT); 1664 1665 uint32_t NextFreeVGPR = 1666 (GranulatedWorkitemVGPRCount + 1) * 1667 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI, EnableWavefrontSize32); 1668 1669 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1670 1671 // We cannot backward compute values used to calculate 1672 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1673 // directives can't be computed: 1674 // .amdhsa_reserve_vcc 1675 // .amdhsa_reserve_flat_scratch 1676 // .amdhsa_reserve_xnack_mask 1677 // They take their respective default values if not specified in the assembly. 1678 // 1679 // GRANULATED_WAVEFRONT_SGPR_COUNT 1680 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1681 // 1682 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1683 // are set to 0. So while disassembling we consider that: 1684 // 1685 // GRANULATED_WAVEFRONT_SGPR_COUNT 1686 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1687 // 1688 // The disassembler cannot recover the original values of those 3 directives. 1689 1690 uint32_t GranulatedWavefrontSGPRCount = 1691 GET_FIELD(COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT); 1692 1693 if (isGFX10Plus() && GranulatedWavefrontSGPRCount) 1694 return MCDisassembler::Fail; 1695 1696 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1697 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1698 1699 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1700 if (!hasArchitectedFlatScratch()) 1701 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1702 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1703 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1704 1705 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY) 1706 return MCDisassembler::Fail; 1707 1708 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1709 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1710 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1711 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1712 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1713 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1714 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1715 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1716 1717 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) 1718 return MCDisassembler::Fail; 1719 1720 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 1721 1722 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) 1723 return MCDisassembler::Fail; 1724 1725 PRINT_DIRECTIVE(".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 1726 1727 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) 1728 return MCDisassembler::Fail; 1729 1730 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER) 1731 return MCDisassembler::Fail; 1732 1733 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_FP16_OVFL); 1734 1735 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED0) 1736 return MCDisassembler::Fail; 1737 1738 if (isGFX10Plus()) { 1739 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1740 COMPUTE_PGM_RSRC1_WGP_MODE); 1741 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_MEM_ORDERED); 1742 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_FWD_PROGRESS); 1743 } 1744 return MCDisassembler::Success; 1745 } 1746 1747 // NOLINTNEXTLINE(readability-identifier-naming) 1748 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 1749 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1750 using namespace amdhsa; 1751 StringRef Indent = "\t"; 1752 if (hasArchitectedFlatScratch()) 1753 PRINT_DIRECTIVE(".amdhsa_enable_private_segment", 1754 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1755 else 1756 PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset", 1757 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1758 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 1759 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 1760 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 1761 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 1762 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 1763 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 1764 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 1765 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 1766 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 1767 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 1768 1769 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH) 1770 return MCDisassembler::Fail; 1771 1772 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY) 1773 return MCDisassembler::Fail; 1774 1775 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE) 1776 return MCDisassembler::Fail; 1777 1778 PRINT_DIRECTIVE( 1779 ".amdhsa_exception_fp_ieee_invalid_op", 1780 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 1781 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 1782 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 1783 PRINT_DIRECTIVE( 1784 ".amdhsa_exception_fp_ieee_div_zero", 1785 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 1786 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 1787 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 1788 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 1789 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 1790 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 1791 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 1792 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 1793 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 1794 1795 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0) 1796 return MCDisassembler::Fail; 1797 1798 return MCDisassembler::Success; 1799 } 1800 1801 // NOLINTNEXTLINE(readability-identifier-naming) 1802 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC3( 1803 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1804 using namespace amdhsa; 1805 StringRef Indent = "\t"; 1806 if (isGFX90A()) { 1807 KdStream << Indent << ".amdhsa_accum_offset " 1808 << (GET_FIELD(COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET) + 1) * 4 1809 << '\n'; 1810 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX90A_RESERVED0) 1811 return MCDisassembler::Fail; 1812 PRINT_DIRECTIVE(".amdhsa_tg_split", COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT); 1813 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX90A_RESERVED1) 1814 return MCDisassembler::Fail; 1815 } else if (isGFX10Plus()) { 1816 if (!EnableWavefrontSize32 || !*EnableWavefrontSize32) { 1817 PRINT_DIRECTIVE(".amdhsa_shared_vgpr_count", 1818 COMPUTE_PGM_RSRC3_GFX10_PLUS_SHARED_VGPR_COUNT); 1819 } else { 1820 PRINT_PSEUDO_DIRECTIVE_COMMENT( 1821 "SHARED_VGPR_COUNT", COMPUTE_PGM_RSRC3_GFX10_PLUS_SHARED_VGPR_COUNT); 1822 } 1823 PRINT_PSEUDO_DIRECTIVE_COMMENT("INST_PREF_SIZE", 1824 COMPUTE_PGM_RSRC3_GFX10_PLUS_INST_PREF_SIZE); 1825 PRINT_PSEUDO_DIRECTIVE_COMMENT("TRAP_ON_START", 1826 COMPUTE_PGM_RSRC3_GFX10_PLUS_TRAP_ON_START); 1827 PRINT_PSEUDO_DIRECTIVE_COMMENT("TRAP_ON_END", 1828 COMPUTE_PGM_RSRC3_GFX10_PLUS_TRAP_ON_END); 1829 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_PLUS_RESERVED0) 1830 return MCDisassembler::Fail; 1831 PRINT_PSEUDO_DIRECTIVE_COMMENT("IMAGE_OP", 1832 COMPUTE_PGM_RSRC3_GFX10_PLUS_TRAP_ON_START); 1833 } else if (FourByteBuffer) { 1834 return MCDisassembler::Fail; 1835 } 1836 return MCDisassembler::Success; 1837 } 1838 #undef PRINT_PSEUDO_DIRECTIVE_COMMENT 1839 #undef PRINT_DIRECTIVE 1840 #undef GET_FIELD 1841 1842 MCDisassembler::DecodeStatus 1843 AMDGPUDisassembler::decodeKernelDescriptorDirective( 1844 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 1845 raw_string_ostream &KdStream) const { 1846 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1847 do { \ 1848 KdStream << Indent << DIRECTIVE " " \ 1849 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1850 } while (0) 1851 1852 uint16_t TwoByteBuffer = 0; 1853 uint32_t FourByteBuffer = 0; 1854 1855 StringRef ReservedBytes; 1856 StringRef Indent = "\t"; 1857 1858 assert(Bytes.size() == 64); 1859 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 1860 1861 switch (Cursor.tell()) { 1862 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 1863 FourByteBuffer = DE.getU32(Cursor); 1864 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 1865 << '\n'; 1866 return MCDisassembler::Success; 1867 1868 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 1869 FourByteBuffer = DE.getU32(Cursor); 1870 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 1871 << FourByteBuffer << '\n'; 1872 return MCDisassembler::Success; 1873 1874 case amdhsa::KERNARG_SIZE_OFFSET: 1875 FourByteBuffer = DE.getU32(Cursor); 1876 KdStream << Indent << ".amdhsa_kernarg_size " 1877 << FourByteBuffer << '\n'; 1878 return MCDisassembler::Success; 1879 1880 case amdhsa::RESERVED0_OFFSET: 1881 // 4 reserved bytes, must be 0. 1882 ReservedBytes = DE.getBytes(Cursor, 4); 1883 for (int I = 0; I < 4; ++I) { 1884 if (ReservedBytes[I] != 0) { 1885 return MCDisassembler::Fail; 1886 } 1887 } 1888 return MCDisassembler::Success; 1889 1890 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 1891 // KERNEL_CODE_ENTRY_BYTE_OFFSET 1892 // So far no directive controls this for Code Object V3, so simply skip for 1893 // disassembly. 1894 DE.skip(Cursor, 8); 1895 return MCDisassembler::Success; 1896 1897 case amdhsa::RESERVED1_OFFSET: 1898 // 20 reserved bytes, must be 0. 1899 ReservedBytes = DE.getBytes(Cursor, 20); 1900 for (int I = 0; I < 20; ++I) { 1901 if (ReservedBytes[I] != 0) { 1902 return MCDisassembler::Fail; 1903 } 1904 } 1905 return MCDisassembler::Success; 1906 1907 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 1908 FourByteBuffer = DE.getU32(Cursor); 1909 return decodeCOMPUTE_PGM_RSRC3(FourByteBuffer, KdStream); 1910 1911 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 1912 FourByteBuffer = DE.getU32(Cursor); 1913 return decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream); 1914 1915 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 1916 FourByteBuffer = DE.getU32(Cursor); 1917 return decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream); 1918 1919 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 1920 using namespace amdhsa; 1921 TwoByteBuffer = DE.getU16(Cursor); 1922 1923 if (!hasArchitectedFlatScratch()) 1924 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 1925 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 1926 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 1927 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 1928 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 1929 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 1930 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 1931 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 1932 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 1933 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 1934 if (!hasArchitectedFlatScratch()) 1935 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 1936 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 1937 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 1938 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 1939 1940 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 1941 return MCDisassembler::Fail; 1942 1943 // Reserved for GFX9 1944 if (isGFX9() && 1945 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 1946 return MCDisassembler::Fail; 1947 } else if (isGFX10Plus()) { 1948 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 1949 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 1950 } 1951 1952 if (AMDGPU::getAmdhsaCodeObjectVersion() >= AMDGPU::AMDHSA_COV5) 1953 PRINT_DIRECTIVE(".amdhsa_uses_dynamic_stack", 1954 KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK); 1955 1956 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) 1957 return MCDisassembler::Fail; 1958 1959 return MCDisassembler::Success; 1960 1961 case amdhsa::KERNARG_PRELOAD_OFFSET: 1962 using namespace amdhsa; 1963 TwoByteBuffer = DE.getU16(Cursor); 1964 if (TwoByteBuffer & KERNARG_PRELOAD_SPEC_LENGTH) { 1965 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_preload_length", 1966 KERNARG_PRELOAD_SPEC_LENGTH); 1967 } 1968 1969 if (TwoByteBuffer & KERNARG_PRELOAD_SPEC_OFFSET) { 1970 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_preload_offset", 1971 KERNARG_PRELOAD_SPEC_OFFSET); 1972 } 1973 return MCDisassembler::Success; 1974 1975 case amdhsa::RESERVED3_OFFSET: 1976 // 4 bytes from here are reserved, must be 0. 1977 ReservedBytes = DE.getBytes(Cursor, 4); 1978 for (int I = 0; I < 4; ++I) { 1979 if (ReservedBytes[I] != 0) 1980 return MCDisassembler::Fail; 1981 } 1982 return MCDisassembler::Success; 1983 1984 default: 1985 llvm_unreachable("Unhandled index. Case statements cover everything."); 1986 return MCDisassembler::Fail; 1987 } 1988 #undef PRINT_DIRECTIVE 1989 } 1990 1991 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( 1992 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 1993 // CP microcode requires the kernel descriptor to be 64 aligned. 1994 if (Bytes.size() != 64 || KdAddress % 64 != 0) 1995 return MCDisassembler::Fail; 1996 1997 // FIXME: We can't actually decode "in order" as is done below, as e.g. GFX10 1998 // requires us to know the setting of .amdhsa_wavefront_size32 in order to 1999 // accurately produce .amdhsa_next_free_vgpr, and they appear in the wrong 2000 // order. Workaround this by first looking up .amdhsa_wavefront_size32 here 2001 // when required. 2002 if (isGFX10Plus()) { 2003 uint16_t KernelCodeProperties = 2004 support::endian::read16(&Bytes[amdhsa::KERNEL_CODE_PROPERTIES_OFFSET], 2005 support::endianness::little); 2006 EnableWavefrontSize32 = 2007 AMDHSA_BITS_GET(KernelCodeProperties, 2008 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 2009 } 2010 2011 std::string Kd; 2012 raw_string_ostream KdStream(Kd); 2013 KdStream << ".amdhsa_kernel " << KdName << '\n'; 2014 2015 DataExtractor::Cursor C(0); 2016 while (C && C.tell() < Bytes.size()) { 2017 MCDisassembler::DecodeStatus Status = 2018 decodeKernelDescriptorDirective(C, Bytes, KdStream); 2019 2020 cantFail(C.takeError()); 2021 2022 if (Status == MCDisassembler::Fail) 2023 return MCDisassembler::Fail; 2024 } 2025 KdStream << ".end_amdhsa_kernel\n"; 2026 outs() << KdStream.str(); 2027 return MCDisassembler::Success; 2028 } 2029 2030 std::optional<MCDisassembler::DecodeStatus> 2031 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 2032 ArrayRef<uint8_t> Bytes, uint64_t Address, 2033 raw_ostream &CStream) const { 2034 // Right now only kernel descriptor needs to be handled. 2035 // We ignore all other symbols for target specific handling. 2036 // TODO: 2037 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 2038 // Object V2 and V3 when symbols are marked protected. 2039 2040 // amd_kernel_code_t for Code Object V2. 2041 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 2042 Size = 256; 2043 return MCDisassembler::Fail; 2044 } 2045 2046 // Code Object V3 kernel descriptors. 2047 StringRef Name = Symbol.Name; 2048 if (Symbol.Type == ELF::STT_OBJECT && Name.endswith(StringRef(".kd"))) { 2049 Size = 64; // Size = 64 regardless of success or failure. 2050 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 2051 } 2052 return std::nullopt; 2053 } 2054 2055 //===----------------------------------------------------------------------===// 2056 // AMDGPUSymbolizer 2057 //===----------------------------------------------------------------------===// 2058 2059 // Try to find symbol name for specified label 2060 bool AMDGPUSymbolizer::tryAddingSymbolicOperand( 2061 MCInst &Inst, raw_ostream & /*cStream*/, int64_t Value, 2062 uint64_t /*Address*/, bool IsBranch, uint64_t /*Offset*/, 2063 uint64_t /*OpSize*/, uint64_t /*InstSize*/) { 2064 2065 if (!IsBranch) { 2066 return false; 2067 } 2068 2069 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 2070 if (!Symbols) 2071 return false; 2072 2073 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { 2074 return Val.Addr == static_cast<uint64_t>(Value) && 2075 Val.Type == ELF::STT_NOTYPE; 2076 }); 2077 if (Result != Symbols->end()) { 2078 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 2079 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 2080 Inst.addOperand(MCOperand::createExpr(Add)); 2081 return true; 2082 } 2083 // Add to list of referenced addresses, so caller can synthesize a label. 2084 ReferencedAddresses.push_back(static_cast<uint64_t>(Value)); 2085 return false; 2086 } 2087 2088 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 2089 int64_t Value, 2090 uint64_t Address) { 2091 llvm_unreachable("unimplemented"); 2092 } 2093 2094 //===----------------------------------------------------------------------===// 2095 // Initialization 2096 //===----------------------------------------------------------------------===// 2097 2098 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 2099 LLVMOpInfoCallback /*GetOpInfo*/, 2100 LLVMSymbolLookupCallback /*SymbolLookUp*/, 2101 void *DisInfo, 2102 MCContext *Ctx, 2103 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 2104 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 2105 } 2106 2107 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 2108 const MCSubtargetInfo &STI, 2109 MCContext &Ctx) { 2110 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 2111 } 2112 2113 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 2114 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 2115 createAMDGPUDisassembler); 2116 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 2117 createAMDGPUSymbolizer); 2118 } 2119