1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "AMDGPU.h" 21 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 22 #include "SIDefines.h" 23 #include "TargetInfo/AMDGPUTargetInfo.h" 24 #include "Utils/AMDGPUBaseInfo.h" 25 #include "llvm-c/Disassembler.h" 26 #include "llvm/ADT/APInt.h" 27 #include "llvm/ADT/ArrayRef.h" 28 #include "llvm/ADT/Twine.h" 29 #include "llvm/BinaryFormat/ELF.h" 30 #include "llvm/MC/MCAsmInfo.h" 31 #include "llvm/MC/MCContext.h" 32 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 33 #include "llvm/MC/MCExpr.h" 34 #include "llvm/MC/MCFixedLenDisassembler.h" 35 #include "llvm/MC/MCInst.h" 36 #include "llvm/MC/MCSubtargetInfo.h" 37 #include "llvm/Support/AMDHSAKernelDescriptor.h" 38 #include "llvm/Support/Endian.h" 39 #include "llvm/Support/ErrorHandling.h" 40 #include "llvm/Support/MathExtras.h" 41 #include "llvm/Support/TargetRegistry.h" 42 #include "llvm/Support/raw_ostream.h" 43 #include <algorithm> 44 #include <cassert> 45 #include <cstddef> 46 #include <cstdint> 47 #include <iterator> 48 #include <tuple> 49 #include <vector> 50 51 using namespace llvm; 52 53 #define DEBUG_TYPE "amdgpu-disassembler" 54 55 #define SGPR_MAX (isGFX10() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 56 : AMDGPU::EncValues::SGPR_MAX_SI) 57 58 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 59 60 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 61 MCContext &Ctx, 62 MCInstrInfo const *MCII) : 63 MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), 64 TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) { 65 66 // ToDo: AMDGPUDisassembler supports only VI ISA. 67 if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10()) 68 report_fatal_error("Disassembly not yet supported for subtarget"); 69 } 70 71 inline static MCDisassembler::DecodeStatus 72 addOperand(MCInst &Inst, const MCOperand& Opnd) { 73 Inst.addOperand(Opnd); 74 return Opnd.isValid() ? 75 MCDisassembler::Success : 76 MCDisassembler::Fail; 77 } 78 79 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 80 uint16_t NameIdx) { 81 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 82 if (OpIdx != -1) { 83 auto I = MI.begin(); 84 std::advance(I, OpIdx); 85 MI.insert(I, Op); 86 } 87 return OpIdx; 88 } 89 90 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, 91 uint64_t Addr, const void *Decoder) { 92 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 93 94 // Our branches take a simm16, but we need two extra bits to account for the 95 // factor of 4. 96 APInt SignedOffset(18, Imm * 4, true); 97 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 98 99 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2)) 100 return MCDisassembler::Success; 101 return addOperand(Inst, MCOperand::createImm(Imm)); 102 } 103 104 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, 105 uint64_t Addr, const void *Decoder) { 106 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 107 int64_t Offset; 108 if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 109 Offset = Imm & 0xFFFFF; 110 } else { // GFX9+ supports 21-bit signed offsets. 111 Offset = SignExtend64<21>(Imm); 112 } 113 return addOperand(Inst, MCOperand::createImm(Offset)); 114 } 115 116 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, 117 uint64_t Addr, const void *Decoder) { 118 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 119 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 120 } 121 122 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 123 static DecodeStatus StaticDecoderName(MCInst &Inst, \ 124 unsigned Imm, \ 125 uint64_t /*Addr*/, \ 126 const void *Decoder) { \ 127 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \ 128 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 129 } 130 131 #define DECODE_OPERAND_REG(RegClass) \ 132 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass) 133 134 DECODE_OPERAND_REG(VGPR_32) 135 DECODE_OPERAND_REG(VRegOrLds_32) 136 DECODE_OPERAND_REG(VS_32) 137 DECODE_OPERAND_REG(VS_64) 138 DECODE_OPERAND_REG(VS_128) 139 140 DECODE_OPERAND_REG(VReg_64) 141 DECODE_OPERAND_REG(VReg_96) 142 DECODE_OPERAND_REG(VReg_128) 143 DECODE_OPERAND_REG(VReg_256) 144 DECODE_OPERAND_REG(VReg_512) 145 146 DECODE_OPERAND_REG(SReg_32) 147 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC) 148 DECODE_OPERAND_REG(SReg_32_XEXEC_HI) 149 DECODE_OPERAND_REG(SRegOrLds_32) 150 DECODE_OPERAND_REG(SReg_64) 151 DECODE_OPERAND_REG(SReg_64_XEXEC) 152 DECODE_OPERAND_REG(SReg_128) 153 DECODE_OPERAND_REG(SReg_256) 154 DECODE_OPERAND_REG(SReg_512) 155 156 DECODE_OPERAND_REG(AGPR_32) 157 DECODE_OPERAND_REG(AReg_128) 158 DECODE_OPERAND_REG(AReg_512) 159 DECODE_OPERAND_REG(AReg_1024) 160 DECODE_OPERAND_REG(AV_32) 161 DECODE_OPERAND_REG(AV_64) 162 163 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, 164 unsigned Imm, 165 uint64_t Addr, 166 const void *Decoder) { 167 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 168 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 169 } 170 171 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, 172 unsigned Imm, 173 uint64_t Addr, 174 const void *Decoder) { 175 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 176 return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm)); 177 } 178 179 static DecodeStatus decodeOperand_VS_16(MCInst &Inst, 180 unsigned Imm, 181 uint64_t Addr, 182 const void *Decoder) { 183 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 184 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 185 } 186 187 static DecodeStatus decodeOperand_VS_32(MCInst &Inst, 188 unsigned Imm, 189 uint64_t Addr, 190 const void *Decoder) { 191 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 192 return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm)); 193 } 194 195 static DecodeStatus decodeOperand_AReg_128(MCInst &Inst, 196 unsigned Imm, 197 uint64_t Addr, 198 const void *Decoder) { 199 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 200 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512)); 201 } 202 203 static DecodeStatus decodeOperand_AReg_512(MCInst &Inst, 204 unsigned Imm, 205 uint64_t Addr, 206 const void *Decoder) { 207 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 208 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512)); 209 } 210 211 static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst, 212 unsigned Imm, 213 uint64_t Addr, 214 const void *Decoder) { 215 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 216 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512)); 217 } 218 219 static DecodeStatus decodeOperand_SReg_32(MCInst &Inst, 220 unsigned Imm, 221 uint64_t Addr, 222 const void *Decoder) { 223 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 224 return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm)); 225 } 226 227 static DecodeStatus decodeOperand_VGPR_32(MCInst &Inst, 228 unsigned Imm, 229 uint64_t Addr, 230 const void *Decoder) { 231 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 232 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW32, Imm)); 233 } 234 235 #define DECODE_SDWA(DecName) \ 236 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 237 238 DECODE_SDWA(Src32) 239 DECODE_SDWA(Src16) 240 DECODE_SDWA(VopcDst) 241 242 #include "AMDGPUGenDisassemblerTables.inc" 243 244 //===----------------------------------------------------------------------===// 245 // 246 //===----------------------------------------------------------------------===// 247 248 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 249 assert(Bytes.size() >= sizeof(T)); 250 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data()); 251 Bytes = Bytes.slice(sizeof(T)); 252 return Res; 253 } 254 255 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table, 256 MCInst &MI, 257 uint64_t Inst, 258 uint64_t Address) const { 259 assert(MI.getOpcode() == 0); 260 assert(MI.getNumOperands() == 0); 261 MCInst TmpInst; 262 HasLiteral = false; 263 const auto SavedBytes = Bytes; 264 if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) { 265 MI = TmpInst; 266 return MCDisassembler::Success; 267 } 268 Bytes = SavedBytes; 269 return MCDisassembler::Fail; 270 } 271 272 static bool isValidDPP8(const MCInst &MI) { 273 using namespace llvm::AMDGPU::DPP; 274 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi); 275 assert(FiIdx != -1); 276 if ((unsigned)FiIdx >= MI.getNumOperands()) 277 return false; 278 unsigned Fi = MI.getOperand(FiIdx).getImm(); 279 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1; 280 } 281 282 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 283 ArrayRef<uint8_t> Bytes_, 284 uint64_t Address, 285 raw_ostream &CS) const { 286 CommentStream = &CS; 287 bool IsSDWA = false; 288 289 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 290 Bytes = Bytes_.slice(0, MaxInstBytesNum); 291 292 DecodeStatus Res = MCDisassembler::Fail; 293 do { 294 // ToDo: better to switch encoding length using some bit predicate 295 // but it is unknown yet, so try all we can 296 297 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 298 // encodings 299 if (Bytes.size() >= 8) { 300 const uint64_t QW = eatBytes<uint64_t>(Bytes); 301 302 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 303 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address); 304 if (Res) { 305 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) 306 == -1) 307 break; 308 if (convertDPP8Inst(MI) == MCDisassembler::Success) 309 break; 310 MI = MCInst(); // clear 311 } 312 } 313 314 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address); 315 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 316 break; 317 318 MI = MCInst(); // clear 319 320 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address); 321 if (Res) break; 322 323 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address); 324 if (Res) { IsSDWA = true; break; } 325 326 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address); 327 if (Res) { IsSDWA = true; break; } 328 329 Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address); 330 if (Res) { IsSDWA = true; break; } 331 332 if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) { 333 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address); 334 if (Res) 335 break; 336 } 337 338 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 339 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 340 // table first so we print the correct name. 341 if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) { 342 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address); 343 if (Res) 344 break; 345 } 346 } 347 348 // Reinitialize Bytes as DPP64 could have eaten too much 349 Bytes = Bytes_.slice(0, MaxInstBytesNum); 350 351 // Try decode 32-bit instruction 352 if (Bytes.size() < 4) break; 353 const uint32_t DW = eatBytes<uint32_t>(Bytes); 354 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address); 355 if (Res) break; 356 357 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address); 358 if (Res) break; 359 360 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address); 361 if (Res) break; 362 363 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 364 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address); 365 if (Res) break; 366 } 367 368 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address); 369 if (Res) break; 370 371 if (Bytes.size() < 4) break; 372 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 373 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address); 374 if (Res) break; 375 376 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address); 377 if (Res) break; 378 379 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address); 380 if (Res) break; 381 382 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address); 383 } while (false); 384 385 if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi || 386 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 || 387 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 || 388 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 || 389 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 || 390 MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi || 391 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi || 392 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 || 393 MI.getOpcode() == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 || 394 MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10)) { 395 // Insert dummy unused src2_modifiers. 396 insertNamedMCOperand(MI, MCOperand::createImm(0), 397 AMDGPU::OpName::src2_modifiers); 398 } 399 400 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 401 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT)) && 402 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::glc1) != -1) { 403 insertNamedMCOperand(MI, MCOperand::createImm(1), AMDGPU::OpName::glc1); 404 } 405 406 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 407 int VAddr0Idx = 408 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 409 int RsrcIdx = 410 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 411 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 412 if (VAddr0Idx >= 0 && NSAArgs > 0) { 413 unsigned NSAWords = (NSAArgs + 3) / 4; 414 if (Bytes.size() < 4 * NSAWords) { 415 Res = MCDisassembler::Fail; 416 } else { 417 for (unsigned i = 0; i < NSAArgs; ++i) { 418 MI.insert(MI.begin() + VAddr0Idx + 1 + i, 419 decodeOperand_VGPR_32(Bytes[i])); 420 } 421 Bytes = Bytes.slice(4 * NSAWords); 422 } 423 } 424 425 if (Res) 426 Res = convertMIMGInst(MI); 427 } 428 429 if (Res && IsSDWA) 430 Res = convertSDWAInst(MI); 431 432 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 433 AMDGPU::OpName::vdst_in); 434 if (VDstIn_Idx != -1) { 435 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 436 MCOI::OperandConstraint::TIED_TO); 437 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 438 !MI.getOperand(VDstIn_Idx).isReg() || 439 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 440 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 441 MI.erase(&MI.getOperand(VDstIn_Idx)); 442 insertNamedMCOperand(MI, 443 MCOperand::createReg(MI.getOperand(Tied).getReg()), 444 AMDGPU::OpName::vdst_in); 445 } 446 } 447 448 // if the opcode was not recognized we'll assume a Size of 4 bytes 449 // (unless there are fewer bytes left) 450 Size = Res ? (MaxInstBytesNum - Bytes.size()) 451 : std::min((size_t)4, Bytes_.size()); 452 return Res; 453 } 454 455 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 456 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 457 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 458 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1) 459 // VOPC - insert clamp 460 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 461 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 462 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 463 if (SDst != -1) { 464 // VOPC - insert VCC register as sdst 465 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 466 AMDGPU::OpName::sdst); 467 } else { 468 // VOP1/2 - insert omod if present in instruction 469 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 470 } 471 } 472 return MCDisassembler::Success; 473 } 474 475 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 476 unsigned Opc = MI.getOpcode(); 477 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 478 479 // Insert dummy unused src modifiers. 480 if (MI.getNumOperands() < DescNumOps && 481 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1) 482 insertNamedMCOperand(MI, MCOperand::createImm(0), 483 AMDGPU::OpName::src0_modifiers); 484 485 if (MI.getNumOperands() < DescNumOps && 486 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1) 487 insertNamedMCOperand(MI, MCOperand::createImm(0), 488 AMDGPU::OpName::src1_modifiers); 489 490 return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail; 491 } 492 493 // Note that before gfx10, the MIMG encoding provided no information about 494 // VADDR size. Consequently, decoded instructions always show address as if it 495 // has 1 dword, which could be not really so. 496 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 497 498 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 499 AMDGPU::OpName::vdst); 500 501 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 502 AMDGPU::OpName::vdata); 503 int VAddr0Idx = 504 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 505 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 506 AMDGPU::OpName::dmask); 507 508 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 509 AMDGPU::OpName::tfe); 510 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 511 AMDGPU::OpName::d16); 512 513 assert(VDataIdx != -1); 514 if (DMaskIdx == -1 || TFEIdx == -1) {// intersect_ray 515 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16) > -1) { 516 assert(MI.getOpcode() == AMDGPU::IMAGE_BVH_INTERSECT_RAY_a16_sa || 517 MI.getOpcode() == AMDGPU::IMAGE_BVH_INTERSECT_RAY_a16_nsa || 518 MI.getOpcode() == AMDGPU::IMAGE_BVH64_INTERSECT_RAY_a16_sa || 519 MI.getOpcode() == AMDGPU::IMAGE_BVH64_INTERSECT_RAY_a16_nsa); 520 addOperand(MI, MCOperand::createImm(1)); 521 } 522 return MCDisassembler::Success; 523 } 524 525 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 526 bool IsAtomic = (VDstIdx != -1); 527 bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4; 528 529 bool IsNSA = false; 530 unsigned AddrSize = Info->VAddrDwords; 531 532 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 533 unsigned DimIdx = 534 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 535 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 536 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 537 const AMDGPU::MIMGDimInfo *Dim = 538 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 539 540 AddrSize = BaseOpcode->NumExtraArgs + 541 (BaseOpcode->Gradients ? Dim->NumGradients : 0) + 542 (BaseOpcode->Coordinates ? Dim->NumCoords : 0) + 543 (BaseOpcode->LodOrClampOrMip ? 1 : 0); 544 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA; 545 if (!IsNSA) { 546 if (AddrSize > 8) 547 AddrSize = 16; 548 else if (AddrSize > 4) 549 AddrSize = 8; 550 } else { 551 if (AddrSize > Info->VAddrDwords) { 552 // The NSA encoding does not contain enough operands for the combination 553 // of base opcode / dimension. Should this be an error? 554 return MCDisassembler::Success; 555 } 556 } 557 } 558 559 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 560 unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u); 561 562 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 563 if (D16 && AMDGPU::hasPackedD16(STI)) { 564 DstSize = (DstSize + 1) / 2; 565 } 566 567 // FIXME: Add tfe support 568 if (MI.getOperand(TFEIdx).getImm()) 569 return MCDisassembler::Success; 570 571 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 572 return MCDisassembler::Success; 573 574 int NewOpcode = 575 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 576 if (NewOpcode == -1) 577 return MCDisassembler::Success; 578 579 // Widen the register to the correct number of enabled channels. 580 unsigned NewVdata = AMDGPU::NoRegister; 581 if (DstSize != Info->VDataDwords) { 582 auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; 583 584 // Get first subregister of VData 585 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 586 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 587 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 588 589 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 590 &MRI.getRegClass(DataRCID)); 591 if (NewVdata == AMDGPU::NoRegister) { 592 // It's possible to encode this such that the low register + enabled 593 // components exceeds the register count. 594 return MCDisassembler::Success; 595 } 596 } 597 598 unsigned NewVAddr0 = AMDGPU::NoRegister; 599 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10] && !IsNSA && 600 AddrSize != Info->VAddrDwords) { 601 unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg(); 602 unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0); 603 VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0; 604 605 auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass; 606 NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0, 607 &MRI.getRegClass(AddrRCID)); 608 if (NewVAddr0 == AMDGPU::NoRegister) 609 return MCDisassembler::Success; 610 } 611 612 MI.setOpcode(NewOpcode); 613 614 if (NewVdata != AMDGPU::NoRegister) { 615 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 616 617 if (IsAtomic) { 618 // Atomic operations have an additional operand (a copy of data) 619 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 620 } 621 } 622 623 if (NewVAddr0 != AMDGPU::NoRegister) { 624 MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0); 625 } else if (IsNSA) { 626 assert(AddrSize <= Info->VAddrDwords); 627 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 628 MI.begin() + VAddr0Idx + Info->VAddrDwords); 629 } 630 631 return MCDisassembler::Success; 632 } 633 634 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 635 return getContext().getRegisterInfo()-> 636 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 637 } 638 639 inline 640 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 641 const Twine& ErrMsg) const { 642 *CommentStream << "Error: " + ErrMsg; 643 644 // ToDo: add support for error operands to MCInst.h 645 // return MCOperand::createError(V); 646 return MCOperand(); 647 } 648 649 inline 650 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 651 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 652 } 653 654 inline 655 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 656 unsigned Val) const { 657 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 658 if (Val >= RegCl.getNumRegs()) 659 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 660 ": unknown register " + Twine(Val)); 661 return createRegOperand(RegCl.getRegister(Val)); 662 } 663 664 inline 665 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 666 unsigned Val) const { 667 // ToDo: SI/CI have 104 SGPRs, VI - 102 668 // Valery: here we accepting as much as we can, let assembler sort it out 669 int shift = 0; 670 switch (SRegClassID) { 671 case AMDGPU::SGPR_32RegClassID: 672 case AMDGPU::TTMP_32RegClassID: 673 break; 674 case AMDGPU::SGPR_64RegClassID: 675 case AMDGPU::TTMP_64RegClassID: 676 shift = 1; 677 break; 678 case AMDGPU::SGPR_128RegClassID: 679 case AMDGPU::TTMP_128RegClassID: 680 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 681 // this bundle? 682 case AMDGPU::SGPR_256RegClassID: 683 case AMDGPU::TTMP_256RegClassID: 684 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 685 // this bundle? 686 case AMDGPU::SGPR_512RegClassID: 687 case AMDGPU::TTMP_512RegClassID: 688 shift = 2; 689 break; 690 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 691 // this bundle? 692 default: 693 llvm_unreachable("unhandled register class"); 694 } 695 696 if (Val % (1 << shift)) { 697 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 698 << ": scalar reg isn't aligned " << Val; 699 } 700 701 return createRegOperand(SRegClassID, Val >> shift); 702 } 703 704 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { 705 return decodeSrcOp(OPW32, Val); 706 } 707 708 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { 709 return decodeSrcOp(OPW64, Val); 710 } 711 712 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const { 713 return decodeSrcOp(OPW128, Val); 714 } 715 716 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const { 717 return decodeSrcOp(OPW16, Val); 718 } 719 720 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const { 721 return decodeSrcOp(OPWV216, Val); 722 } 723 724 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { 725 // Some instructions have operand restrictions beyond what the encoding 726 // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra 727 // high bit. 728 Val &= 255; 729 730 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); 731 } 732 733 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const { 734 return decodeSrcOp(OPW32, Val); 735 } 736 737 MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const { 738 return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255); 739 } 740 741 MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const { 742 return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255); 743 } 744 745 MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const { 746 return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255); 747 } 748 749 MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const { 750 return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255); 751 } 752 753 MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const { 754 return decodeSrcOp(OPW32, Val); 755 } 756 757 MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const { 758 return decodeSrcOp(OPW64, Val); 759 } 760 761 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { 762 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); 763 } 764 765 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { 766 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); 767 } 768 769 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { 770 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); 771 } 772 773 MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const { 774 return createRegOperand(AMDGPU::VReg_256RegClassID, Val); 775 } 776 777 MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const { 778 return createRegOperand(AMDGPU::VReg_512RegClassID, Val); 779 } 780 781 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { 782 // table-gen generated disassembler doesn't care about operand types 783 // leaving only registry class so SSrc_32 operand turns into SReg_32 784 // and therefore we accept immediates and literals here as well 785 return decodeSrcOp(OPW32, Val); 786 } 787 788 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC( 789 unsigned Val) const { 790 // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI 791 return decodeOperand_SReg_32(Val); 792 } 793 794 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI( 795 unsigned Val) const { 796 // SReg_32_XM0 is SReg_32 without EXEC_HI 797 return decodeOperand_SReg_32(Val); 798 } 799 800 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const { 801 // table-gen generated disassembler doesn't care about operand types 802 // leaving only registry class so SSrc_32 operand turns into SReg_32 803 // and therefore we accept immediates and literals here as well 804 return decodeSrcOp(OPW32, Val); 805 } 806 807 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { 808 return decodeSrcOp(OPW64, Val); 809 } 810 811 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const { 812 return decodeSrcOp(OPW64, Val); 813 } 814 815 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { 816 return decodeSrcOp(OPW128, Val); 817 } 818 819 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { 820 return decodeDstOp(OPW256, Val); 821 } 822 823 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { 824 return decodeDstOp(OPW512, Val); 825 } 826 827 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { 828 // For now all literal constants are supposed to be unsigned integer 829 // ToDo: deal with signed/unsigned 64-bit integer constants 830 // ToDo: deal with float/double constants 831 if (!HasLiteral) { 832 if (Bytes.size() < 4) { 833 return errOperand(0, "cannot read literal, inst bytes left " + 834 Twine(Bytes.size())); 835 } 836 HasLiteral = true; 837 Literal = eatBytes<uint32_t>(Bytes); 838 } 839 return MCOperand::createImm(Literal); 840 } 841 842 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 843 using namespace AMDGPU::EncValues; 844 845 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 846 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 847 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 848 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 849 // Cast prevents negative overflow. 850 } 851 852 static int64_t getInlineImmVal32(unsigned Imm) { 853 switch (Imm) { 854 case 240: 855 return FloatToBits(0.5f); 856 case 241: 857 return FloatToBits(-0.5f); 858 case 242: 859 return FloatToBits(1.0f); 860 case 243: 861 return FloatToBits(-1.0f); 862 case 244: 863 return FloatToBits(2.0f); 864 case 245: 865 return FloatToBits(-2.0f); 866 case 246: 867 return FloatToBits(4.0f); 868 case 247: 869 return FloatToBits(-4.0f); 870 case 248: // 1 / (2 * PI) 871 return 0x3e22f983; 872 default: 873 llvm_unreachable("invalid fp inline imm"); 874 } 875 } 876 877 static int64_t getInlineImmVal64(unsigned Imm) { 878 switch (Imm) { 879 case 240: 880 return DoubleToBits(0.5); 881 case 241: 882 return DoubleToBits(-0.5); 883 case 242: 884 return DoubleToBits(1.0); 885 case 243: 886 return DoubleToBits(-1.0); 887 case 244: 888 return DoubleToBits(2.0); 889 case 245: 890 return DoubleToBits(-2.0); 891 case 246: 892 return DoubleToBits(4.0); 893 case 247: 894 return DoubleToBits(-4.0); 895 case 248: // 1 / (2 * PI) 896 return 0x3fc45f306dc9c882; 897 default: 898 llvm_unreachable("invalid fp inline imm"); 899 } 900 } 901 902 static int64_t getInlineImmVal16(unsigned Imm) { 903 switch (Imm) { 904 case 240: 905 return 0x3800; 906 case 241: 907 return 0xB800; 908 case 242: 909 return 0x3C00; 910 case 243: 911 return 0xBC00; 912 case 244: 913 return 0x4000; 914 case 245: 915 return 0xC000; 916 case 246: 917 return 0x4400; 918 case 247: 919 return 0xC400; 920 case 248: // 1 / (2 * PI) 921 return 0x3118; 922 default: 923 llvm_unreachable("invalid fp inline imm"); 924 } 925 } 926 927 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) { 928 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 929 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 930 931 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 932 switch (Width) { 933 case OPW32: 934 case OPW128: // splat constants 935 case OPW512: 936 case OPW1024: 937 return MCOperand::createImm(getInlineImmVal32(Imm)); 938 case OPW64: 939 return MCOperand::createImm(getInlineImmVal64(Imm)); 940 case OPW16: 941 case OPWV216: 942 return MCOperand::createImm(getInlineImmVal16(Imm)); 943 default: 944 llvm_unreachable("implement me"); 945 } 946 } 947 948 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 949 using namespace AMDGPU; 950 951 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 952 switch (Width) { 953 default: // fall 954 case OPW32: 955 case OPW16: 956 case OPWV216: 957 return VGPR_32RegClassID; 958 case OPW64: return VReg_64RegClassID; 959 case OPW128: return VReg_128RegClassID; 960 } 961 } 962 963 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 964 using namespace AMDGPU; 965 966 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 967 switch (Width) { 968 default: // fall 969 case OPW32: 970 case OPW16: 971 case OPWV216: 972 return AGPR_32RegClassID; 973 case OPW64: return AReg_64RegClassID; 974 case OPW128: return AReg_128RegClassID; 975 case OPW256: return AReg_256RegClassID; 976 case OPW512: return AReg_512RegClassID; 977 case OPW1024: return AReg_1024RegClassID; 978 } 979 } 980 981 982 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 983 using namespace AMDGPU; 984 985 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 986 switch (Width) { 987 default: // fall 988 case OPW32: 989 case OPW16: 990 case OPWV216: 991 return SGPR_32RegClassID; 992 case OPW64: return SGPR_64RegClassID; 993 case OPW128: return SGPR_128RegClassID; 994 case OPW256: return SGPR_256RegClassID; 995 case OPW512: return SGPR_512RegClassID; 996 } 997 } 998 999 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 1000 using namespace AMDGPU; 1001 1002 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1003 switch (Width) { 1004 default: // fall 1005 case OPW32: 1006 case OPW16: 1007 case OPWV216: 1008 return TTMP_32RegClassID; 1009 case OPW64: return TTMP_64RegClassID; 1010 case OPW128: return TTMP_128RegClassID; 1011 case OPW256: return TTMP_256RegClassID; 1012 case OPW512: return TTMP_512RegClassID; 1013 } 1014 } 1015 1016 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 1017 using namespace AMDGPU::EncValues; 1018 1019 unsigned TTmpMin = 1020 (isGFX9() || isGFX10()) ? TTMP_GFX9_GFX10_MIN : TTMP_VI_MIN; 1021 unsigned TTmpMax = 1022 (isGFX9() || isGFX10()) ? TTMP_GFX9_GFX10_MAX : TTMP_VI_MAX; 1023 1024 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1025 } 1026 1027 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const { 1028 using namespace AMDGPU::EncValues; 1029 1030 assert(Val < 1024); // enum10 1031 1032 bool IsAGPR = Val & 512; 1033 Val &= 511; 1034 1035 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1036 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1037 : getVgprClassId(Width), Val - VGPR_MIN); 1038 } 1039 if (Val <= SGPR_MAX) { 1040 assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning. 1041 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1042 } 1043 1044 int TTmpIdx = getTTmpIdx(Val); 1045 if (TTmpIdx >= 0) { 1046 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1047 } 1048 1049 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1050 return decodeIntImmed(Val); 1051 1052 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1053 return decodeFPImmed(Width, Val); 1054 1055 if (Val == LITERAL_CONST) 1056 return decodeLiteralConstant(); 1057 1058 switch (Width) { 1059 case OPW32: 1060 case OPW16: 1061 case OPWV216: 1062 return decodeSpecialReg32(Val); 1063 case OPW64: 1064 return decodeSpecialReg64(Val); 1065 default: 1066 llvm_unreachable("unexpected immediate type"); 1067 } 1068 } 1069 1070 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const { 1071 using namespace AMDGPU::EncValues; 1072 1073 assert(Val < 128); 1074 assert(Width == OPW256 || Width == OPW512); 1075 1076 if (Val <= SGPR_MAX) { 1077 assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning. 1078 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1079 } 1080 1081 int TTmpIdx = getTTmpIdx(Val); 1082 if (TTmpIdx >= 0) { 1083 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1084 } 1085 1086 llvm_unreachable("unknown dst register"); 1087 } 1088 1089 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1090 using namespace AMDGPU; 1091 1092 switch (Val) { 1093 case 102: return createRegOperand(FLAT_SCR_LO); 1094 case 103: return createRegOperand(FLAT_SCR_HI); 1095 case 104: return createRegOperand(XNACK_MASK_LO); 1096 case 105: return createRegOperand(XNACK_MASK_HI); 1097 case 106: return createRegOperand(VCC_LO); 1098 case 107: return createRegOperand(VCC_HI); 1099 case 108: return createRegOperand(TBA_LO); 1100 case 109: return createRegOperand(TBA_HI); 1101 case 110: return createRegOperand(TMA_LO); 1102 case 111: return createRegOperand(TMA_HI); 1103 case 124: return createRegOperand(M0); 1104 case 125: return createRegOperand(SGPR_NULL); 1105 case 126: return createRegOperand(EXEC_LO); 1106 case 127: return createRegOperand(EXEC_HI); 1107 case 235: return createRegOperand(SRC_SHARED_BASE); 1108 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1109 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1110 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1111 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1112 case 251: return createRegOperand(SRC_VCCZ); 1113 case 252: return createRegOperand(SRC_EXECZ); 1114 case 253: return createRegOperand(SRC_SCC); 1115 case 254: return createRegOperand(LDS_DIRECT); 1116 default: break; 1117 } 1118 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1119 } 1120 1121 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1122 using namespace AMDGPU; 1123 1124 switch (Val) { 1125 case 102: return createRegOperand(FLAT_SCR); 1126 case 104: return createRegOperand(XNACK_MASK); 1127 case 106: return createRegOperand(VCC); 1128 case 108: return createRegOperand(TBA); 1129 case 110: return createRegOperand(TMA); 1130 case 125: return createRegOperand(SGPR_NULL); 1131 case 126: return createRegOperand(EXEC); 1132 case 235: return createRegOperand(SRC_SHARED_BASE); 1133 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1134 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1135 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1136 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1137 case 251: return createRegOperand(SRC_VCCZ); 1138 case 252: return createRegOperand(SRC_EXECZ); 1139 case 253: return createRegOperand(SRC_SCC); 1140 default: break; 1141 } 1142 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1143 } 1144 1145 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 1146 const unsigned Val) const { 1147 using namespace AMDGPU::SDWA; 1148 using namespace AMDGPU::EncValues; 1149 1150 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1151 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 1152 // XXX: cast to int is needed to avoid stupid warning: 1153 // compare with unsigned is always true 1154 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1155 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1156 return createRegOperand(getVgprClassId(Width), 1157 Val - SDWA9EncValues::SRC_VGPR_MIN); 1158 } 1159 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1160 Val <= (isGFX10() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1161 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1162 return createSRegOperand(getSgprClassId(Width), 1163 Val - SDWA9EncValues::SRC_SGPR_MIN); 1164 } 1165 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1166 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1167 return createSRegOperand(getTtmpClassId(Width), 1168 Val - SDWA9EncValues::SRC_TTMP_MIN); 1169 } 1170 1171 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1172 1173 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1174 return decodeIntImmed(SVal); 1175 1176 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1177 return decodeFPImmed(Width, SVal); 1178 1179 return decodeSpecialReg32(SVal); 1180 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 1181 return createRegOperand(getVgprClassId(Width), Val); 1182 } 1183 llvm_unreachable("unsupported target"); 1184 } 1185 1186 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1187 return decodeSDWASrc(OPW16, Val); 1188 } 1189 1190 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1191 return decodeSDWASrc(OPW32, Val); 1192 } 1193 1194 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1195 using namespace AMDGPU::SDWA; 1196 1197 assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1198 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) && 1199 "SDWAVopcDst should be present only on GFX9+"); 1200 1201 bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64]; 1202 1203 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1204 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1205 1206 int TTmpIdx = getTTmpIdx(Val); 1207 if (TTmpIdx >= 0) { 1208 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1209 return createSRegOperand(TTmpClsId, TTmpIdx); 1210 } else if (Val > SGPR_MAX) { 1211 return IsWave64 ? decodeSpecialReg64(Val) 1212 : decodeSpecialReg32(Val); 1213 } else { 1214 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1215 } 1216 } else { 1217 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1218 } 1219 } 1220 1221 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1222 return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ? 1223 decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val); 1224 } 1225 1226 bool AMDGPUDisassembler::isVI() const { 1227 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]; 1228 } 1229 1230 bool AMDGPUDisassembler::isGFX9() const { 1231 return STI.getFeatureBits()[AMDGPU::FeatureGFX9]; 1232 } 1233 1234 bool AMDGPUDisassembler::isGFX10() const { 1235 return STI.getFeatureBits()[AMDGPU::FeatureGFX10]; 1236 } 1237 1238 //===----------------------------------------------------------------------===// 1239 // AMDGPU specific symbol handling 1240 //===----------------------------------------------------------------------===// 1241 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1242 do { \ 1243 KdStream << Indent << DIRECTIVE " " \ 1244 << ((FourByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1245 } while (0) 1246 1247 // NOLINTNEXTLINE(readability-identifier-naming) 1248 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1249 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1250 using namespace amdhsa; 1251 StringRef Indent = "\t"; 1252 1253 // We cannot accurately backward compute #VGPRs used from 1254 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1255 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1256 // simply calculate the inverse of what the assembler does. 1257 1258 uint32_t GranulatedWorkitemVGPRCount = 1259 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT) >> 1260 COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT; 1261 1262 uint32_t NextFreeVGPR = (GranulatedWorkitemVGPRCount + 1) * 1263 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI); 1264 1265 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1266 1267 // We cannot backward compute values used to calculate 1268 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1269 // directives can't be computed: 1270 // .amdhsa_reserve_vcc 1271 // .amdhsa_reserve_flat_scratch 1272 // .amdhsa_reserve_xnack_mask 1273 // They take their respective default values if not specified in the assembly. 1274 // 1275 // GRANULATED_WAVEFRONT_SGPR_COUNT 1276 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1277 // 1278 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1279 // are set to 0. So while disassembling we consider that: 1280 // 1281 // GRANULATED_WAVEFRONT_SGPR_COUNT 1282 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1283 // 1284 // The disassembler cannot recover the original values of those 3 directives. 1285 1286 uint32_t GranulatedWavefrontSGPRCount = 1287 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT) >> 1288 COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT; 1289 1290 if (isGFX10() && GranulatedWavefrontSGPRCount) 1291 return MCDisassembler::Fail; 1292 1293 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1294 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1295 1296 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1297 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1298 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1299 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1300 1301 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY) 1302 return MCDisassembler::Fail; 1303 1304 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1305 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1306 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1307 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1308 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1309 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1310 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1311 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1312 1313 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) 1314 return MCDisassembler::Fail; 1315 1316 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 1317 1318 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) 1319 return MCDisassembler::Fail; 1320 1321 PRINT_DIRECTIVE(".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 1322 1323 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) 1324 return MCDisassembler::Fail; 1325 1326 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER) 1327 return MCDisassembler::Fail; 1328 1329 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_FP16_OVFL); 1330 1331 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED0) 1332 return MCDisassembler::Fail; 1333 1334 if (isGFX10()) { 1335 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1336 COMPUTE_PGM_RSRC1_WGP_MODE); 1337 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_MEM_ORDERED); 1338 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_FWD_PROGRESS); 1339 } 1340 return MCDisassembler::Success; 1341 } 1342 1343 // NOLINTNEXTLINE(readability-identifier-naming) 1344 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 1345 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1346 using namespace amdhsa; 1347 StringRef Indent = "\t"; 1348 PRINT_DIRECTIVE( 1349 ".amdhsa_system_sgpr_private_segment_wavefront_offset", 1350 COMPUTE_PGM_RSRC2_ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET); 1351 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 1352 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 1353 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 1354 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 1355 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 1356 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 1357 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 1358 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 1359 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 1360 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 1361 1362 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH) 1363 return MCDisassembler::Fail; 1364 1365 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY) 1366 return MCDisassembler::Fail; 1367 1368 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE) 1369 return MCDisassembler::Fail; 1370 1371 PRINT_DIRECTIVE( 1372 ".amdhsa_exception_fp_ieee_invalid_op", 1373 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 1374 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 1375 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 1376 PRINT_DIRECTIVE( 1377 ".amdhsa_exception_fp_ieee_div_zero", 1378 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 1379 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 1380 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 1381 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 1382 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 1383 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 1384 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 1385 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 1386 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 1387 1388 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0) 1389 return MCDisassembler::Fail; 1390 1391 return MCDisassembler::Success; 1392 } 1393 1394 #undef PRINT_DIRECTIVE 1395 1396 MCDisassembler::DecodeStatus 1397 AMDGPUDisassembler::decodeKernelDescriptorDirective( 1398 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 1399 raw_string_ostream &KdStream) const { 1400 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1401 do { \ 1402 KdStream << Indent << DIRECTIVE " " \ 1403 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1404 } while (0) 1405 1406 uint16_t TwoByteBuffer = 0; 1407 uint32_t FourByteBuffer = 0; 1408 uint64_t EightByteBuffer = 0; 1409 1410 StringRef ReservedBytes; 1411 StringRef Indent = "\t"; 1412 1413 assert(Bytes.size() == 64); 1414 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 1415 1416 switch (Cursor.tell()) { 1417 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 1418 FourByteBuffer = DE.getU32(Cursor); 1419 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 1420 << '\n'; 1421 return MCDisassembler::Success; 1422 1423 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 1424 FourByteBuffer = DE.getU32(Cursor); 1425 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 1426 << FourByteBuffer << '\n'; 1427 return MCDisassembler::Success; 1428 1429 case amdhsa::RESERVED0_OFFSET: 1430 // 8 reserved bytes, must be 0. 1431 EightByteBuffer = DE.getU64(Cursor); 1432 if (EightByteBuffer) { 1433 return MCDisassembler::Fail; 1434 } 1435 return MCDisassembler::Success; 1436 1437 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 1438 // KERNEL_CODE_ENTRY_BYTE_OFFSET 1439 // So far no directive controls this for Code Object V3, so simply skip for 1440 // disassembly. 1441 DE.skip(Cursor, 8); 1442 return MCDisassembler::Success; 1443 1444 case amdhsa::RESERVED1_OFFSET: 1445 // 20 reserved bytes, must be 0. 1446 ReservedBytes = DE.getBytes(Cursor, 20); 1447 for (int I = 0; I < 20; ++I) { 1448 if (ReservedBytes[I] != 0) { 1449 return MCDisassembler::Fail; 1450 } 1451 } 1452 return MCDisassembler::Success; 1453 1454 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 1455 // COMPUTE_PGM_RSRC3 1456 // - Only set for GFX10, GFX6-9 have this to be 0. 1457 // - Currently no directives directly control this. 1458 FourByteBuffer = DE.getU32(Cursor); 1459 if (!isGFX10() && FourByteBuffer) { 1460 return MCDisassembler::Fail; 1461 } 1462 return MCDisassembler::Success; 1463 1464 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 1465 FourByteBuffer = DE.getU32(Cursor); 1466 if (decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream) == 1467 MCDisassembler::Fail) { 1468 return MCDisassembler::Fail; 1469 } 1470 return MCDisassembler::Success; 1471 1472 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 1473 FourByteBuffer = DE.getU32(Cursor); 1474 if (decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream) == 1475 MCDisassembler::Fail) { 1476 return MCDisassembler::Fail; 1477 } 1478 return MCDisassembler::Success; 1479 1480 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 1481 using namespace amdhsa; 1482 TwoByteBuffer = DE.getU16(Cursor); 1483 1484 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 1485 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 1486 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 1487 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 1488 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 1489 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 1490 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 1491 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 1492 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 1493 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 1494 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 1495 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 1496 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 1497 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 1498 1499 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 1500 return MCDisassembler::Fail; 1501 1502 // Reserved for GFX9 1503 if (isGFX9() && 1504 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 1505 return MCDisassembler::Fail; 1506 } else if (isGFX10()) { 1507 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 1508 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 1509 } 1510 1511 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) 1512 return MCDisassembler::Fail; 1513 1514 return MCDisassembler::Success; 1515 1516 case amdhsa::RESERVED2_OFFSET: 1517 // 6 bytes from here are reserved, must be 0. 1518 ReservedBytes = DE.getBytes(Cursor, 6); 1519 for (int I = 0; I < 6; ++I) { 1520 if (ReservedBytes[I] != 0) 1521 return MCDisassembler::Fail; 1522 } 1523 return MCDisassembler::Success; 1524 1525 default: 1526 llvm_unreachable("Unhandled index. Case statements cover everything."); 1527 return MCDisassembler::Fail; 1528 } 1529 #undef PRINT_DIRECTIVE 1530 } 1531 1532 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( 1533 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 1534 // CP microcode requires the kernel descriptor to be 64 aligned. 1535 if (Bytes.size() != 64 || KdAddress % 64 != 0) 1536 return MCDisassembler::Fail; 1537 1538 std::string Kd; 1539 raw_string_ostream KdStream(Kd); 1540 KdStream << ".amdhsa_kernel " << KdName << '\n'; 1541 1542 DataExtractor::Cursor C(0); 1543 while (C && C.tell() < Bytes.size()) { 1544 MCDisassembler::DecodeStatus Status = 1545 decodeKernelDescriptorDirective(C, Bytes, KdStream); 1546 1547 cantFail(C.takeError()); 1548 1549 if (Status == MCDisassembler::Fail) 1550 return MCDisassembler::Fail; 1551 } 1552 KdStream << ".end_amdhsa_kernel\n"; 1553 outs() << KdStream.str(); 1554 return MCDisassembler::Success; 1555 } 1556 1557 Optional<MCDisassembler::DecodeStatus> 1558 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 1559 ArrayRef<uint8_t> Bytes, uint64_t Address, 1560 raw_ostream &CStream) const { 1561 // Right now only kernel descriptor needs to be handled. 1562 // We ignore all other symbols for target specific handling. 1563 // TODO: 1564 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 1565 // Object V2 and V3 when symbols are marked protected. 1566 1567 // amd_kernel_code_t for Code Object V2. 1568 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 1569 Size = 256; 1570 return MCDisassembler::Fail; 1571 } 1572 1573 // Code Object V3 kernel descriptors. 1574 StringRef Name = Symbol.Name; 1575 if (Symbol.Type == ELF::STT_OBJECT && Name.endswith(StringRef(".kd"))) { 1576 Size = 64; // Size = 64 regardless of success or failure. 1577 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 1578 } 1579 return None; 1580 } 1581 1582 //===----------------------------------------------------------------------===// 1583 // AMDGPUSymbolizer 1584 //===----------------------------------------------------------------------===// 1585 1586 // Try to find symbol name for specified label 1587 bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst, 1588 raw_ostream &/*cStream*/, int64_t Value, 1589 uint64_t /*Address*/, bool IsBranch, 1590 uint64_t /*Offset*/, uint64_t /*InstSize*/) { 1591 1592 if (!IsBranch) { 1593 return false; 1594 } 1595 1596 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 1597 if (!Symbols) 1598 return false; 1599 1600 auto Result = std::find_if(Symbols->begin(), Symbols->end(), 1601 [Value](const SymbolInfoTy& Val) { 1602 return Val.Addr == static_cast<uint64_t>(Value) 1603 && Val.Type == ELF::STT_NOTYPE; 1604 }); 1605 if (Result != Symbols->end()) { 1606 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 1607 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 1608 Inst.addOperand(MCOperand::createExpr(Add)); 1609 return true; 1610 } 1611 return false; 1612 } 1613 1614 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 1615 int64_t Value, 1616 uint64_t Address) { 1617 llvm_unreachable("unimplemented"); 1618 } 1619 1620 //===----------------------------------------------------------------------===// 1621 // Initialization 1622 //===----------------------------------------------------------------------===// 1623 1624 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 1625 LLVMOpInfoCallback /*GetOpInfo*/, 1626 LLVMSymbolLookupCallback /*SymbolLookUp*/, 1627 void *DisInfo, 1628 MCContext *Ctx, 1629 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 1630 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 1631 } 1632 1633 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 1634 const MCSubtargetInfo &STI, 1635 MCContext &Ctx) { 1636 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 1637 } 1638 1639 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 1640 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 1641 createAMDGPUDisassembler); 1642 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 1643 createAMDGPUSymbolizer); 1644 } 1645