1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "SIDefines.h" 22 #include "SIRegisterInfo.h" 23 #include "TargetInfo/AMDGPUTargetInfo.h" 24 #include "Utils/AMDGPUAsmUtils.h" 25 #include "Utils/AMDGPUBaseInfo.h" 26 #include "llvm-c/DisassemblerTypes.h" 27 #include "llvm/BinaryFormat/ELF.h" 28 #include "llvm/MC/MCAsmInfo.h" 29 #include "llvm/MC/MCContext.h" 30 #include "llvm/MC/MCDecoderOps.h" 31 #include "llvm/MC/MCExpr.h" 32 #include "llvm/MC/MCInstrDesc.h" 33 #include "llvm/MC/MCRegisterInfo.h" 34 #include "llvm/MC/MCSubtargetInfo.h" 35 #include "llvm/MC/TargetRegistry.h" 36 #include "llvm/Support/AMDHSAKernelDescriptor.h" 37 38 using namespace llvm; 39 40 #define DEBUG_TYPE "amdgpu-disassembler" 41 42 #define SGPR_MAX \ 43 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 44 : AMDGPU::EncValues::SGPR_MAX_SI) 45 46 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 47 48 static const MCSubtargetInfo &addDefaultWaveSize(const MCSubtargetInfo &STI, 49 MCContext &Ctx) { 50 if (!STI.hasFeature(AMDGPU::FeatureWavefrontSize64) && 51 !STI.hasFeature(AMDGPU::FeatureWavefrontSize32)) { 52 MCSubtargetInfo &STICopy = Ctx.getSubtargetCopy(STI); 53 // If there is no default wave size it must be a generation before gfx10, 54 // these have FeatureWavefrontSize64 in their definition already. For gfx10+ 55 // set wave32 as a default. 56 STICopy.ToggleFeature(AMDGPU::FeatureWavefrontSize32); 57 return STICopy; 58 } 59 60 return STI; 61 } 62 63 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 64 MCContext &Ctx, MCInstrInfo const *MCII) 65 : MCDisassembler(addDefaultWaveSize(STI, Ctx), Ctx), MCII(MCII), 66 MRI(*Ctx.getRegisterInfo()), MAI(*Ctx.getAsmInfo()), 67 TargetMaxInstBytes(MAI.getMaxInstLength(&STI)), 68 CodeObjectVersion(AMDGPU::getDefaultAMDHSACodeObjectVersion()) { 69 // ToDo: AMDGPUDisassembler supports only VI ISA. 70 if (!STI.hasFeature(AMDGPU::FeatureGCN3Encoding) && !isGFX10Plus()) 71 report_fatal_error("Disassembly not yet supported for subtarget"); 72 73 for (auto [Symbol, Code] : AMDGPU::UCVersion::getGFXVersions()) 74 createConstantSymbolExpr(Symbol, Code); 75 76 UCVersionW64Expr = createConstantSymbolExpr("UC_VERSION_W64_BIT", 0x2000); 77 UCVersionW32Expr = createConstantSymbolExpr("UC_VERSION_W32_BIT", 0x4000); 78 UCVersionMDPExpr = createConstantSymbolExpr("UC_VERSION_MDP_BIT", 0x8000); 79 } 80 81 void AMDGPUDisassembler::setABIVersion(unsigned Version) { 82 CodeObjectVersion = AMDGPU::getAMDHSACodeObjectVersion(Version); 83 } 84 85 inline static MCDisassembler::DecodeStatus 86 addOperand(MCInst &Inst, const MCOperand& Opnd) { 87 Inst.addOperand(Opnd); 88 return Opnd.isValid() ? 89 MCDisassembler::Success : 90 MCDisassembler::Fail; 91 } 92 93 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 94 uint16_t NameIdx) { 95 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 96 if (OpIdx != -1) { 97 auto I = MI.begin(); 98 std::advance(I, OpIdx); 99 MI.insert(I, Op); 100 } 101 return OpIdx; 102 } 103 104 static DecodeStatus decodeSOPPBrTarget(MCInst &Inst, unsigned Imm, 105 uint64_t Addr, 106 const MCDisassembler *Decoder) { 107 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 108 109 // Our branches take a simm16. 110 int64_t Offset = SignExtend64<16>(Imm) * 4 + 4 + Addr; 111 112 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2, 0)) 113 return MCDisassembler::Success; 114 return addOperand(Inst, MCOperand::createImm(Imm)); 115 } 116 117 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, 118 const MCDisassembler *Decoder) { 119 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 120 int64_t Offset; 121 if (DAsm->isGFX12Plus()) { // GFX12 supports 24-bit signed offsets. 122 Offset = SignExtend64<24>(Imm); 123 } else if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 124 Offset = Imm & 0xFFFFF; 125 } else { // GFX9+ supports 21-bit signed offsets. 126 Offset = SignExtend64<21>(Imm); 127 } 128 return addOperand(Inst, MCOperand::createImm(Offset)); 129 } 130 131 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, 132 const MCDisassembler *Decoder) { 133 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 134 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 135 } 136 137 static DecodeStatus decodeSplitBarrier(MCInst &Inst, unsigned Val, 138 uint64_t Addr, 139 const MCDisassembler *Decoder) { 140 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 141 return addOperand(Inst, DAsm->decodeSplitBarrier(Val)); 142 } 143 144 static DecodeStatus decodeDpp8FI(MCInst &Inst, unsigned Val, uint64_t Addr, 145 const MCDisassembler *Decoder) { 146 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 147 return addOperand(Inst, DAsm->decodeDpp8FI(Val)); 148 } 149 150 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 151 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \ 152 uint64_t /*Addr*/, \ 153 const MCDisassembler *Decoder) { \ 154 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 155 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 156 } 157 158 // Decoder for registers, decode directly using RegClassID. Imm(8-bit) is 159 // number of register. Used by VGPR only and AGPR only operands. 160 #define DECODE_OPERAND_REG_8(RegClass) \ 161 static DecodeStatus Decode##RegClass##RegisterClass( \ 162 MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \ 163 const MCDisassembler *Decoder) { \ 164 assert(Imm < (1 << 8) && "8-bit encoding"); \ 165 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 166 return addOperand( \ 167 Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm)); \ 168 } 169 170 #define DECODE_SrcOp(Name, EncSize, OpWidth, EncImm, MandatoryLiteral, \ 171 ImmWidth) \ 172 static DecodeStatus Name(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \ 173 const MCDisassembler *Decoder) { \ 174 assert(Imm < (1 << EncSize) && #EncSize "-bit encoding"); \ 175 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 176 return addOperand(Inst, \ 177 DAsm->decodeSrcOp(AMDGPUDisassembler::OpWidth, EncImm, \ 178 MandatoryLiteral, ImmWidth)); \ 179 } 180 181 static DecodeStatus decodeSrcOp(MCInst &Inst, unsigned EncSize, 182 AMDGPUDisassembler::OpWidthTy OpWidth, 183 unsigned Imm, unsigned EncImm, 184 bool MandatoryLiteral, unsigned ImmWidth, 185 AMDGPU::OperandSemantics Sema, 186 const MCDisassembler *Decoder) { 187 assert(Imm < (1U << EncSize) && "Operand doesn't fit encoding!"); 188 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 189 return addOperand(Inst, DAsm->decodeSrcOp(OpWidth, EncImm, MandatoryLiteral, 190 ImmWidth, Sema)); 191 } 192 193 // Decoder for registers. Imm(7-bit) is number of register, uses decodeSrcOp to 194 // get register class. Used by SGPR only operands. 195 #define DECODE_OPERAND_REG_7(RegClass, OpWidth) \ 196 DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0) 197 198 // Decoder for registers. Imm(10-bit): Imm{7-0} is number of register, 199 // Imm{9} is acc(agpr or vgpr) Imm{8} should be 0 (see VOP3Pe_SMFMAC). 200 // Set Imm{8} to 1 (IS_VGPR) to decode using 'enum10' from decodeSrcOp. 201 // Used by AV_ register classes (AGPR or VGPR only register operands). 202 template <AMDGPUDisassembler::OpWidthTy OpWidth> 203 static DecodeStatus decodeAV10(MCInst &Inst, unsigned Imm, uint64_t /* Addr */, 204 const MCDisassembler *Decoder) { 205 return decodeSrcOp(Inst, 10, OpWidth, Imm, Imm | AMDGPU::EncValues::IS_VGPR, 206 false, 0, AMDGPU::OperandSemantics::INT, Decoder); 207 } 208 209 // Decoder for Src(9-bit encoding) registers only. 210 template <AMDGPUDisassembler::OpWidthTy OpWidth> 211 static DecodeStatus decodeSrcReg9(MCInst &Inst, unsigned Imm, 212 uint64_t /* Addr */, 213 const MCDisassembler *Decoder) { 214 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, false, 0, 215 AMDGPU::OperandSemantics::INT, Decoder); 216 } 217 218 // Decoder for Src(9-bit encoding) AGPR, register number encoded in 9bits, set 219 // Imm{9} to 1 (set acc) and decode using 'enum10' from decodeSrcOp, registers 220 // only. 221 template <AMDGPUDisassembler::OpWidthTy OpWidth> 222 static DecodeStatus decodeSrcA9(MCInst &Inst, unsigned Imm, uint64_t /* Addr */, 223 const MCDisassembler *Decoder) { 224 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm | 512, false, 0, 225 AMDGPU::OperandSemantics::INT, Decoder); 226 } 227 228 // Decoder for 'enum10' from decodeSrcOp, Imm{0-8} is 9-bit Src encoding 229 // Imm{9} is acc, registers only. 230 template <AMDGPUDisassembler::OpWidthTy OpWidth> 231 static DecodeStatus decodeSrcAV10(MCInst &Inst, unsigned Imm, 232 uint64_t /* Addr */, 233 const MCDisassembler *Decoder) { 234 return decodeSrcOp(Inst, 10, OpWidth, Imm, Imm, false, 0, 235 AMDGPU::OperandSemantics::INT, Decoder); 236 } 237 238 // Decoder for RegisterOperands using 9-bit Src encoding. Operand can be 239 // register from RegClass or immediate. Registers that don't belong to RegClass 240 // will be decoded and InstPrinter will report warning. Immediate will be 241 // decoded into constant of size ImmWidth, should match width of immediate used 242 // by OperandType (important for floating point types). 243 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth, 244 unsigned OperandSemantics> 245 static DecodeStatus decodeSrcRegOrImm9(MCInst &Inst, unsigned Imm, 246 uint64_t /* Addr */, 247 const MCDisassembler *Decoder) { 248 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, false, ImmWidth, 249 (AMDGPU::OperandSemantics)OperandSemantics, Decoder); 250 } 251 252 // Decoder for Src(9-bit encoding) AGPR or immediate. Set Imm{9} to 1 (set acc) 253 // and decode using 'enum10' from decodeSrcOp. 254 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth, 255 unsigned OperandSemantics> 256 static DecodeStatus decodeSrcRegOrImmA9(MCInst &Inst, unsigned Imm, 257 uint64_t /* Addr */, 258 const MCDisassembler *Decoder) { 259 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm | 512, false, ImmWidth, 260 (AMDGPU::OperandSemantics)OperandSemantics, Decoder); 261 } 262 263 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth, 264 unsigned OperandSemantics> 265 static DecodeStatus decodeSrcRegOrImmDeferred9(MCInst &Inst, unsigned Imm, 266 uint64_t /* Addr */, 267 const MCDisassembler *Decoder) { 268 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, true, ImmWidth, 269 (AMDGPU::OperandSemantics)OperandSemantics, Decoder); 270 } 271 272 // Default decoders generated by tablegen: 'Decode<RegClass>RegisterClass' 273 // when RegisterClass is used as an operand. Most often used for destination 274 // operands. 275 276 DECODE_OPERAND_REG_8(VGPR_32) 277 DECODE_OPERAND_REG_8(VGPR_32_Lo128) 278 DECODE_OPERAND_REG_8(VReg_64) 279 DECODE_OPERAND_REG_8(VReg_96) 280 DECODE_OPERAND_REG_8(VReg_128) 281 DECODE_OPERAND_REG_8(VReg_256) 282 DECODE_OPERAND_REG_8(VReg_288) 283 DECODE_OPERAND_REG_8(VReg_352) 284 DECODE_OPERAND_REG_8(VReg_384) 285 DECODE_OPERAND_REG_8(VReg_512) 286 DECODE_OPERAND_REG_8(VReg_1024) 287 288 DECODE_OPERAND_REG_7(SReg_32, OPW32) 289 DECODE_OPERAND_REG_7(SReg_32_XEXEC, OPW32) 290 DECODE_OPERAND_REG_7(SReg_32_XM0_XEXEC, OPW32) 291 DECODE_OPERAND_REG_7(SReg_32_XEXEC_HI, OPW32) 292 DECODE_OPERAND_REG_7(SReg_64, OPW64) 293 DECODE_OPERAND_REG_7(SReg_64_XEXEC, OPW64) 294 DECODE_OPERAND_REG_7(SReg_64_XEXEC_XNULL, OPW64) 295 DECODE_OPERAND_REG_7(SReg_96, OPW96) 296 DECODE_OPERAND_REG_7(SReg_128, OPW128) 297 DECODE_OPERAND_REG_7(SReg_256, OPW256) 298 DECODE_OPERAND_REG_7(SReg_512, OPW512) 299 300 DECODE_OPERAND_REG_8(AGPR_32) 301 DECODE_OPERAND_REG_8(AReg_64) 302 DECODE_OPERAND_REG_8(AReg_128) 303 DECODE_OPERAND_REG_8(AReg_256) 304 DECODE_OPERAND_REG_8(AReg_512) 305 DECODE_OPERAND_REG_8(AReg_1024) 306 307 static DecodeStatus DecodeVGPR_16RegisterClass(MCInst &Inst, unsigned Imm, 308 uint64_t /*Addr*/, 309 const MCDisassembler *Decoder) { 310 assert(isUInt<10>(Imm) && "10-bit encoding expected"); 311 assert((Imm & (1 << 8)) == 0 && "Imm{8} should not be used"); 312 313 bool IsHi = Imm & (1 << 9); 314 unsigned RegIdx = Imm & 0xff; 315 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 316 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 317 } 318 319 static DecodeStatus 320 DecodeVGPR_16_Lo128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, 321 const MCDisassembler *Decoder) { 322 assert(isUInt<8>(Imm) && "8-bit encoding expected"); 323 324 bool IsHi = Imm & (1 << 7); 325 unsigned RegIdx = Imm & 0x7f; 326 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 327 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 328 } 329 330 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth, 331 unsigned OperandSemantics> 332 static DecodeStatus decodeOperand_VSrcT16_Lo128(MCInst &Inst, unsigned Imm, 333 uint64_t /*Addr*/, 334 const MCDisassembler *Decoder) { 335 assert(isUInt<9>(Imm) && "9-bit encoding expected"); 336 337 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 338 if (Imm & AMDGPU::EncValues::IS_VGPR) { 339 bool IsHi = Imm & (1 << 7); 340 unsigned RegIdx = Imm & 0x7f; 341 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 342 } 343 return addOperand(Inst, DAsm->decodeNonVGPRSrcOp( 344 OpWidth, Imm & 0xFF, false, ImmWidth, 345 (AMDGPU::OperandSemantics)OperandSemantics)); 346 } 347 348 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth, 349 unsigned OperandSemantics> 350 static DecodeStatus decodeOperand_VSrcT16(MCInst &Inst, unsigned Imm, 351 uint64_t /*Addr*/, 352 const MCDisassembler *Decoder) { 353 assert(isUInt<10>(Imm) && "10-bit encoding expected"); 354 355 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 356 if (Imm & AMDGPU::EncValues::IS_VGPR) { 357 bool IsHi = Imm & (1 << 9); 358 unsigned RegIdx = Imm & 0xff; 359 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 360 } 361 return addOperand(Inst, DAsm->decodeNonVGPRSrcOp( 362 OpWidth, Imm & 0xFF, false, ImmWidth, 363 (AMDGPU::OperandSemantics)OperandSemantics)); 364 } 365 366 static DecodeStatus decodeOperand_KImmFP(MCInst &Inst, unsigned Imm, 367 uint64_t Addr, 368 const MCDisassembler *Decoder) { 369 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 370 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 371 } 372 373 static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val, 374 uint64_t Addr, const void *Decoder) { 375 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 376 return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val)); 377 } 378 379 static bool IsAGPROperand(const MCInst &Inst, int OpIdx, 380 const MCRegisterInfo *MRI) { 381 if (OpIdx < 0) 382 return false; 383 384 const MCOperand &Op = Inst.getOperand(OpIdx); 385 if (!Op.isReg()) 386 return false; 387 388 MCRegister Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); 389 auto Reg = Sub ? Sub : Op.getReg(); 390 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; 391 } 392 393 static DecodeStatus decodeAVLdSt(MCInst &Inst, unsigned Imm, 394 AMDGPUDisassembler::OpWidthTy Opw, 395 const MCDisassembler *Decoder) { 396 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 397 if (!DAsm->isGFX90A()) { 398 Imm &= 511; 399 } else { 400 // If atomic has both vdata and vdst their register classes are tied. 401 // The bit is decoded along with the vdst, first operand. We need to 402 // change register class to AGPR if vdst was AGPR. 403 // If a DS instruction has both data0 and data1 their register classes 404 // are also tied. 405 unsigned Opc = Inst.getOpcode(); 406 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; 407 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 408 : AMDGPU::OpName::vdata; 409 const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo(); 410 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); 411 if ((int)Inst.getNumOperands() == DataIdx) { 412 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); 413 if (IsAGPROperand(Inst, DstIdx, MRI)) 414 Imm |= 512; 415 } 416 417 if (TSFlags & SIInstrFlags::DS) { 418 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); 419 if ((int)Inst.getNumOperands() == Data2Idx && 420 IsAGPROperand(Inst, DataIdx, MRI)) 421 Imm |= 512; 422 } 423 } 424 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); 425 } 426 427 template <AMDGPUDisassembler::OpWidthTy Opw> 428 static DecodeStatus decodeAVLdSt(MCInst &Inst, unsigned Imm, 429 uint64_t /* Addr */, 430 const MCDisassembler *Decoder) { 431 return decodeAVLdSt(Inst, Imm, Opw, Decoder); 432 } 433 434 static DecodeStatus decodeOperand_VSrc_f64(MCInst &Inst, unsigned Imm, 435 uint64_t Addr, 436 const MCDisassembler *Decoder) { 437 assert(Imm < (1 << 9) && "9-bit encoding"); 438 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 439 return addOperand(Inst, 440 DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm, false, 64, 441 AMDGPU::OperandSemantics::FP64)); 442 } 443 444 #define DECODE_SDWA(DecName) \ 445 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 446 447 DECODE_SDWA(Src32) 448 DECODE_SDWA(Src16) 449 DECODE_SDWA(VopcDst) 450 451 static DecodeStatus decodeVersionImm(MCInst &Inst, unsigned Imm, 452 uint64_t /* Addr */, 453 const MCDisassembler *Decoder) { 454 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 455 return addOperand(Inst, DAsm->decodeVersionImm(Imm)); 456 } 457 458 #include "AMDGPUGenDisassemblerTables.inc" 459 460 //===----------------------------------------------------------------------===// 461 // 462 //===----------------------------------------------------------------------===// 463 464 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 465 assert(Bytes.size() >= sizeof(T)); 466 const auto Res = 467 support::endian::read<T, llvm::endianness::little>(Bytes.data()); 468 Bytes = Bytes.slice(sizeof(T)); 469 return Res; 470 } 471 472 static inline DecoderUInt128 eat12Bytes(ArrayRef<uint8_t> &Bytes) { 473 assert(Bytes.size() >= 12); 474 uint64_t Lo = 475 support::endian::read<uint64_t, llvm::endianness::little>(Bytes.data()); 476 Bytes = Bytes.slice(8); 477 uint64_t Hi = 478 support::endian::read<uint32_t, llvm::endianness::little>(Bytes.data()); 479 Bytes = Bytes.slice(4); 480 return DecoderUInt128(Lo, Hi); 481 } 482 483 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 484 ArrayRef<uint8_t> Bytes_, 485 uint64_t Address, 486 raw_ostream &CS) const { 487 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 488 Bytes = Bytes_.slice(0, MaxInstBytesNum); 489 490 // In case the opcode is not recognized we'll assume a Size of 4 bytes (unless 491 // there are fewer bytes left). This will be overridden on success. 492 Size = std::min((size_t)4, Bytes_.size()); 493 494 do { 495 // ToDo: better to switch encoding length using some bit predicate 496 // but it is unknown yet, so try all we can 497 498 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 499 // encodings 500 if (isGFX11Plus() && Bytes.size() >= 12 ) { 501 DecoderUInt128 DecW = eat12Bytes(Bytes); 502 503 if (isGFX11() && 504 tryDecodeInst(DecoderTableGFX1196, DecoderTableGFX11_FAKE1696, MI, 505 DecW, Address, CS)) 506 break; 507 508 if (isGFX12() && 509 tryDecodeInst(DecoderTableGFX1296, DecoderTableGFX12_FAKE1696, MI, 510 DecW, Address, CS)) 511 break; 512 513 if (isGFX12() && 514 tryDecodeInst(DecoderTableGFX12W6496, MI, DecW, Address, CS)) 515 break; 516 517 // Reinitialize Bytes 518 Bytes = Bytes_.slice(0, MaxInstBytesNum); 519 } 520 521 if (Bytes.size() >= 8) { 522 const uint64_t QW = eatBytes<uint64_t>(Bytes); 523 524 if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding) && 525 tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address, CS)) 526 break; 527 528 if (STI.hasFeature(AMDGPU::FeatureUnpackedD16VMem) && 529 tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address, CS)) 530 break; 531 532 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 533 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 534 // table first so we print the correct name. 535 if (STI.hasFeature(AMDGPU::FeatureFmaMixInsts) && 536 tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address, CS)) 537 break; 538 539 if (STI.hasFeature(AMDGPU::FeatureGFX940Insts) && 540 tryDecodeInst(DecoderTableGFX94064, MI, QW, Address, CS)) 541 break; 542 543 if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts) && 544 tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address, CS)) 545 break; 546 547 if ((isVI() || isGFX9()) && 548 tryDecodeInst(DecoderTableGFX864, MI, QW, Address, CS)) 549 break; 550 551 if (isGFX9() && tryDecodeInst(DecoderTableGFX964, MI, QW, Address, CS)) 552 break; 553 554 if (isGFX10() && tryDecodeInst(DecoderTableGFX1064, MI, QW, Address, CS)) 555 break; 556 557 if (isGFX12() && 558 tryDecodeInst(DecoderTableGFX1264, DecoderTableGFX12_FAKE1664, MI, QW, 559 Address, CS)) 560 break; 561 562 if (isGFX11() && 563 tryDecodeInst(DecoderTableGFX1164, DecoderTableGFX11_FAKE1664, MI, QW, 564 Address, CS)) 565 break; 566 567 if (isGFX11() && 568 tryDecodeInst(DecoderTableGFX11W6464, MI, QW, Address, CS)) 569 break; 570 571 if (isGFX12() && 572 tryDecodeInst(DecoderTableGFX12W6464, MI, QW, Address, CS)) 573 break; 574 575 // Reinitialize Bytes 576 Bytes = Bytes_.slice(0, MaxInstBytesNum); 577 } 578 579 // Try decode 32-bit instruction 580 if (Bytes.size() >= 4) { 581 const uint32_t DW = eatBytes<uint32_t>(Bytes); 582 583 if ((isVI() || isGFX9()) && 584 tryDecodeInst(DecoderTableGFX832, MI, DW, Address, CS)) 585 break; 586 587 if (tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address, CS)) 588 break; 589 590 if (isGFX9() && tryDecodeInst(DecoderTableGFX932, MI, DW, Address, CS)) 591 break; 592 593 if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts) && 594 tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address, CS)) 595 break; 596 597 if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding) && 598 tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address, CS)) 599 break; 600 601 if (isGFX10() && tryDecodeInst(DecoderTableGFX1032, MI, DW, Address, CS)) 602 break; 603 604 if (isGFX11() && 605 tryDecodeInst(DecoderTableGFX1132, DecoderTableGFX11_FAKE1632, MI, DW, 606 Address, CS)) 607 break; 608 609 if (isGFX12() && 610 tryDecodeInst(DecoderTableGFX1232, DecoderTableGFX12_FAKE1632, MI, DW, 611 Address, CS)) 612 break; 613 } 614 615 return MCDisassembler::Fail; 616 } while (false); 617 618 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::DPP) { 619 if (isMacDPP(MI)) 620 convertMacDPPInst(MI); 621 622 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3P) 623 convertVOP3PDPPInst(MI); 624 else if ((MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC) || 625 AMDGPU::isVOPC64DPP(MI.getOpcode())) 626 convertVOPCDPPInst(MI); // Special VOP3 case 627 else if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) != 628 -1) 629 convertDPP8Inst(MI); 630 else if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3) 631 convertVOP3DPPInst(MI); // Regular VOP3 case 632 } 633 634 convertTrue16OpSel(MI); 635 636 if (AMDGPU::isMAC(MI.getOpcode())) { 637 // Insert dummy unused src2_modifiers. 638 insertNamedMCOperand(MI, MCOperand::createImm(0), 639 AMDGPU::OpName::src2_modifiers); 640 } 641 642 if (MI.getOpcode() == AMDGPU::V_CVT_SR_BF8_F32_e64_dpp || 643 MI.getOpcode() == AMDGPU::V_CVT_SR_FP8_F32_e64_dpp) { 644 // Insert dummy unused src2_modifiers. 645 insertNamedMCOperand(MI, MCOperand::createImm(0), 646 AMDGPU::OpName::src2_modifiers); 647 } 648 649 if ((MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::DS) && 650 !AMDGPU::hasGDS(STI)) { 651 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::gds); 652 } 653 654 if (MCII->get(MI.getOpcode()).TSFlags & 655 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT | SIInstrFlags::SMRD)) { 656 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 657 AMDGPU::OpName::cpol); 658 if (CPolPos != -1) { 659 unsigned CPol = 660 (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ? 661 AMDGPU::CPol::GLC : 0; 662 if (MI.getNumOperands() <= (unsigned)CPolPos) { 663 insertNamedMCOperand(MI, MCOperand::createImm(CPol), 664 AMDGPU::OpName::cpol); 665 } else if (CPol) { 666 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); 667 } 668 } 669 } 670 671 if ((MCII->get(MI.getOpcode()).TSFlags & 672 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) && 673 (STI.hasFeature(AMDGPU::FeatureGFX90AInsts))) { 674 // GFX90A lost TFE, its place is occupied by ACC. 675 int TFEOpIdx = 676 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); 677 if (TFEOpIdx != -1) { 678 auto TFEIter = MI.begin(); 679 std::advance(TFEIter, TFEOpIdx); 680 MI.insert(TFEIter, MCOperand::createImm(0)); 681 } 682 } 683 684 if (MCII->get(MI.getOpcode()).TSFlags & 685 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) { 686 int SWZOpIdx = 687 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); 688 if (SWZOpIdx != -1) { 689 auto SWZIter = MI.begin(); 690 std::advance(SWZIter, SWZOpIdx); 691 MI.insert(SWZIter, MCOperand::createImm(0)); 692 } 693 } 694 695 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG) { 696 int VAddr0Idx = 697 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 698 int RsrcIdx = 699 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 700 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 701 if (VAddr0Idx >= 0 && NSAArgs > 0) { 702 unsigned NSAWords = (NSAArgs + 3) / 4; 703 if (Bytes.size() < 4 * NSAWords) 704 return MCDisassembler::Fail; 705 for (unsigned i = 0; i < NSAArgs; ++i) { 706 const unsigned VAddrIdx = VAddr0Idx + 1 + i; 707 auto VAddrRCID = 708 MCII->get(MI.getOpcode()).operands()[VAddrIdx].RegClass; 709 MI.insert(MI.begin() + VAddrIdx, createRegOperand(VAddrRCID, Bytes[i])); 710 } 711 Bytes = Bytes.slice(4 * NSAWords); 712 } 713 714 convertMIMGInst(MI); 715 } 716 717 if (MCII->get(MI.getOpcode()).TSFlags & 718 (SIInstrFlags::VIMAGE | SIInstrFlags::VSAMPLE)) 719 convertMIMGInst(MI); 720 721 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::EXP) 722 convertEXPInst(MI); 723 724 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VINTERP) 725 convertVINTERPInst(MI); 726 727 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::SDWA) 728 convertSDWAInst(MI); 729 730 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 731 AMDGPU::OpName::vdst_in); 732 if (VDstIn_Idx != -1) { 733 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 734 MCOI::OperandConstraint::TIED_TO); 735 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 736 !MI.getOperand(VDstIn_Idx).isReg() || 737 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 738 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 739 MI.erase(&MI.getOperand(VDstIn_Idx)); 740 insertNamedMCOperand(MI, 741 MCOperand::createReg(MI.getOperand(Tied).getReg()), 742 AMDGPU::OpName::vdst_in); 743 } 744 } 745 746 int ImmLitIdx = 747 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm); 748 bool IsSOPK = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::SOPK; 749 if (ImmLitIdx != -1 && !IsSOPK) 750 convertFMAanyK(MI, ImmLitIdx); 751 752 Size = MaxInstBytesNum - Bytes.size(); 753 return MCDisassembler::Success; 754 } 755 756 void AMDGPUDisassembler::convertEXPInst(MCInst &MI) const { 757 if (STI.hasFeature(AMDGPU::FeatureGFX11Insts)) { 758 // The MCInst still has these fields even though they are no longer encoded 759 // in the GFX11 instruction. 760 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vm); 761 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::compr); 762 } 763 } 764 765 void AMDGPUDisassembler::convertVINTERPInst(MCInst &MI) const { 766 if (MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx11 || 767 MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx12 || 768 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx11 || 769 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx12 || 770 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx11 || 771 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx12 || 772 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx11 || 773 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx12) { 774 // The MCInst has this field that is not directly encoded in the 775 // instruction. 776 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::op_sel); 777 } 778 } 779 780 void AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 781 if (STI.hasFeature(AMDGPU::FeatureGFX9) || 782 STI.hasFeature(AMDGPU::FeatureGFX10)) { 783 if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::sdst)) 784 // VOPC - insert clamp 785 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 786 } else if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) { 787 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 788 if (SDst != -1) { 789 // VOPC - insert VCC register as sdst 790 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 791 AMDGPU::OpName::sdst); 792 } else { 793 // VOP1/2 - insert omod if present in instruction 794 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 795 } 796 } 797 } 798 799 struct VOPModifiers { 800 unsigned OpSel = 0; 801 unsigned OpSelHi = 0; 802 unsigned NegLo = 0; 803 unsigned NegHi = 0; 804 }; 805 806 // Reconstruct values of VOP3/VOP3P operands such as op_sel. 807 // Note that these values do not affect disassembler output, 808 // so this is only necessary for consistency with src_modifiers. 809 static VOPModifiers collectVOPModifiers(const MCInst &MI, 810 bool IsVOP3P = false) { 811 VOPModifiers Modifiers; 812 unsigned Opc = MI.getOpcode(); 813 const int ModOps[] = {AMDGPU::OpName::src0_modifiers, 814 AMDGPU::OpName::src1_modifiers, 815 AMDGPU::OpName::src2_modifiers}; 816 for (int J = 0; J < 3; ++J) { 817 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]); 818 if (OpIdx == -1) 819 continue; 820 821 unsigned Val = MI.getOperand(OpIdx).getImm(); 822 823 Modifiers.OpSel |= !!(Val & SISrcMods::OP_SEL_0) << J; 824 if (IsVOP3P) { 825 Modifiers.OpSelHi |= !!(Val & SISrcMods::OP_SEL_1) << J; 826 Modifiers.NegLo |= !!(Val & SISrcMods::NEG) << J; 827 Modifiers.NegHi |= !!(Val & SISrcMods::NEG_HI) << J; 828 } else if (J == 0) { 829 Modifiers.OpSel |= !!(Val & SISrcMods::DST_OP_SEL) << 3; 830 } 831 } 832 833 return Modifiers; 834 } 835 836 // Instructions decode the op_sel/suffix bits into the src_modifier 837 // operands. Copy those bits into the src operands for true16 VGPRs. 838 void AMDGPUDisassembler::convertTrue16OpSel(MCInst &MI) const { 839 const unsigned Opc = MI.getOpcode(); 840 const MCRegisterClass &ConversionRC = 841 MRI.getRegClass(AMDGPU::VGPR_16RegClassID); 842 constexpr std::array<std::tuple<int, int, unsigned>, 4> OpAndOpMods = { 843 {{AMDGPU::OpName::src0, AMDGPU::OpName::src0_modifiers, 844 SISrcMods::OP_SEL_0}, 845 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_modifiers, 846 SISrcMods::OP_SEL_0}, 847 {AMDGPU::OpName::src2, AMDGPU::OpName::src2_modifiers, 848 SISrcMods::OP_SEL_0}, 849 {AMDGPU::OpName::vdst, AMDGPU::OpName::src0_modifiers, 850 SISrcMods::DST_OP_SEL}}}; 851 for (const auto &[OpName, OpModsName, OpSelMask] : OpAndOpMods) { 852 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, OpName); 853 int OpModsIdx = AMDGPU::getNamedOperandIdx(Opc, OpModsName); 854 if (OpIdx == -1 || OpModsIdx == -1) 855 continue; 856 MCOperand &Op = MI.getOperand(OpIdx); 857 if (!Op.isReg()) 858 continue; 859 if (!ConversionRC.contains(Op.getReg())) 860 continue; 861 unsigned OpEnc = MRI.getEncodingValue(Op.getReg()); 862 const MCOperand &OpMods = MI.getOperand(OpModsIdx); 863 unsigned ModVal = OpMods.getImm(); 864 if (ModVal & OpSelMask) { // isHi 865 unsigned RegIdx = OpEnc & AMDGPU::HWEncoding::REG_IDX_MASK; 866 Op.setReg(ConversionRC.getRegister(RegIdx * 2 + 1)); 867 } 868 } 869 } 870 871 // MAC opcodes have special old and src2 operands. 872 // src2 is tied to dst, while old is not tied (but assumed to be). 873 bool AMDGPUDisassembler::isMacDPP(MCInst &MI) const { 874 constexpr int DST_IDX = 0; 875 auto Opcode = MI.getOpcode(); 876 const auto &Desc = MCII->get(Opcode); 877 auto OldIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::old); 878 879 if (OldIdx != -1 && Desc.getOperandConstraint( 880 OldIdx, MCOI::OperandConstraint::TIED_TO) == -1) { 881 assert(AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src2)); 882 assert(Desc.getOperandConstraint( 883 AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2), 884 MCOI::OperandConstraint::TIED_TO) == DST_IDX); 885 (void)DST_IDX; 886 return true; 887 } 888 889 return false; 890 } 891 892 // Create dummy old operand and insert dummy unused src2_modifiers 893 void AMDGPUDisassembler::convertMacDPPInst(MCInst &MI) const { 894 assert(MI.getNumOperands() + 1 < MCII->get(MI.getOpcode()).getNumOperands()); 895 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 896 insertNamedMCOperand(MI, MCOperand::createImm(0), 897 AMDGPU::OpName::src2_modifiers); 898 } 899 900 void AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 901 unsigned Opc = MI.getOpcode(); 902 903 int VDstInIdx = 904 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst_in); 905 if (VDstInIdx != -1) 906 insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::vdst_in); 907 908 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 909 if (MI.getNumOperands() < DescNumOps && 910 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { 911 convertTrue16OpSel(MI); 912 auto Mods = collectVOPModifiers(MI); 913 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 914 AMDGPU::OpName::op_sel); 915 } else { 916 // Insert dummy unused src modifiers. 917 if (MI.getNumOperands() < DescNumOps && 918 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) 919 insertNamedMCOperand(MI, MCOperand::createImm(0), 920 AMDGPU::OpName::src0_modifiers); 921 922 if (MI.getNumOperands() < DescNumOps && 923 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers)) 924 insertNamedMCOperand(MI, MCOperand::createImm(0), 925 AMDGPU::OpName::src1_modifiers); 926 } 927 } 928 929 void AMDGPUDisassembler::convertVOP3DPPInst(MCInst &MI) const { 930 convertTrue16OpSel(MI); 931 932 int VDstInIdx = 933 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst_in); 934 if (VDstInIdx != -1) 935 insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::vdst_in); 936 937 unsigned Opc = MI.getOpcode(); 938 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 939 if (MI.getNumOperands() < DescNumOps && 940 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { 941 auto Mods = collectVOPModifiers(MI); 942 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 943 AMDGPU::OpName::op_sel); 944 } 945 } 946 947 // Note that before gfx10, the MIMG encoding provided no information about 948 // VADDR size. Consequently, decoded instructions always show address as if it 949 // has 1 dword, which could be not really so. 950 void AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 951 auto TSFlags = MCII->get(MI.getOpcode()).TSFlags; 952 953 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 954 AMDGPU::OpName::vdst); 955 956 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 957 AMDGPU::OpName::vdata); 958 int VAddr0Idx = 959 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 960 int RsrcOpName = (TSFlags & SIInstrFlags::MIMG) ? AMDGPU::OpName::srsrc 961 : AMDGPU::OpName::rsrc; 962 int RsrcIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), RsrcOpName); 963 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 964 AMDGPU::OpName::dmask); 965 966 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 967 AMDGPU::OpName::tfe); 968 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 969 AMDGPU::OpName::d16); 970 971 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 972 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 973 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 974 975 assert(VDataIdx != -1); 976 if (BaseOpcode->BVH) { 977 // Add A16 operand for intersect_ray instructions 978 addOperand(MI, MCOperand::createImm(BaseOpcode->A16)); 979 return; 980 } 981 982 bool IsAtomic = (VDstIdx != -1); 983 bool IsGather4 = TSFlags & SIInstrFlags::Gather4; 984 bool IsVSample = TSFlags & SIInstrFlags::VSAMPLE; 985 bool IsNSA = false; 986 bool IsPartialNSA = false; 987 unsigned AddrSize = Info->VAddrDwords; 988 989 if (isGFX10Plus()) { 990 unsigned DimIdx = 991 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 992 int A16Idx = 993 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16); 994 const AMDGPU::MIMGDimInfo *Dim = 995 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 996 const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm()); 997 998 AddrSize = 999 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); 1000 1001 // VSAMPLE insts that do not use vaddr3 behave the same as NSA forms. 1002 // VIMAGE insts other than BVH never use vaddr4. 1003 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA || 1004 Info->MIMGEncoding == AMDGPU::MIMGEncGfx11NSA || 1005 Info->MIMGEncoding == AMDGPU::MIMGEncGfx12; 1006 if (!IsNSA) { 1007 if (!IsVSample && AddrSize > 12) 1008 AddrSize = 16; 1009 } else { 1010 if (AddrSize > Info->VAddrDwords) { 1011 if (!STI.hasFeature(AMDGPU::FeaturePartialNSAEncoding)) { 1012 // The NSA encoding does not contain enough operands for the 1013 // combination of base opcode / dimension. Should this be an error? 1014 return; 1015 } 1016 IsPartialNSA = true; 1017 } 1018 } 1019 } 1020 1021 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 1022 unsigned DstSize = IsGather4 ? 4 : std::max(llvm::popcount(DMask), 1); 1023 1024 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 1025 if (D16 && AMDGPU::hasPackedD16(STI)) { 1026 DstSize = (DstSize + 1) / 2; 1027 } 1028 1029 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm()) 1030 DstSize += 1; 1031 1032 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 1033 return; 1034 1035 int NewOpcode = 1036 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 1037 if (NewOpcode == -1) 1038 return; 1039 1040 // Widen the register to the correct number of enabled channels. 1041 unsigned NewVdata = AMDGPU::NoRegister; 1042 if (DstSize != Info->VDataDwords) { 1043 auto DataRCID = MCII->get(NewOpcode).operands()[VDataIdx].RegClass; 1044 1045 // Get first subregister of VData 1046 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 1047 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 1048 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 1049 1050 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 1051 &MRI.getRegClass(DataRCID)); 1052 if (NewVdata == AMDGPU::NoRegister) { 1053 // It's possible to encode this such that the low register + enabled 1054 // components exceeds the register count. 1055 return; 1056 } 1057 } 1058 1059 // If not using NSA on GFX10+, widen vaddr0 address register to correct size. 1060 // If using partial NSA on GFX11+ widen last address register. 1061 int VAddrSAIdx = IsPartialNSA ? (RsrcIdx - 1) : VAddr0Idx; 1062 unsigned NewVAddrSA = AMDGPU::NoRegister; 1063 if (STI.hasFeature(AMDGPU::FeatureNSAEncoding) && (!IsNSA || IsPartialNSA) && 1064 AddrSize != Info->VAddrDwords) { 1065 unsigned VAddrSA = MI.getOperand(VAddrSAIdx).getReg(); 1066 unsigned VAddrSubSA = MRI.getSubReg(VAddrSA, AMDGPU::sub0); 1067 VAddrSA = VAddrSubSA ? VAddrSubSA : VAddrSA; 1068 1069 auto AddrRCID = MCII->get(NewOpcode).operands()[VAddrSAIdx].RegClass; 1070 NewVAddrSA = MRI.getMatchingSuperReg(VAddrSA, AMDGPU::sub0, 1071 &MRI.getRegClass(AddrRCID)); 1072 if (!NewVAddrSA) 1073 return; 1074 } 1075 1076 MI.setOpcode(NewOpcode); 1077 1078 if (NewVdata != AMDGPU::NoRegister) { 1079 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 1080 1081 if (IsAtomic) { 1082 // Atomic operations have an additional operand (a copy of data) 1083 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 1084 } 1085 } 1086 1087 if (NewVAddrSA) { 1088 MI.getOperand(VAddrSAIdx) = MCOperand::createReg(NewVAddrSA); 1089 } else if (IsNSA) { 1090 assert(AddrSize <= Info->VAddrDwords); 1091 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 1092 MI.begin() + VAddr0Idx + Info->VAddrDwords); 1093 } 1094 } 1095 1096 // Opsel and neg bits are used in src_modifiers and standalone operands. Autogen 1097 // decoder only adds to src_modifiers, so manually add the bits to the other 1098 // operands. 1099 void AMDGPUDisassembler::convertVOP3PDPPInst(MCInst &MI) const { 1100 unsigned Opc = MI.getOpcode(); 1101 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1102 auto Mods = collectVOPModifiers(MI, true); 1103 1104 if (MI.getNumOperands() < DescNumOps && 1105 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vdst_in)) 1106 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vdst_in); 1107 1108 if (MI.getNumOperands() < DescNumOps && 1109 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) 1110 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 1111 AMDGPU::OpName::op_sel); 1112 if (MI.getNumOperands() < DescNumOps && 1113 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel_hi)) 1114 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSelHi), 1115 AMDGPU::OpName::op_sel_hi); 1116 if (MI.getNumOperands() < DescNumOps && 1117 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_lo)) 1118 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegLo), 1119 AMDGPU::OpName::neg_lo); 1120 if (MI.getNumOperands() < DescNumOps && 1121 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_hi)) 1122 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegHi), 1123 AMDGPU::OpName::neg_hi); 1124 } 1125 1126 // Create dummy old operand and insert optional operands 1127 void AMDGPUDisassembler::convertVOPCDPPInst(MCInst &MI) const { 1128 unsigned Opc = MI.getOpcode(); 1129 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1130 1131 if (MI.getNumOperands() < DescNumOps && 1132 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::old)) 1133 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 1134 1135 if (MI.getNumOperands() < DescNumOps && 1136 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) 1137 insertNamedMCOperand(MI, MCOperand::createImm(0), 1138 AMDGPU::OpName::src0_modifiers); 1139 1140 if (MI.getNumOperands() < DescNumOps && 1141 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers)) 1142 insertNamedMCOperand(MI, MCOperand::createImm(0), 1143 AMDGPU::OpName::src1_modifiers); 1144 } 1145 1146 void AMDGPUDisassembler::convertFMAanyK(MCInst &MI, int ImmLitIdx) const { 1147 assert(HasLiteral && "Should have decoded a literal"); 1148 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 1149 unsigned DescNumOps = Desc.getNumOperands(); 1150 insertNamedMCOperand(MI, MCOperand::createImm(Literal), 1151 AMDGPU::OpName::immDeferred); 1152 assert(DescNumOps == MI.getNumOperands()); 1153 for (unsigned I = 0; I < DescNumOps; ++I) { 1154 auto &Op = MI.getOperand(I); 1155 auto OpType = Desc.operands()[I].OperandType; 1156 bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED || 1157 OpType == AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED); 1158 if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST && 1159 IsDeferredOp) 1160 Op.setImm(Literal); 1161 } 1162 } 1163 1164 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 1165 return getContext().getRegisterInfo()-> 1166 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 1167 } 1168 1169 inline 1170 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 1171 const Twine& ErrMsg) const { 1172 *CommentStream << "Error: " + ErrMsg; 1173 1174 // ToDo: add support for error operands to MCInst.h 1175 // return MCOperand::createError(V); 1176 return MCOperand(); 1177 } 1178 1179 inline 1180 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 1181 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 1182 } 1183 1184 inline 1185 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 1186 unsigned Val) const { 1187 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 1188 if (Val >= RegCl.getNumRegs()) 1189 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 1190 ": unknown register " + Twine(Val)); 1191 return createRegOperand(RegCl.getRegister(Val)); 1192 } 1193 1194 inline 1195 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 1196 unsigned Val) const { 1197 // ToDo: SI/CI have 104 SGPRs, VI - 102 1198 // Valery: here we accepting as much as we can, let assembler sort it out 1199 int shift = 0; 1200 switch (SRegClassID) { 1201 case AMDGPU::SGPR_32RegClassID: 1202 case AMDGPU::TTMP_32RegClassID: 1203 break; 1204 case AMDGPU::SGPR_64RegClassID: 1205 case AMDGPU::TTMP_64RegClassID: 1206 shift = 1; 1207 break; 1208 case AMDGPU::SGPR_96RegClassID: 1209 case AMDGPU::TTMP_96RegClassID: 1210 case AMDGPU::SGPR_128RegClassID: 1211 case AMDGPU::TTMP_128RegClassID: 1212 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 1213 // this bundle? 1214 case AMDGPU::SGPR_256RegClassID: 1215 case AMDGPU::TTMP_256RegClassID: 1216 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 1217 // this bundle? 1218 case AMDGPU::SGPR_288RegClassID: 1219 case AMDGPU::TTMP_288RegClassID: 1220 case AMDGPU::SGPR_320RegClassID: 1221 case AMDGPU::TTMP_320RegClassID: 1222 case AMDGPU::SGPR_352RegClassID: 1223 case AMDGPU::TTMP_352RegClassID: 1224 case AMDGPU::SGPR_384RegClassID: 1225 case AMDGPU::TTMP_384RegClassID: 1226 case AMDGPU::SGPR_512RegClassID: 1227 case AMDGPU::TTMP_512RegClassID: 1228 shift = 2; 1229 break; 1230 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 1231 // this bundle? 1232 default: 1233 llvm_unreachable("unhandled register class"); 1234 } 1235 1236 if (Val % (1 << shift)) { 1237 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 1238 << ": scalar reg isn't aligned " << Val; 1239 } 1240 1241 return createRegOperand(SRegClassID, Val >> shift); 1242 } 1243 1244 MCOperand AMDGPUDisassembler::createVGPR16Operand(unsigned RegIdx, 1245 bool IsHi) const { 1246 unsigned RegIdxInVGPR16 = RegIdx * 2 + (IsHi ? 1 : 0); 1247 return createRegOperand(AMDGPU::VGPR_16RegClassID, RegIdxInVGPR16); 1248 } 1249 1250 // Decode Literals for insts which always have a literal in the encoding 1251 MCOperand 1252 AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const { 1253 if (HasLiteral) { 1254 assert( 1255 AMDGPU::hasVOPD(STI) && 1256 "Should only decode multiple kimm with VOPD, check VSrc operand types"); 1257 if (Literal != Val) 1258 return errOperand(Val, "More than one unique literal is illegal"); 1259 } 1260 HasLiteral = true; 1261 Literal = Val; 1262 return MCOperand::createImm(Literal); 1263 } 1264 1265 MCOperand AMDGPUDisassembler::decodeLiteralConstant(bool ExtendFP64) const { 1266 // For now all literal constants are supposed to be unsigned integer 1267 // ToDo: deal with signed/unsigned 64-bit integer constants 1268 // ToDo: deal with float/double constants 1269 if (!HasLiteral) { 1270 if (Bytes.size() < 4) { 1271 return errOperand(0, "cannot read literal, inst bytes left " + 1272 Twine(Bytes.size())); 1273 } 1274 HasLiteral = true; 1275 Literal = Literal64 = eatBytes<uint32_t>(Bytes); 1276 if (ExtendFP64) 1277 Literal64 <<= 32; 1278 } 1279 return MCOperand::createImm(ExtendFP64 ? Literal64 : Literal); 1280 } 1281 1282 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 1283 using namespace AMDGPU::EncValues; 1284 1285 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 1286 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 1287 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 1288 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 1289 // Cast prevents negative overflow. 1290 } 1291 1292 static int64_t getInlineImmVal32(unsigned Imm) { 1293 switch (Imm) { 1294 case 240: 1295 return llvm::bit_cast<uint32_t>(0.5f); 1296 case 241: 1297 return llvm::bit_cast<uint32_t>(-0.5f); 1298 case 242: 1299 return llvm::bit_cast<uint32_t>(1.0f); 1300 case 243: 1301 return llvm::bit_cast<uint32_t>(-1.0f); 1302 case 244: 1303 return llvm::bit_cast<uint32_t>(2.0f); 1304 case 245: 1305 return llvm::bit_cast<uint32_t>(-2.0f); 1306 case 246: 1307 return llvm::bit_cast<uint32_t>(4.0f); 1308 case 247: 1309 return llvm::bit_cast<uint32_t>(-4.0f); 1310 case 248: // 1 / (2 * PI) 1311 return 0x3e22f983; 1312 default: 1313 llvm_unreachable("invalid fp inline imm"); 1314 } 1315 } 1316 1317 static int64_t getInlineImmVal64(unsigned Imm) { 1318 switch (Imm) { 1319 case 240: 1320 return llvm::bit_cast<uint64_t>(0.5); 1321 case 241: 1322 return llvm::bit_cast<uint64_t>(-0.5); 1323 case 242: 1324 return llvm::bit_cast<uint64_t>(1.0); 1325 case 243: 1326 return llvm::bit_cast<uint64_t>(-1.0); 1327 case 244: 1328 return llvm::bit_cast<uint64_t>(2.0); 1329 case 245: 1330 return llvm::bit_cast<uint64_t>(-2.0); 1331 case 246: 1332 return llvm::bit_cast<uint64_t>(4.0); 1333 case 247: 1334 return llvm::bit_cast<uint64_t>(-4.0); 1335 case 248: // 1 / (2 * PI) 1336 return 0x3fc45f306dc9c882; 1337 default: 1338 llvm_unreachable("invalid fp inline imm"); 1339 } 1340 } 1341 1342 static int64_t getInlineImmValF16(unsigned Imm) { 1343 switch (Imm) { 1344 case 240: 1345 return 0x3800; 1346 case 241: 1347 return 0xB800; 1348 case 242: 1349 return 0x3C00; 1350 case 243: 1351 return 0xBC00; 1352 case 244: 1353 return 0x4000; 1354 case 245: 1355 return 0xC000; 1356 case 246: 1357 return 0x4400; 1358 case 247: 1359 return 0xC400; 1360 case 248: // 1 / (2 * PI) 1361 return 0x3118; 1362 default: 1363 llvm_unreachable("invalid fp inline imm"); 1364 } 1365 } 1366 1367 static int64_t getInlineImmValBF16(unsigned Imm) { 1368 switch (Imm) { 1369 case 240: 1370 return 0x3F00; 1371 case 241: 1372 return 0xBF00; 1373 case 242: 1374 return 0x3F80; 1375 case 243: 1376 return 0xBF80; 1377 case 244: 1378 return 0x4000; 1379 case 245: 1380 return 0xC000; 1381 case 246: 1382 return 0x4080; 1383 case 247: 1384 return 0xC080; 1385 case 248: // 1 / (2 * PI) 1386 return 0x3E22; 1387 default: 1388 llvm_unreachable("invalid fp inline imm"); 1389 } 1390 } 1391 1392 static int64_t getInlineImmVal16(unsigned Imm, AMDGPU::OperandSemantics Sema) { 1393 return (Sema == AMDGPU::OperandSemantics::BF16) ? getInlineImmValBF16(Imm) 1394 : getInlineImmValF16(Imm); 1395 } 1396 1397 MCOperand AMDGPUDisassembler::decodeFPImmed(unsigned ImmWidth, unsigned Imm, 1398 AMDGPU::OperandSemantics Sema) { 1399 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN && 1400 Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 1401 1402 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 1403 // ImmWidth 0 is a default case where operand should not allow immediates. 1404 // Imm value is still decoded into 32 bit immediate operand, inst printer will 1405 // use it to print verbose error message. 1406 switch (ImmWidth) { 1407 case 0: 1408 case 32: 1409 return MCOperand::createImm(getInlineImmVal32(Imm)); 1410 case 64: 1411 return MCOperand::createImm(getInlineImmVal64(Imm)); 1412 case 16: 1413 return MCOperand::createImm(getInlineImmVal16(Imm, Sema)); 1414 default: 1415 llvm_unreachable("implement me"); 1416 } 1417 } 1418 1419 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 1420 using namespace AMDGPU; 1421 1422 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1423 switch (Width) { 1424 default: // fall 1425 case OPW32: 1426 case OPW16: 1427 case OPWV216: 1428 return VGPR_32RegClassID; 1429 case OPW64: 1430 case OPWV232: return VReg_64RegClassID; 1431 case OPW96: return VReg_96RegClassID; 1432 case OPW128: return VReg_128RegClassID; 1433 case OPW160: return VReg_160RegClassID; 1434 case OPW256: return VReg_256RegClassID; 1435 case OPW288: return VReg_288RegClassID; 1436 case OPW320: return VReg_320RegClassID; 1437 case OPW352: return VReg_352RegClassID; 1438 case OPW384: return VReg_384RegClassID; 1439 case OPW512: return VReg_512RegClassID; 1440 case OPW1024: return VReg_1024RegClassID; 1441 } 1442 } 1443 1444 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 1445 using namespace AMDGPU; 1446 1447 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1448 switch (Width) { 1449 default: // fall 1450 case OPW32: 1451 case OPW16: 1452 case OPWV216: 1453 return AGPR_32RegClassID; 1454 case OPW64: 1455 case OPWV232: return AReg_64RegClassID; 1456 case OPW96: return AReg_96RegClassID; 1457 case OPW128: return AReg_128RegClassID; 1458 case OPW160: return AReg_160RegClassID; 1459 case OPW256: return AReg_256RegClassID; 1460 case OPW288: return AReg_288RegClassID; 1461 case OPW320: return AReg_320RegClassID; 1462 case OPW352: return AReg_352RegClassID; 1463 case OPW384: return AReg_384RegClassID; 1464 case OPW512: return AReg_512RegClassID; 1465 case OPW1024: return AReg_1024RegClassID; 1466 } 1467 } 1468 1469 1470 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 1471 using namespace AMDGPU; 1472 1473 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1474 switch (Width) { 1475 default: // fall 1476 case OPW32: 1477 case OPW16: 1478 case OPWV216: 1479 return SGPR_32RegClassID; 1480 case OPW64: 1481 case OPWV232: return SGPR_64RegClassID; 1482 case OPW96: return SGPR_96RegClassID; 1483 case OPW128: return SGPR_128RegClassID; 1484 case OPW160: return SGPR_160RegClassID; 1485 case OPW256: return SGPR_256RegClassID; 1486 case OPW288: return SGPR_288RegClassID; 1487 case OPW320: return SGPR_320RegClassID; 1488 case OPW352: return SGPR_352RegClassID; 1489 case OPW384: return SGPR_384RegClassID; 1490 case OPW512: return SGPR_512RegClassID; 1491 } 1492 } 1493 1494 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 1495 using namespace AMDGPU; 1496 1497 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1498 switch (Width) { 1499 default: // fall 1500 case OPW32: 1501 case OPW16: 1502 case OPWV216: 1503 return TTMP_32RegClassID; 1504 case OPW64: 1505 case OPWV232: return TTMP_64RegClassID; 1506 case OPW128: return TTMP_128RegClassID; 1507 case OPW256: return TTMP_256RegClassID; 1508 case OPW288: return TTMP_288RegClassID; 1509 case OPW320: return TTMP_320RegClassID; 1510 case OPW352: return TTMP_352RegClassID; 1511 case OPW384: return TTMP_384RegClassID; 1512 case OPW512: return TTMP_512RegClassID; 1513 } 1514 } 1515 1516 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 1517 using namespace AMDGPU::EncValues; 1518 1519 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN; 1520 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX; 1521 1522 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1523 } 1524 1525 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val, 1526 bool MandatoryLiteral, 1527 unsigned ImmWidth, 1528 AMDGPU::OperandSemantics Sema) const { 1529 using namespace AMDGPU::EncValues; 1530 1531 assert(Val < 1024); // enum10 1532 1533 bool IsAGPR = Val & 512; 1534 Val &= 511; 1535 1536 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1537 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1538 : getVgprClassId(Width), Val - VGPR_MIN); 1539 } 1540 return decodeNonVGPRSrcOp(Width, Val & 0xFF, MandatoryLiteral, ImmWidth, 1541 Sema); 1542 } 1543 1544 MCOperand 1545 AMDGPUDisassembler::decodeNonVGPRSrcOp(const OpWidthTy Width, unsigned Val, 1546 bool MandatoryLiteral, unsigned ImmWidth, 1547 AMDGPU::OperandSemantics Sema) const { 1548 // Cases when Val{8} is 1 (vgpr, agpr or true 16 vgpr) should have been 1549 // decoded earlier. 1550 assert(Val < (1 << 8) && "9-bit Src encoding when Val{8} is 0"); 1551 using namespace AMDGPU::EncValues; 1552 1553 if (Val <= SGPR_MAX) { 1554 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1555 static_assert(SGPR_MIN == 0); 1556 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1557 } 1558 1559 int TTmpIdx = getTTmpIdx(Val); 1560 if (TTmpIdx >= 0) { 1561 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1562 } 1563 1564 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1565 return decodeIntImmed(Val); 1566 1567 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1568 return decodeFPImmed(ImmWidth, Val, Sema); 1569 1570 if (Val == LITERAL_CONST) { 1571 if (MandatoryLiteral) 1572 // Keep a sentinel value for deferred setting 1573 return MCOperand::createImm(LITERAL_CONST); 1574 return decodeLiteralConstant(Sema == AMDGPU::OperandSemantics::FP64); 1575 } 1576 1577 switch (Width) { 1578 case OPW32: 1579 case OPW16: 1580 case OPWV216: 1581 return decodeSpecialReg32(Val); 1582 case OPW64: 1583 case OPWV232: 1584 return decodeSpecialReg64(Val); 1585 default: 1586 llvm_unreachable("unexpected immediate type"); 1587 } 1588 } 1589 1590 // Bit 0 of DstY isn't stored in the instruction, because it's always the 1591 // opposite of bit 0 of DstX. 1592 MCOperand AMDGPUDisassembler::decodeVOPDDstYOp(MCInst &Inst, 1593 unsigned Val) const { 1594 int VDstXInd = 1595 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::vdstX); 1596 assert(VDstXInd != -1); 1597 assert(Inst.getOperand(VDstXInd).isReg()); 1598 unsigned XDstReg = MRI.getEncodingValue(Inst.getOperand(VDstXInd).getReg()); 1599 Val |= ~XDstReg & 1; 1600 auto Width = llvm::AMDGPUDisassembler::OPW32; 1601 return createRegOperand(getVgprClassId(Width), Val); 1602 } 1603 1604 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1605 using namespace AMDGPU; 1606 1607 switch (Val) { 1608 // clang-format off 1609 case 102: return createRegOperand(FLAT_SCR_LO); 1610 case 103: return createRegOperand(FLAT_SCR_HI); 1611 case 104: return createRegOperand(XNACK_MASK_LO); 1612 case 105: return createRegOperand(XNACK_MASK_HI); 1613 case 106: return createRegOperand(VCC_LO); 1614 case 107: return createRegOperand(VCC_HI); 1615 case 108: return createRegOperand(TBA_LO); 1616 case 109: return createRegOperand(TBA_HI); 1617 case 110: return createRegOperand(TMA_LO); 1618 case 111: return createRegOperand(TMA_HI); 1619 case 124: 1620 return isGFX11Plus() ? createRegOperand(SGPR_NULL) : createRegOperand(M0); 1621 case 125: 1622 return isGFX11Plus() ? createRegOperand(M0) : createRegOperand(SGPR_NULL); 1623 case 126: return createRegOperand(EXEC_LO); 1624 case 127: return createRegOperand(EXEC_HI); 1625 case 235: return createRegOperand(SRC_SHARED_BASE_LO); 1626 case 236: return createRegOperand(SRC_SHARED_LIMIT_LO); 1627 case 237: return createRegOperand(SRC_PRIVATE_BASE_LO); 1628 case 238: return createRegOperand(SRC_PRIVATE_LIMIT_LO); 1629 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1630 case 251: return createRegOperand(SRC_VCCZ); 1631 case 252: return createRegOperand(SRC_EXECZ); 1632 case 253: return createRegOperand(SRC_SCC); 1633 case 254: return createRegOperand(LDS_DIRECT); 1634 default: break; 1635 // clang-format on 1636 } 1637 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1638 } 1639 1640 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1641 using namespace AMDGPU; 1642 1643 switch (Val) { 1644 case 102: return createRegOperand(FLAT_SCR); 1645 case 104: return createRegOperand(XNACK_MASK); 1646 case 106: return createRegOperand(VCC); 1647 case 108: return createRegOperand(TBA); 1648 case 110: return createRegOperand(TMA); 1649 case 124: 1650 if (isGFX11Plus()) 1651 return createRegOperand(SGPR_NULL); 1652 break; 1653 case 125: 1654 if (!isGFX11Plus()) 1655 return createRegOperand(SGPR_NULL); 1656 break; 1657 case 126: return createRegOperand(EXEC); 1658 case 235: return createRegOperand(SRC_SHARED_BASE); 1659 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1660 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1661 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1662 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1663 case 251: return createRegOperand(SRC_VCCZ); 1664 case 252: return createRegOperand(SRC_EXECZ); 1665 case 253: return createRegOperand(SRC_SCC); 1666 default: break; 1667 } 1668 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1669 } 1670 1671 MCOperand 1672 AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, const unsigned Val, 1673 unsigned ImmWidth, 1674 AMDGPU::OperandSemantics Sema) const { 1675 using namespace AMDGPU::SDWA; 1676 using namespace AMDGPU::EncValues; 1677 1678 if (STI.hasFeature(AMDGPU::FeatureGFX9) || 1679 STI.hasFeature(AMDGPU::FeatureGFX10)) { 1680 // XXX: cast to int is needed to avoid stupid warning: 1681 // compare with unsigned is always true 1682 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1683 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1684 return createRegOperand(getVgprClassId(Width), 1685 Val - SDWA9EncValues::SRC_VGPR_MIN); 1686 } 1687 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1688 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1689 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1690 return createSRegOperand(getSgprClassId(Width), 1691 Val - SDWA9EncValues::SRC_SGPR_MIN); 1692 } 1693 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1694 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1695 return createSRegOperand(getTtmpClassId(Width), 1696 Val - SDWA9EncValues::SRC_TTMP_MIN); 1697 } 1698 1699 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1700 1701 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1702 return decodeIntImmed(SVal); 1703 1704 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1705 return decodeFPImmed(ImmWidth, SVal, Sema); 1706 1707 return decodeSpecialReg32(SVal); 1708 } 1709 if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) 1710 return createRegOperand(getVgprClassId(Width), Val); 1711 llvm_unreachable("unsupported target"); 1712 } 1713 1714 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1715 return decodeSDWASrc(OPW16, Val, 16, AMDGPU::OperandSemantics::FP16); 1716 } 1717 1718 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1719 return decodeSDWASrc(OPW32, Val, 32, AMDGPU::OperandSemantics::FP32); 1720 } 1721 1722 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1723 using namespace AMDGPU::SDWA; 1724 1725 assert((STI.hasFeature(AMDGPU::FeatureGFX9) || 1726 STI.hasFeature(AMDGPU::FeatureGFX10)) && 1727 "SDWAVopcDst should be present only on GFX9+"); 1728 1729 bool IsWave64 = STI.hasFeature(AMDGPU::FeatureWavefrontSize64); 1730 1731 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1732 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1733 1734 int TTmpIdx = getTTmpIdx(Val); 1735 if (TTmpIdx >= 0) { 1736 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1737 return createSRegOperand(TTmpClsId, TTmpIdx); 1738 } 1739 if (Val > SGPR_MAX) { 1740 return IsWave64 ? decodeSpecialReg64(Val) : decodeSpecialReg32(Val); 1741 } 1742 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1743 } 1744 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1745 } 1746 1747 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1748 return STI.hasFeature(AMDGPU::FeatureWavefrontSize64) 1749 ? decodeSrcOp(OPW64, Val) 1750 : decodeSrcOp(OPW32, Val); 1751 } 1752 1753 MCOperand AMDGPUDisassembler::decodeSplitBarrier(unsigned Val) const { 1754 return decodeSrcOp(OPW32, Val); 1755 } 1756 1757 MCOperand AMDGPUDisassembler::decodeDpp8FI(unsigned Val) const { 1758 if (Val != AMDGPU::DPP::DPP8_FI_0 && Val != AMDGPU::DPP::DPP8_FI_1) 1759 return MCOperand(); 1760 return MCOperand::createImm(Val); 1761 } 1762 1763 MCOperand AMDGPUDisassembler::decodeVersionImm(unsigned Imm) const { 1764 using VersionField = AMDGPU::EncodingField<7, 0>; 1765 using W64Bit = AMDGPU::EncodingBit<13>; 1766 using W32Bit = AMDGPU::EncodingBit<14>; 1767 using MDPBit = AMDGPU::EncodingBit<15>; 1768 using Encoding = AMDGPU::EncodingFields<VersionField, W64Bit, W32Bit, MDPBit>; 1769 1770 auto [Version, W64, W32, MDP] = Encoding::decode(Imm); 1771 1772 // Decode into a plain immediate if any unused bits are raised. 1773 if (Encoding::encode(Version, W64, W32, MDP) != Imm) 1774 return MCOperand::createImm(Imm); 1775 1776 const auto &Versions = AMDGPU::UCVersion::getGFXVersions(); 1777 auto I = find_if(Versions, 1778 [Version = Version](const AMDGPU::UCVersion::GFXVersion &V) { 1779 return V.Code == Version; 1780 }); 1781 MCContext &Ctx = getContext(); 1782 const MCExpr *E; 1783 if (I == Versions.end()) 1784 E = MCConstantExpr::create(Version, Ctx); 1785 else 1786 E = MCSymbolRefExpr::create(Ctx.getOrCreateSymbol(I->Symbol), Ctx); 1787 1788 if (W64) 1789 E = MCBinaryExpr::createOr(E, UCVersionW64Expr, Ctx); 1790 if (W32) 1791 E = MCBinaryExpr::createOr(E, UCVersionW32Expr, Ctx); 1792 if (MDP) 1793 E = MCBinaryExpr::createOr(E, UCVersionMDPExpr, Ctx); 1794 1795 return MCOperand::createExpr(E); 1796 } 1797 1798 bool AMDGPUDisassembler::isVI() const { 1799 return STI.hasFeature(AMDGPU::FeatureVolcanicIslands); 1800 } 1801 1802 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } 1803 1804 bool AMDGPUDisassembler::isGFX90A() const { 1805 return STI.hasFeature(AMDGPU::FeatureGFX90AInsts); 1806 } 1807 1808 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } 1809 1810 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } 1811 1812 bool AMDGPUDisassembler::isGFX10Plus() const { 1813 return AMDGPU::isGFX10Plus(STI); 1814 } 1815 1816 bool AMDGPUDisassembler::isGFX11() const { 1817 return STI.hasFeature(AMDGPU::FeatureGFX11); 1818 } 1819 1820 bool AMDGPUDisassembler::isGFX11Plus() const { 1821 return AMDGPU::isGFX11Plus(STI); 1822 } 1823 1824 bool AMDGPUDisassembler::isGFX12() const { 1825 return STI.hasFeature(AMDGPU::FeatureGFX12); 1826 } 1827 1828 bool AMDGPUDisassembler::isGFX12Plus() const { 1829 return AMDGPU::isGFX12Plus(STI); 1830 } 1831 1832 bool AMDGPUDisassembler::hasArchitectedFlatScratch() const { 1833 return STI.hasFeature(AMDGPU::FeatureArchitectedFlatScratch); 1834 } 1835 1836 bool AMDGPUDisassembler::hasKernargPreload() const { 1837 return AMDGPU::hasKernargPreload(STI); 1838 } 1839 1840 //===----------------------------------------------------------------------===// 1841 // AMDGPU specific symbol handling 1842 //===----------------------------------------------------------------------===// 1843 1844 /// Print a string describing the reserved bit range specified by Mask with 1845 /// offset BaseBytes for use in error comments. Mask is a single continuous 1846 /// range of 1s surrounded by zeros. The format here is meant to align with the 1847 /// tables that describe these bits in llvm.org/docs/AMDGPUUsage.html. 1848 static SmallString<32> getBitRangeFromMask(uint32_t Mask, unsigned BaseBytes) { 1849 SmallString<32> Result; 1850 raw_svector_ostream S(Result); 1851 1852 int TrailingZeros = llvm::countr_zero(Mask); 1853 int PopCount = llvm::popcount(Mask); 1854 1855 if (PopCount == 1) { 1856 S << "bit (" << (TrailingZeros + BaseBytes * CHAR_BIT) << ')'; 1857 } else { 1858 S << "bits in range (" 1859 << (TrailingZeros + PopCount - 1 + BaseBytes * CHAR_BIT) << ':' 1860 << (TrailingZeros + BaseBytes * CHAR_BIT) << ')'; 1861 } 1862 1863 return Result; 1864 } 1865 1866 #define GET_FIELD(MASK) (AMDHSA_BITS_GET(FourByteBuffer, MASK)) 1867 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1868 do { \ 1869 KdStream << Indent << DIRECTIVE " " << GET_FIELD(MASK) << '\n'; \ 1870 } while (0) 1871 #define PRINT_PSEUDO_DIRECTIVE_COMMENT(DIRECTIVE, MASK) \ 1872 do { \ 1873 KdStream << Indent << MAI.getCommentString() << ' ' << DIRECTIVE " " \ 1874 << GET_FIELD(MASK) << '\n'; \ 1875 } while (0) 1876 1877 #define CHECK_RESERVED_BITS_IMPL(MASK, DESC, MSG) \ 1878 do { \ 1879 if (FourByteBuffer & (MASK)) { \ 1880 return createStringError(std::errc::invalid_argument, \ 1881 "kernel descriptor " DESC \ 1882 " reserved %s set" MSG, \ 1883 getBitRangeFromMask((MASK), 0).c_str()); \ 1884 } \ 1885 } while (0) 1886 1887 #define CHECK_RESERVED_BITS(MASK) CHECK_RESERVED_BITS_IMPL(MASK, #MASK, "") 1888 #define CHECK_RESERVED_BITS_MSG(MASK, MSG) \ 1889 CHECK_RESERVED_BITS_IMPL(MASK, #MASK, ", " MSG) 1890 #define CHECK_RESERVED_BITS_DESC(MASK, DESC) \ 1891 CHECK_RESERVED_BITS_IMPL(MASK, DESC, "") 1892 #define CHECK_RESERVED_BITS_DESC_MSG(MASK, DESC, MSG) \ 1893 CHECK_RESERVED_BITS_IMPL(MASK, DESC, ", " MSG) 1894 1895 // NOLINTNEXTLINE(readability-identifier-naming) 1896 Expected<bool> AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1897 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1898 using namespace amdhsa; 1899 StringRef Indent = "\t"; 1900 1901 // We cannot accurately backward compute #VGPRs used from 1902 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1903 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1904 // simply calculate the inverse of what the assembler does. 1905 1906 uint32_t GranulatedWorkitemVGPRCount = 1907 GET_FIELD(COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT); 1908 1909 uint32_t NextFreeVGPR = 1910 (GranulatedWorkitemVGPRCount + 1) * 1911 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI, EnableWavefrontSize32); 1912 1913 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1914 1915 // We cannot backward compute values used to calculate 1916 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1917 // directives can't be computed: 1918 // .amdhsa_reserve_vcc 1919 // .amdhsa_reserve_flat_scratch 1920 // .amdhsa_reserve_xnack_mask 1921 // They take their respective default values if not specified in the assembly. 1922 // 1923 // GRANULATED_WAVEFRONT_SGPR_COUNT 1924 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1925 // 1926 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1927 // are set to 0. So while disassembling we consider that: 1928 // 1929 // GRANULATED_WAVEFRONT_SGPR_COUNT 1930 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1931 // 1932 // The disassembler cannot recover the original values of those 3 directives. 1933 1934 uint32_t GranulatedWavefrontSGPRCount = 1935 GET_FIELD(COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT); 1936 1937 if (isGFX10Plus()) 1938 CHECK_RESERVED_BITS_MSG(COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT, 1939 "must be zero on gfx10+"); 1940 1941 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1942 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1943 1944 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1945 if (!hasArchitectedFlatScratch()) 1946 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1947 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1948 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1949 1950 CHECK_RESERVED_BITS(COMPUTE_PGM_RSRC1_PRIORITY); 1951 1952 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1953 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1954 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1955 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1956 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1957 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1958 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1959 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1960 1961 CHECK_RESERVED_BITS(COMPUTE_PGM_RSRC1_PRIV); 1962 1963 if (!isGFX12Plus()) 1964 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", 1965 COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP); 1966 1967 CHECK_RESERVED_BITS(COMPUTE_PGM_RSRC1_DEBUG_MODE); 1968 1969 if (!isGFX12Plus()) 1970 PRINT_DIRECTIVE(".amdhsa_ieee_mode", 1971 COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE); 1972 1973 CHECK_RESERVED_BITS(COMPUTE_PGM_RSRC1_BULKY); 1974 CHECK_RESERVED_BITS(COMPUTE_PGM_RSRC1_CDBG_USER); 1975 1976 if (isGFX9Plus()) 1977 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL); 1978 1979 if (!isGFX9Plus()) 1980 CHECK_RESERVED_BITS_DESC_MSG(COMPUTE_PGM_RSRC1_GFX6_GFX8_RESERVED0, 1981 "COMPUTE_PGM_RSRC1", "must be zero pre-gfx9"); 1982 1983 CHECK_RESERVED_BITS_DESC(COMPUTE_PGM_RSRC1_RESERVED1, "COMPUTE_PGM_RSRC1"); 1984 1985 if (!isGFX10Plus()) 1986 CHECK_RESERVED_BITS_DESC_MSG(COMPUTE_PGM_RSRC1_GFX6_GFX9_RESERVED2, 1987 "COMPUTE_PGM_RSRC1", "must be zero pre-gfx10"); 1988 1989 if (isGFX10Plus()) { 1990 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1991 COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE); 1992 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED); 1993 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS); 1994 } 1995 1996 if (isGFX12Plus()) 1997 PRINT_DIRECTIVE(".amdhsa_round_robin_scheduling", 1998 COMPUTE_PGM_RSRC1_GFX12_PLUS_ENABLE_WG_RR_EN); 1999 2000 return true; 2001 } 2002 2003 // NOLINTNEXTLINE(readability-identifier-naming) 2004 Expected<bool> AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 2005 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 2006 using namespace amdhsa; 2007 StringRef Indent = "\t"; 2008 if (hasArchitectedFlatScratch()) 2009 PRINT_DIRECTIVE(".amdhsa_enable_private_segment", 2010 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 2011 else 2012 PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset", 2013 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 2014 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 2015 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 2016 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 2017 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 2018 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 2019 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 2020 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 2021 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 2022 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 2023 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 2024 2025 CHECK_RESERVED_BITS(COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH); 2026 CHECK_RESERVED_BITS(COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY); 2027 CHECK_RESERVED_BITS(COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE); 2028 2029 PRINT_DIRECTIVE( 2030 ".amdhsa_exception_fp_ieee_invalid_op", 2031 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 2032 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 2033 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 2034 PRINT_DIRECTIVE( 2035 ".amdhsa_exception_fp_ieee_div_zero", 2036 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 2037 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 2038 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 2039 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 2040 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 2041 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 2042 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 2043 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 2044 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 2045 2046 CHECK_RESERVED_BITS_DESC(COMPUTE_PGM_RSRC2_RESERVED0, "COMPUTE_PGM_RSRC2"); 2047 2048 return true; 2049 } 2050 2051 // NOLINTNEXTLINE(readability-identifier-naming) 2052 Expected<bool> AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC3( 2053 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 2054 using namespace amdhsa; 2055 StringRef Indent = "\t"; 2056 if (isGFX90A()) { 2057 KdStream << Indent << ".amdhsa_accum_offset " 2058 << (GET_FIELD(COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET) + 1) * 4 2059 << '\n'; 2060 2061 PRINT_DIRECTIVE(".amdhsa_tg_split", COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT); 2062 2063 CHECK_RESERVED_BITS_DESC_MSG(COMPUTE_PGM_RSRC3_GFX90A_RESERVED0, 2064 "COMPUTE_PGM_RSRC3", "must be zero on gfx90a"); 2065 CHECK_RESERVED_BITS_DESC_MSG(COMPUTE_PGM_RSRC3_GFX90A_RESERVED1, 2066 "COMPUTE_PGM_RSRC3", "must be zero on gfx90a"); 2067 } else if (isGFX10Plus()) { 2068 // Bits [0-3]. 2069 if (!isGFX12Plus()) { 2070 if (!EnableWavefrontSize32 || !*EnableWavefrontSize32) { 2071 PRINT_DIRECTIVE(".amdhsa_shared_vgpr_count", 2072 COMPUTE_PGM_RSRC3_GFX10_GFX11_SHARED_VGPR_COUNT); 2073 } else { 2074 PRINT_PSEUDO_DIRECTIVE_COMMENT( 2075 "SHARED_VGPR_COUNT", 2076 COMPUTE_PGM_RSRC3_GFX10_GFX11_SHARED_VGPR_COUNT); 2077 } 2078 } else { 2079 CHECK_RESERVED_BITS_DESC_MSG(COMPUTE_PGM_RSRC3_GFX12_PLUS_RESERVED0, 2080 "COMPUTE_PGM_RSRC3", 2081 "must be zero on gfx12+"); 2082 } 2083 2084 // Bits [4-11]. 2085 if (isGFX11()) { 2086 PRINT_PSEUDO_DIRECTIVE_COMMENT("INST_PREF_SIZE", 2087 COMPUTE_PGM_RSRC3_GFX11_INST_PREF_SIZE); 2088 PRINT_PSEUDO_DIRECTIVE_COMMENT("TRAP_ON_START", 2089 COMPUTE_PGM_RSRC3_GFX11_TRAP_ON_START); 2090 PRINT_PSEUDO_DIRECTIVE_COMMENT("TRAP_ON_END", 2091 COMPUTE_PGM_RSRC3_GFX11_TRAP_ON_END); 2092 } else if (isGFX12Plus()) { 2093 PRINT_PSEUDO_DIRECTIVE_COMMENT( 2094 "INST_PREF_SIZE", COMPUTE_PGM_RSRC3_GFX12_PLUS_INST_PREF_SIZE); 2095 } else { 2096 CHECK_RESERVED_BITS_DESC_MSG(COMPUTE_PGM_RSRC3_GFX10_RESERVED1, 2097 "COMPUTE_PGM_RSRC3", 2098 "must be zero on gfx10"); 2099 } 2100 2101 // Bits [12]. 2102 CHECK_RESERVED_BITS_DESC_MSG(COMPUTE_PGM_RSRC3_GFX10_PLUS_RESERVED2, 2103 "COMPUTE_PGM_RSRC3", "must be zero on gfx10+"); 2104 2105 // Bits [13]. 2106 if (isGFX12Plus()) { 2107 PRINT_PSEUDO_DIRECTIVE_COMMENT("GLG_EN", 2108 COMPUTE_PGM_RSRC3_GFX12_PLUS_GLG_EN); 2109 } else { 2110 CHECK_RESERVED_BITS_DESC_MSG(COMPUTE_PGM_RSRC3_GFX10_GFX11_RESERVED3, 2111 "COMPUTE_PGM_RSRC3", 2112 "must be zero on gfx10 or gfx11"); 2113 } 2114 2115 // Bits [14-30]. 2116 CHECK_RESERVED_BITS_DESC_MSG(COMPUTE_PGM_RSRC3_GFX10_PLUS_RESERVED4, 2117 "COMPUTE_PGM_RSRC3", "must be zero on gfx10+"); 2118 2119 // Bits [31]. 2120 if (isGFX11Plus()) { 2121 PRINT_PSEUDO_DIRECTIVE_COMMENT("IMAGE_OP", 2122 COMPUTE_PGM_RSRC3_GFX11_PLUS_IMAGE_OP); 2123 } else { 2124 CHECK_RESERVED_BITS_DESC_MSG(COMPUTE_PGM_RSRC3_GFX10_RESERVED5, 2125 "COMPUTE_PGM_RSRC3", 2126 "must be zero on gfx10"); 2127 } 2128 } else if (FourByteBuffer) { 2129 return createStringError( 2130 std::errc::invalid_argument, 2131 "kernel descriptor COMPUTE_PGM_RSRC3 must be all zero before gfx9"); 2132 } 2133 return true; 2134 } 2135 #undef PRINT_PSEUDO_DIRECTIVE_COMMENT 2136 #undef PRINT_DIRECTIVE 2137 #undef GET_FIELD 2138 #undef CHECK_RESERVED_BITS_IMPL 2139 #undef CHECK_RESERVED_BITS 2140 #undef CHECK_RESERVED_BITS_MSG 2141 #undef CHECK_RESERVED_BITS_DESC 2142 #undef CHECK_RESERVED_BITS_DESC_MSG 2143 2144 /// Create an error object to return from onSymbolStart for reserved kernel 2145 /// descriptor bits being set. 2146 static Error createReservedKDBitsError(uint32_t Mask, unsigned BaseBytes, 2147 const char *Msg = "") { 2148 return createStringError( 2149 std::errc::invalid_argument, "kernel descriptor reserved %s set%s%s", 2150 getBitRangeFromMask(Mask, BaseBytes).c_str(), *Msg ? ", " : "", Msg); 2151 } 2152 2153 /// Create an error object to return from onSymbolStart for reserved kernel 2154 /// descriptor bytes being set. 2155 static Error createReservedKDBytesError(unsigned BaseInBytes, 2156 unsigned WidthInBytes) { 2157 // Create an error comment in the same format as the "Kernel Descriptor" 2158 // table here: https://llvm.org/docs/AMDGPUUsage.html#kernel-descriptor . 2159 return createStringError( 2160 std::errc::invalid_argument, 2161 "kernel descriptor reserved bits in range (%u:%u) set", 2162 (BaseInBytes + WidthInBytes) * CHAR_BIT - 1, BaseInBytes * CHAR_BIT); 2163 } 2164 2165 Expected<bool> AMDGPUDisassembler::decodeKernelDescriptorDirective( 2166 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 2167 raw_string_ostream &KdStream) const { 2168 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 2169 do { \ 2170 KdStream << Indent << DIRECTIVE " " \ 2171 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 2172 } while (0) 2173 2174 uint16_t TwoByteBuffer = 0; 2175 uint32_t FourByteBuffer = 0; 2176 2177 StringRef ReservedBytes; 2178 StringRef Indent = "\t"; 2179 2180 assert(Bytes.size() == 64); 2181 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 2182 2183 switch (Cursor.tell()) { 2184 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 2185 FourByteBuffer = DE.getU32(Cursor); 2186 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 2187 << '\n'; 2188 return true; 2189 2190 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 2191 FourByteBuffer = DE.getU32(Cursor); 2192 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 2193 << FourByteBuffer << '\n'; 2194 return true; 2195 2196 case amdhsa::KERNARG_SIZE_OFFSET: 2197 FourByteBuffer = DE.getU32(Cursor); 2198 KdStream << Indent << ".amdhsa_kernarg_size " 2199 << FourByteBuffer << '\n'; 2200 return true; 2201 2202 case amdhsa::RESERVED0_OFFSET: 2203 // 4 reserved bytes, must be 0. 2204 ReservedBytes = DE.getBytes(Cursor, 4); 2205 for (int I = 0; I < 4; ++I) { 2206 if (ReservedBytes[I] != 0) 2207 return createReservedKDBytesError(amdhsa::RESERVED0_OFFSET, 4); 2208 } 2209 return true; 2210 2211 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 2212 // KERNEL_CODE_ENTRY_BYTE_OFFSET 2213 // So far no directive controls this for Code Object V3, so simply skip for 2214 // disassembly. 2215 DE.skip(Cursor, 8); 2216 return true; 2217 2218 case amdhsa::RESERVED1_OFFSET: 2219 // 20 reserved bytes, must be 0. 2220 ReservedBytes = DE.getBytes(Cursor, 20); 2221 for (int I = 0; I < 20; ++I) { 2222 if (ReservedBytes[I] != 0) 2223 return createReservedKDBytesError(amdhsa::RESERVED1_OFFSET, 20); 2224 } 2225 return true; 2226 2227 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 2228 FourByteBuffer = DE.getU32(Cursor); 2229 return decodeCOMPUTE_PGM_RSRC3(FourByteBuffer, KdStream); 2230 2231 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 2232 FourByteBuffer = DE.getU32(Cursor); 2233 return decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream); 2234 2235 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 2236 FourByteBuffer = DE.getU32(Cursor); 2237 return decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream); 2238 2239 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 2240 using namespace amdhsa; 2241 TwoByteBuffer = DE.getU16(Cursor); 2242 2243 if (!hasArchitectedFlatScratch()) 2244 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 2245 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 2246 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 2247 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 2248 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 2249 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 2250 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 2251 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 2252 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 2253 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 2254 if (!hasArchitectedFlatScratch()) 2255 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 2256 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 2257 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 2258 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 2259 2260 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 2261 return createReservedKDBitsError(KERNEL_CODE_PROPERTY_RESERVED0, 2262 amdhsa::KERNEL_CODE_PROPERTIES_OFFSET); 2263 2264 // Reserved for GFX9 2265 if (isGFX9() && 2266 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 2267 return createReservedKDBitsError( 2268 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32, 2269 amdhsa::KERNEL_CODE_PROPERTIES_OFFSET, "must be zero on gfx9"); 2270 } 2271 if (isGFX10Plus()) { 2272 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 2273 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 2274 } 2275 2276 if (CodeObjectVersion >= AMDGPU::AMDHSA_COV5) 2277 PRINT_DIRECTIVE(".amdhsa_uses_dynamic_stack", 2278 KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK); 2279 2280 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) { 2281 return createReservedKDBitsError(KERNEL_CODE_PROPERTY_RESERVED1, 2282 amdhsa::KERNEL_CODE_PROPERTIES_OFFSET); 2283 } 2284 2285 return true; 2286 2287 case amdhsa::KERNARG_PRELOAD_OFFSET: 2288 using namespace amdhsa; 2289 TwoByteBuffer = DE.getU16(Cursor); 2290 if (TwoByteBuffer & KERNARG_PRELOAD_SPEC_LENGTH) { 2291 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_preload_length", 2292 KERNARG_PRELOAD_SPEC_LENGTH); 2293 } 2294 2295 if (TwoByteBuffer & KERNARG_PRELOAD_SPEC_OFFSET) { 2296 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_preload_offset", 2297 KERNARG_PRELOAD_SPEC_OFFSET); 2298 } 2299 return true; 2300 2301 case amdhsa::RESERVED3_OFFSET: 2302 // 4 bytes from here are reserved, must be 0. 2303 ReservedBytes = DE.getBytes(Cursor, 4); 2304 for (int I = 0; I < 4; ++I) { 2305 if (ReservedBytes[I] != 0) 2306 return createReservedKDBytesError(amdhsa::RESERVED3_OFFSET, 4); 2307 } 2308 return true; 2309 2310 default: 2311 llvm_unreachable("Unhandled index. Case statements cover everything."); 2312 return true; 2313 } 2314 #undef PRINT_DIRECTIVE 2315 } 2316 2317 Expected<bool> AMDGPUDisassembler::decodeKernelDescriptor( 2318 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 2319 2320 // CP microcode requires the kernel descriptor to be 64 aligned. 2321 if (Bytes.size() != 64 || KdAddress % 64 != 0) 2322 return createStringError(std::errc::invalid_argument, 2323 "kernel descriptor must be 64-byte aligned"); 2324 2325 // FIXME: We can't actually decode "in order" as is done below, as e.g. GFX10 2326 // requires us to know the setting of .amdhsa_wavefront_size32 in order to 2327 // accurately produce .amdhsa_next_free_vgpr, and they appear in the wrong 2328 // order. Workaround this by first looking up .amdhsa_wavefront_size32 here 2329 // when required. 2330 if (isGFX10Plus()) { 2331 uint16_t KernelCodeProperties = 2332 support::endian::read16(&Bytes[amdhsa::KERNEL_CODE_PROPERTIES_OFFSET], 2333 llvm::endianness::little); 2334 EnableWavefrontSize32 = 2335 AMDHSA_BITS_GET(KernelCodeProperties, 2336 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 2337 } 2338 2339 std::string Kd; 2340 raw_string_ostream KdStream(Kd); 2341 KdStream << ".amdhsa_kernel " << KdName << '\n'; 2342 2343 DataExtractor::Cursor C(0); 2344 while (C && C.tell() < Bytes.size()) { 2345 Expected<bool> Res = decodeKernelDescriptorDirective(C, Bytes, KdStream); 2346 2347 cantFail(C.takeError()); 2348 2349 if (!Res) 2350 return Res; 2351 } 2352 KdStream << ".end_amdhsa_kernel\n"; 2353 outs() << KdStream.str(); 2354 return true; 2355 } 2356 2357 Expected<bool> AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, 2358 uint64_t &Size, 2359 ArrayRef<uint8_t> Bytes, 2360 uint64_t Address) const { 2361 // Right now only kernel descriptor needs to be handled. 2362 // We ignore all other symbols for target specific handling. 2363 // TODO: 2364 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 2365 // Object V2 and V3 when symbols are marked protected. 2366 2367 // amd_kernel_code_t for Code Object V2. 2368 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 2369 Size = 256; 2370 return createStringError(std::errc::invalid_argument, 2371 "code object v2 is not supported"); 2372 } 2373 2374 // Code Object V3 kernel descriptors. 2375 StringRef Name = Symbol.Name; 2376 if (Symbol.Type == ELF::STT_OBJECT && Name.ends_with(StringRef(".kd"))) { 2377 Size = 64; // Size = 64 regardless of success or failure. 2378 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 2379 } 2380 2381 return false; 2382 } 2383 2384 const MCExpr *AMDGPUDisassembler::createConstantSymbolExpr(StringRef Id, 2385 int64_t Val) { 2386 MCContext &Ctx = getContext(); 2387 MCSymbol *Sym = Ctx.getOrCreateSymbol(Id); 2388 // Note: only set value to Val on a new symbol in case an dissassembler 2389 // has already been initialized in this context. 2390 if (!Sym->isVariable()) { 2391 Sym->setVariableValue(MCConstantExpr::create(Val, Ctx)); 2392 } else { 2393 int64_t Res = ~Val; 2394 bool Valid = Sym->getVariableValue()->evaluateAsAbsolute(Res); 2395 if (!Valid || Res != Val) 2396 Ctx.reportWarning(SMLoc(), "unsupported redefinition of " + Id); 2397 } 2398 return MCSymbolRefExpr::create(Sym, Ctx); 2399 } 2400 2401 //===----------------------------------------------------------------------===// 2402 // AMDGPUSymbolizer 2403 //===----------------------------------------------------------------------===// 2404 2405 // Try to find symbol name for specified label 2406 bool AMDGPUSymbolizer::tryAddingSymbolicOperand( 2407 MCInst &Inst, raw_ostream & /*cStream*/, int64_t Value, 2408 uint64_t /*Address*/, bool IsBranch, uint64_t /*Offset*/, 2409 uint64_t /*OpSize*/, uint64_t /*InstSize*/) { 2410 2411 if (!IsBranch) { 2412 return false; 2413 } 2414 2415 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 2416 if (!Symbols) 2417 return false; 2418 2419 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { 2420 return Val.Addr == static_cast<uint64_t>(Value) && 2421 Val.Type == ELF::STT_NOTYPE; 2422 }); 2423 if (Result != Symbols->end()) { 2424 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 2425 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 2426 Inst.addOperand(MCOperand::createExpr(Add)); 2427 return true; 2428 } 2429 // Add to list of referenced addresses, so caller can synthesize a label. 2430 ReferencedAddresses.push_back(static_cast<uint64_t>(Value)); 2431 return false; 2432 } 2433 2434 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 2435 int64_t Value, 2436 uint64_t Address) { 2437 llvm_unreachable("unimplemented"); 2438 } 2439 2440 //===----------------------------------------------------------------------===// 2441 // Initialization 2442 //===----------------------------------------------------------------------===// 2443 2444 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 2445 LLVMOpInfoCallback /*GetOpInfo*/, 2446 LLVMSymbolLookupCallback /*SymbolLookUp*/, 2447 void *DisInfo, 2448 MCContext *Ctx, 2449 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 2450 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 2451 } 2452 2453 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 2454 const MCSubtargetInfo &STI, 2455 MCContext &Ctx) { 2456 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 2457 } 2458 2459 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 2460 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 2461 createAMDGPUDisassembler); 2462 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 2463 createAMDGPUSymbolizer); 2464 } 2465