1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "SIDefines.h" 22 #include "SIRegisterInfo.h" 23 #include "TargetInfo/AMDGPUTargetInfo.h" 24 #include "Utils/AMDGPUBaseInfo.h" 25 #include "llvm-c/DisassemblerTypes.h" 26 #include "llvm/BinaryFormat/ELF.h" 27 #include "llvm/MC/MCAsmInfo.h" 28 #include "llvm/MC/MCContext.h" 29 #include "llvm/MC/MCDecoderOps.h" 30 #include "llvm/MC/MCExpr.h" 31 #include "llvm/MC/MCInstrDesc.h" 32 #include "llvm/MC/MCRegisterInfo.h" 33 #include "llvm/MC/MCSubtargetInfo.h" 34 #include "llvm/MC/TargetRegistry.h" 35 #include "llvm/Support/AMDHSAKernelDescriptor.h" 36 37 using namespace llvm; 38 39 #define DEBUG_TYPE "amdgpu-disassembler" 40 41 #define SGPR_MAX \ 42 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 43 : AMDGPU::EncValues::SGPR_MAX_SI) 44 45 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 46 47 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 48 MCContext &Ctx, 49 MCInstrInfo const *MCII) : 50 MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), 51 TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) { 52 53 // ToDo: AMDGPUDisassembler supports only VI ISA. 54 if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10Plus()) 55 report_fatal_error("Disassembly not yet supported for subtarget"); 56 } 57 58 inline static MCDisassembler::DecodeStatus 59 addOperand(MCInst &Inst, const MCOperand& Opnd) { 60 Inst.addOperand(Opnd); 61 return Opnd.isValid() ? 62 MCDisassembler::Success : 63 MCDisassembler::Fail; 64 } 65 66 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 67 uint16_t NameIdx) { 68 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 69 if (OpIdx != -1) { 70 auto I = MI.begin(); 71 std::advance(I, OpIdx); 72 MI.insert(I, Op); 73 } 74 return OpIdx; 75 } 76 77 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, 78 uint64_t Addr, 79 const MCDisassembler *Decoder) { 80 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 81 82 // Our branches take a simm16, but we need two extra bits to account for the 83 // factor of 4. 84 APInt SignedOffset(18, Imm * 4, true); 85 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 86 87 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2, 0)) 88 return MCDisassembler::Success; 89 return addOperand(Inst, MCOperand::createImm(Imm)); 90 } 91 92 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, 93 const MCDisassembler *Decoder) { 94 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 95 int64_t Offset; 96 if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 97 Offset = Imm & 0xFFFFF; 98 } else { // GFX9+ supports 21-bit signed offsets. 99 Offset = SignExtend64<21>(Imm); 100 } 101 return addOperand(Inst, MCOperand::createImm(Offset)); 102 } 103 104 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, 105 const MCDisassembler *Decoder) { 106 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 107 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 108 } 109 110 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 111 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \ 112 uint64_t /*Addr*/, \ 113 const MCDisassembler *Decoder) { \ 114 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 115 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 116 } 117 118 #define DECODE_OPERAND_REG(RegClass) \ 119 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass) 120 121 DECODE_OPERAND_REG(VGPR_32) 122 DECODE_OPERAND_REG(VRegOrLds_32) 123 DECODE_OPERAND_REG(VS_32) 124 DECODE_OPERAND_REG(VS_64) 125 DECODE_OPERAND_REG(VS_128) 126 127 DECODE_OPERAND_REG(VReg_64) 128 DECODE_OPERAND_REG(VReg_96) 129 DECODE_OPERAND_REG(VReg_128) 130 DECODE_OPERAND_REG(VReg_256) 131 DECODE_OPERAND_REG(VReg_512) 132 DECODE_OPERAND_REG(VReg_1024) 133 134 DECODE_OPERAND_REG(SReg_32) 135 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC) 136 DECODE_OPERAND_REG(SReg_32_XEXEC_HI) 137 DECODE_OPERAND_REG(SRegOrLds_32) 138 DECODE_OPERAND_REG(SReg_64) 139 DECODE_OPERAND_REG(SReg_64_XEXEC) 140 DECODE_OPERAND_REG(SReg_128) 141 DECODE_OPERAND_REG(SReg_256) 142 DECODE_OPERAND_REG(SReg_512) 143 144 DECODE_OPERAND_REG(AGPR_32) 145 DECODE_OPERAND_REG(AReg_64) 146 DECODE_OPERAND_REG(AReg_128) 147 DECODE_OPERAND_REG(AReg_256) 148 DECODE_OPERAND_REG(AReg_512) 149 DECODE_OPERAND_REG(AReg_1024) 150 DECODE_OPERAND_REG(AV_32) 151 DECODE_OPERAND_REG(AV_64) 152 DECODE_OPERAND_REG(AV_128) 153 DECODE_OPERAND_REG(AVDst_128) 154 DECODE_OPERAND_REG(AVDst_512) 155 156 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, unsigned Imm, 157 uint64_t Addr, 158 const MCDisassembler *Decoder) { 159 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 160 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 161 } 162 163 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, unsigned Imm, 164 uint64_t Addr, 165 const MCDisassembler *Decoder) { 166 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 167 return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm)); 168 } 169 170 static DecodeStatus decodeOperand_VSrcV232(MCInst &Inst, unsigned Imm, 171 uint64_t Addr, 172 const MCDisassembler *Decoder) { 173 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 174 return addOperand(Inst, DAsm->decodeOperand_VSrcV232(Imm)); 175 } 176 177 static DecodeStatus decodeOperand_VS_16(MCInst &Inst, unsigned Imm, 178 uint64_t Addr, 179 const MCDisassembler *Decoder) { 180 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 181 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 182 } 183 184 static DecodeStatus decodeOperand_VS_32(MCInst &Inst, unsigned Imm, 185 uint64_t Addr, 186 const MCDisassembler *Decoder) { 187 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 188 return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm)); 189 } 190 191 static DecodeStatus decodeOperand_AReg_64(MCInst &Inst, unsigned Imm, 192 uint64_t Addr, 193 const MCDisassembler *Decoder) { 194 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 195 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm | 512)); 196 } 197 198 static DecodeStatus decodeOperand_AReg_128(MCInst &Inst, unsigned Imm, 199 uint64_t Addr, 200 const MCDisassembler *Decoder) { 201 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 202 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512)); 203 } 204 205 static DecodeStatus decodeOperand_AReg_256(MCInst &Inst, unsigned Imm, 206 uint64_t Addr, 207 const MCDisassembler *Decoder) { 208 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 209 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm | 512)); 210 } 211 212 static DecodeStatus decodeOperand_AReg_512(MCInst &Inst, unsigned Imm, 213 uint64_t Addr, 214 const MCDisassembler *Decoder) { 215 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 216 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512)); 217 } 218 219 static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst, unsigned Imm, 220 uint64_t Addr, 221 const MCDisassembler *Decoder) { 222 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 223 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512)); 224 } 225 226 static DecodeStatus decodeOperand_VReg_64(MCInst &Inst, unsigned Imm, 227 uint64_t Addr, 228 const MCDisassembler *Decoder) { 229 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 230 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm)); 231 } 232 233 static DecodeStatus decodeOperand_VReg_128(MCInst &Inst, unsigned Imm, 234 uint64_t Addr, 235 const MCDisassembler *Decoder) { 236 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 237 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm)); 238 } 239 240 static DecodeStatus decodeOperand_VReg_256(MCInst &Inst, unsigned Imm, 241 uint64_t Addr, 242 const MCDisassembler *Decoder) { 243 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 244 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm)); 245 } 246 247 static DecodeStatus decodeOperand_VReg_512(MCInst &Inst, unsigned Imm, 248 uint64_t Addr, 249 const MCDisassembler *Decoder) { 250 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 251 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm)); 252 } 253 254 static DecodeStatus decodeOperand_VReg_1024(MCInst &Inst, unsigned Imm, 255 uint64_t Addr, 256 const MCDisassembler *Decoder) { 257 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 258 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm)); 259 } 260 261 static DecodeStatus decodeOperand_f32kimm(MCInst &Inst, unsigned Imm, 262 uint64_t Addr, 263 const MCDisassembler *Decoder) { 264 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 265 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 266 } 267 268 static DecodeStatus decodeOperand_f16kimm(MCInst &Inst, unsigned Imm, 269 uint64_t Addr, 270 const MCDisassembler *Decoder) { 271 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 272 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 273 } 274 275 static DecodeStatus 276 decodeOperand_VS_16_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, 277 const MCDisassembler *Decoder) { 278 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 279 return addOperand( 280 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW16, Imm, true)); 281 } 282 283 static DecodeStatus 284 decodeOperand_VS_32_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, 285 const MCDisassembler *Decoder) { 286 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 287 return addOperand( 288 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW32, Imm, true)); 289 } 290 291 static bool IsAGPROperand(const MCInst &Inst, int OpIdx, 292 const MCRegisterInfo *MRI) { 293 if (OpIdx < 0) 294 return false; 295 296 const MCOperand &Op = Inst.getOperand(OpIdx); 297 if (!Op.isReg()) 298 return false; 299 300 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); 301 auto Reg = Sub ? Sub : Op.getReg(); 302 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; 303 } 304 305 static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, unsigned Imm, 306 AMDGPUDisassembler::OpWidthTy Opw, 307 const MCDisassembler *Decoder) { 308 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 309 if (!DAsm->isGFX90A()) { 310 Imm &= 511; 311 } else { 312 // If atomic has both vdata and vdst their register classes are tied. 313 // The bit is decoded along with the vdst, first operand. We need to 314 // change register class to AGPR if vdst was AGPR. 315 // If a DS instruction has both data0 and data1 their register classes 316 // are also tied. 317 unsigned Opc = Inst.getOpcode(); 318 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; 319 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 320 : AMDGPU::OpName::vdata; 321 const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo(); 322 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); 323 if ((int)Inst.getNumOperands() == DataIdx) { 324 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); 325 if (IsAGPROperand(Inst, DstIdx, MRI)) 326 Imm |= 512; 327 } 328 329 if (TSFlags & SIInstrFlags::DS) { 330 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); 331 if ((int)Inst.getNumOperands() == Data2Idx && 332 IsAGPROperand(Inst, DataIdx, MRI)) 333 Imm |= 512; 334 } 335 } 336 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); 337 } 338 339 static DecodeStatus 340 DecodeAVLdSt_32RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 341 const MCDisassembler *Decoder) { 342 return decodeOperand_AVLdSt_Any(Inst, Imm, 343 AMDGPUDisassembler::OPW32, Decoder); 344 } 345 346 static DecodeStatus 347 DecodeAVLdSt_64RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 348 const MCDisassembler *Decoder) { 349 return decodeOperand_AVLdSt_Any(Inst, Imm, 350 AMDGPUDisassembler::OPW64, Decoder); 351 } 352 353 static DecodeStatus 354 DecodeAVLdSt_96RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 355 const MCDisassembler *Decoder) { 356 return decodeOperand_AVLdSt_Any(Inst, Imm, 357 AMDGPUDisassembler::OPW96, Decoder); 358 } 359 360 static DecodeStatus 361 DecodeAVLdSt_128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 362 const MCDisassembler *Decoder) { 363 return decodeOperand_AVLdSt_Any(Inst, Imm, 364 AMDGPUDisassembler::OPW128, Decoder); 365 } 366 367 static DecodeStatus decodeOperand_SReg_32(MCInst &Inst, unsigned Imm, 368 uint64_t Addr, 369 const MCDisassembler *Decoder) { 370 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 371 return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm)); 372 } 373 374 #define DECODE_SDWA(DecName) \ 375 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 376 377 DECODE_SDWA(Src32) 378 DECODE_SDWA(Src16) 379 DECODE_SDWA(VopcDst) 380 381 #include "AMDGPUGenDisassemblerTables.inc" 382 383 //===----------------------------------------------------------------------===// 384 // 385 //===----------------------------------------------------------------------===// 386 387 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 388 assert(Bytes.size() >= sizeof(T)); 389 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data()); 390 Bytes = Bytes.slice(sizeof(T)); 391 return Res; 392 } 393 394 static inline DecoderUInt128 eat12Bytes(ArrayRef<uint8_t> &Bytes) { 395 assert(Bytes.size() >= 12); 396 uint64_t Lo = support::endian::read<uint64_t, support::endianness::little>( 397 Bytes.data()); 398 Bytes = Bytes.slice(8); 399 uint64_t Hi = support::endian::read<uint32_t, support::endianness::little>( 400 Bytes.data()); 401 Bytes = Bytes.slice(4); 402 return DecoderUInt128(Lo, Hi); 403 } 404 405 // The disassembler is greedy, so we need to check FI operand value to 406 // not parse a dpp if the correct literal is not set. For dpp16 the 407 // autogenerated decoder checks the dpp literal 408 static bool isValidDPP8(const MCInst &MI) { 409 using namespace llvm::AMDGPU::DPP; 410 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi); 411 assert(FiIdx != -1); 412 if ((unsigned)FiIdx >= MI.getNumOperands()) 413 return false; 414 unsigned Fi = MI.getOperand(FiIdx).getImm(); 415 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1; 416 } 417 418 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 419 ArrayRef<uint8_t> Bytes_, 420 uint64_t Address, 421 raw_ostream &CS) const { 422 CommentStream = &CS; 423 bool IsSDWA = false; 424 425 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 426 Bytes = Bytes_.slice(0, MaxInstBytesNum); 427 428 DecodeStatus Res = MCDisassembler::Fail; 429 do { 430 // ToDo: better to switch encoding length using some bit predicate 431 // but it is unknown yet, so try all we can 432 433 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 434 // encodings 435 if (isGFX11Plus() && Bytes.size() >= 12 ) { 436 DecoderUInt128 DecW = eat12Bytes(Bytes); 437 Res = tryDecodeInst(DecoderTableDPP8GFX1196, MI, DecW, 438 Address); 439 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 440 break; 441 MI = MCInst(); // clear 442 Res = tryDecodeInst(DecoderTableDPPGFX1196, MI, DecW, 443 Address); 444 if (Res) 445 break; 446 } 447 // Reinitialize Bytes 448 Bytes = Bytes_.slice(0, MaxInstBytesNum); 449 450 if (Bytes.size() >= 8) { 451 const uint64_t QW = eatBytes<uint64_t>(Bytes); 452 453 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 454 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address); 455 if (Res) { 456 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) 457 == -1) 458 break; 459 if (convertDPP8Inst(MI) == MCDisassembler::Success) 460 break; 461 MI = MCInst(); // clear 462 } 463 } 464 465 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address); 466 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 467 break; 468 469 MI = MCInst(); // clear 470 471 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address); 472 if (Res) break; 473 474 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address); 475 if (Res) { IsSDWA = true; break; } 476 477 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address); 478 if (Res) { IsSDWA = true; break; } 479 480 Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address); 481 if (Res) { IsSDWA = true; break; } 482 483 if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) { 484 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address); 485 if (Res) 486 break; 487 } 488 489 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 490 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 491 // table first so we print the correct name. 492 if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) { 493 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address); 494 if (Res) 495 break; 496 } 497 } 498 499 // Reinitialize Bytes as DPP64 could have eaten too much 500 Bytes = Bytes_.slice(0, MaxInstBytesNum); 501 502 // Try decode 32-bit instruction 503 if (Bytes.size() < 4) break; 504 const uint32_t DW = eatBytes<uint32_t>(Bytes); 505 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address); 506 if (Res) break; 507 508 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address); 509 if (Res) break; 510 511 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address); 512 if (Res) break; 513 514 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 515 Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address); 516 if (Res) 517 break; 518 } 519 520 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 521 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address); 522 if (Res) break; 523 } 524 525 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address); 526 if (Res) break; 527 528 Res = tryDecodeInst(DecoderTableGFX1132, MI, DW, Address); 529 if (Res) break; 530 531 if (Bytes.size() < 4) break; 532 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 533 534 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 535 Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address); 536 if (Res) 537 break; 538 } 539 540 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address); 541 if (Res) break; 542 543 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address); 544 if (Res) break; 545 546 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address); 547 if (Res) break; 548 549 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address); 550 if (Res) break; 551 552 Res = tryDecodeInst(DecoderTableGFX1164, MI, QW, Address); 553 } while (false); 554 555 if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi || 556 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 || 557 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 || 558 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 || 559 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 || 560 MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi || 561 MI.getOpcode() == AMDGPU::V_FMAC_F64_e64_gfx90a || 562 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi || 563 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 || 564 MI.getOpcode() == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 || 565 MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10)) { 566 // Insert dummy unused src2_modifiers. 567 insertNamedMCOperand(MI, MCOperand::createImm(0), 568 AMDGPU::OpName::src2_modifiers); 569 } 570 571 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 572 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT | SIInstrFlags::SMRD))) { 573 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 574 AMDGPU::OpName::cpol); 575 if (CPolPos != -1) { 576 unsigned CPol = 577 (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ? 578 AMDGPU::CPol::GLC : 0; 579 if (MI.getNumOperands() <= (unsigned)CPolPos) { 580 insertNamedMCOperand(MI, MCOperand::createImm(CPol), 581 AMDGPU::OpName::cpol); 582 } else if (CPol) { 583 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); 584 } 585 } 586 } 587 588 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 589 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) && 590 (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts])) { 591 // GFX90A lost TFE, its place is occupied by ACC. 592 int TFEOpIdx = 593 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); 594 if (TFEOpIdx != -1) { 595 auto TFEIter = MI.begin(); 596 std::advance(TFEIter, TFEOpIdx); 597 MI.insert(TFEIter, MCOperand::createImm(0)); 598 } 599 } 600 601 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 602 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF))) { 603 int SWZOpIdx = 604 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); 605 if (SWZOpIdx != -1) { 606 auto SWZIter = MI.begin(); 607 std::advance(SWZIter, SWZOpIdx); 608 MI.insert(SWZIter, MCOperand::createImm(0)); 609 } 610 } 611 612 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 613 int VAddr0Idx = 614 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 615 int RsrcIdx = 616 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 617 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 618 if (VAddr0Idx >= 0 && NSAArgs > 0) { 619 unsigned NSAWords = (NSAArgs + 3) / 4; 620 if (Bytes.size() < 4 * NSAWords) { 621 Res = MCDisassembler::Fail; 622 } else { 623 for (unsigned i = 0; i < NSAArgs; ++i) { 624 const unsigned VAddrIdx = VAddr0Idx + 1 + i; 625 auto VAddrRCID = MCII->get(MI.getOpcode()).OpInfo[VAddrIdx].RegClass; 626 MI.insert(MI.begin() + VAddrIdx, 627 createRegOperand(VAddrRCID, Bytes[i])); 628 } 629 Bytes = Bytes.slice(4 * NSAWords); 630 } 631 } 632 633 if (Res) 634 Res = convertMIMGInst(MI); 635 } 636 637 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::EXP)) 638 Res = convertEXPInst(MI); 639 640 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VINTERP)) 641 Res = convertVINTERPInst(MI); 642 643 if (Res && IsSDWA) 644 Res = convertSDWAInst(MI); 645 646 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 647 AMDGPU::OpName::vdst_in); 648 if (VDstIn_Idx != -1) { 649 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 650 MCOI::OperandConstraint::TIED_TO); 651 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 652 !MI.getOperand(VDstIn_Idx).isReg() || 653 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 654 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 655 MI.erase(&MI.getOperand(VDstIn_Idx)); 656 insertNamedMCOperand(MI, 657 MCOperand::createReg(MI.getOperand(Tied).getReg()), 658 AMDGPU::OpName::vdst_in); 659 } 660 } 661 662 int ImmLitIdx = 663 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm); 664 if (Res && ImmLitIdx != -1) 665 Res = convertFMAanyK(MI, ImmLitIdx); 666 667 // if the opcode was not recognized we'll assume a Size of 4 bytes 668 // (unless there are fewer bytes left) 669 Size = Res ? (MaxInstBytesNum - Bytes.size()) 670 : std::min((size_t)4, Bytes_.size()); 671 return Res; 672 } 673 674 DecodeStatus AMDGPUDisassembler::convertEXPInst(MCInst &MI) const { 675 if (STI.getFeatureBits()[AMDGPU::FeatureGFX11]) { 676 // The MCInst still has these fields even though they are no longer encoded 677 // in the GFX11 instruction. 678 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vm); 679 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::compr); 680 } 681 return MCDisassembler::Success; 682 } 683 684 DecodeStatus AMDGPUDisassembler::convertVINTERPInst(MCInst &MI) const { 685 if (MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx11 || 686 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx11 || 687 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx11 || 688 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx11) { 689 // The MCInst has this field that is not directly encoded in the 690 // instruction. 691 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::op_sel); 692 } 693 return MCDisassembler::Success; 694 } 695 696 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 697 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 698 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 699 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1) 700 // VOPC - insert clamp 701 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 702 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 703 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 704 if (SDst != -1) { 705 // VOPC - insert VCC register as sdst 706 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 707 AMDGPU::OpName::sdst); 708 } else { 709 // VOP1/2 - insert omod if present in instruction 710 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 711 } 712 } 713 return MCDisassembler::Success; 714 } 715 716 // We must check FI == literal to reject not genuine dpp8 insts, and we must 717 // first add optional MI operands to check FI 718 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 719 unsigned Opc = MI.getOpcode(); 720 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 721 722 // Insert dummy unused src modifiers. 723 if (MI.getNumOperands() < DescNumOps && 724 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1) 725 insertNamedMCOperand(MI, MCOperand::createImm(0), 726 AMDGPU::OpName::src0_modifiers); 727 728 if (MI.getNumOperands() < DescNumOps && 729 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1) 730 insertNamedMCOperand(MI, MCOperand::createImm(0), 731 AMDGPU::OpName::src1_modifiers); 732 733 return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail; 734 } 735 736 // Note that before gfx10, the MIMG encoding provided no information about 737 // VADDR size. Consequently, decoded instructions always show address as if it 738 // has 1 dword, which could be not really so. 739 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 740 741 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 742 AMDGPU::OpName::vdst); 743 744 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 745 AMDGPU::OpName::vdata); 746 int VAddr0Idx = 747 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 748 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 749 AMDGPU::OpName::dmask); 750 751 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 752 AMDGPU::OpName::tfe); 753 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 754 AMDGPU::OpName::d16); 755 756 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 757 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 758 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 759 760 assert(VDataIdx != -1); 761 if (BaseOpcode->BVH) { 762 // Add A16 operand for intersect_ray instructions 763 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16) > -1) { 764 addOperand(MI, MCOperand::createImm(1)); 765 } 766 return MCDisassembler::Success; 767 } 768 769 bool IsAtomic = (VDstIdx != -1); 770 bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4; 771 bool IsNSA = false; 772 unsigned AddrSize = Info->VAddrDwords; 773 774 if (isGFX10Plus()) { 775 unsigned DimIdx = 776 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 777 int A16Idx = 778 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16); 779 const AMDGPU::MIMGDimInfo *Dim = 780 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 781 const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm()); 782 783 AddrSize = 784 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); 785 786 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA || 787 Info->MIMGEncoding == AMDGPU::MIMGEncGfx11NSA; 788 if (!IsNSA) { 789 if (AddrSize > 8) 790 AddrSize = 16; 791 } else { 792 if (AddrSize > Info->VAddrDwords) { 793 // The NSA encoding does not contain enough operands for the combination 794 // of base opcode / dimension. Should this be an error? 795 return MCDisassembler::Success; 796 } 797 } 798 } 799 800 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 801 unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u); 802 803 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 804 if (D16 && AMDGPU::hasPackedD16(STI)) { 805 DstSize = (DstSize + 1) / 2; 806 } 807 808 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm()) 809 DstSize += 1; 810 811 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 812 return MCDisassembler::Success; 813 814 int NewOpcode = 815 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 816 if (NewOpcode == -1) 817 return MCDisassembler::Success; 818 819 // Widen the register to the correct number of enabled channels. 820 unsigned NewVdata = AMDGPU::NoRegister; 821 if (DstSize != Info->VDataDwords) { 822 auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; 823 824 // Get first subregister of VData 825 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 826 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 827 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 828 829 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 830 &MRI.getRegClass(DataRCID)); 831 if (NewVdata == AMDGPU::NoRegister) { 832 // It's possible to encode this such that the low register + enabled 833 // components exceeds the register count. 834 return MCDisassembler::Success; 835 } 836 } 837 838 // If not using NSA on GFX10+, widen address register to correct size. 839 unsigned NewVAddr0 = AMDGPU::NoRegister; 840 if (isGFX10Plus() && !IsNSA && AddrSize != Info->VAddrDwords) { 841 unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg(); 842 unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0); 843 VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0; 844 845 auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass; 846 NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0, 847 &MRI.getRegClass(AddrRCID)); 848 if (NewVAddr0 == AMDGPU::NoRegister) 849 return MCDisassembler::Success; 850 } 851 852 MI.setOpcode(NewOpcode); 853 854 if (NewVdata != AMDGPU::NoRegister) { 855 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 856 857 if (IsAtomic) { 858 // Atomic operations have an additional operand (a copy of data) 859 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 860 } 861 } 862 863 if (NewVAddr0 != AMDGPU::NoRegister) { 864 MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0); 865 } else if (IsNSA) { 866 assert(AddrSize <= Info->VAddrDwords); 867 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 868 MI.begin() + VAddr0Idx + Info->VAddrDwords); 869 } 870 871 return MCDisassembler::Success; 872 } 873 874 DecodeStatus AMDGPUDisassembler::convertFMAanyK(MCInst &MI, 875 int ImmLitIdx) const { 876 assert(HasLiteral && "Should have decoded a literal"); 877 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 878 unsigned DescNumOps = Desc.getNumOperands(); 879 assert(DescNumOps == MI.getNumOperands()); 880 for (unsigned I = 0; I < DescNumOps; ++I) { 881 auto &Op = MI.getOperand(I); 882 auto OpType = Desc.OpInfo[I].OperandType; 883 bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED || 884 OpType == AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED); 885 if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST && 886 IsDeferredOp) 887 Op.setImm(Literal); 888 } 889 return MCDisassembler::Success; 890 } 891 892 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 893 return getContext().getRegisterInfo()-> 894 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 895 } 896 897 inline 898 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 899 const Twine& ErrMsg) const { 900 *CommentStream << "Error: " + ErrMsg; 901 902 // ToDo: add support for error operands to MCInst.h 903 // return MCOperand::createError(V); 904 return MCOperand(); 905 } 906 907 inline 908 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 909 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 910 } 911 912 inline 913 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 914 unsigned Val) const { 915 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 916 if (Val >= RegCl.getNumRegs()) 917 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 918 ": unknown register " + Twine(Val)); 919 return createRegOperand(RegCl.getRegister(Val)); 920 } 921 922 inline 923 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 924 unsigned Val) const { 925 // ToDo: SI/CI have 104 SGPRs, VI - 102 926 // Valery: here we accepting as much as we can, let assembler sort it out 927 int shift = 0; 928 switch (SRegClassID) { 929 case AMDGPU::SGPR_32RegClassID: 930 case AMDGPU::TTMP_32RegClassID: 931 break; 932 case AMDGPU::SGPR_64RegClassID: 933 case AMDGPU::TTMP_64RegClassID: 934 shift = 1; 935 break; 936 case AMDGPU::SGPR_128RegClassID: 937 case AMDGPU::TTMP_128RegClassID: 938 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 939 // this bundle? 940 case AMDGPU::SGPR_256RegClassID: 941 case AMDGPU::TTMP_256RegClassID: 942 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 943 // this bundle? 944 case AMDGPU::SGPR_512RegClassID: 945 case AMDGPU::TTMP_512RegClassID: 946 shift = 2; 947 break; 948 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 949 // this bundle? 950 default: 951 llvm_unreachable("unhandled register class"); 952 } 953 954 if (Val % (1 << shift)) { 955 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 956 << ": scalar reg isn't aligned " << Val; 957 } 958 959 return createRegOperand(SRegClassID, Val >> shift); 960 } 961 962 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { 963 return decodeSrcOp(OPW32, Val); 964 } 965 966 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { 967 return decodeSrcOp(OPW64, Val); 968 } 969 970 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const { 971 return decodeSrcOp(OPW128, Val); 972 } 973 974 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const { 975 return decodeSrcOp(OPW16, Val); 976 } 977 978 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const { 979 return decodeSrcOp(OPWV216, Val); 980 } 981 982 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV232(unsigned Val) const { 983 return decodeSrcOp(OPWV232, Val); 984 } 985 986 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { 987 // Some instructions have operand restrictions beyond what the encoding 988 // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra 989 // high bit. 990 Val &= 255; 991 992 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); 993 } 994 995 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const { 996 return decodeSrcOp(OPW32, Val); 997 } 998 999 MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const { 1000 return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255); 1001 } 1002 1003 MCOperand AMDGPUDisassembler::decodeOperand_AReg_64(unsigned Val) const { 1004 return createRegOperand(AMDGPU::AReg_64RegClassID, Val & 255); 1005 } 1006 1007 MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const { 1008 return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255); 1009 } 1010 1011 MCOperand AMDGPUDisassembler::decodeOperand_AReg_256(unsigned Val) const { 1012 return createRegOperand(AMDGPU::AReg_256RegClassID, Val & 255); 1013 } 1014 1015 MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const { 1016 return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255); 1017 } 1018 1019 MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const { 1020 return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255); 1021 } 1022 1023 MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const { 1024 return decodeSrcOp(OPW32, Val); 1025 } 1026 1027 MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const { 1028 return decodeSrcOp(OPW64, Val); 1029 } 1030 1031 MCOperand AMDGPUDisassembler::decodeOperand_AV_128(unsigned Val) const { 1032 return decodeSrcOp(OPW128, Val); 1033 } 1034 1035 MCOperand AMDGPUDisassembler::decodeOperand_AVDst_128(unsigned Val) const { 1036 using namespace AMDGPU::EncValues; 1037 assert((Val & IS_VGPR) == 0); // Val{8} is not encoded but assumed to be 1. 1038 return decodeSrcOp(OPW128, Val | IS_VGPR); 1039 } 1040 1041 MCOperand AMDGPUDisassembler::decodeOperand_AVDst_512(unsigned Val) const { 1042 using namespace AMDGPU::EncValues; 1043 assert((Val & IS_VGPR) == 0); // Val{8} is not encoded but assumed to be 1. 1044 return decodeSrcOp(OPW512, Val | IS_VGPR); 1045 } 1046 1047 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { 1048 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); 1049 } 1050 1051 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { 1052 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); 1053 } 1054 1055 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { 1056 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); 1057 } 1058 1059 MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const { 1060 return createRegOperand(AMDGPU::VReg_256RegClassID, Val); 1061 } 1062 1063 MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const { 1064 return createRegOperand(AMDGPU::VReg_512RegClassID, Val); 1065 } 1066 1067 MCOperand AMDGPUDisassembler::decodeOperand_VReg_1024(unsigned Val) const { 1068 return createRegOperand(AMDGPU::VReg_1024RegClassID, Val); 1069 } 1070 1071 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { 1072 // table-gen generated disassembler doesn't care about operand types 1073 // leaving only registry class so SSrc_32 operand turns into SReg_32 1074 // and therefore we accept immediates and literals here as well 1075 return decodeSrcOp(OPW32, Val); 1076 } 1077 1078 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC( 1079 unsigned Val) const { 1080 // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI 1081 return decodeOperand_SReg_32(Val); 1082 } 1083 1084 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI( 1085 unsigned Val) const { 1086 // SReg_32_XM0 is SReg_32 without EXEC_HI 1087 return decodeOperand_SReg_32(Val); 1088 } 1089 1090 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const { 1091 // table-gen generated disassembler doesn't care about operand types 1092 // leaving only registry class so SSrc_32 operand turns into SReg_32 1093 // and therefore we accept immediates and literals here as well 1094 return decodeSrcOp(OPW32, Val); 1095 } 1096 1097 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { 1098 return decodeSrcOp(OPW64, Val); 1099 } 1100 1101 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const { 1102 return decodeSrcOp(OPW64, Val); 1103 } 1104 1105 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { 1106 return decodeSrcOp(OPW128, Val); 1107 } 1108 1109 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { 1110 return decodeDstOp(OPW256, Val); 1111 } 1112 1113 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { 1114 return decodeDstOp(OPW512, Val); 1115 } 1116 1117 // Decode Literals for insts which always have a literal in the encoding 1118 MCOperand 1119 AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const { 1120 if (HasLiteral) { 1121 if (Literal != Val) 1122 return errOperand(Val, "More than one unique literal is illegal"); 1123 } 1124 HasLiteral = true; 1125 Literal = Val; 1126 return MCOperand::createImm(Literal); 1127 } 1128 1129 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { 1130 // For now all literal constants are supposed to be unsigned integer 1131 // ToDo: deal with signed/unsigned 64-bit integer constants 1132 // ToDo: deal with float/double constants 1133 if (!HasLiteral) { 1134 if (Bytes.size() < 4) { 1135 return errOperand(0, "cannot read literal, inst bytes left " + 1136 Twine(Bytes.size())); 1137 } 1138 HasLiteral = true; 1139 Literal = eatBytes<uint32_t>(Bytes); 1140 } 1141 return MCOperand::createImm(Literal); 1142 } 1143 1144 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 1145 using namespace AMDGPU::EncValues; 1146 1147 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 1148 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 1149 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 1150 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 1151 // Cast prevents negative overflow. 1152 } 1153 1154 static int64_t getInlineImmVal32(unsigned Imm) { 1155 switch (Imm) { 1156 case 240: 1157 return FloatToBits(0.5f); 1158 case 241: 1159 return FloatToBits(-0.5f); 1160 case 242: 1161 return FloatToBits(1.0f); 1162 case 243: 1163 return FloatToBits(-1.0f); 1164 case 244: 1165 return FloatToBits(2.0f); 1166 case 245: 1167 return FloatToBits(-2.0f); 1168 case 246: 1169 return FloatToBits(4.0f); 1170 case 247: 1171 return FloatToBits(-4.0f); 1172 case 248: // 1 / (2 * PI) 1173 return 0x3e22f983; 1174 default: 1175 llvm_unreachable("invalid fp inline imm"); 1176 } 1177 } 1178 1179 static int64_t getInlineImmVal64(unsigned Imm) { 1180 switch (Imm) { 1181 case 240: 1182 return DoubleToBits(0.5); 1183 case 241: 1184 return DoubleToBits(-0.5); 1185 case 242: 1186 return DoubleToBits(1.0); 1187 case 243: 1188 return DoubleToBits(-1.0); 1189 case 244: 1190 return DoubleToBits(2.0); 1191 case 245: 1192 return DoubleToBits(-2.0); 1193 case 246: 1194 return DoubleToBits(4.0); 1195 case 247: 1196 return DoubleToBits(-4.0); 1197 case 248: // 1 / (2 * PI) 1198 return 0x3fc45f306dc9c882; 1199 default: 1200 llvm_unreachable("invalid fp inline imm"); 1201 } 1202 } 1203 1204 static int64_t getInlineImmVal16(unsigned Imm) { 1205 switch (Imm) { 1206 case 240: 1207 return 0x3800; 1208 case 241: 1209 return 0xB800; 1210 case 242: 1211 return 0x3C00; 1212 case 243: 1213 return 0xBC00; 1214 case 244: 1215 return 0x4000; 1216 case 245: 1217 return 0xC000; 1218 case 246: 1219 return 0x4400; 1220 case 247: 1221 return 0xC400; 1222 case 248: // 1 / (2 * PI) 1223 return 0x3118; 1224 default: 1225 llvm_unreachable("invalid fp inline imm"); 1226 } 1227 } 1228 1229 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) { 1230 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 1231 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 1232 1233 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 1234 switch (Width) { 1235 case OPW32: 1236 case OPW128: // splat constants 1237 case OPW512: 1238 case OPW1024: 1239 case OPWV232: 1240 return MCOperand::createImm(getInlineImmVal32(Imm)); 1241 case OPW64: 1242 case OPW256: 1243 return MCOperand::createImm(getInlineImmVal64(Imm)); 1244 case OPW16: 1245 case OPWV216: 1246 return MCOperand::createImm(getInlineImmVal16(Imm)); 1247 default: 1248 llvm_unreachable("implement me"); 1249 } 1250 } 1251 1252 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 1253 using namespace AMDGPU; 1254 1255 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1256 switch (Width) { 1257 default: // fall 1258 case OPW32: 1259 case OPW16: 1260 case OPWV216: 1261 return VGPR_32RegClassID; 1262 case OPW64: 1263 case OPWV232: return VReg_64RegClassID; 1264 case OPW96: return VReg_96RegClassID; 1265 case OPW128: return VReg_128RegClassID; 1266 case OPW160: return VReg_160RegClassID; 1267 case OPW256: return VReg_256RegClassID; 1268 case OPW512: return VReg_512RegClassID; 1269 case OPW1024: return VReg_1024RegClassID; 1270 } 1271 } 1272 1273 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 1274 using namespace AMDGPU; 1275 1276 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1277 switch (Width) { 1278 default: // fall 1279 case OPW32: 1280 case OPW16: 1281 case OPWV216: 1282 return AGPR_32RegClassID; 1283 case OPW64: 1284 case OPWV232: return AReg_64RegClassID; 1285 case OPW96: return AReg_96RegClassID; 1286 case OPW128: return AReg_128RegClassID; 1287 case OPW160: return AReg_160RegClassID; 1288 case OPW256: return AReg_256RegClassID; 1289 case OPW512: return AReg_512RegClassID; 1290 case OPW1024: return AReg_1024RegClassID; 1291 } 1292 } 1293 1294 1295 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 1296 using namespace AMDGPU; 1297 1298 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1299 switch (Width) { 1300 default: // fall 1301 case OPW32: 1302 case OPW16: 1303 case OPWV216: 1304 return SGPR_32RegClassID; 1305 case OPW64: 1306 case OPWV232: return SGPR_64RegClassID; 1307 case OPW96: return SGPR_96RegClassID; 1308 case OPW128: return SGPR_128RegClassID; 1309 case OPW160: return SGPR_160RegClassID; 1310 case OPW256: return SGPR_256RegClassID; 1311 case OPW512: return SGPR_512RegClassID; 1312 } 1313 } 1314 1315 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 1316 using namespace AMDGPU; 1317 1318 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1319 switch (Width) { 1320 default: // fall 1321 case OPW32: 1322 case OPW16: 1323 case OPWV216: 1324 return TTMP_32RegClassID; 1325 case OPW64: 1326 case OPWV232: return TTMP_64RegClassID; 1327 case OPW128: return TTMP_128RegClassID; 1328 case OPW256: return TTMP_256RegClassID; 1329 case OPW512: return TTMP_512RegClassID; 1330 } 1331 } 1332 1333 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 1334 using namespace AMDGPU::EncValues; 1335 1336 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN; 1337 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX; 1338 1339 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1340 } 1341 1342 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val, 1343 bool MandatoryLiteral) const { 1344 using namespace AMDGPU::EncValues; 1345 1346 assert(Val < 1024); // enum10 1347 1348 bool IsAGPR = Val & 512; 1349 Val &= 511; 1350 1351 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1352 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1353 : getVgprClassId(Width), Val - VGPR_MIN); 1354 } 1355 if (Val <= SGPR_MAX) { 1356 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1357 static_assert(SGPR_MIN == 0, ""); 1358 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1359 } 1360 1361 int TTmpIdx = getTTmpIdx(Val); 1362 if (TTmpIdx >= 0) { 1363 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1364 } 1365 1366 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1367 return decodeIntImmed(Val); 1368 1369 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1370 return decodeFPImmed(Width, Val); 1371 1372 if (Val == LITERAL_CONST) { 1373 if (MandatoryLiteral) 1374 // Keep a sentinel value for deferred setting 1375 return MCOperand::createImm(LITERAL_CONST); 1376 else 1377 return decodeLiteralConstant(); 1378 } 1379 1380 switch (Width) { 1381 case OPW32: 1382 case OPW16: 1383 case OPWV216: 1384 return decodeSpecialReg32(Val); 1385 case OPW64: 1386 case OPWV232: 1387 return decodeSpecialReg64(Val); 1388 default: 1389 llvm_unreachable("unexpected immediate type"); 1390 } 1391 } 1392 1393 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const { 1394 using namespace AMDGPU::EncValues; 1395 1396 assert(Val < 128); 1397 assert(Width == OPW256 || Width == OPW512); 1398 1399 if (Val <= SGPR_MAX) { 1400 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1401 static_assert(SGPR_MIN == 0, ""); 1402 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1403 } 1404 1405 int TTmpIdx = getTTmpIdx(Val); 1406 if (TTmpIdx >= 0) { 1407 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1408 } 1409 1410 llvm_unreachable("unknown dst register"); 1411 } 1412 1413 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1414 using namespace AMDGPU; 1415 1416 switch (Val) { 1417 case 102: return createRegOperand(FLAT_SCR_LO); 1418 case 103: return createRegOperand(FLAT_SCR_HI); 1419 case 104: return createRegOperand(XNACK_MASK_LO); 1420 case 105: return createRegOperand(XNACK_MASK_HI); 1421 case 106: return createRegOperand(VCC_LO); 1422 case 107: return createRegOperand(VCC_HI); 1423 case 108: return createRegOperand(TBA_LO); 1424 case 109: return createRegOperand(TBA_HI); 1425 case 110: return createRegOperand(TMA_LO); 1426 case 111: return createRegOperand(TMA_HI); 1427 case 124: 1428 return isGFX11Plus() ? createRegOperand(SGPR_NULL) : createRegOperand(M0); 1429 case 125: 1430 return isGFX11Plus() ? createRegOperand(M0) : createRegOperand(SGPR_NULL); 1431 case 126: return createRegOperand(EXEC_LO); 1432 case 127: return createRegOperand(EXEC_HI); 1433 case 235: return createRegOperand(SRC_SHARED_BASE); 1434 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1435 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1436 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1437 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1438 case 251: return createRegOperand(SRC_VCCZ); 1439 case 252: return createRegOperand(SRC_EXECZ); 1440 case 253: return createRegOperand(SRC_SCC); 1441 case 254: return createRegOperand(LDS_DIRECT); 1442 default: break; 1443 } 1444 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1445 } 1446 1447 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1448 using namespace AMDGPU; 1449 1450 switch (Val) { 1451 case 102: return createRegOperand(FLAT_SCR); 1452 case 104: return createRegOperand(XNACK_MASK); 1453 case 106: return createRegOperand(VCC); 1454 case 108: return createRegOperand(TBA); 1455 case 110: return createRegOperand(TMA); 1456 case 124: 1457 if (isGFX11Plus()) 1458 return createRegOperand(SGPR_NULL); 1459 break; 1460 case 125: 1461 if (!isGFX11Plus()) 1462 return createRegOperand(SGPR_NULL); 1463 break; 1464 case 126: return createRegOperand(EXEC); 1465 case 235: return createRegOperand(SRC_SHARED_BASE); 1466 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1467 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1468 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1469 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1470 case 251: return createRegOperand(SRC_VCCZ); 1471 case 252: return createRegOperand(SRC_EXECZ); 1472 case 253: return createRegOperand(SRC_SCC); 1473 default: break; 1474 } 1475 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1476 } 1477 1478 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 1479 const unsigned Val) const { 1480 using namespace AMDGPU::SDWA; 1481 using namespace AMDGPU::EncValues; 1482 1483 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1484 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 1485 // XXX: cast to int is needed to avoid stupid warning: 1486 // compare with unsigned is always true 1487 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1488 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1489 return createRegOperand(getVgprClassId(Width), 1490 Val - SDWA9EncValues::SRC_VGPR_MIN); 1491 } 1492 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1493 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1494 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1495 return createSRegOperand(getSgprClassId(Width), 1496 Val - SDWA9EncValues::SRC_SGPR_MIN); 1497 } 1498 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1499 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1500 return createSRegOperand(getTtmpClassId(Width), 1501 Val - SDWA9EncValues::SRC_TTMP_MIN); 1502 } 1503 1504 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1505 1506 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1507 return decodeIntImmed(SVal); 1508 1509 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1510 return decodeFPImmed(Width, SVal); 1511 1512 return decodeSpecialReg32(SVal); 1513 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 1514 return createRegOperand(getVgprClassId(Width), Val); 1515 } 1516 llvm_unreachable("unsupported target"); 1517 } 1518 1519 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1520 return decodeSDWASrc(OPW16, Val); 1521 } 1522 1523 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1524 return decodeSDWASrc(OPW32, Val); 1525 } 1526 1527 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1528 using namespace AMDGPU::SDWA; 1529 1530 assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1531 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) && 1532 "SDWAVopcDst should be present only on GFX9+"); 1533 1534 bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64]; 1535 1536 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1537 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1538 1539 int TTmpIdx = getTTmpIdx(Val); 1540 if (TTmpIdx >= 0) { 1541 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1542 return createSRegOperand(TTmpClsId, TTmpIdx); 1543 } else if (Val > SGPR_MAX) { 1544 return IsWave64 ? decodeSpecialReg64(Val) 1545 : decodeSpecialReg32(Val); 1546 } else { 1547 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1548 } 1549 } else { 1550 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1551 } 1552 } 1553 1554 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1555 return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ? 1556 decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val); 1557 } 1558 1559 bool AMDGPUDisassembler::isVI() const { 1560 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]; 1561 } 1562 1563 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } 1564 1565 bool AMDGPUDisassembler::isGFX90A() const { 1566 return STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]; 1567 } 1568 1569 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } 1570 1571 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } 1572 1573 bool AMDGPUDisassembler::isGFX10Plus() const { 1574 return AMDGPU::isGFX10Plus(STI); 1575 } 1576 1577 bool AMDGPUDisassembler::isGFX11() const { 1578 return STI.getFeatureBits()[AMDGPU::FeatureGFX11]; 1579 } 1580 1581 bool AMDGPUDisassembler::isGFX11Plus() const { 1582 return AMDGPU::isGFX11Plus(STI); 1583 } 1584 1585 1586 bool AMDGPUDisassembler::hasArchitectedFlatScratch() const { 1587 return STI.getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch]; 1588 } 1589 1590 //===----------------------------------------------------------------------===// 1591 // AMDGPU specific symbol handling 1592 //===----------------------------------------------------------------------===// 1593 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1594 do { \ 1595 KdStream << Indent << DIRECTIVE " " \ 1596 << ((FourByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1597 } while (0) 1598 1599 // NOLINTNEXTLINE(readability-identifier-naming) 1600 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1601 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1602 using namespace amdhsa; 1603 StringRef Indent = "\t"; 1604 1605 // We cannot accurately backward compute #VGPRs used from 1606 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1607 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1608 // simply calculate the inverse of what the assembler does. 1609 1610 uint32_t GranulatedWorkitemVGPRCount = 1611 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT) >> 1612 COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT; 1613 1614 uint32_t NextFreeVGPR = (GranulatedWorkitemVGPRCount + 1) * 1615 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI); 1616 1617 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1618 1619 // We cannot backward compute values used to calculate 1620 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1621 // directives can't be computed: 1622 // .amdhsa_reserve_vcc 1623 // .amdhsa_reserve_flat_scratch 1624 // .amdhsa_reserve_xnack_mask 1625 // They take their respective default values if not specified in the assembly. 1626 // 1627 // GRANULATED_WAVEFRONT_SGPR_COUNT 1628 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1629 // 1630 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1631 // are set to 0. So while disassembling we consider that: 1632 // 1633 // GRANULATED_WAVEFRONT_SGPR_COUNT 1634 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1635 // 1636 // The disassembler cannot recover the original values of those 3 directives. 1637 1638 uint32_t GranulatedWavefrontSGPRCount = 1639 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT) >> 1640 COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT; 1641 1642 if (isGFX10Plus() && GranulatedWavefrontSGPRCount) 1643 return MCDisassembler::Fail; 1644 1645 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1646 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1647 1648 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1649 if (!hasArchitectedFlatScratch()) 1650 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1651 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1652 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1653 1654 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY) 1655 return MCDisassembler::Fail; 1656 1657 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1658 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1659 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1660 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1661 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1662 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1663 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1664 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1665 1666 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) 1667 return MCDisassembler::Fail; 1668 1669 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 1670 1671 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) 1672 return MCDisassembler::Fail; 1673 1674 PRINT_DIRECTIVE(".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 1675 1676 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) 1677 return MCDisassembler::Fail; 1678 1679 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER) 1680 return MCDisassembler::Fail; 1681 1682 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_FP16_OVFL); 1683 1684 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED0) 1685 return MCDisassembler::Fail; 1686 1687 if (isGFX10Plus()) { 1688 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1689 COMPUTE_PGM_RSRC1_WGP_MODE); 1690 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_MEM_ORDERED); 1691 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_FWD_PROGRESS); 1692 } 1693 return MCDisassembler::Success; 1694 } 1695 1696 // NOLINTNEXTLINE(readability-identifier-naming) 1697 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 1698 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1699 using namespace amdhsa; 1700 StringRef Indent = "\t"; 1701 if (hasArchitectedFlatScratch()) 1702 PRINT_DIRECTIVE(".amdhsa_enable_private_segment", 1703 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1704 else 1705 PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset", 1706 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1707 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 1708 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 1709 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 1710 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 1711 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 1712 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 1713 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 1714 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 1715 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 1716 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 1717 1718 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH) 1719 return MCDisassembler::Fail; 1720 1721 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY) 1722 return MCDisassembler::Fail; 1723 1724 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE) 1725 return MCDisassembler::Fail; 1726 1727 PRINT_DIRECTIVE( 1728 ".amdhsa_exception_fp_ieee_invalid_op", 1729 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 1730 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 1731 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 1732 PRINT_DIRECTIVE( 1733 ".amdhsa_exception_fp_ieee_div_zero", 1734 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 1735 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 1736 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 1737 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 1738 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 1739 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 1740 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 1741 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 1742 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 1743 1744 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0) 1745 return MCDisassembler::Fail; 1746 1747 return MCDisassembler::Success; 1748 } 1749 1750 #undef PRINT_DIRECTIVE 1751 1752 MCDisassembler::DecodeStatus 1753 AMDGPUDisassembler::decodeKernelDescriptorDirective( 1754 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 1755 raw_string_ostream &KdStream) const { 1756 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1757 do { \ 1758 KdStream << Indent << DIRECTIVE " " \ 1759 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1760 } while (0) 1761 1762 uint16_t TwoByteBuffer = 0; 1763 uint32_t FourByteBuffer = 0; 1764 1765 StringRef ReservedBytes; 1766 StringRef Indent = "\t"; 1767 1768 assert(Bytes.size() == 64); 1769 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 1770 1771 switch (Cursor.tell()) { 1772 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 1773 FourByteBuffer = DE.getU32(Cursor); 1774 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 1775 << '\n'; 1776 return MCDisassembler::Success; 1777 1778 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 1779 FourByteBuffer = DE.getU32(Cursor); 1780 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 1781 << FourByteBuffer << '\n'; 1782 return MCDisassembler::Success; 1783 1784 case amdhsa::KERNARG_SIZE_OFFSET: 1785 FourByteBuffer = DE.getU32(Cursor); 1786 KdStream << Indent << ".amdhsa_kernarg_size " 1787 << FourByteBuffer << '\n'; 1788 return MCDisassembler::Success; 1789 1790 case amdhsa::RESERVED0_OFFSET: 1791 // 4 reserved bytes, must be 0. 1792 ReservedBytes = DE.getBytes(Cursor, 4); 1793 for (int I = 0; I < 4; ++I) { 1794 if (ReservedBytes[I] != 0) { 1795 return MCDisassembler::Fail; 1796 } 1797 } 1798 return MCDisassembler::Success; 1799 1800 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 1801 // KERNEL_CODE_ENTRY_BYTE_OFFSET 1802 // So far no directive controls this for Code Object V3, so simply skip for 1803 // disassembly. 1804 DE.skip(Cursor, 8); 1805 return MCDisassembler::Success; 1806 1807 case amdhsa::RESERVED1_OFFSET: 1808 // 20 reserved bytes, must be 0. 1809 ReservedBytes = DE.getBytes(Cursor, 20); 1810 for (int I = 0; I < 20; ++I) { 1811 if (ReservedBytes[I] != 0) { 1812 return MCDisassembler::Fail; 1813 } 1814 } 1815 return MCDisassembler::Success; 1816 1817 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 1818 // COMPUTE_PGM_RSRC3 1819 // - Only set for GFX10, GFX6-9 have this to be 0. 1820 // - Currently no directives directly control this. 1821 FourByteBuffer = DE.getU32(Cursor); 1822 if (!isGFX10Plus() && FourByteBuffer) { 1823 return MCDisassembler::Fail; 1824 } 1825 return MCDisassembler::Success; 1826 1827 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 1828 FourByteBuffer = DE.getU32(Cursor); 1829 if (decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream) == 1830 MCDisassembler::Fail) { 1831 return MCDisassembler::Fail; 1832 } 1833 return MCDisassembler::Success; 1834 1835 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 1836 FourByteBuffer = DE.getU32(Cursor); 1837 if (decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream) == 1838 MCDisassembler::Fail) { 1839 return MCDisassembler::Fail; 1840 } 1841 return MCDisassembler::Success; 1842 1843 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 1844 using namespace amdhsa; 1845 TwoByteBuffer = DE.getU16(Cursor); 1846 1847 if (!hasArchitectedFlatScratch()) 1848 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 1849 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 1850 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 1851 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 1852 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 1853 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 1854 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 1855 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 1856 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 1857 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 1858 if (!hasArchitectedFlatScratch()) 1859 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 1860 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 1861 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 1862 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 1863 1864 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 1865 return MCDisassembler::Fail; 1866 1867 // Reserved for GFX9 1868 if (isGFX9() && 1869 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 1870 return MCDisassembler::Fail; 1871 } else if (isGFX10Plus()) { 1872 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 1873 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 1874 } 1875 1876 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) 1877 return MCDisassembler::Fail; 1878 1879 return MCDisassembler::Success; 1880 1881 case amdhsa::RESERVED2_OFFSET: 1882 // 6 bytes from here are reserved, must be 0. 1883 ReservedBytes = DE.getBytes(Cursor, 6); 1884 for (int I = 0; I < 6; ++I) { 1885 if (ReservedBytes[I] != 0) 1886 return MCDisassembler::Fail; 1887 } 1888 return MCDisassembler::Success; 1889 1890 default: 1891 llvm_unreachable("Unhandled index. Case statements cover everything."); 1892 return MCDisassembler::Fail; 1893 } 1894 #undef PRINT_DIRECTIVE 1895 } 1896 1897 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( 1898 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 1899 // CP microcode requires the kernel descriptor to be 64 aligned. 1900 if (Bytes.size() != 64 || KdAddress % 64 != 0) 1901 return MCDisassembler::Fail; 1902 1903 std::string Kd; 1904 raw_string_ostream KdStream(Kd); 1905 KdStream << ".amdhsa_kernel " << KdName << '\n'; 1906 1907 DataExtractor::Cursor C(0); 1908 while (C && C.tell() < Bytes.size()) { 1909 MCDisassembler::DecodeStatus Status = 1910 decodeKernelDescriptorDirective(C, Bytes, KdStream); 1911 1912 cantFail(C.takeError()); 1913 1914 if (Status == MCDisassembler::Fail) 1915 return MCDisassembler::Fail; 1916 } 1917 KdStream << ".end_amdhsa_kernel\n"; 1918 outs() << KdStream.str(); 1919 return MCDisassembler::Success; 1920 } 1921 1922 Optional<MCDisassembler::DecodeStatus> 1923 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 1924 ArrayRef<uint8_t> Bytes, uint64_t Address, 1925 raw_ostream &CStream) const { 1926 // Right now only kernel descriptor needs to be handled. 1927 // We ignore all other symbols for target specific handling. 1928 // TODO: 1929 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 1930 // Object V2 and V3 when symbols are marked protected. 1931 1932 // amd_kernel_code_t for Code Object V2. 1933 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 1934 Size = 256; 1935 return MCDisassembler::Fail; 1936 } 1937 1938 // Code Object V3 kernel descriptors. 1939 StringRef Name = Symbol.Name; 1940 if (Symbol.Type == ELF::STT_OBJECT && Name.endswith(StringRef(".kd"))) { 1941 Size = 64; // Size = 64 regardless of success or failure. 1942 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 1943 } 1944 return None; 1945 } 1946 1947 //===----------------------------------------------------------------------===// 1948 // AMDGPUSymbolizer 1949 //===----------------------------------------------------------------------===// 1950 1951 // Try to find symbol name for specified label 1952 bool AMDGPUSymbolizer::tryAddingSymbolicOperand( 1953 MCInst &Inst, raw_ostream & /*cStream*/, int64_t Value, 1954 uint64_t /*Address*/, bool IsBranch, uint64_t /*Offset*/, 1955 uint64_t /*OpSize*/, uint64_t /*InstSize*/) { 1956 1957 if (!IsBranch) { 1958 return false; 1959 } 1960 1961 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 1962 if (!Symbols) 1963 return false; 1964 1965 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { 1966 return Val.Addr == static_cast<uint64_t>(Value) && 1967 Val.Type == ELF::STT_NOTYPE; 1968 }); 1969 if (Result != Symbols->end()) { 1970 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 1971 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 1972 Inst.addOperand(MCOperand::createExpr(Add)); 1973 return true; 1974 } 1975 // Add to list of referenced addresses, so caller can synthesize a label. 1976 ReferencedAddresses.push_back(static_cast<uint64_t>(Value)); 1977 return false; 1978 } 1979 1980 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 1981 int64_t Value, 1982 uint64_t Address) { 1983 llvm_unreachable("unimplemented"); 1984 } 1985 1986 //===----------------------------------------------------------------------===// 1987 // Initialization 1988 //===----------------------------------------------------------------------===// 1989 1990 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 1991 LLVMOpInfoCallback /*GetOpInfo*/, 1992 LLVMSymbolLookupCallback /*SymbolLookUp*/, 1993 void *DisInfo, 1994 MCContext *Ctx, 1995 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 1996 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 1997 } 1998 1999 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 2000 const MCSubtargetInfo &STI, 2001 MCContext &Ctx) { 2002 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 2003 } 2004 2005 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 2006 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 2007 createAMDGPUDisassembler); 2008 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 2009 createAMDGPUSymbolizer); 2010 } 2011