1 //===-- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 //===----------------------------------------------------------------------===// 11 // 12 /// \file 13 /// 14 /// This file contains definition for AMDGPU ISA disassembler 15 // 16 //===----------------------------------------------------------------------===// 17 18 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 19 20 #include "AMDGPUDisassembler.h" 21 #include "AMDGPU.h" 22 #include "AMDGPURegisterInfo.h" 23 #include "SIDefines.h" 24 #include "Utils/AMDGPUBaseInfo.h" 25 26 #include "llvm/MC/MCContext.h" 27 #include "llvm/MC/MCFixedLenDisassembler.h" 28 #include "llvm/MC/MCInst.h" 29 #include "llvm/MC/MCInstrDesc.h" 30 #include "llvm/MC/MCSubtargetInfo.h" 31 #include "llvm/Support/ELF.h" 32 #include "llvm/Support/Endian.h" 33 #include "llvm/Support/Debug.h" 34 #include "llvm/Support/TargetRegistry.h" 35 36 37 using namespace llvm; 38 39 #define DEBUG_TYPE "amdgpu-disassembler" 40 41 typedef llvm::MCDisassembler::DecodeStatus DecodeStatus; 42 43 44 inline static MCDisassembler::DecodeStatus 45 addOperand(MCInst &Inst, const MCOperand& Opnd) { 46 Inst.addOperand(Opnd); 47 return Opnd.isValid() ? 48 MCDisassembler::Success : 49 MCDisassembler::SoftFail; 50 } 51 52 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, 53 uint64_t Addr, const void *Decoder) { 54 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 55 56 APInt SignedOffset(18, Imm * 4, true); 57 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 58 59 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2)) 60 return MCDisassembler::Success; 61 return addOperand(Inst, MCOperand::createImm(Imm)); 62 } 63 64 #define DECODE_OPERAND2(RegClass, DecName) \ 65 static DecodeStatus Decode##RegClass##RegisterClass(MCInst &Inst, \ 66 unsigned Imm, \ 67 uint64_t /*Addr*/, \ 68 const void *Decoder) { \ 69 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \ 70 return addOperand(Inst, DAsm->decodeOperand_##DecName(Imm)); \ 71 } 72 73 #define DECODE_OPERAND(RegClass) DECODE_OPERAND2(RegClass, RegClass) 74 75 DECODE_OPERAND(VGPR_32) 76 DECODE_OPERAND(VS_32) 77 DECODE_OPERAND(VS_64) 78 79 DECODE_OPERAND(VReg_64) 80 DECODE_OPERAND(VReg_96) 81 DECODE_OPERAND(VReg_128) 82 83 DECODE_OPERAND(SReg_32) 84 DECODE_OPERAND(SReg_32_XM0) 85 DECODE_OPERAND(SReg_64) 86 DECODE_OPERAND(SReg_128) 87 DECODE_OPERAND(SReg_256) 88 DECODE_OPERAND(SReg_512) 89 90 #define GET_SUBTARGETINFO_ENUM 91 #include "AMDGPUGenSubtargetInfo.inc" 92 #undef GET_SUBTARGETINFO_ENUM 93 94 #include "AMDGPUGenDisassemblerTables.inc" 95 96 //===----------------------------------------------------------------------===// 97 // 98 //===----------------------------------------------------------------------===// 99 100 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 101 assert(Bytes.size() >= sizeof(T)); 102 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data()); 103 Bytes = Bytes.slice(sizeof(T)); 104 return Res; 105 } 106 107 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table, 108 MCInst &MI, 109 uint64_t Inst, 110 uint64_t Address) const { 111 assert(MI.getOpcode() == 0); 112 assert(MI.getNumOperands() == 0); 113 MCInst TmpInst; 114 const auto SavedBytes = Bytes; 115 if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) { 116 MI = TmpInst; 117 return MCDisassembler::Success; 118 } 119 Bytes = SavedBytes; 120 return MCDisassembler::Fail; 121 } 122 123 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 124 ArrayRef<uint8_t> Bytes_, 125 uint64_t Address, 126 raw_ostream &WS, 127 raw_ostream &CS) const { 128 CommentStream = &CS; 129 130 // ToDo: AMDGPUDisassembler supports only VI ISA. 131 assert(AMDGPU::isVI(STI) && "Can disassemble only VI ISA."); 132 133 const unsigned MaxInstBytesNum = (std::min)((size_t)8, Bytes_.size()); 134 Bytes = Bytes_.slice(0, MaxInstBytesNum); 135 136 DecodeStatus Res = MCDisassembler::Fail; 137 do { 138 // ToDo: better to switch encoding length using some bit predicate 139 // but it is unknown yet, so try all we can 140 141 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 142 // encodings 143 if (Bytes.size() >= 8) { 144 const uint64_t QW = eatBytes<uint64_t>(Bytes); 145 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address); 146 if (Res) break; 147 148 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address); 149 if (Res) break; 150 } 151 152 // Reinitialize Bytes as DPP64 could have eaten too much 153 Bytes = Bytes_.slice(0, MaxInstBytesNum); 154 155 // Try decode 32-bit instruction 156 if (Bytes.size() < 4) break; 157 const uint32_t DW = eatBytes<uint32_t>(Bytes); 158 Res = tryDecodeInst(DecoderTableVI32, MI, DW, Address); 159 if (Res) break; 160 161 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address); 162 if (Res) break; 163 164 if (Bytes.size() < 4) break; 165 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 166 Res = tryDecodeInst(DecoderTableVI64, MI, QW, Address); 167 if (Res) break; 168 169 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address); 170 } while (false); 171 172 Size = Res ? (MaxInstBytesNum - Bytes.size()) : 0; 173 return Res; 174 } 175 176 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 177 return getContext().getRegisterInfo()-> 178 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 179 } 180 181 inline 182 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 183 const Twine& ErrMsg) const { 184 *CommentStream << "Error: " + ErrMsg; 185 186 // ToDo: add support for error operands to MCInst.h 187 // return MCOperand::createError(V); 188 return MCOperand(); 189 } 190 191 inline 192 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 193 return MCOperand::createReg(RegId); 194 } 195 196 inline 197 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 198 unsigned Val) const { 199 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 200 if (Val >= RegCl.getNumRegs()) 201 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 202 ": unknown register " + Twine(Val)); 203 return createRegOperand(RegCl.getRegister(Val)); 204 } 205 206 inline 207 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 208 unsigned Val) const { 209 // ToDo: SI/CI have 104 SGPRs, VI - 102 210 // Valery: here we accepting as much as we can, let assembler sort it out 211 int shift = 0; 212 switch (SRegClassID) { 213 case AMDGPU::SGPR_32RegClassID: 214 case AMDGPU::TTMP_32RegClassID: 215 break; 216 case AMDGPU::SGPR_64RegClassID: 217 case AMDGPU::TTMP_64RegClassID: 218 shift = 1; 219 break; 220 case AMDGPU::SGPR_128RegClassID: 221 case AMDGPU::TTMP_128RegClassID: 222 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 223 // this bundle? 224 case AMDGPU::SReg_256RegClassID: 225 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 226 // this bundle? 227 case AMDGPU::SReg_512RegClassID: 228 shift = 2; 229 break; 230 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 231 // this bundle? 232 default: 233 assert(false); 234 break; 235 } 236 if (Val % (1 << shift)) 237 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 238 << ": scalar reg isn't aligned " << Val; 239 return createRegOperand(SRegClassID, Val >> shift); 240 } 241 242 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { 243 return decodeSrcOp(OPW32, Val); 244 } 245 246 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { 247 return decodeSrcOp(OPW64, Val); 248 } 249 250 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { 251 // Some instructions have operand restrictions beyond what the encoding 252 // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra 253 // high bit. 254 Val &= 255; 255 256 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); 257 } 258 259 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { 260 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); 261 } 262 263 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { 264 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); 265 } 266 267 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { 268 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); 269 } 270 271 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { 272 // table-gen generated disassembler doesn't care about operand types 273 // leaving only registry class so SSrc_32 operand turns into SReg_32 274 // and therefore we accept immediates and literals here as well 275 return decodeSrcOp(OPW32, Val); 276 } 277 278 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0(unsigned Val) const { 279 // SReg_32_XM0 is SReg_32 without M0 280 return decodeOperand_SReg_32(Val); 281 } 282 283 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { 284 // see decodeOperand_SReg_32 comment 285 return decodeSrcOp(OPW64, Val); 286 } 287 288 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { 289 return decodeSrcOp(OPW128, Val); 290 } 291 292 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { 293 return createSRegOperand(AMDGPU::SReg_256RegClassID, Val); 294 } 295 296 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { 297 return createSRegOperand(AMDGPU::SReg_512RegClassID, Val); 298 } 299 300 301 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { 302 // For now all literal constants are supposed to be unsigned integer 303 // ToDo: deal with signed/unsigned 64-bit integer constants 304 // ToDo: deal with float/double constants 305 if (Bytes.size() < 4) 306 return errOperand(0, "cannot read literal, inst bytes left " + 307 Twine(Bytes.size())); 308 return MCOperand::createImm(eatBytes<uint32_t>(Bytes)); 309 } 310 311 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 312 using namespace AMDGPU::EncValues; 313 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 314 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 315 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 316 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 317 // Cast prevents negative overflow. 318 } 319 320 MCOperand AMDGPUDisassembler::decodeFPImmed(bool Is32, unsigned Imm) { 321 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 322 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 323 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 324 // ToDo: AMDGPUInstPrinter does not support 1/(2*PI). It consider 1/(2*PI) as 325 // literal constant. 326 float V = 0.0f; 327 switch (Imm) { 328 case 240: V = 0.5f; break; 329 case 241: V = -0.5f; break; 330 case 242: V = 1.0f; break; 331 case 243: V = -1.0f; break; 332 case 244: V = 2.0f; break; 333 case 245: V = -2.0f; break; 334 case 246: V = 4.0f; break; 335 case 247: V = -4.0f; break; 336 case 248: return MCOperand::createImm(Is32 ? // 1/(2*PI) 337 0x3e22f983 : 338 0x3fc45f306dc9c882); 339 default: break; 340 } 341 return MCOperand::createImm(Is32? FloatToBits(V) : DoubleToBits(V)); 342 } 343 344 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 345 using namespace AMDGPU; 346 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 347 switch (Width) { 348 default: // fall 349 case OPW32: return VGPR_32RegClassID; 350 case OPW64: return VReg_64RegClassID; 351 case OPW128: return VReg_128RegClassID; 352 } 353 } 354 355 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 356 using namespace AMDGPU; 357 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 358 switch (Width) { 359 default: // fall 360 case OPW32: return SGPR_32RegClassID; 361 case OPW64: return SGPR_64RegClassID; 362 case OPW128: return SGPR_128RegClassID; 363 } 364 } 365 366 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 367 using namespace AMDGPU; 368 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 369 switch (Width) { 370 default: // fall 371 case OPW32: return TTMP_32RegClassID; 372 case OPW64: return TTMP_64RegClassID; 373 case OPW128: return TTMP_128RegClassID; 374 } 375 } 376 377 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const { 378 using namespace AMDGPU::EncValues; 379 assert(Val < 512); // enum9 380 381 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 382 return createRegOperand(getVgprClassId(Width), Val - VGPR_MIN); 383 } 384 if (Val <= SGPR_MAX) { 385 assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning. 386 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 387 } 388 if (TTMP_MIN <= Val && Val <= TTMP_MAX) { 389 return createSRegOperand(getTtmpClassId(Width), Val - TTMP_MIN); 390 } 391 392 assert(Width == OPW32 || Width == OPW64); 393 const bool Is32 = (Width == OPW32); 394 395 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 396 return decodeIntImmed(Val); 397 398 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 399 return decodeFPImmed(Is32, Val); 400 401 if (Val == LITERAL_CONST) 402 return decodeLiteralConstant(); 403 404 return Is32 ? decodeSpecialReg32(Val) : decodeSpecialReg64(Val); 405 } 406 407 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 408 using namespace AMDGPU; 409 switch (Val) { 410 case 102: return createRegOperand(getMCReg(FLAT_SCR_LO, STI)); 411 case 103: return createRegOperand(getMCReg(FLAT_SCR_HI, STI)); 412 // ToDo: no support for xnack_mask_lo/_hi register 413 case 104: 414 case 105: break; 415 case 106: return createRegOperand(VCC_LO); 416 case 107: return createRegOperand(VCC_HI); 417 case 108: return createRegOperand(TBA_LO); 418 case 109: return createRegOperand(TBA_HI); 419 case 110: return createRegOperand(TMA_LO); 420 case 111: return createRegOperand(TMA_HI); 421 case 124: return createRegOperand(M0); 422 case 126: return createRegOperand(EXEC_LO); 423 case 127: return createRegOperand(EXEC_HI); 424 // ToDo: no support for vccz register 425 case 251: break; 426 // ToDo: no support for execz register 427 case 252: break; 428 case 253: return createRegOperand(SCC); 429 default: break; 430 } 431 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 432 } 433 434 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 435 using namespace AMDGPU; 436 switch (Val) { 437 case 102: return createRegOperand(getMCReg(FLAT_SCR, STI)); 438 case 106: return createRegOperand(VCC); 439 case 108: return createRegOperand(TBA); 440 case 110: return createRegOperand(TMA); 441 case 126: return createRegOperand(EXEC); 442 default: break; 443 } 444 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 445 } 446 447 //===----------------------------------------------------------------------===// 448 // AMDGPUSymbolizer 449 //===----------------------------------------------------------------------===// 450 451 // Try to find symbol name for specified label 452 bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst, 453 raw_ostream &/*cStream*/, int64_t Value, 454 uint64_t /*Address*/, bool IsBranch, 455 uint64_t /*Offset*/, uint64_t /*InstSize*/) { 456 typedef std::tuple<uint64_t, StringRef, uint8_t> SymbolInfoTy; 457 typedef std::vector<SymbolInfoTy> SectionSymbolsTy; 458 459 if (!IsBranch) { 460 return false; 461 } 462 463 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 464 auto Result = std::find_if(Symbols->begin(), Symbols->end(), 465 [Value](const SymbolInfoTy& Val) { 466 return std::get<0>(Val) == static_cast<uint64_t>(Value) 467 && std::get<2>(Val) == ELF::STT_NOTYPE; 468 }); 469 if (Result != Symbols->end()) { 470 auto *Sym = Ctx.getOrCreateSymbol(std::get<1>(*Result)); 471 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 472 Inst.addOperand(MCOperand::createExpr(Add)); 473 return true; 474 } 475 return false; 476 } 477 478 //===----------------------------------------------------------------------===// 479 // Initialization 480 //===----------------------------------------------------------------------===// 481 482 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 483 LLVMOpInfoCallback /*GetOpInfo*/, 484 LLVMSymbolLookupCallback /*SymbolLookUp*/, 485 void *DisInfo, 486 MCContext *Ctx, 487 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 488 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 489 } 490 491 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 492 const MCSubtargetInfo &STI, 493 MCContext &Ctx) { 494 return new AMDGPUDisassembler(STI, Ctx); 495 } 496 497 extern "C" void LLVMInitializeAMDGPUDisassembler() { 498 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 499 createAMDGPUDisassembler); 500 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 501 createAMDGPUSymbolizer); 502 } 503