1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "TargetInfo/AMDGPUTargetInfo.h" 22 #include "Utils/AMDGPUBaseInfo.h" 23 #include "llvm-c/DisassemblerTypes.h" 24 #include "llvm/BinaryFormat/ELF.h" 25 #include "llvm/MC/MCAsmInfo.h" 26 #include "llvm/MC/MCContext.h" 27 #include "llvm/MC/MCExpr.h" 28 #include "llvm/MC/MCFixedLenDisassembler.h" 29 #include "llvm/MC/MCInstrDesc.h" 30 #include "llvm/MC/MCRegisterInfo.h" 31 #include "llvm/MC/MCSubtargetInfo.h" 32 #include "llvm/MC/TargetRegistry.h" 33 #include "llvm/Support/AMDHSAKernelDescriptor.h" 34 35 using namespace llvm; 36 37 #define DEBUG_TYPE "amdgpu-disassembler" 38 39 #define SGPR_MAX \ 40 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 41 : AMDGPU::EncValues::SGPR_MAX_SI) 42 43 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 44 45 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 46 MCContext &Ctx, 47 MCInstrInfo const *MCII) : 48 MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), 49 TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) { 50 51 // ToDo: AMDGPUDisassembler supports only VI ISA. 52 if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10Plus()) 53 report_fatal_error("Disassembly not yet supported for subtarget"); 54 } 55 56 inline static MCDisassembler::DecodeStatus 57 addOperand(MCInst &Inst, const MCOperand& Opnd) { 58 Inst.addOperand(Opnd); 59 return Opnd.isValid() ? 60 MCDisassembler::Success : 61 MCDisassembler::Fail; 62 } 63 64 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 65 uint16_t NameIdx) { 66 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 67 if (OpIdx != -1) { 68 auto I = MI.begin(); 69 std::advance(I, OpIdx); 70 MI.insert(I, Op); 71 } 72 return OpIdx; 73 } 74 75 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, 76 uint64_t Addr, const void *Decoder) { 77 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 78 79 // Our branches take a simm16, but we need two extra bits to account for the 80 // factor of 4. 81 APInt SignedOffset(18, Imm * 4, true); 82 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 83 84 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2)) 85 return MCDisassembler::Success; 86 return addOperand(Inst, MCOperand::createImm(Imm)); 87 } 88 89 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, 90 uint64_t Addr, const void *Decoder) { 91 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 92 int64_t Offset; 93 if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 94 Offset = Imm & 0xFFFFF; 95 } else { // GFX9+ supports 21-bit signed offsets. 96 Offset = SignExtend64<21>(Imm); 97 } 98 return addOperand(Inst, MCOperand::createImm(Offset)); 99 } 100 101 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, 102 uint64_t Addr, const void *Decoder) { 103 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 104 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 105 } 106 107 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 108 static DecodeStatus StaticDecoderName(MCInst &Inst, \ 109 unsigned Imm, \ 110 uint64_t /*Addr*/, \ 111 const void *Decoder) { \ 112 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \ 113 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 114 } 115 116 #define DECODE_OPERAND_REG(RegClass) \ 117 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass) 118 119 DECODE_OPERAND_REG(VGPR_32) 120 DECODE_OPERAND_REG(VRegOrLds_32) 121 DECODE_OPERAND_REG(VS_32) 122 DECODE_OPERAND_REG(VS_64) 123 DECODE_OPERAND_REG(VS_128) 124 125 DECODE_OPERAND_REG(VReg_64) 126 DECODE_OPERAND_REG(VReg_96) 127 DECODE_OPERAND_REG(VReg_128) 128 DECODE_OPERAND_REG(VReg_256) 129 DECODE_OPERAND_REG(VReg_512) 130 DECODE_OPERAND_REG(VReg_1024) 131 132 DECODE_OPERAND_REG(SReg_32) 133 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC) 134 DECODE_OPERAND_REG(SReg_32_XEXEC_HI) 135 DECODE_OPERAND_REG(SRegOrLds_32) 136 DECODE_OPERAND_REG(SReg_64) 137 DECODE_OPERAND_REG(SReg_64_XEXEC) 138 DECODE_OPERAND_REG(SReg_128) 139 DECODE_OPERAND_REG(SReg_256) 140 DECODE_OPERAND_REG(SReg_512) 141 142 DECODE_OPERAND_REG(AGPR_32) 143 DECODE_OPERAND_REG(AReg_64) 144 DECODE_OPERAND_REG(AReg_128) 145 DECODE_OPERAND_REG(AReg_256) 146 DECODE_OPERAND_REG(AReg_512) 147 DECODE_OPERAND_REG(AReg_1024) 148 DECODE_OPERAND_REG(AV_32) 149 DECODE_OPERAND_REG(AV_64) 150 151 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, 152 unsigned Imm, 153 uint64_t Addr, 154 const void *Decoder) { 155 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 156 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 157 } 158 159 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, 160 unsigned Imm, 161 uint64_t Addr, 162 const void *Decoder) { 163 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 164 return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm)); 165 } 166 167 static DecodeStatus decodeOperand_VSrcV232(MCInst &Inst, 168 unsigned Imm, 169 uint64_t Addr, 170 const void *Decoder) { 171 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 172 return addOperand(Inst, DAsm->decodeOperand_VSrcV232(Imm)); 173 } 174 175 static DecodeStatus decodeOperand_VS_16(MCInst &Inst, 176 unsigned Imm, 177 uint64_t Addr, 178 const void *Decoder) { 179 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 180 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 181 } 182 183 static DecodeStatus decodeOperand_VS_32(MCInst &Inst, 184 unsigned Imm, 185 uint64_t Addr, 186 const void *Decoder) { 187 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 188 return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm)); 189 } 190 191 static DecodeStatus decodeOperand_AReg_64(MCInst &Inst, 192 unsigned Imm, 193 uint64_t Addr, 194 const void *Decoder) { 195 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 196 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm | 512)); 197 } 198 199 static DecodeStatus decodeOperand_AReg_128(MCInst &Inst, 200 unsigned Imm, 201 uint64_t Addr, 202 const void *Decoder) { 203 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 204 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512)); 205 } 206 207 static DecodeStatus decodeOperand_AReg_256(MCInst &Inst, 208 unsigned Imm, 209 uint64_t Addr, 210 const void *Decoder) { 211 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 212 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm | 512)); 213 } 214 215 static DecodeStatus decodeOperand_AReg_512(MCInst &Inst, 216 unsigned Imm, 217 uint64_t Addr, 218 const void *Decoder) { 219 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 220 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512)); 221 } 222 223 static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst, 224 unsigned Imm, 225 uint64_t Addr, 226 const void *Decoder) { 227 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 228 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512)); 229 } 230 231 static DecodeStatus decodeOperand_VReg_64(MCInst &Inst, 232 unsigned Imm, 233 uint64_t Addr, 234 const void *Decoder) { 235 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 236 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm)); 237 } 238 239 static DecodeStatus decodeOperand_VReg_128(MCInst &Inst, 240 unsigned Imm, 241 uint64_t Addr, 242 const void *Decoder) { 243 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 244 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm)); 245 } 246 247 static DecodeStatus decodeOperand_VReg_256(MCInst &Inst, 248 unsigned Imm, 249 uint64_t Addr, 250 const void *Decoder) { 251 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 252 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm)); 253 } 254 255 static DecodeStatus decodeOperand_VReg_512(MCInst &Inst, 256 unsigned Imm, 257 uint64_t Addr, 258 const void *Decoder) { 259 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 260 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm)); 261 } 262 263 static DecodeStatus decodeOperand_VReg_1024(MCInst &Inst, 264 unsigned Imm, 265 uint64_t Addr, 266 const void *Decoder) { 267 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 268 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm)); 269 } 270 271 static DecodeStatus decodeOperand_f32kimm(MCInst &Inst, unsigned Imm, 272 uint64_t Addr, const void *Decoder) { 273 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 274 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 275 } 276 277 static DecodeStatus decodeOperand_f16kimm(MCInst &Inst, unsigned Imm, 278 uint64_t Addr, const void *Decoder) { 279 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 280 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 281 } 282 283 static DecodeStatus decodeOperand_VS_16_Deferred(MCInst &Inst, unsigned Imm, 284 uint64_t Addr, 285 const void *Decoder) { 286 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 287 return addOperand( 288 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW16, Imm, true)); 289 } 290 291 static DecodeStatus decodeOperand_VS_32_Deferred(MCInst &Inst, unsigned Imm, 292 uint64_t Addr, 293 const void *Decoder) { 294 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 295 return addOperand( 296 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW32, Imm, true)); 297 } 298 299 static bool IsAGPROperand(const MCInst &Inst, int OpIdx, 300 const MCRegisterInfo *MRI) { 301 if (OpIdx < 0) 302 return false; 303 304 const MCOperand &Op = Inst.getOperand(OpIdx); 305 if (!Op.isReg()) 306 return false; 307 308 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); 309 auto Reg = Sub ? Sub : Op.getReg(); 310 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; 311 } 312 313 static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, 314 unsigned Imm, 315 AMDGPUDisassembler::OpWidthTy Opw, 316 const void *Decoder) { 317 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 318 if (!DAsm->isGFX90A()) { 319 Imm &= 511; 320 } else { 321 // If atomic has both vdata and vdst their register classes are tied. 322 // The bit is decoded along with the vdst, first operand. We need to 323 // change register class to AGPR if vdst was AGPR. 324 // If a DS instruction has both data0 and data1 their register classes 325 // are also tied. 326 unsigned Opc = Inst.getOpcode(); 327 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; 328 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 329 : AMDGPU::OpName::vdata; 330 const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo(); 331 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); 332 if ((int)Inst.getNumOperands() == DataIdx) { 333 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); 334 if (IsAGPROperand(Inst, DstIdx, MRI)) 335 Imm |= 512; 336 } 337 338 if (TSFlags & SIInstrFlags::DS) { 339 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); 340 if ((int)Inst.getNumOperands() == Data2Idx && 341 IsAGPROperand(Inst, DataIdx, MRI)) 342 Imm |= 512; 343 } 344 } 345 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); 346 } 347 348 static DecodeStatus DecodeAVLdSt_32RegisterClass(MCInst &Inst, 349 unsigned Imm, 350 uint64_t Addr, 351 const void *Decoder) { 352 return decodeOperand_AVLdSt_Any(Inst, Imm, 353 AMDGPUDisassembler::OPW32, Decoder); 354 } 355 356 static DecodeStatus DecodeAVLdSt_64RegisterClass(MCInst &Inst, 357 unsigned Imm, 358 uint64_t Addr, 359 const void *Decoder) { 360 return decodeOperand_AVLdSt_Any(Inst, Imm, 361 AMDGPUDisassembler::OPW64, Decoder); 362 } 363 364 static DecodeStatus DecodeAVLdSt_96RegisterClass(MCInst &Inst, 365 unsigned Imm, 366 uint64_t Addr, 367 const void *Decoder) { 368 return decodeOperand_AVLdSt_Any(Inst, Imm, 369 AMDGPUDisassembler::OPW96, Decoder); 370 } 371 372 static DecodeStatus DecodeAVLdSt_128RegisterClass(MCInst &Inst, 373 unsigned Imm, 374 uint64_t Addr, 375 const void *Decoder) { 376 return decodeOperand_AVLdSt_Any(Inst, Imm, 377 AMDGPUDisassembler::OPW128, Decoder); 378 } 379 380 static DecodeStatus decodeOperand_SReg_32(MCInst &Inst, 381 unsigned Imm, 382 uint64_t Addr, 383 const void *Decoder) { 384 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 385 return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm)); 386 } 387 388 static DecodeStatus decodeOperand_VGPR_32(MCInst &Inst, 389 unsigned Imm, 390 uint64_t Addr, 391 const void *Decoder) { 392 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 393 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW32, Imm)); 394 } 395 396 #define DECODE_SDWA(DecName) \ 397 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 398 399 DECODE_SDWA(Src32) 400 DECODE_SDWA(Src16) 401 DECODE_SDWA(VopcDst) 402 403 #include "AMDGPUGenDisassemblerTables.inc" 404 405 //===----------------------------------------------------------------------===// 406 // 407 //===----------------------------------------------------------------------===// 408 409 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 410 assert(Bytes.size() >= sizeof(T)); 411 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data()); 412 Bytes = Bytes.slice(sizeof(T)); 413 return Res; 414 } 415 416 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table, 417 MCInst &MI, 418 uint64_t Inst, 419 uint64_t Address) const { 420 assert(MI.getOpcode() == 0); 421 assert(MI.getNumOperands() == 0); 422 MCInst TmpInst; 423 HasLiteral = false; 424 const auto SavedBytes = Bytes; 425 if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) { 426 MI = TmpInst; 427 return MCDisassembler::Success; 428 } 429 Bytes = SavedBytes; 430 return MCDisassembler::Fail; 431 } 432 433 // The disassembler is greedy, so we need to check FI operand value to 434 // not parse a dpp if the correct literal is not set. For dpp16 the 435 // autogenerated decoder checks the dpp literal 436 static bool isValidDPP8(const MCInst &MI) { 437 using namespace llvm::AMDGPU::DPP; 438 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi); 439 assert(FiIdx != -1); 440 if ((unsigned)FiIdx >= MI.getNumOperands()) 441 return false; 442 unsigned Fi = MI.getOperand(FiIdx).getImm(); 443 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1; 444 } 445 446 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 447 ArrayRef<uint8_t> Bytes_, 448 uint64_t Address, 449 raw_ostream &CS) const { 450 CommentStream = &CS; 451 bool IsSDWA = false; 452 453 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 454 Bytes = Bytes_.slice(0, MaxInstBytesNum); 455 456 DecodeStatus Res = MCDisassembler::Fail; 457 do { 458 // ToDo: better to switch encoding length using some bit predicate 459 // but it is unknown yet, so try all we can 460 461 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 462 // encodings 463 if (Bytes.size() >= 8) { 464 const uint64_t QW = eatBytes<uint64_t>(Bytes); 465 466 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 467 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address); 468 if (Res) { 469 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) 470 == -1) 471 break; 472 if (convertDPP8Inst(MI) == MCDisassembler::Success) 473 break; 474 MI = MCInst(); // clear 475 } 476 } 477 478 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address); 479 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 480 break; 481 482 MI = MCInst(); // clear 483 484 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address); 485 if (Res) break; 486 487 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address); 488 if (Res) { IsSDWA = true; break; } 489 490 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address); 491 if (Res) { IsSDWA = true; break; } 492 493 Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address); 494 if (Res) { IsSDWA = true; break; } 495 496 if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) { 497 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address); 498 if (Res) 499 break; 500 } 501 502 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 503 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 504 // table first so we print the correct name. 505 if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) { 506 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address); 507 if (Res) 508 break; 509 } 510 } 511 512 // Reinitialize Bytes as DPP64 could have eaten too much 513 Bytes = Bytes_.slice(0, MaxInstBytesNum); 514 515 // Try decode 32-bit instruction 516 if (Bytes.size() < 4) break; 517 const uint32_t DW = eatBytes<uint32_t>(Bytes); 518 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address); 519 if (Res) break; 520 521 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address); 522 if (Res) break; 523 524 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address); 525 if (Res) break; 526 527 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 528 Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address); 529 if (Res) 530 break; 531 } 532 533 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 534 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address); 535 if (Res) break; 536 } 537 538 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address); 539 if (Res) break; 540 541 if (Bytes.size() < 4) break; 542 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 543 544 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 545 Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address); 546 if (Res) 547 break; 548 } 549 550 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address); 551 if (Res) break; 552 553 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address); 554 if (Res) break; 555 556 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address); 557 if (Res) break; 558 559 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address); 560 } while (false); 561 562 if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi || 563 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 || 564 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 || 565 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 || 566 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 || 567 MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi || 568 MI.getOpcode() == AMDGPU::V_FMAC_F64_e64_gfx90a || 569 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi || 570 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 || 571 MI.getOpcode() == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 || 572 MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10)) { 573 // Insert dummy unused src2_modifiers. 574 insertNamedMCOperand(MI, MCOperand::createImm(0), 575 AMDGPU::OpName::src2_modifiers); 576 } 577 578 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 579 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT | SIInstrFlags::SMRD))) { 580 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 581 AMDGPU::OpName::cpol); 582 if (CPolPos != -1) { 583 unsigned CPol = 584 (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ? 585 AMDGPU::CPol::GLC : 0; 586 if (MI.getNumOperands() <= (unsigned)CPolPos) { 587 insertNamedMCOperand(MI, MCOperand::createImm(CPol), 588 AMDGPU::OpName::cpol); 589 } else if (CPol) { 590 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); 591 } 592 } 593 } 594 595 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 596 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) && 597 (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts])) { 598 // GFX90A lost TFE, its place is occupied by ACC. 599 int TFEOpIdx = 600 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); 601 if (TFEOpIdx != -1) { 602 auto TFEIter = MI.begin(); 603 std::advance(TFEIter, TFEOpIdx); 604 MI.insert(TFEIter, MCOperand::createImm(0)); 605 } 606 } 607 608 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 609 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF))) { 610 int SWZOpIdx = 611 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); 612 if (SWZOpIdx != -1) { 613 auto SWZIter = MI.begin(); 614 std::advance(SWZIter, SWZOpIdx); 615 MI.insert(SWZIter, MCOperand::createImm(0)); 616 } 617 } 618 619 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 620 int VAddr0Idx = 621 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 622 int RsrcIdx = 623 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 624 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 625 if (VAddr0Idx >= 0 && NSAArgs > 0) { 626 unsigned NSAWords = (NSAArgs + 3) / 4; 627 if (Bytes.size() < 4 * NSAWords) { 628 Res = MCDisassembler::Fail; 629 } else { 630 for (unsigned i = 0; i < NSAArgs; ++i) { 631 MI.insert(MI.begin() + VAddr0Idx + 1 + i, 632 decodeOperand_VGPR_32(Bytes[i])); 633 } 634 Bytes = Bytes.slice(4 * NSAWords); 635 } 636 } 637 638 if (Res) 639 Res = convertMIMGInst(MI); 640 } 641 642 if (Res && IsSDWA) 643 Res = convertSDWAInst(MI); 644 645 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 646 AMDGPU::OpName::vdst_in); 647 if (VDstIn_Idx != -1) { 648 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 649 MCOI::OperandConstraint::TIED_TO); 650 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 651 !MI.getOperand(VDstIn_Idx).isReg() || 652 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 653 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 654 MI.erase(&MI.getOperand(VDstIn_Idx)); 655 insertNamedMCOperand(MI, 656 MCOperand::createReg(MI.getOperand(Tied).getReg()), 657 AMDGPU::OpName::vdst_in); 658 } 659 } 660 661 int ImmLitIdx = 662 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm); 663 if (Res && ImmLitIdx != -1) 664 Res = convertFMAanyK(MI, ImmLitIdx); 665 666 // if the opcode was not recognized we'll assume a Size of 4 bytes 667 // (unless there are fewer bytes left) 668 Size = Res ? (MaxInstBytesNum - Bytes.size()) 669 : std::min((size_t)4, Bytes_.size()); 670 return Res; 671 } 672 673 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 674 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 675 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 676 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1) 677 // VOPC - insert clamp 678 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 679 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 680 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 681 if (SDst != -1) { 682 // VOPC - insert VCC register as sdst 683 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 684 AMDGPU::OpName::sdst); 685 } else { 686 // VOP1/2 - insert omod if present in instruction 687 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 688 } 689 } 690 return MCDisassembler::Success; 691 } 692 693 // We must check FI == literal to reject not genuine dpp8 insts, and we must 694 // first add optional MI operands to check FI 695 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 696 unsigned Opc = MI.getOpcode(); 697 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 698 699 // Insert dummy unused src modifiers. 700 if (MI.getNumOperands() < DescNumOps && 701 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1) 702 insertNamedMCOperand(MI, MCOperand::createImm(0), 703 AMDGPU::OpName::src0_modifiers); 704 705 if (MI.getNumOperands() < DescNumOps && 706 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1) 707 insertNamedMCOperand(MI, MCOperand::createImm(0), 708 AMDGPU::OpName::src1_modifiers); 709 710 return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail; 711 } 712 713 // Note that before gfx10, the MIMG encoding provided no information about 714 // VADDR size. Consequently, decoded instructions always show address as if it 715 // has 1 dword, which could be not really so. 716 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 717 718 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 719 AMDGPU::OpName::vdst); 720 721 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 722 AMDGPU::OpName::vdata); 723 int VAddr0Idx = 724 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 725 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 726 AMDGPU::OpName::dmask); 727 728 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 729 AMDGPU::OpName::tfe); 730 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 731 AMDGPU::OpName::d16); 732 733 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 734 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 735 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 736 737 assert(VDataIdx != -1); 738 if (BaseOpcode->BVH) { 739 // Add A16 operand for intersect_ray instructions 740 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16) > -1) { 741 addOperand(MI, MCOperand::createImm(1)); 742 } 743 return MCDisassembler::Success; 744 } 745 746 bool IsAtomic = (VDstIdx != -1); 747 bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4; 748 bool IsNSA = false; 749 unsigned AddrSize = Info->VAddrDwords; 750 751 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 752 unsigned DimIdx = 753 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 754 int A16Idx = 755 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16); 756 const AMDGPU::MIMGDimInfo *Dim = 757 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 758 const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm()); 759 760 AddrSize = 761 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); 762 763 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA; 764 if (!IsNSA) { 765 if (AddrSize > 8) 766 AddrSize = 16; 767 } else { 768 if (AddrSize > Info->VAddrDwords) { 769 // The NSA encoding does not contain enough operands for the combination 770 // of base opcode / dimension. Should this be an error? 771 return MCDisassembler::Success; 772 } 773 } 774 } 775 776 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 777 unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u); 778 779 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 780 if (D16 && AMDGPU::hasPackedD16(STI)) { 781 DstSize = (DstSize + 1) / 2; 782 } 783 784 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm()) 785 DstSize += 1; 786 787 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 788 return MCDisassembler::Success; 789 790 int NewOpcode = 791 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 792 if (NewOpcode == -1) 793 return MCDisassembler::Success; 794 795 // Widen the register to the correct number of enabled channels. 796 unsigned NewVdata = AMDGPU::NoRegister; 797 if (DstSize != Info->VDataDwords) { 798 auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; 799 800 // Get first subregister of VData 801 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 802 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 803 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 804 805 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 806 &MRI.getRegClass(DataRCID)); 807 if (NewVdata == AMDGPU::NoRegister) { 808 // It's possible to encode this such that the low register + enabled 809 // components exceeds the register count. 810 return MCDisassembler::Success; 811 } 812 } 813 814 unsigned NewVAddr0 = AMDGPU::NoRegister; 815 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10] && !IsNSA && 816 AddrSize != Info->VAddrDwords) { 817 unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg(); 818 unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0); 819 VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0; 820 821 auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass; 822 NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0, 823 &MRI.getRegClass(AddrRCID)); 824 if (NewVAddr0 == AMDGPU::NoRegister) 825 return MCDisassembler::Success; 826 } 827 828 MI.setOpcode(NewOpcode); 829 830 if (NewVdata != AMDGPU::NoRegister) { 831 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 832 833 if (IsAtomic) { 834 // Atomic operations have an additional operand (a copy of data) 835 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 836 } 837 } 838 839 if (NewVAddr0 != AMDGPU::NoRegister) { 840 MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0); 841 } else if (IsNSA) { 842 assert(AddrSize <= Info->VAddrDwords); 843 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 844 MI.begin() + VAddr0Idx + Info->VAddrDwords); 845 } 846 847 return MCDisassembler::Success; 848 } 849 850 DecodeStatus AMDGPUDisassembler::convertFMAanyK(MCInst &MI, 851 int ImmLitIdx) const { 852 assert(HasLiteral && "Should have decoded a literal"); 853 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 854 unsigned DescNumOps = Desc.getNumOperands(); 855 assert(DescNumOps == MI.getNumOperands()); 856 for (unsigned I = 0; I < DescNumOps; ++I) { 857 auto &Op = MI.getOperand(I); 858 auto OpType = Desc.OpInfo[I].OperandType; 859 bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED || 860 OpType == AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED); 861 if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST && 862 IsDeferredOp) 863 Op.setImm(Literal); 864 } 865 return MCDisassembler::Success; 866 } 867 868 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 869 return getContext().getRegisterInfo()-> 870 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 871 } 872 873 inline 874 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 875 const Twine& ErrMsg) const { 876 *CommentStream << "Error: " + ErrMsg; 877 878 // ToDo: add support for error operands to MCInst.h 879 // return MCOperand::createError(V); 880 return MCOperand(); 881 } 882 883 inline 884 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 885 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 886 } 887 888 inline 889 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 890 unsigned Val) const { 891 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 892 if (Val >= RegCl.getNumRegs()) 893 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 894 ": unknown register " + Twine(Val)); 895 return createRegOperand(RegCl.getRegister(Val)); 896 } 897 898 inline 899 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 900 unsigned Val) const { 901 // ToDo: SI/CI have 104 SGPRs, VI - 102 902 // Valery: here we accepting as much as we can, let assembler sort it out 903 int shift = 0; 904 switch (SRegClassID) { 905 case AMDGPU::SGPR_32RegClassID: 906 case AMDGPU::TTMP_32RegClassID: 907 break; 908 case AMDGPU::SGPR_64RegClassID: 909 case AMDGPU::TTMP_64RegClassID: 910 shift = 1; 911 break; 912 case AMDGPU::SGPR_128RegClassID: 913 case AMDGPU::TTMP_128RegClassID: 914 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 915 // this bundle? 916 case AMDGPU::SGPR_256RegClassID: 917 case AMDGPU::TTMP_256RegClassID: 918 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 919 // this bundle? 920 case AMDGPU::SGPR_512RegClassID: 921 case AMDGPU::TTMP_512RegClassID: 922 shift = 2; 923 break; 924 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 925 // this bundle? 926 default: 927 llvm_unreachable("unhandled register class"); 928 } 929 930 if (Val % (1 << shift)) { 931 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 932 << ": scalar reg isn't aligned " << Val; 933 } 934 935 return createRegOperand(SRegClassID, Val >> shift); 936 } 937 938 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { 939 return decodeSrcOp(OPW32, Val); 940 } 941 942 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { 943 return decodeSrcOp(OPW64, Val); 944 } 945 946 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const { 947 return decodeSrcOp(OPW128, Val); 948 } 949 950 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const { 951 return decodeSrcOp(OPW16, Val); 952 } 953 954 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const { 955 return decodeSrcOp(OPWV216, Val); 956 } 957 958 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV232(unsigned Val) const { 959 return decodeSrcOp(OPWV232, Val); 960 } 961 962 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { 963 // Some instructions have operand restrictions beyond what the encoding 964 // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra 965 // high bit. 966 Val &= 255; 967 968 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); 969 } 970 971 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const { 972 return decodeSrcOp(OPW32, Val); 973 } 974 975 MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const { 976 return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255); 977 } 978 979 MCOperand AMDGPUDisassembler::decodeOperand_AReg_64(unsigned Val) const { 980 return createRegOperand(AMDGPU::AReg_64RegClassID, Val & 255); 981 } 982 983 MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const { 984 return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255); 985 } 986 987 MCOperand AMDGPUDisassembler::decodeOperand_AReg_256(unsigned Val) const { 988 return createRegOperand(AMDGPU::AReg_256RegClassID, Val & 255); 989 } 990 991 MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const { 992 return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255); 993 } 994 995 MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const { 996 return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255); 997 } 998 999 MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const { 1000 return decodeSrcOp(OPW32, Val); 1001 } 1002 1003 MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const { 1004 return decodeSrcOp(OPW64, Val); 1005 } 1006 1007 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { 1008 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); 1009 } 1010 1011 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { 1012 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); 1013 } 1014 1015 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { 1016 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); 1017 } 1018 1019 MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const { 1020 return createRegOperand(AMDGPU::VReg_256RegClassID, Val); 1021 } 1022 1023 MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const { 1024 return createRegOperand(AMDGPU::VReg_512RegClassID, Val); 1025 } 1026 1027 MCOperand AMDGPUDisassembler::decodeOperand_VReg_1024(unsigned Val) const { 1028 return createRegOperand(AMDGPU::VReg_1024RegClassID, Val); 1029 } 1030 1031 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { 1032 // table-gen generated disassembler doesn't care about operand types 1033 // leaving only registry class so SSrc_32 operand turns into SReg_32 1034 // and therefore we accept immediates and literals here as well 1035 return decodeSrcOp(OPW32, Val); 1036 } 1037 1038 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC( 1039 unsigned Val) const { 1040 // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI 1041 return decodeOperand_SReg_32(Val); 1042 } 1043 1044 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI( 1045 unsigned Val) const { 1046 // SReg_32_XM0 is SReg_32 without EXEC_HI 1047 return decodeOperand_SReg_32(Val); 1048 } 1049 1050 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const { 1051 // table-gen generated disassembler doesn't care about operand types 1052 // leaving only registry class so SSrc_32 operand turns into SReg_32 1053 // and therefore we accept immediates and literals here as well 1054 return decodeSrcOp(OPW32, Val); 1055 } 1056 1057 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { 1058 return decodeSrcOp(OPW64, Val); 1059 } 1060 1061 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const { 1062 return decodeSrcOp(OPW64, Val); 1063 } 1064 1065 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { 1066 return decodeSrcOp(OPW128, Val); 1067 } 1068 1069 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { 1070 return decodeDstOp(OPW256, Val); 1071 } 1072 1073 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { 1074 return decodeDstOp(OPW512, Val); 1075 } 1076 1077 // Decode Literals for insts which always have a literal in the encoding 1078 MCOperand 1079 AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const { 1080 if (HasLiteral) { 1081 if (Literal != Val) 1082 return errOperand(Val, "More than one unique literal is illegal"); 1083 } 1084 HasLiteral = true; 1085 Literal = Val; 1086 return MCOperand::createImm(Literal); 1087 } 1088 1089 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { 1090 // For now all literal constants are supposed to be unsigned integer 1091 // ToDo: deal with signed/unsigned 64-bit integer constants 1092 // ToDo: deal with float/double constants 1093 if (!HasLiteral) { 1094 if (Bytes.size() < 4) { 1095 return errOperand(0, "cannot read literal, inst bytes left " + 1096 Twine(Bytes.size())); 1097 } 1098 HasLiteral = true; 1099 Literal = eatBytes<uint32_t>(Bytes); 1100 } 1101 return MCOperand::createImm(Literal); 1102 } 1103 1104 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 1105 using namespace AMDGPU::EncValues; 1106 1107 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 1108 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 1109 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 1110 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 1111 // Cast prevents negative overflow. 1112 } 1113 1114 static int64_t getInlineImmVal32(unsigned Imm) { 1115 switch (Imm) { 1116 case 240: 1117 return FloatToBits(0.5f); 1118 case 241: 1119 return FloatToBits(-0.5f); 1120 case 242: 1121 return FloatToBits(1.0f); 1122 case 243: 1123 return FloatToBits(-1.0f); 1124 case 244: 1125 return FloatToBits(2.0f); 1126 case 245: 1127 return FloatToBits(-2.0f); 1128 case 246: 1129 return FloatToBits(4.0f); 1130 case 247: 1131 return FloatToBits(-4.0f); 1132 case 248: // 1 / (2 * PI) 1133 return 0x3e22f983; 1134 default: 1135 llvm_unreachable("invalid fp inline imm"); 1136 } 1137 } 1138 1139 static int64_t getInlineImmVal64(unsigned Imm) { 1140 switch (Imm) { 1141 case 240: 1142 return DoubleToBits(0.5); 1143 case 241: 1144 return DoubleToBits(-0.5); 1145 case 242: 1146 return DoubleToBits(1.0); 1147 case 243: 1148 return DoubleToBits(-1.0); 1149 case 244: 1150 return DoubleToBits(2.0); 1151 case 245: 1152 return DoubleToBits(-2.0); 1153 case 246: 1154 return DoubleToBits(4.0); 1155 case 247: 1156 return DoubleToBits(-4.0); 1157 case 248: // 1 / (2 * PI) 1158 return 0x3fc45f306dc9c882; 1159 default: 1160 llvm_unreachable("invalid fp inline imm"); 1161 } 1162 } 1163 1164 static int64_t getInlineImmVal16(unsigned Imm) { 1165 switch (Imm) { 1166 case 240: 1167 return 0x3800; 1168 case 241: 1169 return 0xB800; 1170 case 242: 1171 return 0x3C00; 1172 case 243: 1173 return 0xBC00; 1174 case 244: 1175 return 0x4000; 1176 case 245: 1177 return 0xC000; 1178 case 246: 1179 return 0x4400; 1180 case 247: 1181 return 0xC400; 1182 case 248: // 1 / (2 * PI) 1183 return 0x3118; 1184 default: 1185 llvm_unreachable("invalid fp inline imm"); 1186 } 1187 } 1188 1189 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) { 1190 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 1191 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 1192 1193 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 1194 switch (Width) { 1195 case OPW32: 1196 case OPW128: // splat constants 1197 case OPW512: 1198 case OPW1024: 1199 case OPWV232: 1200 return MCOperand::createImm(getInlineImmVal32(Imm)); 1201 case OPW64: 1202 case OPW256: 1203 return MCOperand::createImm(getInlineImmVal64(Imm)); 1204 case OPW16: 1205 case OPWV216: 1206 return MCOperand::createImm(getInlineImmVal16(Imm)); 1207 default: 1208 llvm_unreachable("implement me"); 1209 } 1210 } 1211 1212 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 1213 using namespace AMDGPU; 1214 1215 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1216 switch (Width) { 1217 default: // fall 1218 case OPW32: 1219 case OPW16: 1220 case OPWV216: 1221 return VGPR_32RegClassID; 1222 case OPW64: 1223 case OPWV232: return VReg_64RegClassID; 1224 case OPW96: return VReg_96RegClassID; 1225 case OPW128: return VReg_128RegClassID; 1226 case OPW160: return VReg_160RegClassID; 1227 case OPW256: return VReg_256RegClassID; 1228 case OPW512: return VReg_512RegClassID; 1229 case OPW1024: return VReg_1024RegClassID; 1230 } 1231 } 1232 1233 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 1234 using namespace AMDGPU; 1235 1236 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1237 switch (Width) { 1238 default: // fall 1239 case OPW32: 1240 case OPW16: 1241 case OPWV216: 1242 return AGPR_32RegClassID; 1243 case OPW64: 1244 case OPWV232: return AReg_64RegClassID; 1245 case OPW96: return AReg_96RegClassID; 1246 case OPW128: return AReg_128RegClassID; 1247 case OPW160: return AReg_160RegClassID; 1248 case OPW256: return AReg_256RegClassID; 1249 case OPW512: return AReg_512RegClassID; 1250 case OPW1024: return AReg_1024RegClassID; 1251 } 1252 } 1253 1254 1255 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 1256 using namespace AMDGPU; 1257 1258 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1259 switch (Width) { 1260 default: // fall 1261 case OPW32: 1262 case OPW16: 1263 case OPWV216: 1264 return SGPR_32RegClassID; 1265 case OPW64: 1266 case OPWV232: return SGPR_64RegClassID; 1267 case OPW96: return SGPR_96RegClassID; 1268 case OPW128: return SGPR_128RegClassID; 1269 case OPW160: return SGPR_160RegClassID; 1270 case OPW256: return SGPR_256RegClassID; 1271 case OPW512: return SGPR_512RegClassID; 1272 } 1273 } 1274 1275 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 1276 using namespace AMDGPU; 1277 1278 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1279 switch (Width) { 1280 default: // fall 1281 case OPW32: 1282 case OPW16: 1283 case OPWV216: 1284 return TTMP_32RegClassID; 1285 case OPW64: 1286 case OPWV232: return TTMP_64RegClassID; 1287 case OPW128: return TTMP_128RegClassID; 1288 case OPW256: return TTMP_256RegClassID; 1289 case OPW512: return TTMP_512RegClassID; 1290 } 1291 } 1292 1293 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 1294 using namespace AMDGPU::EncValues; 1295 1296 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN; 1297 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX; 1298 1299 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1300 } 1301 1302 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val, 1303 bool MandatoryLiteral) const { 1304 using namespace AMDGPU::EncValues; 1305 1306 assert(Val < 1024); // enum10 1307 1308 bool IsAGPR = Val & 512; 1309 Val &= 511; 1310 1311 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1312 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1313 : getVgprClassId(Width), Val - VGPR_MIN); 1314 } 1315 if (Val <= SGPR_MAX) { 1316 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1317 static_assert(SGPR_MIN == 0, ""); 1318 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1319 } 1320 1321 int TTmpIdx = getTTmpIdx(Val); 1322 if (TTmpIdx >= 0) { 1323 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1324 } 1325 1326 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1327 return decodeIntImmed(Val); 1328 1329 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1330 return decodeFPImmed(Width, Val); 1331 1332 if (Val == LITERAL_CONST) { 1333 if (MandatoryLiteral) 1334 // Keep a sentinel value for deferred setting 1335 return MCOperand::createImm(LITERAL_CONST); 1336 else 1337 return decodeLiteralConstant(); 1338 } 1339 1340 switch (Width) { 1341 case OPW32: 1342 case OPW16: 1343 case OPWV216: 1344 return decodeSpecialReg32(Val); 1345 case OPW64: 1346 case OPWV232: 1347 return decodeSpecialReg64(Val); 1348 default: 1349 llvm_unreachable("unexpected immediate type"); 1350 } 1351 } 1352 1353 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const { 1354 using namespace AMDGPU::EncValues; 1355 1356 assert(Val < 128); 1357 assert(Width == OPW256 || Width == OPW512); 1358 1359 if (Val <= SGPR_MAX) { 1360 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1361 static_assert(SGPR_MIN == 0, ""); 1362 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1363 } 1364 1365 int TTmpIdx = getTTmpIdx(Val); 1366 if (TTmpIdx >= 0) { 1367 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1368 } 1369 1370 llvm_unreachable("unknown dst register"); 1371 } 1372 1373 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1374 using namespace AMDGPU; 1375 1376 switch (Val) { 1377 case 102: return createRegOperand(FLAT_SCR_LO); 1378 case 103: return createRegOperand(FLAT_SCR_HI); 1379 case 104: return createRegOperand(XNACK_MASK_LO); 1380 case 105: return createRegOperand(XNACK_MASK_HI); 1381 case 106: return createRegOperand(VCC_LO); 1382 case 107: return createRegOperand(VCC_HI); 1383 case 108: return createRegOperand(TBA_LO); 1384 case 109: return createRegOperand(TBA_HI); 1385 case 110: return createRegOperand(TMA_LO); 1386 case 111: return createRegOperand(TMA_HI); 1387 case 124: return createRegOperand(M0); 1388 case 125: return createRegOperand(SGPR_NULL); 1389 case 126: return createRegOperand(EXEC_LO); 1390 case 127: return createRegOperand(EXEC_HI); 1391 case 235: return createRegOperand(SRC_SHARED_BASE); 1392 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1393 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1394 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1395 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1396 case 251: return createRegOperand(SRC_VCCZ); 1397 case 252: return createRegOperand(SRC_EXECZ); 1398 case 253: return createRegOperand(SRC_SCC); 1399 case 254: return createRegOperand(LDS_DIRECT); 1400 default: break; 1401 } 1402 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1403 } 1404 1405 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1406 using namespace AMDGPU; 1407 1408 switch (Val) { 1409 case 102: return createRegOperand(FLAT_SCR); 1410 case 104: return createRegOperand(XNACK_MASK); 1411 case 106: return createRegOperand(VCC); 1412 case 108: return createRegOperand(TBA); 1413 case 110: return createRegOperand(TMA); 1414 case 125: return createRegOperand(SGPR_NULL); 1415 case 126: return createRegOperand(EXEC); 1416 case 235: return createRegOperand(SRC_SHARED_BASE); 1417 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1418 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1419 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1420 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1421 case 251: return createRegOperand(SRC_VCCZ); 1422 case 252: return createRegOperand(SRC_EXECZ); 1423 case 253: return createRegOperand(SRC_SCC); 1424 default: break; 1425 } 1426 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1427 } 1428 1429 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 1430 const unsigned Val) const { 1431 using namespace AMDGPU::SDWA; 1432 using namespace AMDGPU::EncValues; 1433 1434 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1435 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 1436 // XXX: cast to int is needed to avoid stupid warning: 1437 // compare with unsigned is always true 1438 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1439 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1440 return createRegOperand(getVgprClassId(Width), 1441 Val - SDWA9EncValues::SRC_VGPR_MIN); 1442 } 1443 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1444 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1445 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1446 return createSRegOperand(getSgprClassId(Width), 1447 Val - SDWA9EncValues::SRC_SGPR_MIN); 1448 } 1449 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1450 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1451 return createSRegOperand(getTtmpClassId(Width), 1452 Val - SDWA9EncValues::SRC_TTMP_MIN); 1453 } 1454 1455 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1456 1457 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1458 return decodeIntImmed(SVal); 1459 1460 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1461 return decodeFPImmed(Width, SVal); 1462 1463 return decodeSpecialReg32(SVal); 1464 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 1465 return createRegOperand(getVgprClassId(Width), Val); 1466 } 1467 llvm_unreachable("unsupported target"); 1468 } 1469 1470 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1471 return decodeSDWASrc(OPW16, Val); 1472 } 1473 1474 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1475 return decodeSDWASrc(OPW32, Val); 1476 } 1477 1478 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1479 using namespace AMDGPU::SDWA; 1480 1481 assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1482 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) && 1483 "SDWAVopcDst should be present only on GFX9+"); 1484 1485 bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64]; 1486 1487 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1488 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1489 1490 int TTmpIdx = getTTmpIdx(Val); 1491 if (TTmpIdx >= 0) { 1492 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1493 return createSRegOperand(TTmpClsId, TTmpIdx); 1494 } else if (Val > SGPR_MAX) { 1495 return IsWave64 ? decodeSpecialReg64(Val) 1496 : decodeSpecialReg32(Val); 1497 } else { 1498 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1499 } 1500 } else { 1501 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1502 } 1503 } 1504 1505 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1506 return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ? 1507 decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val); 1508 } 1509 1510 bool AMDGPUDisassembler::isVI() const { 1511 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]; 1512 } 1513 1514 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } 1515 1516 bool AMDGPUDisassembler::isGFX90A() const { 1517 return STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]; 1518 } 1519 1520 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } 1521 1522 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } 1523 1524 bool AMDGPUDisassembler::isGFX10Plus() const { 1525 return AMDGPU::isGFX10Plus(STI); 1526 } 1527 1528 bool AMDGPUDisassembler::hasArchitectedFlatScratch() const { 1529 return STI.getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch]; 1530 } 1531 1532 //===----------------------------------------------------------------------===// 1533 // AMDGPU specific symbol handling 1534 //===----------------------------------------------------------------------===// 1535 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1536 do { \ 1537 KdStream << Indent << DIRECTIVE " " \ 1538 << ((FourByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1539 } while (0) 1540 1541 // NOLINTNEXTLINE(readability-identifier-naming) 1542 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1543 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1544 using namespace amdhsa; 1545 StringRef Indent = "\t"; 1546 1547 // We cannot accurately backward compute #VGPRs used from 1548 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1549 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1550 // simply calculate the inverse of what the assembler does. 1551 1552 uint32_t GranulatedWorkitemVGPRCount = 1553 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT) >> 1554 COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT; 1555 1556 uint32_t NextFreeVGPR = (GranulatedWorkitemVGPRCount + 1) * 1557 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI); 1558 1559 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1560 1561 // We cannot backward compute values used to calculate 1562 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1563 // directives can't be computed: 1564 // .amdhsa_reserve_vcc 1565 // .amdhsa_reserve_flat_scratch 1566 // .amdhsa_reserve_xnack_mask 1567 // They take their respective default values if not specified in the assembly. 1568 // 1569 // GRANULATED_WAVEFRONT_SGPR_COUNT 1570 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1571 // 1572 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1573 // are set to 0. So while disassembling we consider that: 1574 // 1575 // GRANULATED_WAVEFRONT_SGPR_COUNT 1576 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1577 // 1578 // The disassembler cannot recover the original values of those 3 directives. 1579 1580 uint32_t GranulatedWavefrontSGPRCount = 1581 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT) >> 1582 COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT; 1583 1584 if (isGFX10Plus() && GranulatedWavefrontSGPRCount) 1585 return MCDisassembler::Fail; 1586 1587 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1588 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1589 1590 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1591 if (!hasArchitectedFlatScratch()) 1592 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1593 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1594 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1595 1596 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY) 1597 return MCDisassembler::Fail; 1598 1599 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1600 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1601 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1602 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1603 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1604 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1605 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1606 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1607 1608 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) 1609 return MCDisassembler::Fail; 1610 1611 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 1612 1613 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) 1614 return MCDisassembler::Fail; 1615 1616 PRINT_DIRECTIVE(".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 1617 1618 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) 1619 return MCDisassembler::Fail; 1620 1621 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER) 1622 return MCDisassembler::Fail; 1623 1624 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_FP16_OVFL); 1625 1626 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED0) 1627 return MCDisassembler::Fail; 1628 1629 if (isGFX10Plus()) { 1630 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1631 COMPUTE_PGM_RSRC1_WGP_MODE); 1632 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_MEM_ORDERED); 1633 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_FWD_PROGRESS); 1634 } 1635 return MCDisassembler::Success; 1636 } 1637 1638 // NOLINTNEXTLINE(readability-identifier-naming) 1639 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 1640 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1641 using namespace amdhsa; 1642 StringRef Indent = "\t"; 1643 if (hasArchitectedFlatScratch()) 1644 PRINT_DIRECTIVE(".amdhsa_enable_private_segment", 1645 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1646 else 1647 PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset", 1648 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1649 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 1650 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 1651 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 1652 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 1653 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 1654 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 1655 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 1656 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 1657 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 1658 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 1659 1660 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH) 1661 return MCDisassembler::Fail; 1662 1663 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY) 1664 return MCDisassembler::Fail; 1665 1666 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE) 1667 return MCDisassembler::Fail; 1668 1669 PRINT_DIRECTIVE( 1670 ".amdhsa_exception_fp_ieee_invalid_op", 1671 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 1672 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 1673 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 1674 PRINT_DIRECTIVE( 1675 ".amdhsa_exception_fp_ieee_div_zero", 1676 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 1677 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 1678 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 1679 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 1680 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 1681 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 1682 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 1683 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 1684 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 1685 1686 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0) 1687 return MCDisassembler::Fail; 1688 1689 return MCDisassembler::Success; 1690 } 1691 1692 #undef PRINT_DIRECTIVE 1693 1694 MCDisassembler::DecodeStatus 1695 AMDGPUDisassembler::decodeKernelDescriptorDirective( 1696 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 1697 raw_string_ostream &KdStream) const { 1698 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1699 do { \ 1700 KdStream << Indent << DIRECTIVE " " \ 1701 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1702 } while (0) 1703 1704 uint16_t TwoByteBuffer = 0; 1705 uint32_t FourByteBuffer = 0; 1706 1707 StringRef ReservedBytes; 1708 StringRef Indent = "\t"; 1709 1710 assert(Bytes.size() == 64); 1711 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 1712 1713 switch (Cursor.tell()) { 1714 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 1715 FourByteBuffer = DE.getU32(Cursor); 1716 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 1717 << '\n'; 1718 return MCDisassembler::Success; 1719 1720 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 1721 FourByteBuffer = DE.getU32(Cursor); 1722 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 1723 << FourByteBuffer << '\n'; 1724 return MCDisassembler::Success; 1725 1726 case amdhsa::KERNARG_SIZE_OFFSET: 1727 FourByteBuffer = DE.getU32(Cursor); 1728 KdStream << Indent << ".amdhsa_kernarg_size " 1729 << FourByteBuffer << '\n'; 1730 return MCDisassembler::Success; 1731 1732 case amdhsa::RESERVED0_OFFSET: 1733 // 4 reserved bytes, must be 0. 1734 ReservedBytes = DE.getBytes(Cursor, 4); 1735 for (int I = 0; I < 4; ++I) { 1736 if (ReservedBytes[I] != 0) { 1737 return MCDisassembler::Fail; 1738 } 1739 } 1740 return MCDisassembler::Success; 1741 1742 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 1743 // KERNEL_CODE_ENTRY_BYTE_OFFSET 1744 // So far no directive controls this for Code Object V3, so simply skip for 1745 // disassembly. 1746 DE.skip(Cursor, 8); 1747 return MCDisassembler::Success; 1748 1749 case amdhsa::RESERVED1_OFFSET: 1750 // 20 reserved bytes, must be 0. 1751 ReservedBytes = DE.getBytes(Cursor, 20); 1752 for (int I = 0; I < 20; ++I) { 1753 if (ReservedBytes[I] != 0) { 1754 return MCDisassembler::Fail; 1755 } 1756 } 1757 return MCDisassembler::Success; 1758 1759 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 1760 // COMPUTE_PGM_RSRC3 1761 // - Only set for GFX10, GFX6-9 have this to be 0. 1762 // - Currently no directives directly control this. 1763 FourByteBuffer = DE.getU32(Cursor); 1764 if (!isGFX10Plus() && FourByteBuffer) { 1765 return MCDisassembler::Fail; 1766 } 1767 return MCDisassembler::Success; 1768 1769 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 1770 FourByteBuffer = DE.getU32(Cursor); 1771 if (decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream) == 1772 MCDisassembler::Fail) { 1773 return MCDisassembler::Fail; 1774 } 1775 return MCDisassembler::Success; 1776 1777 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 1778 FourByteBuffer = DE.getU32(Cursor); 1779 if (decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream) == 1780 MCDisassembler::Fail) { 1781 return MCDisassembler::Fail; 1782 } 1783 return MCDisassembler::Success; 1784 1785 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 1786 using namespace amdhsa; 1787 TwoByteBuffer = DE.getU16(Cursor); 1788 1789 if (!hasArchitectedFlatScratch()) 1790 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 1791 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 1792 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 1793 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 1794 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 1795 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 1796 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 1797 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 1798 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 1799 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 1800 if (!hasArchitectedFlatScratch()) 1801 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 1802 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 1803 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 1804 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 1805 1806 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 1807 return MCDisassembler::Fail; 1808 1809 // Reserved for GFX9 1810 if (isGFX9() && 1811 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 1812 return MCDisassembler::Fail; 1813 } else if (isGFX10Plus()) { 1814 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 1815 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 1816 } 1817 1818 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) 1819 return MCDisassembler::Fail; 1820 1821 return MCDisassembler::Success; 1822 1823 case amdhsa::RESERVED2_OFFSET: 1824 // 6 bytes from here are reserved, must be 0. 1825 ReservedBytes = DE.getBytes(Cursor, 6); 1826 for (int I = 0; I < 6; ++I) { 1827 if (ReservedBytes[I] != 0) 1828 return MCDisassembler::Fail; 1829 } 1830 return MCDisassembler::Success; 1831 1832 default: 1833 llvm_unreachable("Unhandled index. Case statements cover everything."); 1834 return MCDisassembler::Fail; 1835 } 1836 #undef PRINT_DIRECTIVE 1837 } 1838 1839 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( 1840 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 1841 // CP microcode requires the kernel descriptor to be 64 aligned. 1842 if (Bytes.size() != 64 || KdAddress % 64 != 0) 1843 return MCDisassembler::Fail; 1844 1845 std::string Kd; 1846 raw_string_ostream KdStream(Kd); 1847 KdStream << ".amdhsa_kernel " << KdName << '\n'; 1848 1849 DataExtractor::Cursor C(0); 1850 while (C && C.tell() < Bytes.size()) { 1851 MCDisassembler::DecodeStatus Status = 1852 decodeKernelDescriptorDirective(C, Bytes, KdStream); 1853 1854 cantFail(C.takeError()); 1855 1856 if (Status == MCDisassembler::Fail) 1857 return MCDisassembler::Fail; 1858 } 1859 KdStream << ".end_amdhsa_kernel\n"; 1860 outs() << KdStream.str(); 1861 return MCDisassembler::Success; 1862 } 1863 1864 Optional<MCDisassembler::DecodeStatus> 1865 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 1866 ArrayRef<uint8_t> Bytes, uint64_t Address, 1867 raw_ostream &CStream) const { 1868 // Right now only kernel descriptor needs to be handled. 1869 // We ignore all other symbols for target specific handling. 1870 // TODO: 1871 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 1872 // Object V2 and V3 when symbols are marked protected. 1873 1874 // amd_kernel_code_t for Code Object V2. 1875 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 1876 Size = 256; 1877 return MCDisassembler::Fail; 1878 } 1879 1880 // Code Object V3 kernel descriptors. 1881 StringRef Name = Symbol.Name; 1882 if (Symbol.Type == ELF::STT_OBJECT && Name.endswith(StringRef(".kd"))) { 1883 Size = 64; // Size = 64 regardless of success or failure. 1884 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 1885 } 1886 return None; 1887 } 1888 1889 //===----------------------------------------------------------------------===// 1890 // AMDGPUSymbolizer 1891 //===----------------------------------------------------------------------===// 1892 1893 // Try to find symbol name for specified label 1894 bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst, 1895 raw_ostream &/*cStream*/, int64_t Value, 1896 uint64_t /*Address*/, bool IsBranch, 1897 uint64_t /*Offset*/, uint64_t /*InstSize*/) { 1898 1899 if (!IsBranch) { 1900 return false; 1901 } 1902 1903 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 1904 if (!Symbols) 1905 return false; 1906 1907 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { 1908 return Val.Addr == static_cast<uint64_t>(Value) && 1909 Val.Type == ELF::STT_NOTYPE; 1910 }); 1911 if (Result != Symbols->end()) { 1912 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 1913 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 1914 Inst.addOperand(MCOperand::createExpr(Add)); 1915 return true; 1916 } 1917 // Add to list of referenced addresses, so caller can synthesize a label. 1918 ReferencedAddresses.push_back(static_cast<uint64_t>(Value)); 1919 return false; 1920 } 1921 1922 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 1923 int64_t Value, 1924 uint64_t Address) { 1925 llvm_unreachable("unimplemented"); 1926 } 1927 1928 //===----------------------------------------------------------------------===// 1929 // Initialization 1930 //===----------------------------------------------------------------------===// 1931 1932 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 1933 LLVMOpInfoCallback /*GetOpInfo*/, 1934 LLVMSymbolLookupCallback /*SymbolLookUp*/, 1935 void *DisInfo, 1936 MCContext *Ctx, 1937 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 1938 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 1939 } 1940 1941 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 1942 const MCSubtargetInfo &STI, 1943 MCContext &Ctx) { 1944 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 1945 } 1946 1947 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 1948 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 1949 createAMDGPUDisassembler); 1950 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 1951 createAMDGPUSymbolizer); 1952 } 1953