1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "AMDGPU.h" 21 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 22 #include "SIDefines.h" 23 #include "TargetInfo/AMDGPUTargetInfo.h" 24 #include "Utils/AMDGPUBaseInfo.h" 25 #include "llvm-c/Disassembler.h" 26 #include "llvm/ADT/APInt.h" 27 #include "llvm/ADT/ArrayRef.h" 28 #include "llvm/ADT/Twine.h" 29 #include "llvm/BinaryFormat/ELF.h" 30 #include "llvm/MC/MCAsmInfo.h" 31 #include "llvm/MC/MCContext.h" 32 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 33 #include "llvm/MC/MCExpr.h" 34 #include "llvm/MC/MCFixedLenDisassembler.h" 35 #include "llvm/MC/MCInst.h" 36 #include "llvm/MC/MCSubtargetInfo.h" 37 #include "llvm/Support/AMDHSAKernelDescriptor.h" 38 #include "llvm/Support/Endian.h" 39 #include "llvm/Support/ErrorHandling.h" 40 #include "llvm/Support/MathExtras.h" 41 #include "llvm/Support/TargetRegistry.h" 42 #include "llvm/Support/raw_ostream.h" 43 #include <algorithm> 44 #include <cassert> 45 #include <cstddef> 46 #include <cstdint> 47 #include <iterator> 48 #include <tuple> 49 #include <vector> 50 51 using namespace llvm; 52 53 #define DEBUG_TYPE "amdgpu-disassembler" 54 55 #define SGPR_MAX (isGFX10() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 56 : AMDGPU::EncValues::SGPR_MAX_SI) 57 58 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 59 60 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 61 MCContext &Ctx, 62 MCInstrInfo const *MCII) : 63 MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), 64 TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) { 65 66 // ToDo: AMDGPUDisassembler supports only VI ISA. 67 if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10()) 68 report_fatal_error("Disassembly not yet supported for subtarget"); 69 } 70 71 inline static MCDisassembler::DecodeStatus 72 addOperand(MCInst &Inst, const MCOperand& Opnd) { 73 Inst.addOperand(Opnd); 74 return Opnd.isValid() ? 75 MCDisassembler::Success : 76 MCDisassembler::Fail; 77 } 78 79 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 80 uint16_t NameIdx) { 81 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 82 if (OpIdx != -1) { 83 auto I = MI.begin(); 84 std::advance(I, OpIdx); 85 MI.insert(I, Op); 86 } 87 return OpIdx; 88 } 89 90 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, 91 uint64_t Addr, const void *Decoder) { 92 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 93 94 // Our branches take a simm16, but we need two extra bits to account for the 95 // factor of 4. 96 APInt SignedOffset(18, Imm * 4, true); 97 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 98 99 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2)) 100 return MCDisassembler::Success; 101 return addOperand(Inst, MCOperand::createImm(Imm)); 102 } 103 104 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, 105 uint64_t Addr, const void *Decoder) { 106 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 107 int64_t Offset; 108 if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 109 Offset = Imm & 0xFFFFF; 110 } else { // GFX9+ supports 21-bit signed offsets. 111 Offset = SignExtend64<21>(Imm); 112 } 113 return addOperand(Inst, MCOperand::createImm(Offset)); 114 } 115 116 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, 117 uint64_t Addr, const void *Decoder) { 118 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 119 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 120 } 121 122 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 123 static DecodeStatus StaticDecoderName(MCInst &Inst, \ 124 unsigned Imm, \ 125 uint64_t /*Addr*/, \ 126 const void *Decoder) { \ 127 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \ 128 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 129 } 130 131 #define DECODE_OPERAND_REG(RegClass) \ 132 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass) 133 134 DECODE_OPERAND_REG(VGPR_32) 135 DECODE_OPERAND_REG(VRegOrLds_32) 136 DECODE_OPERAND_REG(VS_32) 137 DECODE_OPERAND_REG(VS_64) 138 DECODE_OPERAND_REG(VS_128) 139 140 DECODE_OPERAND_REG(VReg_64) 141 DECODE_OPERAND_REG(VReg_96) 142 DECODE_OPERAND_REG(VReg_128) 143 DECODE_OPERAND_REG(VReg_256) 144 DECODE_OPERAND_REG(VReg_512) 145 146 DECODE_OPERAND_REG(SReg_32) 147 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC) 148 DECODE_OPERAND_REG(SReg_32_XEXEC_HI) 149 DECODE_OPERAND_REG(SRegOrLds_32) 150 DECODE_OPERAND_REG(SReg_64) 151 DECODE_OPERAND_REG(SReg_64_XEXEC) 152 DECODE_OPERAND_REG(SReg_128) 153 DECODE_OPERAND_REG(SReg_256) 154 DECODE_OPERAND_REG(SReg_512) 155 156 DECODE_OPERAND_REG(AGPR_32) 157 DECODE_OPERAND_REG(AReg_128) 158 DECODE_OPERAND_REG(AReg_512) 159 DECODE_OPERAND_REG(AReg_1024) 160 DECODE_OPERAND_REG(AV_32) 161 DECODE_OPERAND_REG(AV_64) 162 163 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, 164 unsigned Imm, 165 uint64_t Addr, 166 const void *Decoder) { 167 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 168 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 169 } 170 171 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, 172 unsigned Imm, 173 uint64_t Addr, 174 const void *Decoder) { 175 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 176 return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm)); 177 } 178 179 static DecodeStatus decodeOperand_VS_16(MCInst &Inst, 180 unsigned Imm, 181 uint64_t Addr, 182 const void *Decoder) { 183 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 184 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 185 } 186 187 static DecodeStatus decodeOperand_VS_32(MCInst &Inst, 188 unsigned Imm, 189 uint64_t Addr, 190 const void *Decoder) { 191 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 192 return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm)); 193 } 194 195 static DecodeStatus decodeOperand_AReg_128(MCInst &Inst, 196 unsigned Imm, 197 uint64_t Addr, 198 const void *Decoder) { 199 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 200 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512)); 201 } 202 203 static DecodeStatus decodeOperand_AReg_512(MCInst &Inst, 204 unsigned Imm, 205 uint64_t Addr, 206 const void *Decoder) { 207 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 208 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512)); 209 } 210 211 static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst, 212 unsigned Imm, 213 uint64_t Addr, 214 const void *Decoder) { 215 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 216 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512)); 217 } 218 219 static DecodeStatus decodeOperand_SReg_32(MCInst &Inst, 220 unsigned Imm, 221 uint64_t Addr, 222 const void *Decoder) { 223 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 224 return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm)); 225 } 226 227 static DecodeStatus decodeOperand_VGPR_32(MCInst &Inst, 228 unsigned Imm, 229 uint64_t Addr, 230 const void *Decoder) { 231 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 232 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW32, Imm)); 233 } 234 235 #define DECODE_SDWA(DecName) \ 236 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 237 238 DECODE_SDWA(Src32) 239 DECODE_SDWA(Src16) 240 DECODE_SDWA(VopcDst) 241 242 #include "AMDGPUGenDisassemblerTables.inc" 243 244 //===----------------------------------------------------------------------===// 245 // 246 //===----------------------------------------------------------------------===// 247 248 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 249 assert(Bytes.size() >= sizeof(T)); 250 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data()); 251 Bytes = Bytes.slice(sizeof(T)); 252 return Res; 253 } 254 255 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table, 256 MCInst &MI, 257 uint64_t Inst, 258 uint64_t Address) const { 259 assert(MI.getOpcode() == 0); 260 assert(MI.getNumOperands() == 0); 261 MCInst TmpInst; 262 HasLiteral = false; 263 const auto SavedBytes = Bytes; 264 if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) { 265 MI = TmpInst; 266 return MCDisassembler::Success; 267 } 268 Bytes = SavedBytes; 269 return MCDisassembler::Fail; 270 } 271 272 static bool isValidDPP8(const MCInst &MI) { 273 using namespace llvm::AMDGPU::DPP; 274 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi); 275 assert(FiIdx != -1); 276 if ((unsigned)FiIdx >= MI.getNumOperands()) 277 return false; 278 unsigned Fi = MI.getOperand(FiIdx).getImm(); 279 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1; 280 } 281 282 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 283 ArrayRef<uint8_t> Bytes_, 284 uint64_t Address, 285 raw_ostream &CS) const { 286 CommentStream = &CS; 287 bool IsSDWA = false; 288 289 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 290 Bytes = Bytes_.slice(0, MaxInstBytesNum); 291 292 DecodeStatus Res = MCDisassembler::Fail; 293 do { 294 // ToDo: better to switch encoding length using some bit predicate 295 // but it is unknown yet, so try all we can 296 297 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 298 // encodings 299 if (Bytes.size() >= 8) { 300 const uint64_t QW = eatBytes<uint64_t>(Bytes); 301 302 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 303 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address); 304 if (Res) { 305 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) 306 == -1) 307 break; 308 if (convertDPP8Inst(MI) == MCDisassembler::Success) 309 break; 310 MI = MCInst(); // clear 311 } 312 } 313 314 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address); 315 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 316 break; 317 318 MI = MCInst(); // clear 319 320 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address); 321 if (Res) break; 322 323 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address); 324 if (Res) { IsSDWA = true; break; } 325 326 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address); 327 if (Res) { IsSDWA = true; break; } 328 329 Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address); 330 if (Res) { IsSDWA = true; break; } 331 332 if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) { 333 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address); 334 if (Res) 335 break; 336 } 337 338 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 339 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 340 // table first so we print the correct name. 341 if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) { 342 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address); 343 if (Res) 344 break; 345 } 346 } 347 348 // Reinitialize Bytes as DPP64 could have eaten too much 349 Bytes = Bytes_.slice(0, MaxInstBytesNum); 350 351 // Try decode 32-bit instruction 352 if (Bytes.size() < 4) break; 353 const uint32_t DW = eatBytes<uint32_t>(Bytes); 354 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address); 355 if (Res) break; 356 357 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address); 358 if (Res) break; 359 360 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address); 361 if (Res) break; 362 363 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 364 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address); 365 if (Res) break; 366 } 367 368 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address); 369 if (Res) break; 370 371 if (Bytes.size() < 4) break; 372 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 373 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address); 374 if (Res) break; 375 376 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address); 377 if (Res) break; 378 379 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address); 380 if (Res) break; 381 382 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address); 383 } while (false); 384 385 if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi || 386 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 || 387 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 || 388 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 || 389 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 || 390 MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi || 391 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi || 392 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 || 393 MI.getOpcode() == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 || 394 MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10)) { 395 // Insert dummy unused src2_modifiers. 396 insertNamedMCOperand(MI, MCOperand::createImm(0), 397 AMDGPU::OpName::src2_modifiers); 398 } 399 400 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 401 int VAddr0Idx = 402 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 403 int RsrcIdx = 404 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 405 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 406 if (VAddr0Idx >= 0 && NSAArgs > 0) { 407 unsigned NSAWords = (NSAArgs + 3) / 4; 408 if (Bytes.size() < 4 * NSAWords) { 409 Res = MCDisassembler::Fail; 410 } else { 411 for (unsigned i = 0; i < NSAArgs; ++i) { 412 MI.insert(MI.begin() + VAddr0Idx + 1 + i, 413 decodeOperand_VGPR_32(Bytes[i])); 414 } 415 Bytes = Bytes.slice(4 * NSAWords); 416 } 417 } 418 419 if (Res) 420 Res = convertMIMGInst(MI); 421 } 422 423 if (Res && IsSDWA) 424 Res = convertSDWAInst(MI); 425 426 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 427 AMDGPU::OpName::vdst_in); 428 if (VDstIn_Idx != -1) { 429 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 430 MCOI::OperandConstraint::TIED_TO); 431 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 432 !MI.getOperand(VDstIn_Idx).isReg() || 433 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 434 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 435 MI.erase(&MI.getOperand(VDstIn_Idx)); 436 insertNamedMCOperand(MI, 437 MCOperand::createReg(MI.getOperand(Tied).getReg()), 438 AMDGPU::OpName::vdst_in); 439 } 440 } 441 442 // if the opcode was not recognized we'll assume a Size of 4 bytes 443 // (unless there are fewer bytes left) 444 Size = Res ? (MaxInstBytesNum - Bytes.size()) 445 : std::min((size_t)4, Bytes_.size()); 446 return Res; 447 } 448 449 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 450 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 451 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 452 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1) 453 // VOPC - insert clamp 454 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 455 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 456 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 457 if (SDst != -1) { 458 // VOPC - insert VCC register as sdst 459 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 460 AMDGPU::OpName::sdst); 461 } else { 462 // VOP1/2 - insert omod if present in instruction 463 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 464 } 465 } 466 return MCDisassembler::Success; 467 } 468 469 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 470 unsigned Opc = MI.getOpcode(); 471 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 472 473 // Insert dummy unused src modifiers. 474 if (MI.getNumOperands() < DescNumOps && 475 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1) 476 insertNamedMCOperand(MI, MCOperand::createImm(0), 477 AMDGPU::OpName::src0_modifiers); 478 479 if (MI.getNumOperands() < DescNumOps && 480 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1) 481 insertNamedMCOperand(MI, MCOperand::createImm(0), 482 AMDGPU::OpName::src1_modifiers); 483 484 return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail; 485 } 486 487 // Note that before gfx10, the MIMG encoding provided no information about 488 // VADDR size. Consequently, decoded instructions always show address as if it 489 // has 1 dword, which could be not really so. 490 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 491 492 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 493 AMDGPU::OpName::vdst); 494 495 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 496 AMDGPU::OpName::vdata); 497 int VAddr0Idx = 498 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 499 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 500 AMDGPU::OpName::dmask); 501 502 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 503 AMDGPU::OpName::tfe); 504 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 505 AMDGPU::OpName::d16); 506 507 assert(VDataIdx != -1); 508 if (DMaskIdx == -1 || TFEIdx == -1) {// intersect_ray 509 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16) > -1) { 510 assert(MI.getOpcode() == AMDGPU::IMAGE_BVH_INTERSECT_RAY_a16_sa || 511 MI.getOpcode() == AMDGPU::IMAGE_BVH_INTERSECT_RAY_a16_nsa || 512 MI.getOpcode() == AMDGPU::IMAGE_BVH64_INTERSECT_RAY_a16_sa || 513 MI.getOpcode() == AMDGPU::IMAGE_BVH64_INTERSECT_RAY_a16_nsa); 514 addOperand(MI, MCOperand::createImm(1)); 515 } 516 return MCDisassembler::Success; 517 } 518 519 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 520 bool IsAtomic = (VDstIdx != -1); 521 bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4; 522 523 bool IsNSA = false; 524 unsigned AddrSize = Info->VAddrDwords; 525 526 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 527 unsigned DimIdx = 528 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 529 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 530 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 531 const AMDGPU::MIMGDimInfo *Dim = 532 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 533 534 AddrSize = BaseOpcode->NumExtraArgs + 535 (BaseOpcode->Gradients ? Dim->NumGradients : 0) + 536 (BaseOpcode->Coordinates ? Dim->NumCoords : 0) + 537 (BaseOpcode->LodOrClampOrMip ? 1 : 0); 538 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA; 539 if (!IsNSA) { 540 if (AddrSize > 8) 541 AddrSize = 16; 542 else if (AddrSize > 4) 543 AddrSize = 8; 544 } else { 545 if (AddrSize > Info->VAddrDwords) { 546 // The NSA encoding does not contain enough operands for the combination 547 // of base opcode / dimension. Should this be an error? 548 return MCDisassembler::Success; 549 } 550 } 551 } 552 553 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 554 unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u); 555 556 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 557 if (D16 && AMDGPU::hasPackedD16(STI)) { 558 DstSize = (DstSize + 1) / 2; 559 } 560 561 // FIXME: Add tfe support 562 if (MI.getOperand(TFEIdx).getImm()) 563 return MCDisassembler::Success; 564 565 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 566 return MCDisassembler::Success; 567 568 int NewOpcode = 569 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 570 if (NewOpcode == -1) 571 return MCDisassembler::Success; 572 573 // Widen the register to the correct number of enabled channels. 574 unsigned NewVdata = AMDGPU::NoRegister; 575 if (DstSize != Info->VDataDwords) { 576 auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; 577 578 // Get first subregister of VData 579 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 580 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 581 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 582 583 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 584 &MRI.getRegClass(DataRCID)); 585 if (NewVdata == AMDGPU::NoRegister) { 586 // It's possible to encode this such that the low register + enabled 587 // components exceeds the register count. 588 return MCDisassembler::Success; 589 } 590 } 591 592 unsigned NewVAddr0 = AMDGPU::NoRegister; 593 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10] && !IsNSA && 594 AddrSize != Info->VAddrDwords) { 595 unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg(); 596 unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0); 597 VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0; 598 599 auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass; 600 NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0, 601 &MRI.getRegClass(AddrRCID)); 602 if (NewVAddr0 == AMDGPU::NoRegister) 603 return MCDisassembler::Success; 604 } 605 606 MI.setOpcode(NewOpcode); 607 608 if (NewVdata != AMDGPU::NoRegister) { 609 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 610 611 if (IsAtomic) { 612 // Atomic operations have an additional operand (a copy of data) 613 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 614 } 615 } 616 617 if (NewVAddr0 != AMDGPU::NoRegister) { 618 MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0); 619 } else if (IsNSA) { 620 assert(AddrSize <= Info->VAddrDwords); 621 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 622 MI.begin() + VAddr0Idx + Info->VAddrDwords); 623 } 624 625 return MCDisassembler::Success; 626 } 627 628 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 629 return getContext().getRegisterInfo()-> 630 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 631 } 632 633 inline 634 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 635 const Twine& ErrMsg) const { 636 *CommentStream << "Error: " + ErrMsg; 637 638 // ToDo: add support for error operands to MCInst.h 639 // return MCOperand::createError(V); 640 return MCOperand(); 641 } 642 643 inline 644 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 645 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 646 } 647 648 inline 649 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 650 unsigned Val) const { 651 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 652 if (Val >= RegCl.getNumRegs()) 653 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 654 ": unknown register " + Twine(Val)); 655 return createRegOperand(RegCl.getRegister(Val)); 656 } 657 658 inline 659 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 660 unsigned Val) const { 661 // ToDo: SI/CI have 104 SGPRs, VI - 102 662 // Valery: here we accepting as much as we can, let assembler sort it out 663 int shift = 0; 664 switch (SRegClassID) { 665 case AMDGPU::SGPR_32RegClassID: 666 case AMDGPU::TTMP_32RegClassID: 667 break; 668 case AMDGPU::SGPR_64RegClassID: 669 case AMDGPU::TTMP_64RegClassID: 670 shift = 1; 671 break; 672 case AMDGPU::SGPR_128RegClassID: 673 case AMDGPU::TTMP_128RegClassID: 674 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 675 // this bundle? 676 case AMDGPU::SGPR_256RegClassID: 677 case AMDGPU::TTMP_256RegClassID: 678 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 679 // this bundle? 680 case AMDGPU::SGPR_512RegClassID: 681 case AMDGPU::TTMP_512RegClassID: 682 shift = 2; 683 break; 684 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 685 // this bundle? 686 default: 687 llvm_unreachable("unhandled register class"); 688 } 689 690 if (Val % (1 << shift)) { 691 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 692 << ": scalar reg isn't aligned " << Val; 693 } 694 695 return createRegOperand(SRegClassID, Val >> shift); 696 } 697 698 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { 699 return decodeSrcOp(OPW32, Val); 700 } 701 702 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { 703 return decodeSrcOp(OPW64, Val); 704 } 705 706 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const { 707 return decodeSrcOp(OPW128, Val); 708 } 709 710 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const { 711 return decodeSrcOp(OPW16, Val); 712 } 713 714 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const { 715 return decodeSrcOp(OPWV216, Val); 716 } 717 718 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { 719 // Some instructions have operand restrictions beyond what the encoding 720 // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra 721 // high bit. 722 Val &= 255; 723 724 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); 725 } 726 727 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const { 728 return decodeSrcOp(OPW32, Val); 729 } 730 731 MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const { 732 return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255); 733 } 734 735 MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const { 736 return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255); 737 } 738 739 MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const { 740 return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255); 741 } 742 743 MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const { 744 return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255); 745 } 746 747 MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const { 748 return decodeSrcOp(OPW32, Val); 749 } 750 751 MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const { 752 return decodeSrcOp(OPW64, Val); 753 } 754 755 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { 756 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); 757 } 758 759 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { 760 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); 761 } 762 763 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { 764 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); 765 } 766 767 MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const { 768 return createRegOperand(AMDGPU::VReg_256RegClassID, Val); 769 } 770 771 MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const { 772 return createRegOperand(AMDGPU::VReg_512RegClassID, Val); 773 } 774 775 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { 776 // table-gen generated disassembler doesn't care about operand types 777 // leaving only registry class so SSrc_32 operand turns into SReg_32 778 // and therefore we accept immediates and literals here as well 779 return decodeSrcOp(OPW32, Val); 780 } 781 782 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC( 783 unsigned Val) const { 784 // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI 785 return decodeOperand_SReg_32(Val); 786 } 787 788 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI( 789 unsigned Val) const { 790 // SReg_32_XM0 is SReg_32 without EXEC_HI 791 return decodeOperand_SReg_32(Val); 792 } 793 794 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const { 795 // table-gen generated disassembler doesn't care about operand types 796 // leaving only registry class so SSrc_32 operand turns into SReg_32 797 // and therefore we accept immediates and literals here as well 798 return decodeSrcOp(OPW32, Val); 799 } 800 801 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { 802 return decodeSrcOp(OPW64, Val); 803 } 804 805 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const { 806 return decodeSrcOp(OPW64, Val); 807 } 808 809 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { 810 return decodeSrcOp(OPW128, Val); 811 } 812 813 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { 814 return decodeDstOp(OPW256, Val); 815 } 816 817 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { 818 return decodeDstOp(OPW512, Val); 819 } 820 821 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { 822 // For now all literal constants are supposed to be unsigned integer 823 // ToDo: deal with signed/unsigned 64-bit integer constants 824 // ToDo: deal with float/double constants 825 if (!HasLiteral) { 826 if (Bytes.size() < 4) { 827 return errOperand(0, "cannot read literal, inst bytes left " + 828 Twine(Bytes.size())); 829 } 830 HasLiteral = true; 831 Literal = eatBytes<uint32_t>(Bytes); 832 } 833 return MCOperand::createImm(Literal); 834 } 835 836 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 837 using namespace AMDGPU::EncValues; 838 839 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 840 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 841 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 842 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 843 // Cast prevents negative overflow. 844 } 845 846 static int64_t getInlineImmVal32(unsigned Imm) { 847 switch (Imm) { 848 case 240: 849 return FloatToBits(0.5f); 850 case 241: 851 return FloatToBits(-0.5f); 852 case 242: 853 return FloatToBits(1.0f); 854 case 243: 855 return FloatToBits(-1.0f); 856 case 244: 857 return FloatToBits(2.0f); 858 case 245: 859 return FloatToBits(-2.0f); 860 case 246: 861 return FloatToBits(4.0f); 862 case 247: 863 return FloatToBits(-4.0f); 864 case 248: // 1 / (2 * PI) 865 return 0x3e22f983; 866 default: 867 llvm_unreachable("invalid fp inline imm"); 868 } 869 } 870 871 static int64_t getInlineImmVal64(unsigned Imm) { 872 switch (Imm) { 873 case 240: 874 return DoubleToBits(0.5); 875 case 241: 876 return DoubleToBits(-0.5); 877 case 242: 878 return DoubleToBits(1.0); 879 case 243: 880 return DoubleToBits(-1.0); 881 case 244: 882 return DoubleToBits(2.0); 883 case 245: 884 return DoubleToBits(-2.0); 885 case 246: 886 return DoubleToBits(4.0); 887 case 247: 888 return DoubleToBits(-4.0); 889 case 248: // 1 / (2 * PI) 890 return 0x3fc45f306dc9c882; 891 default: 892 llvm_unreachable("invalid fp inline imm"); 893 } 894 } 895 896 static int64_t getInlineImmVal16(unsigned Imm) { 897 switch (Imm) { 898 case 240: 899 return 0x3800; 900 case 241: 901 return 0xB800; 902 case 242: 903 return 0x3C00; 904 case 243: 905 return 0xBC00; 906 case 244: 907 return 0x4000; 908 case 245: 909 return 0xC000; 910 case 246: 911 return 0x4400; 912 case 247: 913 return 0xC400; 914 case 248: // 1 / (2 * PI) 915 return 0x3118; 916 default: 917 llvm_unreachable("invalid fp inline imm"); 918 } 919 } 920 921 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) { 922 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 923 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 924 925 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 926 switch (Width) { 927 case OPW32: 928 case OPW128: // splat constants 929 case OPW512: 930 case OPW1024: 931 return MCOperand::createImm(getInlineImmVal32(Imm)); 932 case OPW64: 933 return MCOperand::createImm(getInlineImmVal64(Imm)); 934 case OPW16: 935 case OPWV216: 936 return MCOperand::createImm(getInlineImmVal16(Imm)); 937 default: 938 llvm_unreachable("implement me"); 939 } 940 } 941 942 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 943 using namespace AMDGPU; 944 945 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 946 switch (Width) { 947 default: // fall 948 case OPW32: 949 case OPW16: 950 case OPWV216: 951 return VGPR_32RegClassID; 952 case OPW64: return VReg_64RegClassID; 953 case OPW128: return VReg_128RegClassID; 954 } 955 } 956 957 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 958 using namespace AMDGPU; 959 960 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 961 switch (Width) { 962 default: // fall 963 case OPW32: 964 case OPW16: 965 case OPWV216: 966 return AGPR_32RegClassID; 967 case OPW64: return AReg_64RegClassID; 968 case OPW128: return AReg_128RegClassID; 969 case OPW256: return AReg_256RegClassID; 970 case OPW512: return AReg_512RegClassID; 971 case OPW1024: return AReg_1024RegClassID; 972 } 973 } 974 975 976 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 977 using namespace AMDGPU; 978 979 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 980 switch (Width) { 981 default: // fall 982 case OPW32: 983 case OPW16: 984 case OPWV216: 985 return SGPR_32RegClassID; 986 case OPW64: return SGPR_64RegClassID; 987 case OPW128: return SGPR_128RegClassID; 988 case OPW256: return SGPR_256RegClassID; 989 case OPW512: return SGPR_512RegClassID; 990 } 991 } 992 993 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 994 using namespace AMDGPU; 995 996 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 997 switch (Width) { 998 default: // fall 999 case OPW32: 1000 case OPW16: 1001 case OPWV216: 1002 return TTMP_32RegClassID; 1003 case OPW64: return TTMP_64RegClassID; 1004 case OPW128: return TTMP_128RegClassID; 1005 case OPW256: return TTMP_256RegClassID; 1006 case OPW512: return TTMP_512RegClassID; 1007 } 1008 } 1009 1010 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 1011 using namespace AMDGPU::EncValues; 1012 1013 unsigned TTmpMin = 1014 (isGFX9() || isGFX10()) ? TTMP_GFX9_GFX10_MIN : TTMP_VI_MIN; 1015 unsigned TTmpMax = 1016 (isGFX9() || isGFX10()) ? TTMP_GFX9_GFX10_MAX : TTMP_VI_MAX; 1017 1018 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1019 } 1020 1021 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const { 1022 using namespace AMDGPU::EncValues; 1023 1024 assert(Val < 1024); // enum10 1025 1026 bool IsAGPR = Val & 512; 1027 Val &= 511; 1028 1029 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1030 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1031 : getVgprClassId(Width), Val - VGPR_MIN); 1032 } 1033 if (Val <= SGPR_MAX) { 1034 assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning. 1035 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1036 } 1037 1038 int TTmpIdx = getTTmpIdx(Val); 1039 if (TTmpIdx >= 0) { 1040 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1041 } 1042 1043 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1044 return decodeIntImmed(Val); 1045 1046 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1047 return decodeFPImmed(Width, Val); 1048 1049 if (Val == LITERAL_CONST) 1050 return decodeLiteralConstant(); 1051 1052 switch (Width) { 1053 case OPW32: 1054 case OPW16: 1055 case OPWV216: 1056 return decodeSpecialReg32(Val); 1057 case OPW64: 1058 return decodeSpecialReg64(Val); 1059 default: 1060 llvm_unreachable("unexpected immediate type"); 1061 } 1062 } 1063 1064 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const { 1065 using namespace AMDGPU::EncValues; 1066 1067 assert(Val < 128); 1068 assert(Width == OPW256 || Width == OPW512); 1069 1070 if (Val <= SGPR_MAX) { 1071 assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning. 1072 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1073 } 1074 1075 int TTmpIdx = getTTmpIdx(Val); 1076 if (TTmpIdx >= 0) { 1077 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1078 } 1079 1080 llvm_unreachable("unknown dst register"); 1081 } 1082 1083 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1084 using namespace AMDGPU; 1085 1086 switch (Val) { 1087 case 102: return createRegOperand(FLAT_SCR_LO); 1088 case 103: return createRegOperand(FLAT_SCR_HI); 1089 case 104: return createRegOperand(XNACK_MASK_LO); 1090 case 105: return createRegOperand(XNACK_MASK_HI); 1091 case 106: return createRegOperand(VCC_LO); 1092 case 107: return createRegOperand(VCC_HI); 1093 case 108: return createRegOperand(TBA_LO); 1094 case 109: return createRegOperand(TBA_HI); 1095 case 110: return createRegOperand(TMA_LO); 1096 case 111: return createRegOperand(TMA_HI); 1097 case 124: return createRegOperand(M0); 1098 case 125: return createRegOperand(SGPR_NULL); 1099 case 126: return createRegOperand(EXEC_LO); 1100 case 127: return createRegOperand(EXEC_HI); 1101 case 235: return createRegOperand(SRC_SHARED_BASE); 1102 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1103 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1104 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1105 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1106 case 251: return createRegOperand(SRC_VCCZ); 1107 case 252: return createRegOperand(SRC_EXECZ); 1108 case 253: return createRegOperand(SRC_SCC); 1109 case 254: return createRegOperand(LDS_DIRECT); 1110 default: break; 1111 } 1112 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1113 } 1114 1115 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1116 using namespace AMDGPU; 1117 1118 switch (Val) { 1119 case 102: return createRegOperand(FLAT_SCR); 1120 case 104: return createRegOperand(XNACK_MASK); 1121 case 106: return createRegOperand(VCC); 1122 case 108: return createRegOperand(TBA); 1123 case 110: return createRegOperand(TMA); 1124 case 125: return createRegOperand(SGPR_NULL); 1125 case 126: return createRegOperand(EXEC); 1126 case 235: return createRegOperand(SRC_SHARED_BASE); 1127 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1128 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1129 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1130 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1131 case 251: return createRegOperand(SRC_VCCZ); 1132 case 252: return createRegOperand(SRC_EXECZ); 1133 case 253: return createRegOperand(SRC_SCC); 1134 default: break; 1135 } 1136 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1137 } 1138 1139 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 1140 const unsigned Val) const { 1141 using namespace AMDGPU::SDWA; 1142 using namespace AMDGPU::EncValues; 1143 1144 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1145 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 1146 // XXX: cast to int is needed to avoid stupid warning: 1147 // compare with unsigned is always true 1148 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1149 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1150 return createRegOperand(getVgprClassId(Width), 1151 Val - SDWA9EncValues::SRC_VGPR_MIN); 1152 } 1153 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1154 Val <= (isGFX10() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1155 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1156 return createSRegOperand(getSgprClassId(Width), 1157 Val - SDWA9EncValues::SRC_SGPR_MIN); 1158 } 1159 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1160 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1161 return createSRegOperand(getTtmpClassId(Width), 1162 Val - SDWA9EncValues::SRC_TTMP_MIN); 1163 } 1164 1165 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1166 1167 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1168 return decodeIntImmed(SVal); 1169 1170 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1171 return decodeFPImmed(Width, SVal); 1172 1173 return decodeSpecialReg32(SVal); 1174 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 1175 return createRegOperand(getVgprClassId(Width), Val); 1176 } 1177 llvm_unreachable("unsupported target"); 1178 } 1179 1180 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1181 return decodeSDWASrc(OPW16, Val); 1182 } 1183 1184 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1185 return decodeSDWASrc(OPW32, Val); 1186 } 1187 1188 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1189 using namespace AMDGPU::SDWA; 1190 1191 assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1192 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) && 1193 "SDWAVopcDst should be present only on GFX9+"); 1194 1195 bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64]; 1196 1197 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1198 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1199 1200 int TTmpIdx = getTTmpIdx(Val); 1201 if (TTmpIdx >= 0) { 1202 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1203 return createSRegOperand(TTmpClsId, TTmpIdx); 1204 } else if (Val > SGPR_MAX) { 1205 return IsWave64 ? decodeSpecialReg64(Val) 1206 : decodeSpecialReg32(Val); 1207 } else { 1208 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1209 } 1210 } else { 1211 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1212 } 1213 } 1214 1215 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1216 return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ? 1217 decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val); 1218 } 1219 1220 bool AMDGPUDisassembler::isVI() const { 1221 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]; 1222 } 1223 1224 bool AMDGPUDisassembler::isGFX9() const { 1225 return STI.getFeatureBits()[AMDGPU::FeatureGFX9]; 1226 } 1227 1228 bool AMDGPUDisassembler::isGFX10() const { 1229 return STI.getFeatureBits()[AMDGPU::FeatureGFX10]; 1230 } 1231 1232 //===----------------------------------------------------------------------===// 1233 // AMDGPU specific symbol handling 1234 //===----------------------------------------------------------------------===// 1235 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1236 do { \ 1237 KdStream << Indent << DIRECTIVE " " \ 1238 << ((FourByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1239 } while (0) 1240 1241 // NOLINTNEXTLINE(readability-identifier-naming) 1242 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1243 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1244 using namespace amdhsa; 1245 StringRef Indent = "\t"; 1246 1247 // We cannot accurately backward compute #VGPRs used from 1248 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1249 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1250 // simply calculate the inverse of what the assembler does. 1251 1252 uint32_t GranulatedWorkitemVGPRCount = 1253 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT) >> 1254 COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT; 1255 1256 uint32_t NextFreeVGPR = (GranulatedWorkitemVGPRCount + 1) * 1257 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI); 1258 1259 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1260 1261 // We cannot backward compute values used to calculate 1262 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1263 // directives can't be computed: 1264 // .amdhsa_reserve_vcc 1265 // .amdhsa_reserve_flat_scratch 1266 // .amdhsa_reserve_xnack_mask 1267 // They take their respective default values if not specified in the assembly. 1268 // 1269 // GRANULATED_WAVEFRONT_SGPR_COUNT 1270 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1271 // 1272 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1273 // are set to 0. So while disassembling we consider that: 1274 // 1275 // GRANULATED_WAVEFRONT_SGPR_COUNT 1276 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1277 // 1278 // The disassembler cannot recover the original values of those 3 directives. 1279 1280 uint32_t GranulatedWavefrontSGPRCount = 1281 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT) >> 1282 COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT; 1283 1284 if (isGFX10() && GranulatedWavefrontSGPRCount) 1285 return MCDisassembler::Fail; 1286 1287 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1288 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1289 1290 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1291 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1292 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1293 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1294 1295 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY) 1296 return MCDisassembler::Fail; 1297 1298 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1299 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1300 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1301 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1302 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1303 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1304 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1305 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1306 1307 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) 1308 return MCDisassembler::Fail; 1309 1310 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 1311 1312 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) 1313 return MCDisassembler::Fail; 1314 1315 PRINT_DIRECTIVE(".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 1316 1317 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) 1318 return MCDisassembler::Fail; 1319 1320 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER) 1321 return MCDisassembler::Fail; 1322 1323 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_FP16_OVFL); 1324 1325 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED0) 1326 return MCDisassembler::Fail; 1327 1328 if (isGFX10()) { 1329 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1330 COMPUTE_PGM_RSRC1_WGP_MODE); 1331 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_MEM_ORDERED); 1332 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_FWD_PROGRESS); 1333 } 1334 return MCDisassembler::Success; 1335 } 1336 1337 // NOLINTNEXTLINE(readability-identifier-naming) 1338 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 1339 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1340 using namespace amdhsa; 1341 StringRef Indent = "\t"; 1342 PRINT_DIRECTIVE( 1343 ".amdhsa_system_sgpr_private_segment_wavefront_offset", 1344 COMPUTE_PGM_RSRC2_ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET); 1345 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 1346 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 1347 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 1348 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 1349 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 1350 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 1351 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 1352 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 1353 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 1354 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 1355 1356 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH) 1357 return MCDisassembler::Fail; 1358 1359 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY) 1360 return MCDisassembler::Fail; 1361 1362 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE) 1363 return MCDisassembler::Fail; 1364 1365 PRINT_DIRECTIVE( 1366 ".amdhsa_exception_fp_ieee_invalid_op", 1367 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 1368 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 1369 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 1370 PRINT_DIRECTIVE( 1371 ".amdhsa_exception_fp_ieee_div_zero", 1372 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 1373 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 1374 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 1375 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 1376 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 1377 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 1378 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 1379 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 1380 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 1381 1382 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0) 1383 return MCDisassembler::Fail; 1384 1385 return MCDisassembler::Success; 1386 } 1387 1388 #undef PRINT_DIRECTIVE 1389 1390 MCDisassembler::DecodeStatus 1391 AMDGPUDisassembler::decodeKernelDescriptorDirective( 1392 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 1393 raw_string_ostream &KdStream) const { 1394 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1395 do { \ 1396 KdStream << Indent << DIRECTIVE " " \ 1397 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1398 } while (0) 1399 1400 uint16_t TwoByteBuffer = 0; 1401 uint32_t FourByteBuffer = 0; 1402 uint64_t EightByteBuffer = 0; 1403 1404 StringRef ReservedBytes; 1405 StringRef Indent = "\t"; 1406 1407 assert(Bytes.size() == 64); 1408 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 1409 1410 switch (Cursor.tell()) { 1411 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 1412 FourByteBuffer = DE.getU32(Cursor); 1413 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 1414 << '\n'; 1415 return MCDisassembler::Success; 1416 1417 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 1418 FourByteBuffer = DE.getU32(Cursor); 1419 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 1420 << FourByteBuffer << '\n'; 1421 return MCDisassembler::Success; 1422 1423 case amdhsa::RESERVED0_OFFSET: 1424 // 8 reserved bytes, must be 0. 1425 EightByteBuffer = DE.getU64(Cursor); 1426 if (EightByteBuffer) { 1427 return MCDisassembler::Fail; 1428 } 1429 return MCDisassembler::Success; 1430 1431 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 1432 // KERNEL_CODE_ENTRY_BYTE_OFFSET 1433 // So far no directive controls this for Code Object V3, so simply skip for 1434 // disassembly. 1435 DE.skip(Cursor, 8); 1436 return MCDisassembler::Success; 1437 1438 case amdhsa::RESERVED1_OFFSET: 1439 // 20 reserved bytes, must be 0. 1440 ReservedBytes = DE.getBytes(Cursor, 20); 1441 for (int I = 0; I < 20; ++I) { 1442 if (ReservedBytes[I] != 0) { 1443 return MCDisassembler::Fail; 1444 } 1445 } 1446 return MCDisassembler::Success; 1447 1448 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 1449 // COMPUTE_PGM_RSRC3 1450 // - Only set for GFX10, GFX6-9 have this to be 0. 1451 // - Currently no directives directly control this. 1452 FourByteBuffer = DE.getU32(Cursor); 1453 if (!isGFX10() && FourByteBuffer) { 1454 return MCDisassembler::Fail; 1455 } 1456 return MCDisassembler::Success; 1457 1458 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 1459 FourByteBuffer = DE.getU32(Cursor); 1460 if (decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream) == 1461 MCDisassembler::Fail) { 1462 return MCDisassembler::Fail; 1463 } 1464 return MCDisassembler::Success; 1465 1466 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 1467 FourByteBuffer = DE.getU32(Cursor); 1468 if (decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream) == 1469 MCDisassembler::Fail) { 1470 return MCDisassembler::Fail; 1471 } 1472 return MCDisassembler::Success; 1473 1474 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 1475 using namespace amdhsa; 1476 TwoByteBuffer = DE.getU16(Cursor); 1477 1478 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 1479 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 1480 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 1481 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 1482 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 1483 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 1484 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 1485 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 1486 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 1487 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 1488 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 1489 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 1490 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 1491 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 1492 1493 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 1494 return MCDisassembler::Fail; 1495 1496 // Reserved for GFX9 1497 if (isGFX9() && 1498 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 1499 return MCDisassembler::Fail; 1500 } else if (isGFX10()) { 1501 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 1502 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 1503 } 1504 1505 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) 1506 return MCDisassembler::Fail; 1507 1508 return MCDisassembler::Success; 1509 1510 case amdhsa::RESERVED2_OFFSET: 1511 // 6 bytes from here are reserved, must be 0. 1512 ReservedBytes = DE.getBytes(Cursor, 6); 1513 for (int I = 0; I < 6; ++I) { 1514 if (ReservedBytes[I] != 0) 1515 return MCDisassembler::Fail; 1516 } 1517 return MCDisassembler::Success; 1518 1519 default: 1520 llvm_unreachable("Unhandled index. Case statements cover everything."); 1521 return MCDisassembler::Fail; 1522 } 1523 #undef PRINT_DIRECTIVE 1524 } 1525 1526 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( 1527 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 1528 // CP microcode requires the kernel descriptor to be 64 aligned. 1529 if (Bytes.size() != 64 || KdAddress % 64 != 0) 1530 return MCDisassembler::Fail; 1531 1532 std::string Kd; 1533 raw_string_ostream KdStream(Kd); 1534 KdStream << ".amdhsa_kernel " << KdName << '\n'; 1535 1536 DataExtractor::Cursor C(0); 1537 while (C && C.tell() < Bytes.size()) { 1538 MCDisassembler::DecodeStatus Status = 1539 decodeKernelDescriptorDirective(C, Bytes, KdStream); 1540 1541 cantFail(C.takeError()); 1542 1543 if (Status == MCDisassembler::Fail) 1544 return MCDisassembler::Fail; 1545 } 1546 KdStream << ".end_amdhsa_kernel\n"; 1547 outs() << KdStream.str(); 1548 return MCDisassembler::Success; 1549 } 1550 1551 Optional<MCDisassembler::DecodeStatus> 1552 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 1553 ArrayRef<uint8_t> Bytes, uint64_t Address, 1554 raw_ostream &CStream) const { 1555 // Right now only kernel descriptor needs to be handled. 1556 // We ignore all other symbols for target specific handling. 1557 // TODO: 1558 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 1559 // Object V2 and V3 when symbols are marked protected. 1560 1561 // amd_kernel_code_t for Code Object V2. 1562 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 1563 Size = 256; 1564 return MCDisassembler::Fail; 1565 } 1566 1567 // Code Object V3 kernel descriptors. 1568 StringRef Name = Symbol.Name; 1569 if (Symbol.Type == ELF::STT_OBJECT && Name.endswith(StringRef(".kd"))) { 1570 Size = 64; // Size = 64 regardless of success or failure. 1571 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 1572 } 1573 return None; 1574 } 1575 1576 //===----------------------------------------------------------------------===// 1577 // AMDGPUSymbolizer 1578 //===----------------------------------------------------------------------===// 1579 1580 // Try to find symbol name for specified label 1581 bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst, 1582 raw_ostream &/*cStream*/, int64_t Value, 1583 uint64_t /*Address*/, bool IsBranch, 1584 uint64_t /*Offset*/, uint64_t /*InstSize*/) { 1585 1586 if (!IsBranch) { 1587 return false; 1588 } 1589 1590 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 1591 if (!Symbols) 1592 return false; 1593 1594 auto Result = std::find_if(Symbols->begin(), Symbols->end(), 1595 [Value](const SymbolInfoTy& Val) { 1596 return Val.Addr == static_cast<uint64_t>(Value) 1597 && Val.Type == ELF::STT_NOTYPE; 1598 }); 1599 if (Result != Symbols->end()) { 1600 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 1601 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 1602 Inst.addOperand(MCOperand::createExpr(Add)); 1603 return true; 1604 } 1605 return false; 1606 } 1607 1608 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 1609 int64_t Value, 1610 uint64_t Address) { 1611 llvm_unreachable("unimplemented"); 1612 } 1613 1614 //===----------------------------------------------------------------------===// 1615 // Initialization 1616 //===----------------------------------------------------------------------===// 1617 1618 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 1619 LLVMOpInfoCallback /*GetOpInfo*/, 1620 LLVMSymbolLookupCallback /*SymbolLookUp*/, 1621 void *DisInfo, 1622 MCContext *Ctx, 1623 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 1624 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 1625 } 1626 1627 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 1628 const MCSubtargetInfo &STI, 1629 MCContext &Ctx) { 1630 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 1631 } 1632 1633 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 1634 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 1635 createAMDGPUDisassembler); 1636 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 1637 createAMDGPUSymbolizer); 1638 } 1639