1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "SIDefines.h" 22 #include "SIRegisterInfo.h" 23 #include "TargetInfo/AMDGPUTargetInfo.h" 24 #include "Utils/AMDGPUBaseInfo.h" 25 #include "llvm-c/DisassemblerTypes.h" 26 #include "llvm/BinaryFormat/ELF.h" 27 #include "llvm/MC/MCAsmInfo.h" 28 #include "llvm/MC/MCContext.h" 29 #include "llvm/MC/MCDecoderOps.h" 30 #include "llvm/MC/MCExpr.h" 31 #include "llvm/MC/MCInstrDesc.h" 32 #include "llvm/MC/MCRegisterInfo.h" 33 #include "llvm/MC/MCSubtargetInfo.h" 34 #include "llvm/MC/TargetRegistry.h" 35 #include "llvm/Support/AMDHSAKernelDescriptor.h" 36 37 using namespace llvm; 38 39 #define DEBUG_TYPE "amdgpu-disassembler" 40 41 #define SGPR_MAX \ 42 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 43 : AMDGPU::EncValues::SGPR_MAX_SI) 44 45 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 46 47 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 48 MCContext &Ctx, 49 MCInstrInfo const *MCII) : 50 MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), 51 TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) { 52 53 // ToDo: AMDGPUDisassembler supports only VI ISA. 54 if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10Plus()) 55 report_fatal_error("Disassembly not yet supported for subtarget"); 56 } 57 58 inline static MCDisassembler::DecodeStatus 59 addOperand(MCInst &Inst, const MCOperand& Opnd) { 60 Inst.addOperand(Opnd); 61 return Opnd.isValid() ? 62 MCDisassembler::Success : 63 MCDisassembler::Fail; 64 } 65 66 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 67 uint16_t NameIdx) { 68 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 69 if (OpIdx != -1) { 70 auto I = MI.begin(); 71 std::advance(I, OpIdx); 72 MI.insert(I, Op); 73 } 74 return OpIdx; 75 } 76 77 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, 78 uint64_t Addr, 79 const MCDisassembler *Decoder) { 80 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 81 82 // Our branches take a simm16, but we need two extra bits to account for the 83 // factor of 4. 84 APInt SignedOffset(18, Imm * 4, true); 85 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 86 87 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2, 0)) 88 return MCDisassembler::Success; 89 return addOperand(Inst, MCOperand::createImm(Imm)); 90 } 91 92 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, 93 const MCDisassembler *Decoder) { 94 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 95 int64_t Offset; 96 if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 97 Offset = Imm & 0xFFFFF; 98 } else { // GFX9+ supports 21-bit signed offsets. 99 Offset = SignExtend64<21>(Imm); 100 } 101 return addOperand(Inst, MCOperand::createImm(Offset)); 102 } 103 104 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, 105 const MCDisassembler *Decoder) { 106 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 107 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 108 } 109 110 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 111 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \ 112 uint64_t /*Addr*/, \ 113 const MCDisassembler *Decoder) { \ 114 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 115 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 116 } 117 118 #define DECODE_OPERAND_REG(RegClass) \ 119 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass) 120 121 DECODE_OPERAND_REG(VGPR_32) 122 DECODE_OPERAND_REG(VRegOrLds_32) 123 DECODE_OPERAND_REG(VS_32) 124 DECODE_OPERAND_REG(VS_64) 125 DECODE_OPERAND_REG(VS_128) 126 127 DECODE_OPERAND_REG(VReg_64) 128 DECODE_OPERAND_REG(VReg_96) 129 DECODE_OPERAND_REG(VReg_128) 130 DECODE_OPERAND_REG(VReg_256) 131 DECODE_OPERAND_REG(VReg_512) 132 DECODE_OPERAND_REG(VReg_1024) 133 134 DECODE_OPERAND_REG(SReg_32) 135 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC) 136 DECODE_OPERAND_REG(SReg_32_XEXEC_HI) 137 DECODE_OPERAND_REG(SRegOrLds_32) 138 DECODE_OPERAND_REG(SReg_64) 139 DECODE_OPERAND_REG(SReg_64_XEXEC) 140 DECODE_OPERAND_REG(SReg_128) 141 DECODE_OPERAND_REG(SReg_256) 142 DECODE_OPERAND_REG(SReg_512) 143 144 DECODE_OPERAND_REG(AGPR_32) 145 DECODE_OPERAND_REG(AReg_64) 146 DECODE_OPERAND_REG(AReg_128) 147 DECODE_OPERAND_REG(AReg_256) 148 DECODE_OPERAND_REG(AReg_512) 149 DECODE_OPERAND_REG(AReg_1024) 150 DECODE_OPERAND_REG(AV_32) 151 DECODE_OPERAND_REG(AV_64) 152 DECODE_OPERAND_REG(AV_128) 153 DECODE_OPERAND_REG(AVDst_128) 154 DECODE_OPERAND_REG(AVDst_512) 155 156 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, unsigned Imm, 157 uint64_t Addr, 158 const MCDisassembler *Decoder) { 159 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 160 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 161 } 162 163 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, unsigned Imm, 164 uint64_t Addr, 165 const MCDisassembler *Decoder) { 166 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 167 return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm)); 168 } 169 170 static DecodeStatus decodeOperand_VSrcV232(MCInst &Inst, unsigned Imm, 171 uint64_t Addr, 172 const MCDisassembler *Decoder) { 173 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 174 return addOperand(Inst, DAsm->decodeOperand_VSrcV232(Imm)); 175 } 176 177 static DecodeStatus decodeOperand_VS_16(MCInst &Inst, unsigned Imm, 178 uint64_t Addr, 179 const MCDisassembler *Decoder) { 180 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 181 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 182 } 183 184 static DecodeStatus decodeOperand_VS_32(MCInst &Inst, unsigned Imm, 185 uint64_t Addr, 186 const MCDisassembler *Decoder) { 187 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 188 return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm)); 189 } 190 191 static DecodeStatus decodeOperand_AReg_64(MCInst &Inst, unsigned Imm, 192 uint64_t Addr, 193 const MCDisassembler *Decoder) { 194 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 195 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm | 512)); 196 } 197 198 static DecodeStatus decodeOperand_AReg_128(MCInst &Inst, unsigned Imm, 199 uint64_t Addr, 200 const MCDisassembler *Decoder) { 201 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 202 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512)); 203 } 204 205 static DecodeStatus decodeOperand_AReg_256(MCInst &Inst, unsigned Imm, 206 uint64_t Addr, 207 const MCDisassembler *Decoder) { 208 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 209 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm | 512)); 210 } 211 212 static DecodeStatus decodeOperand_AReg_512(MCInst &Inst, unsigned Imm, 213 uint64_t Addr, 214 const MCDisassembler *Decoder) { 215 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 216 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512)); 217 } 218 219 static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst, unsigned Imm, 220 uint64_t Addr, 221 const MCDisassembler *Decoder) { 222 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 223 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512)); 224 } 225 226 static DecodeStatus decodeOperand_VReg_64(MCInst &Inst, unsigned Imm, 227 uint64_t Addr, 228 const MCDisassembler *Decoder) { 229 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 230 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm)); 231 } 232 233 static DecodeStatus decodeOperand_VReg_128(MCInst &Inst, unsigned Imm, 234 uint64_t Addr, 235 const MCDisassembler *Decoder) { 236 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 237 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm)); 238 } 239 240 static DecodeStatus decodeOperand_VReg_256(MCInst &Inst, unsigned Imm, 241 uint64_t Addr, 242 const MCDisassembler *Decoder) { 243 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 244 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm)); 245 } 246 247 static DecodeStatus decodeOperand_VReg_512(MCInst &Inst, unsigned Imm, 248 uint64_t Addr, 249 const MCDisassembler *Decoder) { 250 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 251 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm)); 252 } 253 254 static DecodeStatus decodeOperand_VReg_1024(MCInst &Inst, unsigned Imm, 255 uint64_t Addr, 256 const MCDisassembler *Decoder) { 257 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 258 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm)); 259 } 260 261 static DecodeStatus decodeOperand_f32kimm(MCInst &Inst, unsigned Imm, 262 uint64_t Addr, 263 const MCDisassembler *Decoder) { 264 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 265 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 266 } 267 268 static DecodeStatus decodeOperand_f16kimm(MCInst &Inst, unsigned Imm, 269 uint64_t Addr, 270 const MCDisassembler *Decoder) { 271 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 272 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 273 } 274 275 static DecodeStatus 276 decodeOperand_VS_16_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, 277 const MCDisassembler *Decoder) { 278 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 279 return addOperand( 280 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW16, Imm, true)); 281 } 282 283 static DecodeStatus 284 decodeOperand_VS_32_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, 285 const MCDisassembler *Decoder) { 286 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 287 return addOperand( 288 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW32, Imm, true)); 289 } 290 291 static bool IsAGPROperand(const MCInst &Inst, int OpIdx, 292 const MCRegisterInfo *MRI) { 293 if (OpIdx < 0) 294 return false; 295 296 const MCOperand &Op = Inst.getOperand(OpIdx); 297 if (!Op.isReg()) 298 return false; 299 300 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); 301 auto Reg = Sub ? Sub : Op.getReg(); 302 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; 303 } 304 305 static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, unsigned Imm, 306 AMDGPUDisassembler::OpWidthTy Opw, 307 const MCDisassembler *Decoder) { 308 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 309 if (!DAsm->isGFX90A()) { 310 Imm &= 511; 311 } else { 312 // If atomic has both vdata and vdst their register classes are tied. 313 // The bit is decoded along with the vdst, first operand. We need to 314 // change register class to AGPR if vdst was AGPR. 315 // If a DS instruction has both data0 and data1 their register classes 316 // are also tied. 317 unsigned Opc = Inst.getOpcode(); 318 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; 319 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 320 : AMDGPU::OpName::vdata; 321 const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo(); 322 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); 323 if ((int)Inst.getNumOperands() == DataIdx) { 324 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); 325 if (IsAGPROperand(Inst, DstIdx, MRI)) 326 Imm |= 512; 327 } 328 329 if (TSFlags & SIInstrFlags::DS) { 330 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); 331 if ((int)Inst.getNumOperands() == Data2Idx && 332 IsAGPROperand(Inst, DataIdx, MRI)) 333 Imm |= 512; 334 } 335 } 336 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); 337 } 338 339 static DecodeStatus 340 DecodeAVLdSt_32RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 341 const MCDisassembler *Decoder) { 342 return decodeOperand_AVLdSt_Any(Inst, Imm, 343 AMDGPUDisassembler::OPW32, Decoder); 344 } 345 346 static DecodeStatus 347 DecodeAVLdSt_64RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 348 const MCDisassembler *Decoder) { 349 return decodeOperand_AVLdSt_Any(Inst, Imm, 350 AMDGPUDisassembler::OPW64, Decoder); 351 } 352 353 static DecodeStatus 354 DecodeAVLdSt_96RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 355 const MCDisassembler *Decoder) { 356 return decodeOperand_AVLdSt_Any(Inst, Imm, 357 AMDGPUDisassembler::OPW96, Decoder); 358 } 359 360 static DecodeStatus 361 DecodeAVLdSt_128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 362 const MCDisassembler *Decoder) { 363 return decodeOperand_AVLdSt_Any(Inst, Imm, 364 AMDGPUDisassembler::OPW128, Decoder); 365 } 366 367 static DecodeStatus decodeOperand_SReg_32(MCInst &Inst, unsigned Imm, 368 uint64_t Addr, 369 const MCDisassembler *Decoder) { 370 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 371 return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm)); 372 } 373 374 #define DECODE_SDWA(DecName) \ 375 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 376 377 DECODE_SDWA(Src32) 378 DECODE_SDWA(Src16) 379 DECODE_SDWA(VopcDst) 380 381 #include "AMDGPUGenDisassemblerTables.inc" 382 383 //===----------------------------------------------------------------------===// 384 // 385 //===----------------------------------------------------------------------===// 386 387 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 388 assert(Bytes.size() >= sizeof(T)); 389 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data()); 390 Bytes = Bytes.slice(sizeof(T)); 391 return Res; 392 } 393 394 // The disassembler is greedy, so we need to check FI operand value to 395 // not parse a dpp if the correct literal is not set. For dpp16 the 396 // autogenerated decoder checks the dpp literal 397 static bool isValidDPP8(const MCInst &MI) { 398 using namespace llvm::AMDGPU::DPP; 399 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi); 400 assert(FiIdx != -1); 401 if ((unsigned)FiIdx >= MI.getNumOperands()) 402 return false; 403 unsigned Fi = MI.getOperand(FiIdx).getImm(); 404 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1; 405 } 406 407 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 408 ArrayRef<uint8_t> Bytes_, 409 uint64_t Address, 410 raw_ostream &CS) const { 411 CommentStream = &CS; 412 bool IsSDWA = false; 413 414 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 415 Bytes = Bytes_.slice(0, MaxInstBytesNum); 416 417 DecodeStatus Res = MCDisassembler::Fail; 418 do { 419 // ToDo: better to switch encoding length using some bit predicate 420 // but it is unknown yet, so try all we can 421 422 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 423 // encodings 424 if (Bytes.size() >= 8) { 425 const uint64_t QW = eatBytes<uint64_t>(Bytes); 426 427 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 428 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address); 429 if (Res) { 430 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) 431 == -1) 432 break; 433 if (convertDPP8Inst(MI) == MCDisassembler::Success) 434 break; 435 MI = MCInst(); // clear 436 } 437 } 438 439 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address); 440 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 441 break; 442 443 MI = MCInst(); // clear 444 445 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address); 446 if (Res) break; 447 448 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address); 449 if (Res) { IsSDWA = true; break; } 450 451 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address); 452 if (Res) { IsSDWA = true; break; } 453 454 Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address); 455 if (Res) { IsSDWA = true; break; } 456 457 if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) { 458 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address); 459 if (Res) 460 break; 461 } 462 463 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 464 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 465 // table first so we print the correct name. 466 if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) { 467 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address); 468 if (Res) 469 break; 470 } 471 } 472 473 // Reinitialize Bytes as DPP64 could have eaten too much 474 Bytes = Bytes_.slice(0, MaxInstBytesNum); 475 476 // Try decode 32-bit instruction 477 if (Bytes.size() < 4) break; 478 const uint32_t DW = eatBytes<uint32_t>(Bytes); 479 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address); 480 if (Res) break; 481 482 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address); 483 if (Res) break; 484 485 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address); 486 if (Res) break; 487 488 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 489 Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address); 490 if (Res) 491 break; 492 } 493 494 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 495 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address); 496 if (Res) break; 497 } 498 499 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address); 500 if (Res) break; 501 502 Res = tryDecodeInst(DecoderTableGFX1132, MI, DW, Address); 503 if (Res) break; 504 505 if (Bytes.size() < 4) break; 506 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 507 508 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 509 Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address); 510 if (Res) 511 break; 512 } 513 514 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address); 515 if (Res) break; 516 517 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address); 518 if (Res) break; 519 520 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address); 521 if (Res) break; 522 523 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address); 524 if (Res) break; 525 526 Res = tryDecodeInst(DecoderTableGFX1164, MI, QW, Address); 527 } while (false); 528 529 if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi || 530 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 || 531 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 || 532 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 || 533 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 || 534 MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi || 535 MI.getOpcode() == AMDGPU::V_FMAC_F64_e64_gfx90a || 536 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi || 537 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 || 538 MI.getOpcode() == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 || 539 MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10)) { 540 // Insert dummy unused src2_modifiers. 541 insertNamedMCOperand(MI, MCOperand::createImm(0), 542 AMDGPU::OpName::src2_modifiers); 543 } 544 545 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 546 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT | SIInstrFlags::SMRD))) { 547 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 548 AMDGPU::OpName::cpol); 549 if (CPolPos != -1) { 550 unsigned CPol = 551 (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ? 552 AMDGPU::CPol::GLC : 0; 553 if (MI.getNumOperands() <= (unsigned)CPolPos) { 554 insertNamedMCOperand(MI, MCOperand::createImm(CPol), 555 AMDGPU::OpName::cpol); 556 } else if (CPol) { 557 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); 558 } 559 } 560 } 561 562 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 563 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) && 564 (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts])) { 565 // GFX90A lost TFE, its place is occupied by ACC. 566 int TFEOpIdx = 567 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); 568 if (TFEOpIdx != -1) { 569 auto TFEIter = MI.begin(); 570 std::advance(TFEIter, TFEOpIdx); 571 MI.insert(TFEIter, MCOperand::createImm(0)); 572 } 573 } 574 575 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 576 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF))) { 577 int SWZOpIdx = 578 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); 579 if (SWZOpIdx != -1) { 580 auto SWZIter = MI.begin(); 581 std::advance(SWZIter, SWZOpIdx); 582 MI.insert(SWZIter, MCOperand::createImm(0)); 583 } 584 } 585 586 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 587 int VAddr0Idx = 588 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 589 int RsrcIdx = 590 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 591 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 592 if (VAddr0Idx >= 0 && NSAArgs > 0) { 593 unsigned NSAWords = (NSAArgs + 3) / 4; 594 if (Bytes.size() < 4 * NSAWords) { 595 Res = MCDisassembler::Fail; 596 } else { 597 for (unsigned i = 0; i < NSAArgs; ++i) { 598 const unsigned VAddrIdx = VAddr0Idx + 1 + i; 599 auto VAddrRCID = MCII->get(MI.getOpcode()).OpInfo[VAddrIdx].RegClass; 600 MI.insert(MI.begin() + VAddrIdx, 601 createRegOperand(VAddrRCID, Bytes[i])); 602 } 603 Bytes = Bytes.slice(4 * NSAWords); 604 } 605 } 606 607 if (Res) 608 Res = convertMIMGInst(MI); 609 } 610 611 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::EXP)) 612 Res = convertEXPInst(MI); 613 614 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VINTERP)) 615 Res = convertVINTERPInst(MI); 616 617 if (Res && IsSDWA) 618 Res = convertSDWAInst(MI); 619 620 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 621 AMDGPU::OpName::vdst_in); 622 if (VDstIn_Idx != -1) { 623 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 624 MCOI::OperandConstraint::TIED_TO); 625 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 626 !MI.getOperand(VDstIn_Idx).isReg() || 627 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 628 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 629 MI.erase(&MI.getOperand(VDstIn_Idx)); 630 insertNamedMCOperand(MI, 631 MCOperand::createReg(MI.getOperand(Tied).getReg()), 632 AMDGPU::OpName::vdst_in); 633 } 634 } 635 636 int ImmLitIdx = 637 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm); 638 if (Res && ImmLitIdx != -1) 639 Res = convertFMAanyK(MI, ImmLitIdx); 640 641 // if the opcode was not recognized we'll assume a Size of 4 bytes 642 // (unless there are fewer bytes left) 643 Size = Res ? (MaxInstBytesNum - Bytes.size()) 644 : std::min((size_t)4, Bytes_.size()); 645 return Res; 646 } 647 648 DecodeStatus AMDGPUDisassembler::convertEXPInst(MCInst &MI) const { 649 if (STI.getFeatureBits()[AMDGPU::FeatureGFX11]) { 650 // The MCInst still has these fields even though they are no longer encoded 651 // in the GFX11 instruction. 652 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vm); 653 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::compr); 654 } 655 return MCDisassembler::Success; 656 } 657 658 DecodeStatus AMDGPUDisassembler::convertVINTERPInst(MCInst &MI) const { 659 if (MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx11 || 660 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx11 || 661 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx11 || 662 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx11) { 663 // The MCInst has this field that is not directly encoded in the 664 // instruction. 665 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::op_sel); 666 } 667 return MCDisassembler::Success; 668 } 669 670 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 671 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 672 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 673 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1) 674 // VOPC - insert clamp 675 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 676 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 677 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 678 if (SDst != -1) { 679 // VOPC - insert VCC register as sdst 680 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 681 AMDGPU::OpName::sdst); 682 } else { 683 // VOP1/2 - insert omod if present in instruction 684 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 685 } 686 } 687 return MCDisassembler::Success; 688 } 689 690 // We must check FI == literal to reject not genuine dpp8 insts, and we must 691 // first add optional MI operands to check FI 692 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 693 unsigned Opc = MI.getOpcode(); 694 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 695 696 // Insert dummy unused src modifiers. 697 if (MI.getNumOperands() < DescNumOps && 698 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1) 699 insertNamedMCOperand(MI, MCOperand::createImm(0), 700 AMDGPU::OpName::src0_modifiers); 701 702 if (MI.getNumOperands() < DescNumOps && 703 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1) 704 insertNamedMCOperand(MI, MCOperand::createImm(0), 705 AMDGPU::OpName::src1_modifiers); 706 707 return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail; 708 } 709 710 // Note that before gfx10, the MIMG encoding provided no information about 711 // VADDR size. Consequently, decoded instructions always show address as if it 712 // has 1 dword, which could be not really so. 713 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 714 715 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 716 AMDGPU::OpName::vdst); 717 718 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 719 AMDGPU::OpName::vdata); 720 int VAddr0Idx = 721 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 722 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 723 AMDGPU::OpName::dmask); 724 725 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 726 AMDGPU::OpName::tfe); 727 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 728 AMDGPU::OpName::d16); 729 730 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 731 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 732 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 733 734 assert(VDataIdx != -1); 735 if (BaseOpcode->BVH) { 736 // Add A16 operand for intersect_ray instructions 737 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16) > -1) { 738 addOperand(MI, MCOperand::createImm(1)); 739 } 740 return MCDisassembler::Success; 741 } 742 743 bool IsAtomic = (VDstIdx != -1); 744 bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4; 745 bool IsNSA = false; 746 unsigned AddrSize = Info->VAddrDwords; 747 748 if (isGFX10Plus()) { 749 unsigned DimIdx = 750 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 751 int A16Idx = 752 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16); 753 const AMDGPU::MIMGDimInfo *Dim = 754 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 755 const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm()); 756 757 AddrSize = 758 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); 759 760 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA || 761 Info->MIMGEncoding == AMDGPU::MIMGEncGfx11NSA; 762 if (!IsNSA) { 763 if (AddrSize > 8) 764 AddrSize = 16; 765 } else { 766 if (AddrSize > Info->VAddrDwords) { 767 // The NSA encoding does not contain enough operands for the combination 768 // of base opcode / dimension. Should this be an error? 769 return MCDisassembler::Success; 770 } 771 } 772 } 773 774 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 775 unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u); 776 777 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 778 if (D16 && AMDGPU::hasPackedD16(STI)) { 779 DstSize = (DstSize + 1) / 2; 780 } 781 782 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm()) 783 DstSize += 1; 784 785 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 786 return MCDisassembler::Success; 787 788 int NewOpcode = 789 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 790 if (NewOpcode == -1) 791 return MCDisassembler::Success; 792 793 // Widen the register to the correct number of enabled channels. 794 unsigned NewVdata = AMDGPU::NoRegister; 795 if (DstSize != Info->VDataDwords) { 796 auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; 797 798 // Get first subregister of VData 799 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 800 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 801 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 802 803 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 804 &MRI.getRegClass(DataRCID)); 805 if (NewVdata == AMDGPU::NoRegister) { 806 // It's possible to encode this such that the low register + enabled 807 // components exceeds the register count. 808 return MCDisassembler::Success; 809 } 810 } 811 812 // If not using NSA on GFX10+, widen address register to correct size. 813 unsigned NewVAddr0 = AMDGPU::NoRegister; 814 if (isGFX10Plus() && !IsNSA && AddrSize != Info->VAddrDwords) { 815 unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg(); 816 unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0); 817 VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0; 818 819 auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass; 820 NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0, 821 &MRI.getRegClass(AddrRCID)); 822 if (NewVAddr0 == AMDGPU::NoRegister) 823 return MCDisassembler::Success; 824 } 825 826 MI.setOpcode(NewOpcode); 827 828 if (NewVdata != AMDGPU::NoRegister) { 829 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 830 831 if (IsAtomic) { 832 // Atomic operations have an additional operand (a copy of data) 833 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 834 } 835 } 836 837 if (NewVAddr0 != AMDGPU::NoRegister) { 838 MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0); 839 } else if (IsNSA) { 840 assert(AddrSize <= Info->VAddrDwords); 841 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 842 MI.begin() + VAddr0Idx + Info->VAddrDwords); 843 } 844 845 return MCDisassembler::Success; 846 } 847 848 DecodeStatus AMDGPUDisassembler::convertFMAanyK(MCInst &MI, 849 int ImmLitIdx) const { 850 assert(HasLiteral && "Should have decoded a literal"); 851 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 852 unsigned DescNumOps = Desc.getNumOperands(); 853 assert(DescNumOps == MI.getNumOperands()); 854 for (unsigned I = 0; I < DescNumOps; ++I) { 855 auto &Op = MI.getOperand(I); 856 auto OpType = Desc.OpInfo[I].OperandType; 857 bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED || 858 OpType == AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED); 859 if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST && 860 IsDeferredOp) 861 Op.setImm(Literal); 862 } 863 return MCDisassembler::Success; 864 } 865 866 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 867 return getContext().getRegisterInfo()-> 868 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 869 } 870 871 inline 872 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 873 const Twine& ErrMsg) const { 874 *CommentStream << "Error: " + ErrMsg; 875 876 // ToDo: add support for error operands to MCInst.h 877 // return MCOperand::createError(V); 878 return MCOperand(); 879 } 880 881 inline 882 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 883 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 884 } 885 886 inline 887 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 888 unsigned Val) const { 889 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 890 if (Val >= RegCl.getNumRegs()) 891 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 892 ": unknown register " + Twine(Val)); 893 return createRegOperand(RegCl.getRegister(Val)); 894 } 895 896 inline 897 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 898 unsigned Val) const { 899 // ToDo: SI/CI have 104 SGPRs, VI - 102 900 // Valery: here we accepting as much as we can, let assembler sort it out 901 int shift = 0; 902 switch (SRegClassID) { 903 case AMDGPU::SGPR_32RegClassID: 904 case AMDGPU::TTMP_32RegClassID: 905 break; 906 case AMDGPU::SGPR_64RegClassID: 907 case AMDGPU::TTMP_64RegClassID: 908 shift = 1; 909 break; 910 case AMDGPU::SGPR_128RegClassID: 911 case AMDGPU::TTMP_128RegClassID: 912 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 913 // this bundle? 914 case AMDGPU::SGPR_256RegClassID: 915 case AMDGPU::TTMP_256RegClassID: 916 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 917 // this bundle? 918 case AMDGPU::SGPR_512RegClassID: 919 case AMDGPU::TTMP_512RegClassID: 920 shift = 2; 921 break; 922 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 923 // this bundle? 924 default: 925 llvm_unreachable("unhandled register class"); 926 } 927 928 if (Val % (1 << shift)) { 929 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 930 << ": scalar reg isn't aligned " << Val; 931 } 932 933 return createRegOperand(SRegClassID, Val >> shift); 934 } 935 936 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { 937 return decodeSrcOp(OPW32, Val); 938 } 939 940 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { 941 return decodeSrcOp(OPW64, Val); 942 } 943 944 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const { 945 return decodeSrcOp(OPW128, Val); 946 } 947 948 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const { 949 return decodeSrcOp(OPW16, Val); 950 } 951 952 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const { 953 return decodeSrcOp(OPWV216, Val); 954 } 955 956 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV232(unsigned Val) const { 957 return decodeSrcOp(OPWV232, Val); 958 } 959 960 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { 961 // Some instructions have operand restrictions beyond what the encoding 962 // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra 963 // high bit. 964 Val &= 255; 965 966 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); 967 } 968 969 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const { 970 return decodeSrcOp(OPW32, Val); 971 } 972 973 MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const { 974 return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255); 975 } 976 977 MCOperand AMDGPUDisassembler::decodeOperand_AReg_64(unsigned Val) const { 978 return createRegOperand(AMDGPU::AReg_64RegClassID, Val & 255); 979 } 980 981 MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const { 982 return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255); 983 } 984 985 MCOperand AMDGPUDisassembler::decodeOperand_AReg_256(unsigned Val) const { 986 return createRegOperand(AMDGPU::AReg_256RegClassID, Val & 255); 987 } 988 989 MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const { 990 return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255); 991 } 992 993 MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const { 994 return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255); 995 } 996 997 MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const { 998 return decodeSrcOp(OPW32, Val); 999 } 1000 1001 MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const { 1002 return decodeSrcOp(OPW64, Val); 1003 } 1004 1005 MCOperand AMDGPUDisassembler::decodeOperand_AV_128(unsigned Val) const { 1006 return decodeSrcOp(OPW128, Val); 1007 } 1008 1009 MCOperand AMDGPUDisassembler::decodeOperand_AVDst_128(unsigned Val) const { 1010 using namespace AMDGPU::EncValues; 1011 assert((Val & IS_VGPR) == 0); // Val{8} is not encoded but assumed to be 1. 1012 return decodeSrcOp(OPW128, Val | IS_VGPR); 1013 } 1014 1015 MCOperand AMDGPUDisassembler::decodeOperand_AVDst_512(unsigned Val) const { 1016 using namespace AMDGPU::EncValues; 1017 assert((Val & IS_VGPR) == 0); // Val{8} is not encoded but assumed to be 1. 1018 return decodeSrcOp(OPW512, Val | IS_VGPR); 1019 } 1020 1021 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { 1022 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); 1023 } 1024 1025 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { 1026 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); 1027 } 1028 1029 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { 1030 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); 1031 } 1032 1033 MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const { 1034 return createRegOperand(AMDGPU::VReg_256RegClassID, Val); 1035 } 1036 1037 MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const { 1038 return createRegOperand(AMDGPU::VReg_512RegClassID, Val); 1039 } 1040 1041 MCOperand AMDGPUDisassembler::decodeOperand_VReg_1024(unsigned Val) const { 1042 return createRegOperand(AMDGPU::VReg_1024RegClassID, Val); 1043 } 1044 1045 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { 1046 // table-gen generated disassembler doesn't care about operand types 1047 // leaving only registry class so SSrc_32 operand turns into SReg_32 1048 // and therefore we accept immediates and literals here as well 1049 return decodeSrcOp(OPW32, Val); 1050 } 1051 1052 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC( 1053 unsigned Val) const { 1054 // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI 1055 return decodeOperand_SReg_32(Val); 1056 } 1057 1058 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI( 1059 unsigned Val) const { 1060 // SReg_32_XM0 is SReg_32 without EXEC_HI 1061 return decodeOperand_SReg_32(Val); 1062 } 1063 1064 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const { 1065 // table-gen generated disassembler doesn't care about operand types 1066 // leaving only registry class so SSrc_32 operand turns into SReg_32 1067 // and therefore we accept immediates and literals here as well 1068 return decodeSrcOp(OPW32, Val); 1069 } 1070 1071 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { 1072 return decodeSrcOp(OPW64, Val); 1073 } 1074 1075 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const { 1076 return decodeSrcOp(OPW64, Val); 1077 } 1078 1079 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { 1080 return decodeSrcOp(OPW128, Val); 1081 } 1082 1083 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { 1084 return decodeDstOp(OPW256, Val); 1085 } 1086 1087 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { 1088 return decodeDstOp(OPW512, Val); 1089 } 1090 1091 // Decode Literals for insts which always have a literal in the encoding 1092 MCOperand 1093 AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const { 1094 if (HasLiteral) { 1095 if (Literal != Val) 1096 return errOperand(Val, "More than one unique literal is illegal"); 1097 } 1098 HasLiteral = true; 1099 Literal = Val; 1100 return MCOperand::createImm(Literal); 1101 } 1102 1103 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { 1104 // For now all literal constants are supposed to be unsigned integer 1105 // ToDo: deal with signed/unsigned 64-bit integer constants 1106 // ToDo: deal with float/double constants 1107 if (!HasLiteral) { 1108 if (Bytes.size() < 4) { 1109 return errOperand(0, "cannot read literal, inst bytes left " + 1110 Twine(Bytes.size())); 1111 } 1112 HasLiteral = true; 1113 Literal = eatBytes<uint32_t>(Bytes); 1114 } 1115 return MCOperand::createImm(Literal); 1116 } 1117 1118 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 1119 using namespace AMDGPU::EncValues; 1120 1121 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 1122 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 1123 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 1124 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 1125 // Cast prevents negative overflow. 1126 } 1127 1128 static int64_t getInlineImmVal32(unsigned Imm) { 1129 switch (Imm) { 1130 case 240: 1131 return FloatToBits(0.5f); 1132 case 241: 1133 return FloatToBits(-0.5f); 1134 case 242: 1135 return FloatToBits(1.0f); 1136 case 243: 1137 return FloatToBits(-1.0f); 1138 case 244: 1139 return FloatToBits(2.0f); 1140 case 245: 1141 return FloatToBits(-2.0f); 1142 case 246: 1143 return FloatToBits(4.0f); 1144 case 247: 1145 return FloatToBits(-4.0f); 1146 case 248: // 1 / (2 * PI) 1147 return 0x3e22f983; 1148 default: 1149 llvm_unreachable("invalid fp inline imm"); 1150 } 1151 } 1152 1153 static int64_t getInlineImmVal64(unsigned Imm) { 1154 switch (Imm) { 1155 case 240: 1156 return DoubleToBits(0.5); 1157 case 241: 1158 return DoubleToBits(-0.5); 1159 case 242: 1160 return DoubleToBits(1.0); 1161 case 243: 1162 return DoubleToBits(-1.0); 1163 case 244: 1164 return DoubleToBits(2.0); 1165 case 245: 1166 return DoubleToBits(-2.0); 1167 case 246: 1168 return DoubleToBits(4.0); 1169 case 247: 1170 return DoubleToBits(-4.0); 1171 case 248: // 1 / (2 * PI) 1172 return 0x3fc45f306dc9c882; 1173 default: 1174 llvm_unreachable("invalid fp inline imm"); 1175 } 1176 } 1177 1178 static int64_t getInlineImmVal16(unsigned Imm) { 1179 switch (Imm) { 1180 case 240: 1181 return 0x3800; 1182 case 241: 1183 return 0xB800; 1184 case 242: 1185 return 0x3C00; 1186 case 243: 1187 return 0xBC00; 1188 case 244: 1189 return 0x4000; 1190 case 245: 1191 return 0xC000; 1192 case 246: 1193 return 0x4400; 1194 case 247: 1195 return 0xC400; 1196 case 248: // 1 / (2 * PI) 1197 return 0x3118; 1198 default: 1199 llvm_unreachable("invalid fp inline imm"); 1200 } 1201 } 1202 1203 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) { 1204 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 1205 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 1206 1207 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 1208 switch (Width) { 1209 case OPW32: 1210 case OPW128: // splat constants 1211 case OPW512: 1212 case OPW1024: 1213 case OPWV232: 1214 return MCOperand::createImm(getInlineImmVal32(Imm)); 1215 case OPW64: 1216 case OPW256: 1217 return MCOperand::createImm(getInlineImmVal64(Imm)); 1218 case OPW16: 1219 case OPWV216: 1220 return MCOperand::createImm(getInlineImmVal16(Imm)); 1221 default: 1222 llvm_unreachable("implement me"); 1223 } 1224 } 1225 1226 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 1227 using namespace AMDGPU; 1228 1229 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1230 switch (Width) { 1231 default: // fall 1232 case OPW32: 1233 case OPW16: 1234 case OPWV216: 1235 return VGPR_32RegClassID; 1236 case OPW64: 1237 case OPWV232: return VReg_64RegClassID; 1238 case OPW96: return VReg_96RegClassID; 1239 case OPW128: return VReg_128RegClassID; 1240 case OPW160: return VReg_160RegClassID; 1241 case OPW256: return VReg_256RegClassID; 1242 case OPW512: return VReg_512RegClassID; 1243 case OPW1024: return VReg_1024RegClassID; 1244 } 1245 } 1246 1247 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 1248 using namespace AMDGPU; 1249 1250 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1251 switch (Width) { 1252 default: // fall 1253 case OPW32: 1254 case OPW16: 1255 case OPWV216: 1256 return AGPR_32RegClassID; 1257 case OPW64: 1258 case OPWV232: return AReg_64RegClassID; 1259 case OPW96: return AReg_96RegClassID; 1260 case OPW128: return AReg_128RegClassID; 1261 case OPW160: return AReg_160RegClassID; 1262 case OPW256: return AReg_256RegClassID; 1263 case OPW512: return AReg_512RegClassID; 1264 case OPW1024: return AReg_1024RegClassID; 1265 } 1266 } 1267 1268 1269 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 1270 using namespace AMDGPU; 1271 1272 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1273 switch (Width) { 1274 default: // fall 1275 case OPW32: 1276 case OPW16: 1277 case OPWV216: 1278 return SGPR_32RegClassID; 1279 case OPW64: 1280 case OPWV232: return SGPR_64RegClassID; 1281 case OPW96: return SGPR_96RegClassID; 1282 case OPW128: return SGPR_128RegClassID; 1283 case OPW160: return SGPR_160RegClassID; 1284 case OPW256: return SGPR_256RegClassID; 1285 case OPW512: return SGPR_512RegClassID; 1286 } 1287 } 1288 1289 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 1290 using namespace AMDGPU; 1291 1292 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1293 switch (Width) { 1294 default: // fall 1295 case OPW32: 1296 case OPW16: 1297 case OPWV216: 1298 return TTMP_32RegClassID; 1299 case OPW64: 1300 case OPWV232: return TTMP_64RegClassID; 1301 case OPW128: return TTMP_128RegClassID; 1302 case OPW256: return TTMP_256RegClassID; 1303 case OPW512: return TTMP_512RegClassID; 1304 } 1305 } 1306 1307 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 1308 using namespace AMDGPU::EncValues; 1309 1310 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN; 1311 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX; 1312 1313 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1314 } 1315 1316 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val, 1317 bool MandatoryLiteral) const { 1318 using namespace AMDGPU::EncValues; 1319 1320 assert(Val < 1024); // enum10 1321 1322 bool IsAGPR = Val & 512; 1323 Val &= 511; 1324 1325 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1326 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1327 : getVgprClassId(Width), Val - VGPR_MIN); 1328 } 1329 if (Val <= SGPR_MAX) { 1330 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1331 static_assert(SGPR_MIN == 0, ""); 1332 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1333 } 1334 1335 int TTmpIdx = getTTmpIdx(Val); 1336 if (TTmpIdx >= 0) { 1337 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1338 } 1339 1340 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1341 return decodeIntImmed(Val); 1342 1343 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1344 return decodeFPImmed(Width, Val); 1345 1346 if (Val == LITERAL_CONST) { 1347 if (MandatoryLiteral) 1348 // Keep a sentinel value for deferred setting 1349 return MCOperand::createImm(LITERAL_CONST); 1350 else 1351 return decodeLiteralConstant(); 1352 } 1353 1354 switch (Width) { 1355 case OPW32: 1356 case OPW16: 1357 case OPWV216: 1358 return decodeSpecialReg32(Val); 1359 case OPW64: 1360 case OPWV232: 1361 return decodeSpecialReg64(Val); 1362 default: 1363 llvm_unreachable("unexpected immediate type"); 1364 } 1365 } 1366 1367 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const { 1368 using namespace AMDGPU::EncValues; 1369 1370 assert(Val < 128); 1371 assert(Width == OPW256 || Width == OPW512); 1372 1373 if (Val <= SGPR_MAX) { 1374 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1375 static_assert(SGPR_MIN == 0, ""); 1376 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1377 } 1378 1379 int TTmpIdx = getTTmpIdx(Val); 1380 if (TTmpIdx >= 0) { 1381 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1382 } 1383 1384 llvm_unreachable("unknown dst register"); 1385 } 1386 1387 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1388 using namespace AMDGPU; 1389 1390 switch (Val) { 1391 case 102: return createRegOperand(FLAT_SCR_LO); 1392 case 103: return createRegOperand(FLAT_SCR_HI); 1393 case 104: return createRegOperand(XNACK_MASK_LO); 1394 case 105: return createRegOperand(XNACK_MASK_HI); 1395 case 106: return createRegOperand(VCC_LO); 1396 case 107: return createRegOperand(VCC_HI); 1397 case 108: return createRegOperand(TBA_LO); 1398 case 109: return createRegOperand(TBA_HI); 1399 case 110: return createRegOperand(TMA_LO); 1400 case 111: return createRegOperand(TMA_HI); 1401 case 124: 1402 return isGFX11Plus() ? createRegOperand(SGPR_NULL) : createRegOperand(M0); 1403 case 125: 1404 return isGFX11Plus() ? createRegOperand(M0) : createRegOperand(SGPR_NULL); 1405 case 126: return createRegOperand(EXEC_LO); 1406 case 127: return createRegOperand(EXEC_HI); 1407 case 235: return createRegOperand(SRC_SHARED_BASE); 1408 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1409 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1410 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1411 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1412 case 251: return createRegOperand(SRC_VCCZ); 1413 case 252: return createRegOperand(SRC_EXECZ); 1414 case 253: return createRegOperand(SRC_SCC); 1415 case 254: return createRegOperand(LDS_DIRECT); 1416 default: break; 1417 } 1418 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1419 } 1420 1421 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1422 using namespace AMDGPU; 1423 1424 switch (Val) { 1425 case 102: return createRegOperand(FLAT_SCR); 1426 case 104: return createRegOperand(XNACK_MASK); 1427 case 106: return createRegOperand(VCC); 1428 case 108: return createRegOperand(TBA); 1429 case 110: return createRegOperand(TMA); 1430 case 124: 1431 if (isGFX11Plus()) 1432 return createRegOperand(SGPR_NULL); 1433 break; 1434 case 125: 1435 if (!isGFX11Plus()) 1436 return createRegOperand(SGPR_NULL); 1437 break; 1438 case 126: return createRegOperand(EXEC); 1439 case 235: return createRegOperand(SRC_SHARED_BASE); 1440 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1441 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1442 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1443 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1444 case 251: return createRegOperand(SRC_VCCZ); 1445 case 252: return createRegOperand(SRC_EXECZ); 1446 case 253: return createRegOperand(SRC_SCC); 1447 default: break; 1448 } 1449 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1450 } 1451 1452 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 1453 const unsigned Val) const { 1454 using namespace AMDGPU::SDWA; 1455 using namespace AMDGPU::EncValues; 1456 1457 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1458 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 1459 // XXX: cast to int is needed to avoid stupid warning: 1460 // compare with unsigned is always true 1461 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1462 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1463 return createRegOperand(getVgprClassId(Width), 1464 Val - SDWA9EncValues::SRC_VGPR_MIN); 1465 } 1466 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1467 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1468 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1469 return createSRegOperand(getSgprClassId(Width), 1470 Val - SDWA9EncValues::SRC_SGPR_MIN); 1471 } 1472 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1473 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1474 return createSRegOperand(getTtmpClassId(Width), 1475 Val - SDWA9EncValues::SRC_TTMP_MIN); 1476 } 1477 1478 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1479 1480 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1481 return decodeIntImmed(SVal); 1482 1483 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1484 return decodeFPImmed(Width, SVal); 1485 1486 return decodeSpecialReg32(SVal); 1487 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 1488 return createRegOperand(getVgprClassId(Width), Val); 1489 } 1490 llvm_unreachable("unsupported target"); 1491 } 1492 1493 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1494 return decodeSDWASrc(OPW16, Val); 1495 } 1496 1497 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1498 return decodeSDWASrc(OPW32, Val); 1499 } 1500 1501 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1502 using namespace AMDGPU::SDWA; 1503 1504 assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1505 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) && 1506 "SDWAVopcDst should be present only on GFX9+"); 1507 1508 bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64]; 1509 1510 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1511 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1512 1513 int TTmpIdx = getTTmpIdx(Val); 1514 if (TTmpIdx >= 0) { 1515 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1516 return createSRegOperand(TTmpClsId, TTmpIdx); 1517 } else if (Val > SGPR_MAX) { 1518 return IsWave64 ? decodeSpecialReg64(Val) 1519 : decodeSpecialReg32(Val); 1520 } else { 1521 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1522 } 1523 } else { 1524 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1525 } 1526 } 1527 1528 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1529 return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ? 1530 decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val); 1531 } 1532 1533 bool AMDGPUDisassembler::isVI() const { 1534 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]; 1535 } 1536 1537 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } 1538 1539 bool AMDGPUDisassembler::isGFX90A() const { 1540 return STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]; 1541 } 1542 1543 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } 1544 1545 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } 1546 1547 bool AMDGPUDisassembler::isGFX10Plus() const { 1548 return AMDGPU::isGFX10Plus(STI); 1549 } 1550 1551 bool AMDGPUDisassembler::isGFX11() const { 1552 return STI.getFeatureBits()[AMDGPU::FeatureGFX11]; 1553 } 1554 1555 bool AMDGPUDisassembler::isGFX11Plus() const { 1556 return AMDGPU::isGFX11Plus(STI); 1557 } 1558 1559 1560 bool AMDGPUDisassembler::hasArchitectedFlatScratch() const { 1561 return STI.getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch]; 1562 } 1563 1564 //===----------------------------------------------------------------------===// 1565 // AMDGPU specific symbol handling 1566 //===----------------------------------------------------------------------===// 1567 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1568 do { \ 1569 KdStream << Indent << DIRECTIVE " " \ 1570 << ((FourByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1571 } while (0) 1572 1573 // NOLINTNEXTLINE(readability-identifier-naming) 1574 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1575 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1576 using namespace amdhsa; 1577 StringRef Indent = "\t"; 1578 1579 // We cannot accurately backward compute #VGPRs used from 1580 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1581 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1582 // simply calculate the inverse of what the assembler does. 1583 1584 uint32_t GranulatedWorkitemVGPRCount = 1585 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT) >> 1586 COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT; 1587 1588 uint32_t NextFreeVGPR = (GranulatedWorkitemVGPRCount + 1) * 1589 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI); 1590 1591 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1592 1593 // We cannot backward compute values used to calculate 1594 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1595 // directives can't be computed: 1596 // .amdhsa_reserve_vcc 1597 // .amdhsa_reserve_flat_scratch 1598 // .amdhsa_reserve_xnack_mask 1599 // They take their respective default values if not specified in the assembly. 1600 // 1601 // GRANULATED_WAVEFRONT_SGPR_COUNT 1602 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1603 // 1604 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1605 // are set to 0. So while disassembling we consider that: 1606 // 1607 // GRANULATED_WAVEFRONT_SGPR_COUNT 1608 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1609 // 1610 // The disassembler cannot recover the original values of those 3 directives. 1611 1612 uint32_t GranulatedWavefrontSGPRCount = 1613 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT) >> 1614 COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT; 1615 1616 if (isGFX10Plus() && GranulatedWavefrontSGPRCount) 1617 return MCDisassembler::Fail; 1618 1619 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1620 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1621 1622 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1623 if (!hasArchitectedFlatScratch()) 1624 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1625 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1626 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1627 1628 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY) 1629 return MCDisassembler::Fail; 1630 1631 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1632 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1633 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1634 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1635 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1636 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1637 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1638 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1639 1640 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) 1641 return MCDisassembler::Fail; 1642 1643 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 1644 1645 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) 1646 return MCDisassembler::Fail; 1647 1648 PRINT_DIRECTIVE(".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 1649 1650 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) 1651 return MCDisassembler::Fail; 1652 1653 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER) 1654 return MCDisassembler::Fail; 1655 1656 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_FP16_OVFL); 1657 1658 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED0) 1659 return MCDisassembler::Fail; 1660 1661 if (isGFX10Plus()) { 1662 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1663 COMPUTE_PGM_RSRC1_WGP_MODE); 1664 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_MEM_ORDERED); 1665 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_FWD_PROGRESS); 1666 } 1667 return MCDisassembler::Success; 1668 } 1669 1670 // NOLINTNEXTLINE(readability-identifier-naming) 1671 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 1672 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1673 using namespace amdhsa; 1674 StringRef Indent = "\t"; 1675 if (hasArchitectedFlatScratch()) 1676 PRINT_DIRECTIVE(".amdhsa_enable_private_segment", 1677 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1678 else 1679 PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset", 1680 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1681 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 1682 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 1683 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 1684 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 1685 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 1686 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 1687 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 1688 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 1689 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 1690 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 1691 1692 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH) 1693 return MCDisassembler::Fail; 1694 1695 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY) 1696 return MCDisassembler::Fail; 1697 1698 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE) 1699 return MCDisassembler::Fail; 1700 1701 PRINT_DIRECTIVE( 1702 ".amdhsa_exception_fp_ieee_invalid_op", 1703 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 1704 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 1705 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 1706 PRINT_DIRECTIVE( 1707 ".amdhsa_exception_fp_ieee_div_zero", 1708 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 1709 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 1710 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 1711 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 1712 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 1713 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 1714 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 1715 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 1716 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 1717 1718 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0) 1719 return MCDisassembler::Fail; 1720 1721 return MCDisassembler::Success; 1722 } 1723 1724 #undef PRINT_DIRECTIVE 1725 1726 MCDisassembler::DecodeStatus 1727 AMDGPUDisassembler::decodeKernelDescriptorDirective( 1728 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 1729 raw_string_ostream &KdStream) const { 1730 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1731 do { \ 1732 KdStream << Indent << DIRECTIVE " " \ 1733 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1734 } while (0) 1735 1736 uint16_t TwoByteBuffer = 0; 1737 uint32_t FourByteBuffer = 0; 1738 1739 StringRef ReservedBytes; 1740 StringRef Indent = "\t"; 1741 1742 assert(Bytes.size() == 64); 1743 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 1744 1745 switch (Cursor.tell()) { 1746 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 1747 FourByteBuffer = DE.getU32(Cursor); 1748 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 1749 << '\n'; 1750 return MCDisassembler::Success; 1751 1752 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 1753 FourByteBuffer = DE.getU32(Cursor); 1754 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 1755 << FourByteBuffer << '\n'; 1756 return MCDisassembler::Success; 1757 1758 case amdhsa::KERNARG_SIZE_OFFSET: 1759 FourByteBuffer = DE.getU32(Cursor); 1760 KdStream << Indent << ".amdhsa_kernarg_size " 1761 << FourByteBuffer << '\n'; 1762 return MCDisassembler::Success; 1763 1764 case amdhsa::RESERVED0_OFFSET: 1765 // 4 reserved bytes, must be 0. 1766 ReservedBytes = DE.getBytes(Cursor, 4); 1767 for (int I = 0; I < 4; ++I) { 1768 if (ReservedBytes[I] != 0) { 1769 return MCDisassembler::Fail; 1770 } 1771 } 1772 return MCDisassembler::Success; 1773 1774 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 1775 // KERNEL_CODE_ENTRY_BYTE_OFFSET 1776 // So far no directive controls this for Code Object V3, so simply skip for 1777 // disassembly. 1778 DE.skip(Cursor, 8); 1779 return MCDisassembler::Success; 1780 1781 case amdhsa::RESERVED1_OFFSET: 1782 // 20 reserved bytes, must be 0. 1783 ReservedBytes = DE.getBytes(Cursor, 20); 1784 for (int I = 0; I < 20; ++I) { 1785 if (ReservedBytes[I] != 0) { 1786 return MCDisassembler::Fail; 1787 } 1788 } 1789 return MCDisassembler::Success; 1790 1791 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 1792 // COMPUTE_PGM_RSRC3 1793 // - Only set for GFX10, GFX6-9 have this to be 0. 1794 // - Currently no directives directly control this. 1795 FourByteBuffer = DE.getU32(Cursor); 1796 if (!isGFX10Plus() && FourByteBuffer) { 1797 return MCDisassembler::Fail; 1798 } 1799 return MCDisassembler::Success; 1800 1801 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 1802 FourByteBuffer = DE.getU32(Cursor); 1803 if (decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream) == 1804 MCDisassembler::Fail) { 1805 return MCDisassembler::Fail; 1806 } 1807 return MCDisassembler::Success; 1808 1809 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 1810 FourByteBuffer = DE.getU32(Cursor); 1811 if (decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream) == 1812 MCDisassembler::Fail) { 1813 return MCDisassembler::Fail; 1814 } 1815 return MCDisassembler::Success; 1816 1817 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 1818 using namespace amdhsa; 1819 TwoByteBuffer = DE.getU16(Cursor); 1820 1821 if (!hasArchitectedFlatScratch()) 1822 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 1823 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 1824 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 1825 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 1826 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 1827 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 1828 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 1829 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 1830 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 1831 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 1832 if (!hasArchitectedFlatScratch()) 1833 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 1834 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 1835 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 1836 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 1837 1838 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 1839 return MCDisassembler::Fail; 1840 1841 // Reserved for GFX9 1842 if (isGFX9() && 1843 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 1844 return MCDisassembler::Fail; 1845 } else if (isGFX10Plus()) { 1846 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 1847 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 1848 } 1849 1850 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) 1851 return MCDisassembler::Fail; 1852 1853 return MCDisassembler::Success; 1854 1855 case amdhsa::RESERVED2_OFFSET: 1856 // 6 bytes from here are reserved, must be 0. 1857 ReservedBytes = DE.getBytes(Cursor, 6); 1858 for (int I = 0; I < 6; ++I) { 1859 if (ReservedBytes[I] != 0) 1860 return MCDisassembler::Fail; 1861 } 1862 return MCDisassembler::Success; 1863 1864 default: 1865 llvm_unreachable("Unhandled index. Case statements cover everything."); 1866 return MCDisassembler::Fail; 1867 } 1868 #undef PRINT_DIRECTIVE 1869 } 1870 1871 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( 1872 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 1873 // CP microcode requires the kernel descriptor to be 64 aligned. 1874 if (Bytes.size() != 64 || KdAddress % 64 != 0) 1875 return MCDisassembler::Fail; 1876 1877 std::string Kd; 1878 raw_string_ostream KdStream(Kd); 1879 KdStream << ".amdhsa_kernel " << KdName << '\n'; 1880 1881 DataExtractor::Cursor C(0); 1882 while (C && C.tell() < Bytes.size()) { 1883 MCDisassembler::DecodeStatus Status = 1884 decodeKernelDescriptorDirective(C, Bytes, KdStream); 1885 1886 cantFail(C.takeError()); 1887 1888 if (Status == MCDisassembler::Fail) 1889 return MCDisassembler::Fail; 1890 } 1891 KdStream << ".end_amdhsa_kernel\n"; 1892 outs() << KdStream.str(); 1893 return MCDisassembler::Success; 1894 } 1895 1896 Optional<MCDisassembler::DecodeStatus> 1897 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 1898 ArrayRef<uint8_t> Bytes, uint64_t Address, 1899 raw_ostream &CStream) const { 1900 // Right now only kernel descriptor needs to be handled. 1901 // We ignore all other symbols for target specific handling. 1902 // TODO: 1903 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 1904 // Object V2 and V3 when symbols are marked protected. 1905 1906 // amd_kernel_code_t for Code Object V2. 1907 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 1908 Size = 256; 1909 return MCDisassembler::Fail; 1910 } 1911 1912 // Code Object V3 kernel descriptors. 1913 StringRef Name = Symbol.Name; 1914 if (Symbol.Type == ELF::STT_OBJECT && Name.endswith(StringRef(".kd"))) { 1915 Size = 64; // Size = 64 regardless of success or failure. 1916 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 1917 } 1918 return None; 1919 } 1920 1921 //===----------------------------------------------------------------------===// 1922 // AMDGPUSymbolizer 1923 //===----------------------------------------------------------------------===// 1924 1925 // Try to find symbol name for specified label 1926 bool AMDGPUSymbolizer::tryAddingSymbolicOperand( 1927 MCInst &Inst, raw_ostream & /*cStream*/, int64_t Value, 1928 uint64_t /*Address*/, bool IsBranch, uint64_t /*Offset*/, 1929 uint64_t /*OpSize*/, uint64_t /*InstSize*/) { 1930 1931 if (!IsBranch) { 1932 return false; 1933 } 1934 1935 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 1936 if (!Symbols) 1937 return false; 1938 1939 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { 1940 return Val.Addr == static_cast<uint64_t>(Value) && 1941 Val.Type == ELF::STT_NOTYPE; 1942 }); 1943 if (Result != Symbols->end()) { 1944 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 1945 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 1946 Inst.addOperand(MCOperand::createExpr(Add)); 1947 return true; 1948 } 1949 // Add to list of referenced addresses, so caller can synthesize a label. 1950 ReferencedAddresses.push_back(static_cast<uint64_t>(Value)); 1951 return false; 1952 } 1953 1954 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 1955 int64_t Value, 1956 uint64_t Address) { 1957 llvm_unreachable("unimplemented"); 1958 } 1959 1960 //===----------------------------------------------------------------------===// 1961 // Initialization 1962 //===----------------------------------------------------------------------===// 1963 1964 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 1965 LLVMOpInfoCallback /*GetOpInfo*/, 1966 LLVMSymbolLookupCallback /*SymbolLookUp*/, 1967 void *DisInfo, 1968 MCContext *Ctx, 1969 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 1970 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 1971 } 1972 1973 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 1974 const MCSubtargetInfo &STI, 1975 MCContext &Ctx) { 1976 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 1977 } 1978 1979 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 1980 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 1981 createAMDGPUDisassembler); 1982 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 1983 createAMDGPUSymbolizer); 1984 } 1985