1 //===-- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 //===----------------------------------------------------------------------===// 11 // 12 /// \file 13 /// 14 /// This file contains definition for AMDGPU ISA disassembler 15 // 16 //===----------------------------------------------------------------------===// 17 18 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 19 20 #include "AMDGPUDisassembler.h" 21 #include "AMDGPU.h" 22 #include "AMDGPURegisterInfo.h" 23 #include "Utils/AMDGPUBaseInfo.h" 24 25 #include "llvm/MC/MCContext.h" 26 #include "llvm/MC/MCFixedLenDisassembler.h" 27 #include "llvm/MC/MCInst.h" 28 #include "llvm/MC/MCInstrDesc.h" 29 #include "llvm/MC/MCSubtargetInfo.h" 30 #include "llvm/Support/Endian.h" 31 #include "llvm/Support/Debug.h" 32 #include "llvm/Support/TargetRegistry.h" 33 34 35 using namespace llvm; 36 37 #define DEBUG_TYPE "amdgpu-disassembler" 38 39 typedef llvm::MCDisassembler::DecodeStatus DecodeStatus; 40 41 42 inline static MCDisassembler::DecodeStatus 43 addOperand(MCInst &Inst, const MCOperand& Opnd) { 44 Inst.addOperand(Opnd); 45 return Opnd.isValid() ? 46 MCDisassembler::Success : 47 MCDisassembler::SoftFail; 48 } 49 50 #define DECODE_OPERAND2(RegClass, DecName) \ 51 static DecodeStatus Decode##RegClass##RegisterClass(MCInst &Inst, \ 52 unsigned Imm, \ 53 uint64_t /*Addr*/, \ 54 const void *Decoder) { \ 55 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \ 56 return addOperand(Inst, DAsm->decodeOperand_##DecName(Imm)); \ 57 } 58 59 #define DECODE_OPERAND(RegClass) DECODE_OPERAND2(RegClass, RegClass) 60 61 DECODE_OPERAND(VGPR_32) 62 DECODE_OPERAND(VS_32) 63 DECODE_OPERAND(VS_64) 64 65 DECODE_OPERAND(VReg_64) 66 DECODE_OPERAND(VReg_96) 67 DECODE_OPERAND(VReg_128) 68 69 DECODE_OPERAND(SReg_32) 70 DECODE_OPERAND(SReg_64) 71 DECODE_OPERAND(SReg_128) 72 DECODE_OPERAND(SReg_256) 73 74 #define GET_SUBTARGETINFO_ENUM 75 #include "AMDGPUGenSubtargetInfo.inc" 76 #undef GET_SUBTARGETINFO_ENUM 77 78 #include "AMDGPUGenDisassemblerTables.inc" 79 80 //===----------------------------------------------------------------------===// 81 // 82 //===----------------------------------------------------------------------===// 83 84 static inline uint32_t eatB32(ArrayRef<uint8_t>& Bytes) { 85 assert(Bytes.size() >= sizeof eatB32(Bytes)); 86 const auto Res = support::endian::read32le(Bytes.data()); 87 Bytes = Bytes.slice(sizeof Res); 88 return Res; 89 } 90 91 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table, 92 MCInst &MI, 93 uint64_t Inst, 94 uint64_t Address) const { 95 assert(MI.getOpcode() == 0); 96 assert(MI.getNumOperands() == 0); 97 MCInst TmpInst; 98 const auto SavedBytes = Bytes; 99 if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) { 100 MI = TmpInst; 101 return MCDisassembler::Success; 102 } 103 Bytes = SavedBytes; 104 return MCDisassembler::Fail; 105 } 106 107 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 108 ArrayRef<uint8_t> Bytes_, 109 uint64_t Address, 110 raw_ostream &WS, 111 raw_ostream &CS) const { 112 CommentStream = &CS; 113 114 // ToDo: AMDGPUDisassembler supports only VI ISA. 115 assert(AMDGPU::isVI(STI) && "Can disassemble only VI ISA."); 116 117 const unsigned MaxInstBytesNum = (std::min)((size_t)8, Bytes_.size()); 118 Bytes = Bytes_.slice(0, MaxInstBytesNum); 119 120 DecodeStatus Res = MCDisassembler::Fail; 121 do { 122 // ToDo: better to switch enc len using some bit predicate 123 // but it is unknown yet, so try all we can 124 if (Bytes.size() < 4) break; 125 const uint32_t DW = eatB32(Bytes); 126 Res = tryDecodeInst(DecoderTableVI32, MI, DW, Address); 127 if (Res) break; 128 129 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address); 130 if (Res) break; 131 132 if (Bytes.size() < 4) break; 133 const uint64_t QW = ((uint64_t)eatB32(Bytes) << 32) | DW; 134 Res = tryDecodeInst(DecoderTableVI64, MI, QW, Address); 135 if (Res) break; 136 137 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address); 138 } while (false); 139 140 Size = Res ? (MaxInstBytesNum - Bytes.size()) : 0; 141 return Res; 142 } 143 144 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 145 return getContext().getRegisterInfo()-> 146 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 147 } 148 149 inline 150 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 151 const Twine& ErrMsg) const { 152 *CommentStream << "Error: " + ErrMsg; 153 154 // ToDo: add support for error operands to MCInst.h 155 // return MCOperand::createError(V); 156 return MCOperand(); 157 } 158 159 inline 160 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 161 return MCOperand::createReg(RegId); 162 } 163 164 inline 165 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 166 unsigned Val) const { 167 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 168 if (Val >= RegCl.getNumRegs()) 169 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 170 ": unknown register " + Twine(Val)); 171 return createRegOperand(RegCl.getRegister(Val)); 172 } 173 174 inline 175 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 176 unsigned Val) const { 177 // ToDo: SI/CI have 104 SGPRs, VI - 102 178 // Valery: here we accepting as much as we can, let assembler sort it out 179 int shift = 0; 180 switch (SRegClassID) { 181 case AMDGPU::SGPR_32RegClassID: 182 case AMDGPU::SReg_32RegClassID: break; 183 case AMDGPU::SGPR_64RegClassID: 184 case AMDGPU::SReg_64RegClassID: shift = 1; break; 185 case AMDGPU::SReg_128RegClassID: 186 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 187 // this bundle? 188 case AMDGPU::SReg_256RegClassID: 189 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 190 // this bundle? 191 case AMDGPU::SReg_512RegClassID: shift = 2; break; 192 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 193 // this bundle? 194 default: assert(false); break; 195 } 196 if (Val % (1 << shift)) 197 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 198 << ": scalar reg isn't aligned " << Val; 199 return createRegOperand(SRegClassID, Val >> shift); 200 } 201 202 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { 203 return decodeSrcOp(OP32, Val); 204 } 205 206 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { 207 return decodeSrcOp(OP64, Val); 208 } 209 210 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { 211 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); 212 } 213 214 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { 215 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); 216 } 217 218 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { 219 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); 220 } 221 222 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { 223 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); 224 } 225 226 MCOperand AMDGPUDisassembler::decodeOperand_SGPR_32(unsigned Val) const { 227 return createSRegOperand(AMDGPU::SGPR_32RegClassID, Val); 228 } 229 230 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { 231 // table-gen generated disassembler doesn't care about operand types 232 // leaving only registry class so SSrc_32 operand turns into SReg_32 233 // and therefore we accept immediates and literals here as well 234 return decodeSrcOp(OP32, Val); 235 } 236 237 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { 238 // see decodeOperand_SReg_32 comment 239 return decodeSrcOp(OP64, Val); 240 } 241 242 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { 243 return createSRegOperand(AMDGPU::SReg_128RegClassID, Val); 244 } 245 246 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { 247 return createSRegOperand(AMDGPU::SReg_256RegClassID, Val); 248 } 249 250 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { 251 return createSRegOperand(AMDGPU::SReg_512RegClassID, Val); 252 } 253 254 255 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { 256 // For now all literal constants are supposed to be unsigned integer 257 // ToDo: deal with signed/unsigned 64-bit integer constants 258 // ToDo: deal with float/double constants 259 if (Bytes.size() < 4) 260 return errOperand(0, "cannot read literal, inst bytes left " + 261 Twine(Bytes.size())); 262 return MCOperand::createImm(eatB32(Bytes)); 263 } 264 265 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 266 assert(Imm >= 128 && Imm <= 208); 267 return MCOperand::createImm((Imm <= 192) ? (Imm - 128) : (192 - Imm)); 268 } 269 270 MCOperand AMDGPUDisassembler::decodeFPImmed(bool Is32, unsigned Imm) { 271 assert(Imm >= 240 && Imm <= 248); 272 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 273 // ToDo: AMDGPUInstPrinter does not support 1/(2*PI). It consider 1/(2*PI) as 274 // literal constant. 275 float V = 0.0f; 276 switch (Imm) { 277 case 240: V = 0.5f; break; 278 case 241: V = -0.5f; break; 279 case 242: V = 1.0f; break; 280 case 243: V = -1.0f; break; 281 case 244: V = 2.0f; break; 282 case 245: V = -2.0f; break; 283 case 246: V = 4.0f; break; 284 case 247: V = -4.0f; break; 285 case 248: return MCOperand::createImm(Is32 ? // 1/(2*PI) 286 0x3e22f983 : 287 0x3fc45f306dc9c882); 288 default: break; 289 } 290 return MCOperand::createImm(Is32? FloatToBits(V) : DoubleToBits(V)); 291 } 292 293 MCOperand AMDGPUDisassembler::decodeSrcOp(bool Is32, unsigned Val) const { 294 using namespace AMDGPU; 295 assert(Val < 512); // enum9 296 297 if (Val >= 256) 298 return createRegOperand(Is32 ? VGPR_32RegClassID : VReg_64RegClassID, 299 Val - 256); 300 if (Val <= 101) 301 return createSRegOperand(Is32 ? SGPR_32RegClassID : SGPR_64RegClassID, 302 Val); 303 304 if (Val >= 128 && Val <= 208) 305 return decodeIntImmed(Val); 306 307 if (Val >= 240 && Val <= 248) 308 return decodeFPImmed(Is32, Val); 309 310 if (Val == 255) 311 return decodeLiteralConstant(); 312 313 return Is32 ? decodeSpecialReg32(Val) : decodeSpecialReg64(Val); 314 } 315 316 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 317 using namespace AMDGPU; 318 switch (Val) { 319 case 102: return createRegOperand(getMCReg(FLAT_SCR_LO, STI)); 320 case 103: return createRegOperand(getMCReg(FLAT_SCR_HI, STI)); 321 // ToDo: no support for xnack_mask_lo/_hi register 322 case 104: 323 case 105: break; 324 case 106: return createRegOperand(VCC_LO); 325 case 107: return createRegOperand(VCC_HI); 326 // ToDo: no support for tba_lo/_hi register 327 case 108: 328 case 109: break; 329 // ToDo: no support for tma_lo/_hi register 330 case 110: 331 case 111: break; 332 // ToDo: no support for ttmp[0:11] register 333 case 112: 334 case 113: 335 case 114: 336 case 115: 337 case 116: 338 case 117: 339 case 118: 340 case 119: 341 case 120: 342 case 121: 343 case 122: 344 case 123: break; 345 case 124: return createRegOperand(M0); 346 case 126: return createRegOperand(EXEC_LO); 347 case 127: return createRegOperand(EXEC_HI); 348 // ToDo: no support for vccz register 349 case 251: break; 350 // ToDo: no support for execz register 351 case 252: break; 352 case 253: return createRegOperand(SCC); 353 default: break; 354 } 355 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 356 } 357 358 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 359 using namespace AMDGPU; 360 switch (Val) { 361 case 102: return createRegOperand(getMCReg(FLAT_SCR, STI)); 362 case 106: return createRegOperand(VCC); 363 case 126: return createRegOperand(EXEC); 364 default: break; 365 } 366 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 367 } 368 369 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 370 const MCSubtargetInfo &STI, 371 MCContext &Ctx) { 372 return new AMDGPUDisassembler(STI, Ctx); 373 } 374 375 extern "C" void LLVMInitializeAMDGPUDisassembler() { 376 TargetRegistry::RegisterMCDisassembler(TheGCNTarget, createAMDGPUDisassembler); 377 } 378