1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "SIDefines.h" 22 #include "SIRegisterInfo.h" 23 #include "TargetInfo/AMDGPUTargetInfo.h" 24 #include "Utils/AMDGPUBaseInfo.h" 25 #include "llvm-c/DisassemblerTypes.h" 26 #include "llvm/BinaryFormat/ELF.h" 27 #include "llvm/MC/MCAsmInfo.h" 28 #include "llvm/MC/MCContext.h" 29 #include "llvm/MC/MCDecoderOps.h" 30 #include "llvm/MC/MCExpr.h" 31 #include "llvm/MC/MCInstrDesc.h" 32 #include "llvm/MC/MCRegisterInfo.h" 33 #include "llvm/MC/MCSubtargetInfo.h" 34 #include "llvm/MC/TargetRegistry.h" 35 #include "llvm/Support/AMDHSAKernelDescriptor.h" 36 37 using namespace llvm; 38 39 #define DEBUG_TYPE "amdgpu-disassembler" 40 41 #define SGPR_MAX \ 42 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 43 : AMDGPU::EncValues::SGPR_MAX_SI) 44 45 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 46 47 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 48 MCContext &Ctx, MCInstrInfo const *MCII) 49 : MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), 50 MAI(*Ctx.getAsmInfo()), TargetMaxInstBytes(MAI.getMaxInstLength(&STI)), 51 CodeObjectVersion(AMDGPU::getDefaultAMDHSACodeObjectVersion()) { 52 // ToDo: AMDGPUDisassembler supports only VI ISA. 53 if (!STI.hasFeature(AMDGPU::FeatureGCN3Encoding) && !isGFX10Plus()) 54 report_fatal_error("Disassembly not yet supported for subtarget"); 55 } 56 57 void AMDGPUDisassembler::setABIVersion(unsigned Version) { 58 CodeObjectVersion = AMDGPU::getAMDHSACodeObjectVersion(Version); 59 } 60 61 inline static MCDisassembler::DecodeStatus 62 addOperand(MCInst &Inst, const MCOperand& Opnd) { 63 Inst.addOperand(Opnd); 64 return Opnd.isValid() ? 65 MCDisassembler::Success : 66 MCDisassembler::Fail; 67 } 68 69 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 70 uint16_t NameIdx) { 71 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 72 if (OpIdx != -1) { 73 auto I = MI.begin(); 74 std::advance(I, OpIdx); 75 MI.insert(I, Op); 76 } 77 return OpIdx; 78 } 79 80 static DecodeStatus decodeSOPPBrTarget(MCInst &Inst, unsigned Imm, 81 uint64_t Addr, 82 const MCDisassembler *Decoder) { 83 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 84 85 // Our branches take a simm16, but we need two extra bits to account for the 86 // factor of 4. 87 APInt SignedOffset(18, Imm * 4, true); 88 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 89 90 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2, 0)) 91 return MCDisassembler::Success; 92 return addOperand(Inst, MCOperand::createImm(Imm)); 93 } 94 95 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, 96 const MCDisassembler *Decoder) { 97 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 98 int64_t Offset; 99 if (DAsm->isGFX12Plus()) { // GFX12 supports 24-bit signed offsets. 100 Offset = SignExtend64<24>(Imm); 101 } else if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 102 Offset = Imm & 0xFFFFF; 103 } else { // GFX9+ supports 21-bit signed offsets. 104 Offset = SignExtend64<21>(Imm); 105 } 106 return addOperand(Inst, MCOperand::createImm(Offset)); 107 } 108 109 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, 110 const MCDisassembler *Decoder) { 111 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 112 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 113 } 114 115 static DecodeStatus decodeSplitBarrier(MCInst &Inst, unsigned Val, 116 uint64_t Addr, 117 const MCDisassembler *Decoder) { 118 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 119 return addOperand(Inst, DAsm->decodeSplitBarrier(Val)); 120 } 121 122 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 123 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \ 124 uint64_t /*Addr*/, \ 125 const MCDisassembler *Decoder) { \ 126 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 127 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 128 } 129 130 // Decoder for registers, decode directly using RegClassID. Imm(8-bit) is 131 // number of register. Used by VGPR only and AGPR only operands. 132 #define DECODE_OPERAND_REG_8(RegClass) \ 133 static DecodeStatus Decode##RegClass##RegisterClass( \ 134 MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \ 135 const MCDisassembler *Decoder) { \ 136 assert(Imm < (1 << 8) && "8-bit encoding"); \ 137 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 138 return addOperand( \ 139 Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm)); \ 140 } 141 142 #define DECODE_SrcOp(Name, EncSize, OpWidth, EncImm, MandatoryLiteral, \ 143 ImmWidth) \ 144 static DecodeStatus Name(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \ 145 const MCDisassembler *Decoder) { \ 146 assert(Imm < (1 << EncSize) && #EncSize "-bit encoding"); \ 147 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 148 return addOperand(Inst, \ 149 DAsm->decodeSrcOp(AMDGPUDisassembler::OpWidth, EncImm, \ 150 MandatoryLiteral, ImmWidth)); \ 151 } 152 153 static DecodeStatus decodeSrcOp(MCInst &Inst, unsigned EncSize, 154 AMDGPUDisassembler::OpWidthTy OpWidth, 155 unsigned Imm, unsigned EncImm, 156 bool MandatoryLiteral, unsigned ImmWidth, 157 const MCDisassembler *Decoder) { 158 assert(Imm < (1U << EncSize) && "Operand doesn't fit encoding!"); 159 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 160 return addOperand( 161 Inst, DAsm->decodeSrcOp(OpWidth, EncImm, MandatoryLiteral, ImmWidth)); 162 } 163 164 // Decoder for registers. Imm(7-bit) is number of register, uses decodeSrcOp to 165 // get register class. Used by SGPR only operands. 166 #define DECODE_OPERAND_REG_7(RegClass, OpWidth) \ 167 DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0) 168 169 // Decoder for registers. Imm(10-bit): Imm{7-0} is number of register, 170 // Imm{9} is acc(agpr or vgpr) Imm{8} should be 0 (see VOP3Pe_SMFMAC). 171 // Set Imm{8} to 1 (IS_VGPR) to decode using 'enum10' from decodeSrcOp. 172 // Used by AV_ register classes (AGPR or VGPR only register operands). 173 template <AMDGPUDisassembler::OpWidthTy OpWidth> 174 static DecodeStatus decodeAV10(MCInst &Inst, unsigned Imm, uint64_t /* Addr */, 175 const MCDisassembler *Decoder) { 176 return decodeSrcOp(Inst, 10, OpWidth, Imm, Imm | AMDGPU::EncValues::IS_VGPR, 177 false, 0, Decoder); 178 } 179 180 // Decoder for Src(9-bit encoding) registers only. 181 template <AMDGPUDisassembler::OpWidthTy OpWidth> 182 static DecodeStatus decodeSrcReg9(MCInst &Inst, unsigned Imm, 183 uint64_t /* Addr */, 184 const MCDisassembler *Decoder) { 185 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, false, 0, Decoder); 186 } 187 188 // Decoder for Src(9-bit encoding) AGPR, register number encoded in 9bits, set 189 // Imm{9} to 1 (set acc) and decode using 'enum10' from decodeSrcOp, registers 190 // only. 191 template <AMDGPUDisassembler::OpWidthTy OpWidth> 192 static DecodeStatus decodeSrcA9(MCInst &Inst, unsigned Imm, uint64_t /* Addr */, 193 const MCDisassembler *Decoder) { 194 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm | 512, false, 0, Decoder); 195 } 196 197 // Decoder for 'enum10' from decodeSrcOp, Imm{0-8} is 9-bit Src encoding 198 // Imm{9} is acc, registers only. 199 template <AMDGPUDisassembler::OpWidthTy OpWidth> 200 static DecodeStatus decodeSrcAV10(MCInst &Inst, unsigned Imm, 201 uint64_t /* Addr */, 202 const MCDisassembler *Decoder) { 203 return decodeSrcOp(Inst, 10, OpWidth, Imm, Imm, false, 0, Decoder); 204 } 205 206 // Decoder for RegisterOperands using 9-bit Src encoding. Operand can be 207 // register from RegClass or immediate. Registers that don't belong to RegClass 208 // will be decoded and InstPrinter will report warning. Immediate will be 209 // decoded into constant of size ImmWidth, should match width of immediate used 210 // by OperandType (important for floating point types). 211 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth> 212 static DecodeStatus decodeSrcRegOrImm9(MCInst &Inst, unsigned Imm, 213 uint64_t /* Addr */, 214 const MCDisassembler *Decoder) { 215 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, false, ImmWidth, Decoder); 216 } 217 218 // Decoder for Src(9-bit encoding) AGPR or immediate. Set Imm{9} to 1 (set acc) 219 // and decode using 'enum10' from decodeSrcOp. 220 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth> 221 static DecodeStatus decodeSrcRegOrImmA9(MCInst &Inst, unsigned Imm, 222 uint64_t /* Addr */, 223 const MCDisassembler *Decoder) { 224 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm | 512, false, ImmWidth, 225 Decoder); 226 } 227 228 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth> 229 static DecodeStatus decodeSrcRegOrImmDeferred9(MCInst &Inst, unsigned Imm, 230 uint64_t /* Addr */, 231 const MCDisassembler *Decoder) { 232 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, true, ImmWidth, Decoder); 233 } 234 235 // Default decoders generated by tablegen: 'Decode<RegClass>RegisterClass' 236 // when RegisterClass is used as an operand. Most often used for destination 237 // operands. 238 239 DECODE_OPERAND_REG_8(VGPR_32) 240 DECODE_OPERAND_REG_8(VGPR_32_Lo128) 241 DECODE_OPERAND_REG_8(VReg_64) 242 DECODE_OPERAND_REG_8(VReg_96) 243 DECODE_OPERAND_REG_8(VReg_128) 244 DECODE_OPERAND_REG_8(VReg_256) 245 DECODE_OPERAND_REG_8(VReg_288) 246 DECODE_OPERAND_REG_8(VReg_352) 247 DECODE_OPERAND_REG_8(VReg_384) 248 DECODE_OPERAND_REG_8(VReg_512) 249 DECODE_OPERAND_REG_8(VReg_1024) 250 251 DECODE_OPERAND_REG_7(SReg_32, OPW32) 252 DECODE_OPERAND_REG_7(SReg_32_XEXEC, OPW32) 253 DECODE_OPERAND_REG_7(SReg_32_XM0_XEXEC, OPW32) 254 DECODE_OPERAND_REG_7(SReg_32_XEXEC_HI, OPW32) 255 DECODE_OPERAND_REG_7(SReg_64, OPW64) 256 DECODE_OPERAND_REG_7(SReg_64_XEXEC, OPW64) 257 DECODE_OPERAND_REG_7(SReg_96, OPW96) 258 DECODE_OPERAND_REG_7(SReg_128, OPW128) 259 DECODE_OPERAND_REG_7(SReg_256, OPW256) 260 DECODE_OPERAND_REG_7(SReg_512, OPW512) 261 262 DECODE_OPERAND_REG_8(AGPR_32) 263 DECODE_OPERAND_REG_8(AReg_64) 264 DECODE_OPERAND_REG_8(AReg_128) 265 DECODE_OPERAND_REG_8(AReg_256) 266 DECODE_OPERAND_REG_8(AReg_512) 267 DECODE_OPERAND_REG_8(AReg_1024) 268 269 static DecodeStatus DecodeVGPR_16RegisterClass(MCInst &Inst, unsigned Imm, 270 uint64_t /*Addr*/, 271 const MCDisassembler *Decoder) { 272 assert(isUInt<10>(Imm) && "10-bit encoding expected"); 273 assert((Imm & (1 << 8)) == 0 && "Imm{8} should not be used"); 274 275 bool IsHi = Imm & (1 << 9); 276 unsigned RegIdx = Imm & 0xff; 277 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 278 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 279 } 280 281 static DecodeStatus 282 DecodeVGPR_16_Lo128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, 283 const MCDisassembler *Decoder) { 284 assert(isUInt<8>(Imm) && "8-bit encoding expected"); 285 286 bool IsHi = Imm & (1 << 7); 287 unsigned RegIdx = Imm & 0x7f; 288 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 289 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 290 } 291 292 static DecodeStatus decodeOperand_VSrcT16_Lo128(MCInst &Inst, unsigned Imm, 293 uint64_t /*Addr*/, 294 const MCDisassembler *Decoder) { 295 assert(isUInt<9>(Imm) && "9-bit encoding expected"); 296 297 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 298 bool IsVGPR = Imm & (1 << 8); 299 if (IsVGPR) { 300 bool IsHi = Imm & (1 << 7); 301 unsigned RegIdx = Imm & 0x7f; 302 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 303 } 304 return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(AMDGPUDisassembler::OPW16, 305 Imm & 0xFF, false, 16)); 306 } 307 308 static DecodeStatus decodeOperand_VSrcT16(MCInst &Inst, unsigned Imm, 309 uint64_t /*Addr*/, 310 const MCDisassembler *Decoder) { 311 assert(isUInt<10>(Imm) && "10-bit encoding expected"); 312 313 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 314 bool IsVGPR = Imm & (1 << 8); 315 if (IsVGPR) { 316 bool IsHi = Imm & (1 << 9); 317 unsigned RegIdx = Imm & 0xff; 318 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 319 } 320 return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(AMDGPUDisassembler::OPW16, 321 Imm & 0xFF, false, 16)); 322 } 323 324 static DecodeStatus decodeOperand_KImmFP(MCInst &Inst, unsigned Imm, 325 uint64_t Addr, 326 const MCDisassembler *Decoder) { 327 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 328 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 329 } 330 331 static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val, 332 uint64_t Addr, const void *Decoder) { 333 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 334 return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val)); 335 } 336 337 static bool IsAGPROperand(const MCInst &Inst, int OpIdx, 338 const MCRegisterInfo *MRI) { 339 if (OpIdx < 0) 340 return false; 341 342 const MCOperand &Op = Inst.getOperand(OpIdx); 343 if (!Op.isReg()) 344 return false; 345 346 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); 347 auto Reg = Sub ? Sub : Op.getReg(); 348 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; 349 } 350 351 static DecodeStatus decodeAVLdSt(MCInst &Inst, unsigned Imm, 352 AMDGPUDisassembler::OpWidthTy Opw, 353 const MCDisassembler *Decoder) { 354 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 355 if (!DAsm->isGFX90A()) { 356 Imm &= 511; 357 } else { 358 // If atomic has both vdata and vdst their register classes are tied. 359 // The bit is decoded along with the vdst, first operand. We need to 360 // change register class to AGPR if vdst was AGPR. 361 // If a DS instruction has both data0 and data1 their register classes 362 // are also tied. 363 unsigned Opc = Inst.getOpcode(); 364 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; 365 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 366 : AMDGPU::OpName::vdata; 367 const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo(); 368 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); 369 if ((int)Inst.getNumOperands() == DataIdx) { 370 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); 371 if (IsAGPROperand(Inst, DstIdx, MRI)) 372 Imm |= 512; 373 } 374 375 if (TSFlags & SIInstrFlags::DS) { 376 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); 377 if ((int)Inst.getNumOperands() == Data2Idx && 378 IsAGPROperand(Inst, DataIdx, MRI)) 379 Imm |= 512; 380 } 381 } 382 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); 383 } 384 385 template <AMDGPUDisassembler::OpWidthTy Opw> 386 static DecodeStatus decodeAVLdSt(MCInst &Inst, unsigned Imm, 387 uint64_t /* Addr */, 388 const MCDisassembler *Decoder) { 389 return decodeAVLdSt(Inst, Imm, Opw, Decoder); 390 } 391 392 static DecodeStatus decodeOperand_VSrc_f64(MCInst &Inst, unsigned Imm, 393 uint64_t Addr, 394 const MCDisassembler *Decoder) { 395 assert(Imm < (1 << 9) && "9-bit encoding"); 396 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 397 return addOperand( 398 Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm, false, 64, true)); 399 } 400 401 #define DECODE_SDWA(DecName) \ 402 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 403 404 DECODE_SDWA(Src32) 405 DECODE_SDWA(Src16) 406 DECODE_SDWA(VopcDst) 407 408 #include "AMDGPUGenDisassemblerTables.inc" 409 410 //===----------------------------------------------------------------------===// 411 // 412 //===----------------------------------------------------------------------===// 413 414 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 415 assert(Bytes.size() >= sizeof(T)); 416 const auto Res = 417 support::endian::read<T, llvm::endianness::little>(Bytes.data()); 418 Bytes = Bytes.slice(sizeof(T)); 419 return Res; 420 } 421 422 static inline DecoderUInt128 eat12Bytes(ArrayRef<uint8_t> &Bytes) { 423 assert(Bytes.size() >= 12); 424 uint64_t Lo = 425 support::endian::read<uint64_t, llvm::endianness::little>(Bytes.data()); 426 Bytes = Bytes.slice(8); 427 uint64_t Hi = 428 support::endian::read<uint32_t, llvm::endianness::little>(Bytes.data()); 429 Bytes = Bytes.slice(4); 430 return DecoderUInt128(Lo, Hi); 431 } 432 433 // The disassembler is greedy, so we need to check FI operand value to 434 // not parse a dpp if the correct literal is not set. For dpp16 the 435 // autogenerated decoder checks the dpp literal 436 static bool isValidDPP8(const MCInst &MI) { 437 using namespace llvm::AMDGPU::DPP; 438 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi); 439 assert(FiIdx != -1); 440 if ((unsigned)FiIdx >= MI.getNumOperands()) 441 return false; 442 unsigned Fi = MI.getOperand(FiIdx).getImm(); 443 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1; 444 } 445 446 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 447 ArrayRef<uint8_t> Bytes_, 448 uint64_t Address, 449 raw_ostream &CS) const { 450 bool IsSDWA = false; 451 452 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 453 Bytes = Bytes_.slice(0, MaxInstBytesNum); 454 455 DecodeStatus Res = MCDisassembler::Fail; 456 do { 457 // ToDo: better to switch encoding length using some bit predicate 458 // but it is unknown yet, so try all we can 459 460 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 461 // encodings 462 if (isGFX11Plus() && Bytes.size() >= 12 ) { 463 DecoderUInt128 DecW = eat12Bytes(Bytes); 464 Res = 465 tryDecodeInst(DecoderTableDPP8GFX1196, DecoderTableDPP8GFX11_FAKE1696, 466 MI, DecW, Address, CS); 467 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 468 break; 469 MI = MCInst(); // clear 470 Res = 471 tryDecodeInst(DecoderTableDPP8GFX1296, DecoderTableDPP8GFX12_FAKE1696, 472 MI, DecW, Address, CS); 473 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 474 break; 475 MI = MCInst(); // clear 476 477 const auto convertVOPDPP = [&]() { 478 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3P) { 479 convertVOP3PDPPInst(MI); 480 } else if (AMDGPU::isVOPC64DPP(MI.getOpcode())) { 481 convertVOPCDPPInst(MI); // Special VOP3 case 482 } else { 483 assert(MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3); 484 convertVOP3DPPInst(MI); // Regular VOP3 case 485 } 486 }; 487 Res = tryDecodeInst(DecoderTableDPPGFX1196, DecoderTableDPPGFX11_FAKE1696, 488 MI, DecW, Address, CS); 489 if (Res) { 490 convertVOPDPP(); 491 break; 492 } 493 Res = tryDecodeInst(DecoderTableDPPGFX1296, DecoderTableDPPGFX12_FAKE1696, 494 MI, DecW, Address, CS); 495 if (Res) { 496 convertVOPDPP(); 497 break; 498 } 499 Res = tryDecodeInst(DecoderTableGFX1196, MI, DecW, Address, CS); 500 if (Res) 501 break; 502 503 Res = tryDecodeInst(DecoderTableGFX1296, MI, DecW, Address, CS); 504 if (Res) 505 break; 506 507 Res = tryDecodeInst(DecoderTableGFX12W6496, MI, DecW, Address, CS); 508 if (Res) 509 break; 510 } 511 // Reinitialize Bytes 512 Bytes = Bytes_.slice(0, MaxInstBytesNum); 513 514 if (Bytes.size() >= 8) { 515 const uint64_t QW = eatBytes<uint64_t>(Bytes); 516 517 if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding)) { 518 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address, CS); 519 if (Res) { 520 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) 521 == -1) 522 break; 523 if (convertDPP8Inst(MI) == MCDisassembler::Success) 524 break; 525 MI = MCInst(); // clear 526 } 527 } 528 529 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address, CS); 530 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 531 break; 532 MI = MCInst(); // clear 533 534 Res = tryDecodeInst(DecoderTableDPP8GFX1164, 535 DecoderTableDPP8GFX11_FAKE1664, MI, QW, Address, CS); 536 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 537 break; 538 MI = MCInst(); // clear 539 540 Res = tryDecodeInst(DecoderTableDPP8GFX1264, 541 DecoderTableDPP8GFX12_FAKE1664, MI, QW, Address, CS); 542 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 543 break; 544 MI = MCInst(); // clear 545 546 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address, CS); 547 if (Res) break; 548 549 Res = tryDecodeInst(DecoderTableDPPGFX1164, DecoderTableDPPGFX11_FAKE1664, 550 MI, QW, Address, CS); 551 if (Res) { 552 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC) 553 convertVOPCDPPInst(MI); 554 break; 555 } 556 557 Res = tryDecodeInst(DecoderTableDPPGFX1264, DecoderTableDPPGFX12_FAKE1664, 558 MI, QW, Address, CS); 559 if (Res) { 560 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC) 561 convertVOPCDPPInst(MI); 562 break; 563 } 564 565 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address, CS); 566 if (Res) { IsSDWA = true; break; } 567 568 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address, CS); 569 if (Res) { IsSDWA = true; break; } 570 571 Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address, CS); 572 if (Res) { IsSDWA = true; break; } 573 574 if (STI.hasFeature(AMDGPU::FeatureUnpackedD16VMem)) { 575 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address, CS); 576 if (Res) 577 break; 578 } 579 580 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 581 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 582 // table first so we print the correct name. 583 if (STI.hasFeature(AMDGPU::FeatureFmaMixInsts)) { 584 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address, CS); 585 if (Res) 586 break; 587 } 588 } 589 590 // Reinitialize Bytes as DPP64 could have eaten too much 591 Bytes = Bytes_.slice(0, MaxInstBytesNum); 592 593 // Try decode 32-bit instruction 594 if (Bytes.size() < 4) break; 595 const uint32_t DW = eatBytes<uint32_t>(Bytes); 596 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address, CS); 597 if (Res) break; 598 599 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address, CS); 600 if (Res) break; 601 602 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address, CS); 603 if (Res) break; 604 605 if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts)) { 606 Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address, CS); 607 if (Res) 608 break; 609 } 610 611 if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding)) { 612 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address, CS); 613 if (Res) break; 614 } 615 616 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address, CS); 617 if (Res) break; 618 619 Res = tryDecodeInst(DecoderTableGFX1132, DecoderTableGFX11_FAKE1632, MI, DW, 620 Address, CS); 621 if (Res) break; 622 623 Res = tryDecodeInst(DecoderTableGFX1232, DecoderTableGFX12_FAKE1632, MI, DW, 624 Address, CS); 625 if (Res) 626 break; 627 628 if (Bytes.size() < 4) break; 629 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 630 631 if (STI.hasFeature(AMDGPU::FeatureGFX940Insts)) { 632 Res = tryDecodeInst(DecoderTableGFX94064, MI, QW, Address, CS); 633 if (Res) 634 break; 635 } 636 637 if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts)) { 638 Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address, CS); 639 if (Res) 640 break; 641 } 642 643 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address, CS); 644 if (Res) break; 645 646 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address, CS); 647 if (Res) break; 648 649 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address, CS); 650 if (Res) break; 651 652 Res = tryDecodeInst(DecoderTableGFX1264, DecoderTableGFX12_FAKE1664, MI, QW, 653 Address, CS); 654 if (Res) 655 break; 656 657 Res = tryDecodeInst(DecoderTableGFX1164, DecoderTableGFX11_FAKE1664, MI, QW, 658 Address, CS); 659 if (Res) 660 break; 661 662 Res = tryDecodeInst(DecoderTableGFX11W6464, MI, QW, Address, CS); 663 if (Res) 664 break; 665 666 Res = tryDecodeInst(DecoderTableGFX12W6464, MI, QW, Address, CS); 667 } while (false); 668 669 if (Res && AMDGPU::isMAC(MI.getOpcode())) { 670 // Insert dummy unused src2_modifiers. 671 insertNamedMCOperand(MI, MCOperand::createImm(0), 672 AMDGPU::OpName::src2_modifiers); 673 } 674 675 if (Res && (MI.getOpcode() == AMDGPU::V_CVT_SR_BF8_F32_e64_dpp || 676 MI.getOpcode() == AMDGPU::V_CVT_SR_FP8_F32_e64_dpp)) { 677 // Insert dummy unused src2_modifiers. 678 insertNamedMCOperand(MI, MCOperand::createImm(0), 679 AMDGPU::OpName::src2_modifiers); 680 } 681 682 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::DS) && 683 !AMDGPU::hasGDS(STI)) { 684 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::gds); 685 } 686 687 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 688 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT | SIInstrFlags::SMRD))) { 689 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 690 AMDGPU::OpName::cpol); 691 if (CPolPos != -1) { 692 unsigned CPol = 693 (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ? 694 AMDGPU::CPol::GLC : 0; 695 if (MI.getNumOperands() <= (unsigned)CPolPos) { 696 insertNamedMCOperand(MI, MCOperand::createImm(CPol), 697 AMDGPU::OpName::cpol); 698 } else if (CPol) { 699 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); 700 } 701 } 702 } 703 704 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 705 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) && 706 (STI.hasFeature(AMDGPU::FeatureGFX90AInsts))) { 707 // GFX90A lost TFE, its place is occupied by ACC. 708 int TFEOpIdx = 709 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); 710 if (TFEOpIdx != -1) { 711 auto TFEIter = MI.begin(); 712 std::advance(TFEIter, TFEOpIdx); 713 MI.insert(TFEIter, MCOperand::createImm(0)); 714 } 715 } 716 717 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 718 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF))) { 719 int SWZOpIdx = 720 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); 721 if (SWZOpIdx != -1) { 722 auto SWZIter = MI.begin(); 723 std::advance(SWZIter, SWZOpIdx); 724 MI.insert(SWZIter, MCOperand::createImm(0)); 725 } 726 } 727 728 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 729 int VAddr0Idx = 730 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 731 int RsrcIdx = 732 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 733 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 734 if (VAddr0Idx >= 0 && NSAArgs > 0) { 735 unsigned NSAWords = (NSAArgs + 3) / 4; 736 if (Bytes.size() < 4 * NSAWords) { 737 Res = MCDisassembler::Fail; 738 } else { 739 for (unsigned i = 0; i < NSAArgs; ++i) { 740 const unsigned VAddrIdx = VAddr0Idx + 1 + i; 741 auto VAddrRCID = 742 MCII->get(MI.getOpcode()).operands()[VAddrIdx].RegClass; 743 MI.insert(MI.begin() + VAddrIdx, 744 createRegOperand(VAddrRCID, Bytes[i])); 745 } 746 Bytes = Bytes.slice(4 * NSAWords); 747 } 748 } 749 750 if (Res) 751 Res = convertMIMGInst(MI); 752 } 753 754 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 755 (SIInstrFlags::VIMAGE | SIInstrFlags::VSAMPLE))) 756 Res = convertMIMGInst(MI); 757 758 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::EXP)) 759 Res = convertEXPInst(MI); 760 761 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VINTERP)) 762 Res = convertVINTERPInst(MI); 763 764 if (Res && IsSDWA) 765 Res = convertSDWAInst(MI); 766 767 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 768 AMDGPU::OpName::vdst_in); 769 if (VDstIn_Idx != -1) { 770 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 771 MCOI::OperandConstraint::TIED_TO); 772 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 773 !MI.getOperand(VDstIn_Idx).isReg() || 774 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 775 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 776 MI.erase(&MI.getOperand(VDstIn_Idx)); 777 insertNamedMCOperand(MI, 778 MCOperand::createReg(MI.getOperand(Tied).getReg()), 779 AMDGPU::OpName::vdst_in); 780 } 781 } 782 783 int ImmLitIdx = 784 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm); 785 bool IsSOPK = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::SOPK; 786 if (Res && ImmLitIdx != -1 && !IsSOPK) 787 Res = convertFMAanyK(MI, ImmLitIdx); 788 789 // if the opcode was not recognized we'll assume a Size of 4 bytes 790 // (unless there are fewer bytes left) 791 Size = Res ? (MaxInstBytesNum - Bytes.size()) 792 : std::min((size_t)4, Bytes_.size()); 793 return Res; 794 } 795 796 DecodeStatus AMDGPUDisassembler::convertEXPInst(MCInst &MI) const { 797 if (STI.hasFeature(AMDGPU::FeatureGFX11Insts)) { 798 // The MCInst still has these fields even though they are no longer encoded 799 // in the GFX11 instruction. 800 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vm); 801 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::compr); 802 } 803 return MCDisassembler::Success; 804 } 805 806 DecodeStatus AMDGPUDisassembler::convertVINTERPInst(MCInst &MI) const { 807 if (MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx11 || 808 MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx12 || 809 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx11 || 810 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx12 || 811 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx11 || 812 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx12 || 813 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx11 || 814 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx12) { 815 // The MCInst has this field that is not directly encoded in the 816 // instruction. 817 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::op_sel); 818 } 819 return MCDisassembler::Success; 820 } 821 822 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 823 if (STI.hasFeature(AMDGPU::FeatureGFX9) || 824 STI.hasFeature(AMDGPU::FeatureGFX10)) { 825 if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::sdst)) 826 // VOPC - insert clamp 827 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 828 } else if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) { 829 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 830 if (SDst != -1) { 831 // VOPC - insert VCC register as sdst 832 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 833 AMDGPU::OpName::sdst); 834 } else { 835 // VOP1/2 - insert omod if present in instruction 836 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 837 } 838 } 839 return MCDisassembler::Success; 840 } 841 842 struct VOPModifiers { 843 unsigned OpSel = 0; 844 unsigned OpSelHi = 0; 845 unsigned NegLo = 0; 846 unsigned NegHi = 0; 847 }; 848 849 // Reconstruct values of VOP3/VOP3P operands such as op_sel. 850 // Note that these values do not affect disassembler output, 851 // so this is only necessary for consistency with src_modifiers. 852 static VOPModifiers collectVOPModifiers(const MCInst &MI, 853 bool IsVOP3P = false) { 854 VOPModifiers Modifiers; 855 unsigned Opc = MI.getOpcode(); 856 const int ModOps[] = {AMDGPU::OpName::src0_modifiers, 857 AMDGPU::OpName::src1_modifiers, 858 AMDGPU::OpName::src2_modifiers}; 859 for (int J = 0; J < 3; ++J) { 860 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]); 861 if (OpIdx == -1) 862 continue; 863 864 unsigned Val = MI.getOperand(OpIdx).getImm(); 865 866 Modifiers.OpSel |= !!(Val & SISrcMods::OP_SEL_0) << J; 867 if (IsVOP3P) { 868 Modifiers.OpSelHi |= !!(Val & SISrcMods::OP_SEL_1) << J; 869 Modifiers.NegLo |= !!(Val & SISrcMods::NEG) << J; 870 Modifiers.NegHi |= !!(Val & SISrcMods::NEG_HI) << J; 871 } else if (J == 0) { 872 Modifiers.OpSel |= !!(Val & SISrcMods::DST_OP_SEL) << 3; 873 } 874 } 875 876 return Modifiers; 877 } 878 879 // Instructions decode the op_sel/suffix bits into the src_modifier 880 // operands. Copy those bits into the src operands for true16 VGPRs. 881 void AMDGPUDisassembler::convertTrue16OpSel(MCInst &MI) const { 882 const unsigned Opc = MI.getOpcode(); 883 const MCRegisterClass &ConversionRC = 884 MRI.getRegClass(AMDGPU::VGPR_16RegClassID); 885 constexpr std::array<std::tuple<int, int, unsigned>, 4> OpAndOpMods = { 886 {{AMDGPU::OpName::src0, AMDGPU::OpName::src0_modifiers, 887 SISrcMods::OP_SEL_0}, 888 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_modifiers, 889 SISrcMods::OP_SEL_0}, 890 {AMDGPU::OpName::src2, AMDGPU::OpName::src2_modifiers, 891 SISrcMods::OP_SEL_0}, 892 {AMDGPU::OpName::vdst, AMDGPU::OpName::src0_modifiers, 893 SISrcMods::DST_OP_SEL}}}; 894 for (const auto &[OpName, OpModsName, OpSelMask] : OpAndOpMods) { 895 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, OpName); 896 int OpModsIdx = AMDGPU::getNamedOperandIdx(Opc, OpModsName); 897 if (OpIdx == -1 || OpModsIdx == -1) 898 continue; 899 MCOperand &Op = MI.getOperand(OpIdx); 900 if (!Op.isReg()) 901 continue; 902 if (!ConversionRC.contains(Op.getReg())) 903 continue; 904 unsigned OpEnc = MRI.getEncodingValue(Op.getReg()); 905 const MCOperand &OpMods = MI.getOperand(OpModsIdx); 906 unsigned ModVal = OpMods.getImm(); 907 if (ModVal & OpSelMask) { // isHi 908 unsigned RegIdx = OpEnc & AMDGPU::HWEncoding::REG_IDX_MASK; 909 Op.setReg(ConversionRC.getRegister(RegIdx * 2 + 1)); 910 } 911 } 912 } 913 914 // MAC opcodes have special old and src2 operands. 915 // src2 is tied to dst, while old is not tied (but assumed to be). 916 bool AMDGPUDisassembler::isMacDPP(MCInst &MI) const { 917 constexpr int DST_IDX = 0; 918 auto Opcode = MI.getOpcode(); 919 const auto &Desc = MCII->get(Opcode); 920 auto OldIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::old); 921 922 if (OldIdx != -1 && Desc.getOperandConstraint( 923 OldIdx, MCOI::OperandConstraint::TIED_TO) == -1) { 924 assert(AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src2)); 925 assert(Desc.getOperandConstraint( 926 AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2), 927 MCOI::OperandConstraint::TIED_TO) == DST_IDX); 928 (void)DST_IDX; 929 return true; 930 } 931 932 return false; 933 } 934 935 // Create dummy old operand and insert dummy unused src2_modifiers 936 void AMDGPUDisassembler::convertMacDPPInst(MCInst &MI) const { 937 assert(MI.getNumOperands() + 1 < MCII->get(MI.getOpcode()).getNumOperands()); 938 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 939 insertNamedMCOperand(MI, MCOperand::createImm(0), 940 AMDGPU::OpName::src2_modifiers); 941 } 942 943 // We must check FI == literal to reject not genuine dpp8 insts, and we must 944 // first add optional MI operands to check FI 945 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 946 unsigned Opc = MI.getOpcode(); 947 948 if (MCII->get(Opc).TSFlags & SIInstrFlags::VOP3P) { 949 convertVOP3PDPPInst(MI); 950 } else if ((MCII->get(Opc).TSFlags & SIInstrFlags::VOPC) || 951 AMDGPU::isVOPC64DPP(Opc)) { 952 convertVOPCDPPInst(MI); 953 } else { 954 if (isMacDPP(MI)) 955 convertMacDPPInst(MI); 956 957 int VDstInIdx = 958 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst_in); 959 if (VDstInIdx != -1) 960 insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::vdst_in); 961 962 if (MI.getOpcode() == AMDGPU::V_CVT_SR_BF8_F32_e64_dpp8_gfx12 || 963 MI.getOpcode() == AMDGPU::V_CVT_SR_FP8_F32_e64_dpp8_gfx12) 964 insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::src2); 965 966 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 967 if (MI.getNumOperands() < DescNumOps && 968 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { 969 convertTrue16OpSel(MI); 970 auto Mods = collectVOPModifiers(MI); 971 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 972 AMDGPU::OpName::op_sel); 973 } else { 974 // Insert dummy unused src modifiers. 975 if (MI.getNumOperands() < DescNumOps && 976 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) 977 insertNamedMCOperand(MI, MCOperand::createImm(0), 978 AMDGPU::OpName::src0_modifiers); 979 980 if (MI.getNumOperands() < DescNumOps && 981 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers)) 982 insertNamedMCOperand(MI, MCOperand::createImm(0), 983 AMDGPU::OpName::src1_modifiers); 984 } 985 } 986 return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail; 987 } 988 989 DecodeStatus AMDGPUDisassembler::convertVOP3DPPInst(MCInst &MI) const { 990 if (isMacDPP(MI)) 991 convertMacDPPInst(MI); 992 993 convertTrue16OpSel(MI); 994 995 int VDstInIdx = 996 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst_in); 997 if (VDstInIdx != -1) 998 insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::vdst_in); 999 1000 if (MI.getOpcode() == AMDGPU::V_CVT_SR_BF8_F32_e64_dpp_gfx12 || 1001 MI.getOpcode() == AMDGPU::V_CVT_SR_FP8_F32_e64_dpp_gfx12) 1002 insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::src2); 1003 1004 unsigned Opc = MI.getOpcode(); 1005 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1006 if (MI.getNumOperands() < DescNumOps && 1007 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { 1008 auto Mods = collectVOPModifiers(MI); 1009 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 1010 AMDGPU::OpName::op_sel); 1011 } 1012 return MCDisassembler::Success; 1013 } 1014 1015 // Note that before gfx10, the MIMG encoding provided no information about 1016 // VADDR size. Consequently, decoded instructions always show address as if it 1017 // has 1 dword, which could be not really so. 1018 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 1019 auto TSFlags = MCII->get(MI.getOpcode()).TSFlags; 1020 1021 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 1022 AMDGPU::OpName::vdst); 1023 1024 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 1025 AMDGPU::OpName::vdata); 1026 int VAddr0Idx = 1027 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 1028 int RsrcOpName = TSFlags & SIInstrFlags::MIMG ? AMDGPU::OpName::srsrc 1029 : AMDGPU::OpName::rsrc; 1030 int RsrcIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), RsrcOpName); 1031 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 1032 AMDGPU::OpName::dmask); 1033 1034 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 1035 AMDGPU::OpName::tfe); 1036 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 1037 AMDGPU::OpName::d16); 1038 1039 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 1040 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 1041 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 1042 1043 assert(VDataIdx != -1); 1044 if (BaseOpcode->BVH) { 1045 // Add A16 operand for intersect_ray instructions 1046 addOperand(MI, MCOperand::createImm(BaseOpcode->A16)); 1047 return MCDisassembler::Success; 1048 } 1049 1050 bool IsAtomic = (VDstIdx != -1); 1051 bool IsGather4 = TSFlags & SIInstrFlags::Gather4; 1052 bool IsVSample = TSFlags & SIInstrFlags::VSAMPLE; 1053 bool IsNSA = false; 1054 bool IsPartialNSA = false; 1055 unsigned AddrSize = Info->VAddrDwords; 1056 1057 if (isGFX10Plus()) { 1058 unsigned DimIdx = 1059 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 1060 int A16Idx = 1061 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16); 1062 const AMDGPU::MIMGDimInfo *Dim = 1063 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 1064 const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm()); 1065 1066 AddrSize = 1067 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); 1068 1069 // VSAMPLE insts that do not use vaddr3 behave the same as NSA forms. 1070 // VIMAGE insts other than BVH never use vaddr4. 1071 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA || 1072 Info->MIMGEncoding == AMDGPU::MIMGEncGfx11NSA || 1073 Info->MIMGEncoding == AMDGPU::MIMGEncGfx12; 1074 if (!IsNSA) { 1075 if (!IsVSample && AddrSize > 12) 1076 AddrSize = 16; 1077 } else { 1078 if (AddrSize > Info->VAddrDwords) { 1079 if (!STI.hasFeature(AMDGPU::FeaturePartialNSAEncoding)) { 1080 // The NSA encoding does not contain enough operands for the 1081 // combination of base opcode / dimension. Should this be an error? 1082 return MCDisassembler::Success; 1083 } 1084 IsPartialNSA = true; 1085 } 1086 } 1087 } 1088 1089 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 1090 unsigned DstSize = IsGather4 ? 4 : std::max(llvm::popcount(DMask), 1); 1091 1092 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 1093 if (D16 && AMDGPU::hasPackedD16(STI)) { 1094 DstSize = (DstSize + 1) / 2; 1095 } 1096 1097 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm()) 1098 DstSize += 1; 1099 1100 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 1101 return MCDisassembler::Success; 1102 1103 int NewOpcode = 1104 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 1105 if (NewOpcode == -1) 1106 return MCDisassembler::Success; 1107 1108 // Widen the register to the correct number of enabled channels. 1109 unsigned NewVdata = AMDGPU::NoRegister; 1110 if (DstSize != Info->VDataDwords) { 1111 auto DataRCID = MCII->get(NewOpcode).operands()[VDataIdx].RegClass; 1112 1113 // Get first subregister of VData 1114 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 1115 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 1116 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 1117 1118 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 1119 &MRI.getRegClass(DataRCID)); 1120 if (NewVdata == AMDGPU::NoRegister) { 1121 // It's possible to encode this such that the low register + enabled 1122 // components exceeds the register count. 1123 return MCDisassembler::Success; 1124 } 1125 } 1126 1127 // If not using NSA on GFX10+, widen vaddr0 address register to correct size. 1128 // If using partial NSA on GFX11+ widen last address register. 1129 int VAddrSAIdx = IsPartialNSA ? (RsrcIdx - 1) : VAddr0Idx; 1130 unsigned NewVAddrSA = AMDGPU::NoRegister; 1131 if (STI.hasFeature(AMDGPU::FeatureNSAEncoding) && (!IsNSA || IsPartialNSA) && 1132 AddrSize != Info->VAddrDwords) { 1133 unsigned VAddrSA = MI.getOperand(VAddrSAIdx).getReg(); 1134 unsigned VAddrSubSA = MRI.getSubReg(VAddrSA, AMDGPU::sub0); 1135 VAddrSA = VAddrSubSA ? VAddrSubSA : VAddrSA; 1136 1137 auto AddrRCID = MCII->get(NewOpcode).operands()[VAddrSAIdx].RegClass; 1138 NewVAddrSA = MRI.getMatchingSuperReg(VAddrSA, AMDGPU::sub0, 1139 &MRI.getRegClass(AddrRCID)); 1140 if (!NewVAddrSA) 1141 return MCDisassembler::Success; 1142 } 1143 1144 MI.setOpcode(NewOpcode); 1145 1146 if (NewVdata != AMDGPU::NoRegister) { 1147 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 1148 1149 if (IsAtomic) { 1150 // Atomic operations have an additional operand (a copy of data) 1151 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 1152 } 1153 } 1154 1155 if (NewVAddrSA) { 1156 MI.getOperand(VAddrSAIdx) = MCOperand::createReg(NewVAddrSA); 1157 } else if (IsNSA) { 1158 assert(AddrSize <= Info->VAddrDwords); 1159 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 1160 MI.begin() + VAddr0Idx + Info->VAddrDwords); 1161 } 1162 1163 return MCDisassembler::Success; 1164 } 1165 1166 // Opsel and neg bits are used in src_modifiers and standalone operands. Autogen 1167 // decoder only adds to src_modifiers, so manually add the bits to the other 1168 // operands. 1169 DecodeStatus AMDGPUDisassembler::convertVOP3PDPPInst(MCInst &MI) const { 1170 unsigned Opc = MI.getOpcode(); 1171 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1172 auto Mods = collectVOPModifiers(MI, true); 1173 1174 if (MI.getNumOperands() < DescNumOps && 1175 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vdst_in)) 1176 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vdst_in); 1177 1178 if (MI.getNumOperands() < DescNumOps && 1179 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) 1180 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 1181 AMDGPU::OpName::op_sel); 1182 if (MI.getNumOperands() < DescNumOps && 1183 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel_hi)) 1184 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSelHi), 1185 AMDGPU::OpName::op_sel_hi); 1186 if (MI.getNumOperands() < DescNumOps && 1187 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_lo)) 1188 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegLo), 1189 AMDGPU::OpName::neg_lo); 1190 if (MI.getNumOperands() < DescNumOps && 1191 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_hi)) 1192 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegHi), 1193 AMDGPU::OpName::neg_hi); 1194 1195 return MCDisassembler::Success; 1196 } 1197 1198 // Create dummy old operand and insert optional operands 1199 DecodeStatus AMDGPUDisassembler::convertVOPCDPPInst(MCInst &MI) const { 1200 unsigned Opc = MI.getOpcode(); 1201 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1202 1203 if (MI.getNumOperands() < DescNumOps && 1204 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::old)) 1205 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 1206 1207 if (MI.getNumOperands() < DescNumOps && 1208 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) 1209 insertNamedMCOperand(MI, MCOperand::createImm(0), 1210 AMDGPU::OpName::src0_modifiers); 1211 1212 if (MI.getNumOperands() < DescNumOps && 1213 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers)) 1214 insertNamedMCOperand(MI, MCOperand::createImm(0), 1215 AMDGPU::OpName::src1_modifiers); 1216 return MCDisassembler::Success; 1217 } 1218 1219 DecodeStatus AMDGPUDisassembler::convertFMAanyK(MCInst &MI, 1220 int ImmLitIdx) const { 1221 assert(HasLiteral && "Should have decoded a literal"); 1222 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 1223 unsigned DescNumOps = Desc.getNumOperands(); 1224 insertNamedMCOperand(MI, MCOperand::createImm(Literal), 1225 AMDGPU::OpName::immDeferred); 1226 assert(DescNumOps == MI.getNumOperands()); 1227 for (unsigned I = 0; I < DescNumOps; ++I) { 1228 auto &Op = MI.getOperand(I); 1229 auto OpType = Desc.operands()[I].OperandType; 1230 bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED || 1231 OpType == AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED); 1232 if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST && 1233 IsDeferredOp) 1234 Op.setImm(Literal); 1235 } 1236 return MCDisassembler::Success; 1237 } 1238 1239 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 1240 return getContext().getRegisterInfo()-> 1241 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 1242 } 1243 1244 inline 1245 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 1246 const Twine& ErrMsg) const { 1247 *CommentStream << "Error: " + ErrMsg; 1248 1249 // ToDo: add support for error operands to MCInst.h 1250 // return MCOperand::createError(V); 1251 return MCOperand(); 1252 } 1253 1254 inline 1255 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 1256 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 1257 } 1258 1259 inline 1260 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 1261 unsigned Val) const { 1262 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 1263 if (Val >= RegCl.getNumRegs()) 1264 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 1265 ": unknown register " + Twine(Val)); 1266 return createRegOperand(RegCl.getRegister(Val)); 1267 } 1268 1269 inline 1270 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 1271 unsigned Val) const { 1272 // ToDo: SI/CI have 104 SGPRs, VI - 102 1273 // Valery: here we accepting as much as we can, let assembler sort it out 1274 int shift = 0; 1275 switch (SRegClassID) { 1276 case AMDGPU::SGPR_32RegClassID: 1277 case AMDGPU::TTMP_32RegClassID: 1278 break; 1279 case AMDGPU::SGPR_64RegClassID: 1280 case AMDGPU::TTMP_64RegClassID: 1281 shift = 1; 1282 break; 1283 case AMDGPU::SGPR_96RegClassID: 1284 case AMDGPU::TTMP_96RegClassID: 1285 case AMDGPU::SGPR_128RegClassID: 1286 case AMDGPU::TTMP_128RegClassID: 1287 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 1288 // this bundle? 1289 case AMDGPU::SGPR_256RegClassID: 1290 case AMDGPU::TTMP_256RegClassID: 1291 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 1292 // this bundle? 1293 case AMDGPU::SGPR_288RegClassID: 1294 case AMDGPU::TTMP_288RegClassID: 1295 case AMDGPU::SGPR_320RegClassID: 1296 case AMDGPU::TTMP_320RegClassID: 1297 case AMDGPU::SGPR_352RegClassID: 1298 case AMDGPU::TTMP_352RegClassID: 1299 case AMDGPU::SGPR_384RegClassID: 1300 case AMDGPU::TTMP_384RegClassID: 1301 case AMDGPU::SGPR_512RegClassID: 1302 case AMDGPU::TTMP_512RegClassID: 1303 shift = 2; 1304 break; 1305 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 1306 // this bundle? 1307 default: 1308 llvm_unreachable("unhandled register class"); 1309 } 1310 1311 if (Val % (1 << shift)) { 1312 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 1313 << ": scalar reg isn't aligned " << Val; 1314 } 1315 1316 return createRegOperand(SRegClassID, Val >> shift); 1317 } 1318 1319 MCOperand AMDGPUDisassembler::createVGPR16Operand(unsigned RegIdx, 1320 bool IsHi) const { 1321 unsigned RegIdxInVGPR16 = RegIdx * 2 + (IsHi ? 1 : 0); 1322 return createRegOperand(AMDGPU::VGPR_16RegClassID, RegIdxInVGPR16); 1323 } 1324 1325 // Decode Literals for insts which always have a literal in the encoding 1326 MCOperand 1327 AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const { 1328 if (HasLiteral) { 1329 assert( 1330 AMDGPU::hasVOPD(STI) && 1331 "Should only decode multiple kimm with VOPD, check VSrc operand types"); 1332 if (Literal != Val) 1333 return errOperand(Val, "More than one unique literal is illegal"); 1334 } 1335 HasLiteral = true; 1336 Literal = Val; 1337 return MCOperand::createImm(Literal); 1338 } 1339 1340 MCOperand AMDGPUDisassembler::decodeLiteralConstant(bool ExtendFP64) const { 1341 // For now all literal constants are supposed to be unsigned integer 1342 // ToDo: deal with signed/unsigned 64-bit integer constants 1343 // ToDo: deal with float/double constants 1344 if (!HasLiteral) { 1345 if (Bytes.size() < 4) { 1346 return errOperand(0, "cannot read literal, inst bytes left " + 1347 Twine(Bytes.size())); 1348 } 1349 HasLiteral = true; 1350 Literal = Literal64 = eatBytes<uint32_t>(Bytes); 1351 if (ExtendFP64) 1352 Literal64 <<= 32; 1353 } 1354 return MCOperand::createImm(ExtendFP64 ? Literal64 : Literal); 1355 } 1356 1357 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 1358 using namespace AMDGPU::EncValues; 1359 1360 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 1361 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 1362 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 1363 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 1364 // Cast prevents negative overflow. 1365 } 1366 1367 static int64_t getInlineImmVal32(unsigned Imm) { 1368 switch (Imm) { 1369 case 240: 1370 return llvm::bit_cast<uint32_t>(0.5f); 1371 case 241: 1372 return llvm::bit_cast<uint32_t>(-0.5f); 1373 case 242: 1374 return llvm::bit_cast<uint32_t>(1.0f); 1375 case 243: 1376 return llvm::bit_cast<uint32_t>(-1.0f); 1377 case 244: 1378 return llvm::bit_cast<uint32_t>(2.0f); 1379 case 245: 1380 return llvm::bit_cast<uint32_t>(-2.0f); 1381 case 246: 1382 return llvm::bit_cast<uint32_t>(4.0f); 1383 case 247: 1384 return llvm::bit_cast<uint32_t>(-4.0f); 1385 case 248: // 1 / (2 * PI) 1386 return 0x3e22f983; 1387 default: 1388 llvm_unreachable("invalid fp inline imm"); 1389 } 1390 } 1391 1392 static int64_t getInlineImmVal64(unsigned Imm) { 1393 switch (Imm) { 1394 case 240: 1395 return llvm::bit_cast<uint64_t>(0.5); 1396 case 241: 1397 return llvm::bit_cast<uint64_t>(-0.5); 1398 case 242: 1399 return llvm::bit_cast<uint64_t>(1.0); 1400 case 243: 1401 return llvm::bit_cast<uint64_t>(-1.0); 1402 case 244: 1403 return llvm::bit_cast<uint64_t>(2.0); 1404 case 245: 1405 return llvm::bit_cast<uint64_t>(-2.0); 1406 case 246: 1407 return llvm::bit_cast<uint64_t>(4.0); 1408 case 247: 1409 return llvm::bit_cast<uint64_t>(-4.0); 1410 case 248: // 1 / (2 * PI) 1411 return 0x3fc45f306dc9c882; 1412 default: 1413 llvm_unreachable("invalid fp inline imm"); 1414 } 1415 } 1416 1417 static int64_t getInlineImmVal16(unsigned Imm) { 1418 switch (Imm) { 1419 case 240: 1420 return 0x3800; 1421 case 241: 1422 return 0xB800; 1423 case 242: 1424 return 0x3C00; 1425 case 243: 1426 return 0xBC00; 1427 case 244: 1428 return 0x4000; 1429 case 245: 1430 return 0xC000; 1431 case 246: 1432 return 0x4400; 1433 case 247: 1434 return 0xC400; 1435 case 248: // 1 / (2 * PI) 1436 return 0x3118; 1437 default: 1438 llvm_unreachable("invalid fp inline imm"); 1439 } 1440 } 1441 1442 MCOperand AMDGPUDisassembler::decodeFPImmed(unsigned ImmWidth, unsigned Imm) { 1443 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 1444 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 1445 1446 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 1447 // ImmWidth 0 is a default case where operand should not allow immediates. 1448 // Imm value is still decoded into 32 bit immediate operand, inst printer will 1449 // use it to print verbose error message. 1450 switch (ImmWidth) { 1451 case 0: 1452 case 32: 1453 return MCOperand::createImm(getInlineImmVal32(Imm)); 1454 case 64: 1455 return MCOperand::createImm(getInlineImmVal64(Imm)); 1456 case 16: 1457 return MCOperand::createImm(getInlineImmVal16(Imm)); 1458 default: 1459 llvm_unreachable("implement me"); 1460 } 1461 } 1462 1463 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 1464 using namespace AMDGPU; 1465 1466 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1467 switch (Width) { 1468 default: // fall 1469 case OPW32: 1470 case OPW16: 1471 case OPWV216: 1472 return VGPR_32RegClassID; 1473 case OPW64: 1474 case OPWV232: return VReg_64RegClassID; 1475 case OPW96: return VReg_96RegClassID; 1476 case OPW128: return VReg_128RegClassID; 1477 case OPW160: return VReg_160RegClassID; 1478 case OPW256: return VReg_256RegClassID; 1479 case OPW288: return VReg_288RegClassID; 1480 case OPW320: return VReg_320RegClassID; 1481 case OPW352: return VReg_352RegClassID; 1482 case OPW384: return VReg_384RegClassID; 1483 case OPW512: return VReg_512RegClassID; 1484 case OPW1024: return VReg_1024RegClassID; 1485 } 1486 } 1487 1488 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 1489 using namespace AMDGPU; 1490 1491 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1492 switch (Width) { 1493 default: // fall 1494 case OPW32: 1495 case OPW16: 1496 case OPWV216: 1497 return AGPR_32RegClassID; 1498 case OPW64: 1499 case OPWV232: return AReg_64RegClassID; 1500 case OPW96: return AReg_96RegClassID; 1501 case OPW128: return AReg_128RegClassID; 1502 case OPW160: return AReg_160RegClassID; 1503 case OPW256: return AReg_256RegClassID; 1504 case OPW288: return AReg_288RegClassID; 1505 case OPW320: return AReg_320RegClassID; 1506 case OPW352: return AReg_352RegClassID; 1507 case OPW384: return AReg_384RegClassID; 1508 case OPW512: return AReg_512RegClassID; 1509 case OPW1024: return AReg_1024RegClassID; 1510 } 1511 } 1512 1513 1514 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 1515 using namespace AMDGPU; 1516 1517 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1518 switch (Width) { 1519 default: // fall 1520 case OPW32: 1521 case OPW16: 1522 case OPWV216: 1523 return SGPR_32RegClassID; 1524 case OPW64: 1525 case OPWV232: return SGPR_64RegClassID; 1526 case OPW96: return SGPR_96RegClassID; 1527 case OPW128: return SGPR_128RegClassID; 1528 case OPW160: return SGPR_160RegClassID; 1529 case OPW256: return SGPR_256RegClassID; 1530 case OPW288: return SGPR_288RegClassID; 1531 case OPW320: return SGPR_320RegClassID; 1532 case OPW352: return SGPR_352RegClassID; 1533 case OPW384: return SGPR_384RegClassID; 1534 case OPW512: return SGPR_512RegClassID; 1535 } 1536 } 1537 1538 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 1539 using namespace AMDGPU; 1540 1541 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1542 switch (Width) { 1543 default: // fall 1544 case OPW32: 1545 case OPW16: 1546 case OPWV216: 1547 return TTMP_32RegClassID; 1548 case OPW64: 1549 case OPWV232: return TTMP_64RegClassID; 1550 case OPW128: return TTMP_128RegClassID; 1551 case OPW256: return TTMP_256RegClassID; 1552 case OPW288: return TTMP_288RegClassID; 1553 case OPW320: return TTMP_320RegClassID; 1554 case OPW352: return TTMP_352RegClassID; 1555 case OPW384: return TTMP_384RegClassID; 1556 case OPW512: return TTMP_512RegClassID; 1557 } 1558 } 1559 1560 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 1561 using namespace AMDGPU::EncValues; 1562 1563 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN; 1564 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX; 1565 1566 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1567 } 1568 1569 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val, 1570 bool MandatoryLiteral, 1571 unsigned ImmWidth, bool IsFP) const { 1572 using namespace AMDGPU::EncValues; 1573 1574 assert(Val < 1024); // enum10 1575 1576 bool IsAGPR = Val & 512; 1577 Val &= 511; 1578 1579 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1580 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1581 : getVgprClassId(Width), Val - VGPR_MIN); 1582 } 1583 return decodeNonVGPRSrcOp(Width, Val & 0xFF, MandatoryLiteral, ImmWidth, 1584 IsFP); 1585 } 1586 1587 MCOperand AMDGPUDisassembler::decodeNonVGPRSrcOp(const OpWidthTy Width, 1588 unsigned Val, 1589 bool MandatoryLiteral, 1590 unsigned ImmWidth, 1591 bool IsFP) const { 1592 // Cases when Val{8} is 1 (vgpr, agpr or true 16 vgpr) should have been 1593 // decoded earlier. 1594 assert(Val < (1 << 8) && "9-bit Src encoding when Val{8} is 0"); 1595 using namespace AMDGPU::EncValues; 1596 1597 if (Val <= SGPR_MAX) { 1598 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1599 static_assert(SGPR_MIN == 0); 1600 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1601 } 1602 1603 int TTmpIdx = getTTmpIdx(Val); 1604 if (TTmpIdx >= 0) { 1605 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1606 } 1607 1608 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1609 return decodeIntImmed(Val); 1610 1611 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1612 return decodeFPImmed(ImmWidth, Val); 1613 1614 if (Val == LITERAL_CONST) { 1615 if (MandatoryLiteral) 1616 // Keep a sentinel value for deferred setting 1617 return MCOperand::createImm(LITERAL_CONST); 1618 else 1619 return decodeLiteralConstant(IsFP && ImmWidth == 64); 1620 } 1621 1622 switch (Width) { 1623 case OPW32: 1624 case OPW16: 1625 case OPWV216: 1626 return decodeSpecialReg32(Val); 1627 case OPW64: 1628 case OPWV232: 1629 return decodeSpecialReg64(Val); 1630 default: 1631 llvm_unreachable("unexpected immediate type"); 1632 } 1633 } 1634 1635 // Bit 0 of DstY isn't stored in the instruction, because it's always the 1636 // opposite of bit 0 of DstX. 1637 MCOperand AMDGPUDisassembler::decodeVOPDDstYOp(MCInst &Inst, 1638 unsigned Val) const { 1639 int VDstXInd = 1640 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::vdstX); 1641 assert(VDstXInd != -1); 1642 assert(Inst.getOperand(VDstXInd).isReg()); 1643 unsigned XDstReg = MRI.getEncodingValue(Inst.getOperand(VDstXInd).getReg()); 1644 Val |= ~XDstReg & 1; 1645 auto Width = llvm::AMDGPUDisassembler::OPW32; 1646 return createRegOperand(getVgprClassId(Width), Val); 1647 } 1648 1649 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1650 using namespace AMDGPU; 1651 1652 switch (Val) { 1653 // clang-format off 1654 case 102: return createRegOperand(FLAT_SCR_LO); 1655 case 103: return createRegOperand(FLAT_SCR_HI); 1656 case 104: return createRegOperand(XNACK_MASK_LO); 1657 case 105: return createRegOperand(XNACK_MASK_HI); 1658 case 106: return createRegOperand(VCC_LO); 1659 case 107: return createRegOperand(VCC_HI); 1660 case 108: return createRegOperand(TBA_LO); 1661 case 109: return createRegOperand(TBA_HI); 1662 case 110: return createRegOperand(TMA_LO); 1663 case 111: return createRegOperand(TMA_HI); 1664 case 124: 1665 return isGFX11Plus() ? createRegOperand(SGPR_NULL) : createRegOperand(M0); 1666 case 125: 1667 return isGFX11Plus() ? createRegOperand(M0) : createRegOperand(SGPR_NULL); 1668 case 126: return createRegOperand(EXEC_LO); 1669 case 127: return createRegOperand(EXEC_HI); 1670 case 235: return createRegOperand(SRC_SHARED_BASE_LO); 1671 case 236: return createRegOperand(SRC_SHARED_LIMIT_LO); 1672 case 237: return createRegOperand(SRC_PRIVATE_BASE_LO); 1673 case 238: return createRegOperand(SRC_PRIVATE_LIMIT_LO); 1674 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1675 case 251: return createRegOperand(SRC_VCCZ); 1676 case 252: return createRegOperand(SRC_EXECZ); 1677 case 253: return createRegOperand(SRC_SCC); 1678 case 254: return createRegOperand(LDS_DIRECT); 1679 default: break; 1680 // clang-format on 1681 } 1682 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1683 } 1684 1685 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1686 using namespace AMDGPU; 1687 1688 switch (Val) { 1689 case 102: return createRegOperand(FLAT_SCR); 1690 case 104: return createRegOperand(XNACK_MASK); 1691 case 106: return createRegOperand(VCC); 1692 case 108: return createRegOperand(TBA); 1693 case 110: return createRegOperand(TMA); 1694 case 124: 1695 if (isGFX11Plus()) 1696 return createRegOperand(SGPR_NULL); 1697 break; 1698 case 125: 1699 if (!isGFX11Plus()) 1700 return createRegOperand(SGPR_NULL); 1701 break; 1702 case 126: return createRegOperand(EXEC); 1703 case 235: return createRegOperand(SRC_SHARED_BASE); 1704 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1705 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1706 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1707 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1708 case 251: return createRegOperand(SRC_VCCZ); 1709 case 252: return createRegOperand(SRC_EXECZ); 1710 case 253: return createRegOperand(SRC_SCC); 1711 default: break; 1712 } 1713 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1714 } 1715 1716 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 1717 const unsigned Val, 1718 unsigned ImmWidth) const { 1719 using namespace AMDGPU::SDWA; 1720 using namespace AMDGPU::EncValues; 1721 1722 if (STI.hasFeature(AMDGPU::FeatureGFX9) || 1723 STI.hasFeature(AMDGPU::FeatureGFX10)) { 1724 // XXX: cast to int is needed to avoid stupid warning: 1725 // compare with unsigned is always true 1726 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1727 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1728 return createRegOperand(getVgprClassId(Width), 1729 Val - SDWA9EncValues::SRC_VGPR_MIN); 1730 } 1731 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1732 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1733 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1734 return createSRegOperand(getSgprClassId(Width), 1735 Val - SDWA9EncValues::SRC_SGPR_MIN); 1736 } 1737 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1738 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1739 return createSRegOperand(getTtmpClassId(Width), 1740 Val - SDWA9EncValues::SRC_TTMP_MIN); 1741 } 1742 1743 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1744 1745 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1746 return decodeIntImmed(SVal); 1747 1748 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1749 return decodeFPImmed(ImmWidth, SVal); 1750 1751 return decodeSpecialReg32(SVal); 1752 } else if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) { 1753 return createRegOperand(getVgprClassId(Width), Val); 1754 } 1755 llvm_unreachable("unsupported target"); 1756 } 1757 1758 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1759 return decodeSDWASrc(OPW16, Val, 16); 1760 } 1761 1762 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1763 return decodeSDWASrc(OPW32, Val, 32); 1764 } 1765 1766 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1767 using namespace AMDGPU::SDWA; 1768 1769 assert((STI.hasFeature(AMDGPU::FeatureGFX9) || 1770 STI.hasFeature(AMDGPU::FeatureGFX10)) && 1771 "SDWAVopcDst should be present only on GFX9+"); 1772 1773 bool IsWave64 = STI.hasFeature(AMDGPU::FeatureWavefrontSize64); 1774 1775 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1776 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1777 1778 int TTmpIdx = getTTmpIdx(Val); 1779 if (TTmpIdx >= 0) { 1780 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1781 return createSRegOperand(TTmpClsId, TTmpIdx); 1782 } else if (Val > SGPR_MAX) { 1783 return IsWave64 ? decodeSpecialReg64(Val) 1784 : decodeSpecialReg32(Val); 1785 } else { 1786 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1787 } 1788 } else { 1789 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1790 } 1791 } 1792 1793 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1794 return STI.hasFeature(AMDGPU::FeatureWavefrontSize64) 1795 ? decodeSrcOp(OPW64, Val) 1796 : decodeSrcOp(OPW32, Val); 1797 } 1798 1799 MCOperand AMDGPUDisassembler::decodeSplitBarrier(unsigned Val) const { 1800 return decodeSrcOp(OPW32, Val); 1801 } 1802 1803 bool AMDGPUDisassembler::isVI() const { 1804 return STI.hasFeature(AMDGPU::FeatureVolcanicIslands); 1805 } 1806 1807 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } 1808 1809 bool AMDGPUDisassembler::isGFX90A() const { 1810 return STI.hasFeature(AMDGPU::FeatureGFX90AInsts); 1811 } 1812 1813 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } 1814 1815 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } 1816 1817 bool AMDGPUDisassembler::isGFX10Plus() const { 1818 return AMDGPU::isGFX10Plus(STI); 1819 } 1820 1821 bool AMDGPUDisassembler::isGFX11() const { 1822 return STI.hasFeature(AMDGPU::FeatureGFX11); 1823 } 1824 1825 bool AMDGPUDisassembler::isGFX11Plus() const { 1826 return AMDGPU::isGFX11Plus(STI); 1827 } 1828 1829 bool AMDGPUDisassembler::isGFX12Plus() const { 1830 return AMDGPU::isGFX12Plus(STI); 1831 } 1832 1833 bool AMDGPUDisassembler::hasArchitectedFlatScratch() const { 1834 return STI.hasFeature(AMDGPU::FeatureArchitectedFlatScratch); 1835 } 1836 1837 bool AMDGPUDisassembler::hasKernargPreload() const { 1838 return AMDGPU::hasKernargPreload(STI); 1839 } 1840 1841 //===----------------------------------------------------------------------===// 1842 // AMDGPU specific symbol handling 1843 //===----------------------------------------------------------------------===// 1844 #define GET_FIELD(MASK) (AMDHSA_BITS_GET(FourByteBuffer, MASK)) 1845 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1846 do { \ 1847 KdStream << Indent << DIRECTIVE " " << GET_FIELD(MASK) << '\n'; \ 1848 } while (0) 1849 #define PRINT_PSEUDO_DIRECTIVE_COMMENT(DIRECTIVE, MASK) \ 1850 do { \ 1851 KdStream << Indent << MAI.getCommentString() << ' ' << DIRECTIVE " " \ 1852 << GET_FIELD(MASK) << '\n'; \ 1853 } while (0) 1854 1855 // NOLINTNEXTLINE(readability-identifier-naming) 1856 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1857 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1858 using namespace amdhsa; 1859 StringRef Indent = "\t"; 1860 1861 // We cannot accurately backward compute #VGPRs used from 1862 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1863 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1864 // simply calculate the inverse of what the assembler does. 1865 1866 uint32_t GranulatedWorkitemVGPRCount = 1867 GET_FIELD(COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT); 1868 1869 uint32_t NextFreeVGPR = 1870 (GranulatedWorkitemVGPRCount + 1) * 1871 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI, EnableWavefrontSize32); 1872 1873 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1874 1875 // We cannot backward compute values used to calculate 1876 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1877 // directives can't be computed: 1878 // .amdhsa_reserve_vcc 1879 // .amdhsa_reserve_flat_scratch 1880 // .amdhsa_reserve_xnack_mask 1881 // They take their respective default values if not specified in the assembly. 1882 // 1883 // GRANULATED_WAVEFRONT_SGPR_COUNT 1884 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1885 // 1886 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1887 // are set to 0. So while disassembling we consider that: 1888 // 1889 // GRANULATED_WAVEFRONT_SGPR_COUNT 1890 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1891 // 1892 // The disassembler cannot recover the original values of those 3 directives. 1893 1894 uint32_t GranulatedWavefrontSGPRCount = 1895 GET_FIELD(COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT); 1896 1897 if (isGFX10Plus() && GranulatedWavefrontSGPRCount) 1898 return MCDisassembler::Fail; 1899 1900 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1901 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1902 1903 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1904 if (!hasArchitectedFlatScratch()) 1905 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1906 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1907 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1908 1909 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY) 1910 return MCDisassembler::Fail; 1911 1912 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1913 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1914 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1915 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1916 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1917 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1918 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1919 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1920 1921 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) 1922 return MCDisassembler::Fail; 1923 1924 if (!isGFX12Plus()) 1925 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", 1926 COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP); 1927 1928 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) 1929 return MCDisassembler::Fail; 1930 1931 if (!isGFX12Plus()) 1932 PRINT_DIRECTIVE(".amdhsa_ieee_mode", 1933 COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE); 1934 1935 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) 1936 return MCDisassembler::Fail; 1937 1938 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER) 1939 return MCDisassembler::Fail; 1940 1941 if (isGFX9Plus()) 1942 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL); 1943 1944 if (!isGFX9Plus()) 1945 if (FourByteBuffer & COMPUTE_PGM_RSRC1_GFX6_GFX8_RESERVED0) 1946 return MCDisassembler::Fail; 1947 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED1) 1948 return MCDisassembler::Fail; 1949 if (!isGFX10Plus()) 1950 if (FourByteBuffer & COMPUTE_PGM_RSRC1_GFX6_GFX9_RESERVED2) 1951 return MCDisassembler::Fail; 1952 1953 if (isGFX10Plus()) { 1954 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1955 COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE); 1956 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED); 1957 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS); 1958 } 1959 1960 if (isGFX12Plus()) 1961 PRINT_DIRECTIVE(".amdhsa_round_robin_scheduling", 1962 COMPUTE_PGM_RSRC1_GFX12_PLUS_ENABLE_WG_RR_EN); 1963 1964 return MCDisassembler::Success; 1965 } 1966 1967 // NOLINTNEXTLINE(readability-identifier-naming) 1968 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 1969 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1970 using namespace amdhsa; 1971 StringRef Indent = "\t"; 1972 if (hasArchitectedFlatScratch()) 1973 PRINT_DIRECTIVE(".amdhsa_enable_private_segment", 1974 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1975 else 1976 PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset", 1977 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1978 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 1979 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 1980 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 1981 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 1982 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 1983 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 1984 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 1985 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 1986 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 1987 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 1988 1989 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH) 1990 return MCDisassembler::Fail; 1991 1992 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY) 1993 return MCDisassembler::Fail; 1994 1995 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE) 1996 return MCDisassembler::Fail; 1997 1998 PRINT_DIRECTIVE( 1999 ".amdhsa_exception_fp_ieee_invalid_op", 2000 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 2001 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 2002 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 2003 PRINT_DIRECTIVE( 2004 ".amdhsa_exception_fp_ieee_div_zero", 2005 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 2006 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 2007 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 2008 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 2009 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 2010 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 2011 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 2012 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 2013 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 2014 2015 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0) 2016 return MCDisassembler::Fail; 2017 2018 return MCDisassembler::Success; 2019 } 2020 2021 // NOLINTNEXTLINE(readability-identifier-naming) 2022 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC3( 2023 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 2024 using namespace amdhsa; 2025 StringRef Indent = "\t"; 2026 if (isGFX90A()) { 2027 KdStream << Indent << ".amdhsa_accum_offset " 2028 << (GET_FIELD(COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET) + 1) * 4 2029 << '\n'; 2030 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX90A_RESERVED0) 2031 return MCDisassembler::Fail; 2032 PRINT_DIRECTIVE(".amdhsa_tg_split", COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT); 2033 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX90A_RESERVED1) 2034 return MCDisassembler::Fail; 2035 } else if (isGFX10Plus()) { 2036 // Bits [0-3]. 2037 if (!isGFX12Plus()) { 2038 if (!EnableWavefrontSize32 || !*EnableWavefrontSize32) { 2039 PRINT_DIRECTIVE(".amdhsa_shared_vgpr_count", 2040 COMPUTE_PGM_RSRC3_GFX10_GFX11_SHARED_VGPR_COUNT); 2041 } else { 2042 PRINT_PSEUDO_DIRECTIVE_COMMENT( 2043 "SHARED_VGPR_COUNT", 2044 COMPUTE_PGM_RSRC3_GFX10_GFX11_SHARED_VGPR_COUNT); 2045 } 2046 } else { 2047 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX12_PLUS_RESERVED0) 2048 return MCDisassembler::Fail; 2049 } 2050 2051 // Bits [4-11]. 2052 if (isGFX11()) { 2053 PRINT_PSEUDO_DIRECTIVE_COMMENT("INST_PREF_SIZE", 2054 COMPUTE_PGM_RSRC3_GFX11_INST_PREF_SIZE); 2055 PRINT_PSEUDO_DIRECTIVE_COMMENT("TRAP_ON_START", 2056 COMPUTE_PGM_RSRC3_GFX11_TRAP_ON_START); 2057 PRINT_PSEUDO_DIRECTIVE_COMMENT("TRAP_ON_END", 2058 COMPUTE_PGM_RSRC3_GFX11_TRAP_ON_END); 2059 } else if (isGFX12Plus()) { 2060 PRINT_PSEUDO_DIRECTIVE_COMMENT( 2061 "INST_PREF_SIZE", COMPUTE_PGM_RSRC3_GFX12_PLUS_INST_PREF_SIZE); 2062 } else { 2063 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_RESERVED1) 2064 return MCDisassembler::Fail; 2065 } 2066 2067 // Bits [12]. 2068 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_PLUS_RESERVED2) 2069 return MCDisassembler::Fail; 2070 2071 // Bits [13]. 2072 if (isGFX12Plus()) { 2073 PRINT_PSEUDO_DIRECTIVE_COMMENT("GLG_EN", 2074 COMPUTE_PGM_RSRC3_GFX12_PLUS_GLG_EN); 2075 } else { 2076 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_GFX11_RESERVED3) 2077 return MCDisassembler::Fail; 2078 } 2079 2080 // Bits [14-30]. 2081 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_PLUS_RESERVED4) 2082 return MCDisassembler::Fail; 2083 2084 // Bits [31]. 2085 if (isGFX11Plus()) { 2086 PRINT_PSEUDO_DIRECTIVE_COMMENT("IMAGE_OP", 2087 COMPUTE_PGM_RSRC3_GFX11_PLUS_IMAGE_OP); 2088 } else { 2089 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_RESERVED5) 2090 return MCDisassembler::Fail; 2091 } 2092 } else if (FourByteBuffer) { 2093 return MCDisassembler::Fail; 2094 } 2095 return MCDisassembler::Success; 2096 } 2097 #undef PRINT_PSEUDO_DIRECTIVE_COMMENT 2098 #undef PRINT_DIRECTIVE 2099 #undef GET_FIELD 2100 2101 MCDisassembler::DecodeStatus 2102 AMDGPUDisassembler::decodeKernelDescriptorDirective( 2103 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 2104 raw_string_ostream &KdStream) const { 2105 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 2106 do { \ 2107 KdStream << Indent << DIRECTIVE " " \ 2108 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 2109 } while (0) 2110 2111 uint16_t TwoByteBuffer = 0; 2112 uint32_t FourByteBuffer = 0; 2113 2114 StringRef ReservedBytes; 2115 StringRef Indent = "\t"; 2116 2117 assert(Bytes.size() == 64); 2118 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 2119 2120 switch (Cursor.tell()) { 2121 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 2122 FourByteBuffer = DE.getU32(Cursor); 2123 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 2124 << '\n'; 2125 return MCDisassembler::Success; 2126 2127 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 2128 FourByteBuffer = DE.getU32(Cursor); 2129 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 2130 << FourByteBuffer << '\n'; 2131 return MCDisassembler::Success; 2132 2133 case amdhsa::KERNARG_SIZE_OFFSET: 2134 FourByteBuffer = DE.getU32(Cursor); 2135 KdStream << Indent << ".amdhsa_kernarg_size " 2136 << FourByteBuffer << '\n'; 2137 return MCDisassembler::Success; 2138 2139 case amdhsa::RESERVED0_OFFSET: 2140 // 4 reserved bytes, must be 0. 2141 ReservedBytes = DE.getBytes(Cursor, 4); 2142 for (int I = 0; I < 4; ++I) { 2143 if (ReservedBytes[I] != 0) { 2144 return MCDisassembler::Fail; 2145 } 2146 } 2147 return MCDisassembler::Success; 2148 2149 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 2150 // KERNEL_CODE_ENTRY_BYTE_OFFSET 2151 // So far no directive controls this for Code Object V3, so simply skip for 2152 // disassembly. 2153 DE.skip(Cursor, 8); 2154 return MCDisassembler::Success; 2155 2156 case amdhsa::RESERVED1_OFFSET: 2157 // 20 reserved bytes, must be 0. 2158 ReservedBytes = DE.getBytes(Cursor, 20); 2159 for (int I = 0; I < 20; ++I) { 2160 if (ReservedBytes[I] != 0) { 2161 return MCDisassembler::Fail; 2162 } 2163 } 2164 return MCDisassembler::Success; 2165 2166 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 2167 FourByteBuffer = DE.getU32(Cursor); 2168 return decodeCOMPUTE_PGM_RSRC3(FourByteBuffer, KdStream); 2169 2170 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 2171 FourByteBuffer = DE.getU32(Cursor); 2172 return decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream); 2173 2174 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 2175 FourByteBuffer = DE.getU32(Cursor); 2176 return decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream); 2177 2178 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 2179 using namespace amdhsa; 2180 TwoByteBuffer = DE.getU16(Cursor); 2181 2182 if (!hasArchitectedFlatScratch()) 2183 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 2184 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 2185 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 2186 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 2187 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 2188 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 2189 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 2190 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 2191 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 2192 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 2193 if (!hasArchitectedFlatScratch()) 2194 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 2195 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 2196 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 2197 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 2198 2199 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 2200 return MCDisassembler::Fail; 2201 2202 // Reserved for GFX9 2203 if (isGFX9() && 2204 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 2205 return MCDisassembler::Fail; 2206 } else if (isGFX10Plus()) { 2207 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 2208 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 2209 } 2210 2211 if (CodeObjectVersion >= AMDGPU::AMDHSA_COV5) 2212 PRINT_DIRECTIVE(".amdhsa_uses_dynamic_stack", 2213 KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK); 2214 2215 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) 2216 return MCDisassembler::Fail; 2217 2218 return MCDisassembler::Success; 2219 2220 case amdhsa::KERNARG_PRELOAD_OFFSET: 2221 using namespace amdhsa; 2222 TwoByteBuffer = DE.getU16(Cursor); 2223 if (TwoByteBuffer & KERNARG_PRELOAD_SPEC_LENGTH) { 2224 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_preload_length", 2225 KERNARG_PRELOAD_SPEC_LENGTH); 2226 } 2227 2228 if (TwoByteBuffer & KERNARG_PRELOAD_SPEC_OFFSET) { 2229 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_preload_offset", 2230 KERNARG_PRELOAD_SPEC_OFFSET); 2231 } 2232 return MCDisassembler::Success; 2233 2234 case amdhsa::RESERVED3_OFFSET: 2235 // 4 bytes from here are reserved, must be 0. 2236 ReservedBytes = DE.getBytes(Cursor, 4); 2237 for (int I = 0; I < 4; ++I) { 2238 if (ReservedBytes[I] != 0) 2239 return MCDisassembler::Fail; 2240 } 2241 return MCDisassembler::Success; 2242 2243 default: 2244 llvm_unreachable("Unhandled index. Case statements cover everything."); 2245 return MCDisassembler::Fail; 2246 } 2247 #undef PRINT_DIRECTIVE 2248 } 2249 2250 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( 2251 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 2252 // CP microcode requires the kernel descriptor to be 64 aligned. 2253 if (Bytes.size() != 64 || KdAddress % 64 != 0) 2254 return MCDisassembler::Fail; 2255 2256 // FIXME: We can't actually decode "in order" as is done below, as e.g. GFX10 2257 // requires us to know the setting of .amdhsa_wavefront_size32 in order to 2258 // accurately produce .amdhsa_next_free_vgpr, and they appear in the wrong 2259 // order. Workaround this by first looking up .amdhsa_wavefront_size32 here 2260 // when required. 2261 if (isGFX10Plus()) { 2262 uint16_t KernelCodeProperties = 2263 support::endian::read16(&Bytes[amdhsa::KERNEL_CODE_PROPERTIES_OFFSET], 2264 llvm::endianness::little); 2265 EnableWavefrontSize32 = 2266 AMDHSA_BITS_GET(KernelCodeProperties, 2267 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 2268 } 2269 2270 std::string Kd; 2271 raw_string_ostream KdStream(Kd); 2272 KdStream << ".amdhsa_kernel " << KdName << '\n'; 2273 2274 DataExtractor::Cursor C(0); 2275 while (C && C.tell() < Bytes.size()) { 2276 MCDisassembler::DecodeStatus Status = 2277 decodeKernelDescriptorDirective(C, Bytes, KdStream); 2278 2279 cantFail(C.takeError()); 2280 2281 if (Status == MCDisassembler::Fail) 2282 return MCDisassembler::Fail; 2283 } 2284 KdStream << ".end_amdhsa_kernel\n"; 2285 outs() << KdStream.str(); 2286 return MCDisassembler::Success; 2287 } 2288 2289 std::optional<MCDisassembler::DecodeStatus> 2290 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 2291 ArrayRef<uint8_t> Bytes, uint64_t Address, 2292 raw_ostream &CStream) const { 2293 // Right now only kernel descriptor needs to be handled. 2294 // We ignore all other symbols for target specific handling. 2295 // TODO: 2296 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 2297 // Object V2 and V3 when symbols are marked protected. 2298 2299 // amd_kernel_code_t for Code Object V2. 2300 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 2301 Size = 256; 2302 return MCDisassembler::Fail; 2303 } 2304 2305 // Code Object V3 kernel descriptors. 2306 StringRef Name = Symbol.Name; 2307 if (Symbol.Type == ELF::STT_OBJECT && Name.ends_with(StringRef(".kd"))) { 2308 Size = 64; // Size = 64 regardless of success or failure. 2309 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 2310 } 2311 return std::nullopt; 2312 } 2313 2314 //===----------------------------------------------------------------------===// 2315 // AMDGPUSymbolizer 2316 //===----------------------------------------------------------------------===// 2317 2318 // Try to find symbol name for specified label 2319 bool AMDGPUSymbolizer::tryAddingSymbolicOperand( 2320 MCInst &Inst, raw_ostream & /*cStream*/, int64_t Value, 2321 uint64_t /*Address*/, bool IsBranch, uint64_t /*Offset*/, 2322 uint64_t /*OpSize*/, uint64_t /*InstSize*/) { 2323 2324 if (!IsBranch) { 2325 return false; 2326 } 2327 2328 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 2329 if (!Symbols) 2330 return false; 2331 2332 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { 2333 return Val.Addr == static_cast<uint64_t>(Value) && 2334 Val.Type == ELF::STT_NOTYPE; 2335 }); 2336 if (Result != Symbols->end()) { 2337 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 2338 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 2339 Inst.addOperand(MCOperand::createExpr(Add)); 2340 return true; 2341 } 2342 // Add to list of referenced addresses, so caller can synthesize a label. 2343 ReferencedAddresses.push_back(static_cast<uint64_t>(Value)); 2344 return false; 2345 } 2346 2347 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 2348 int64_t Value, 2349 uint64_t Address) { 2350 llvm_unreachable("unimplemented"); 2351 } 2352 2353 //===----------------------------------------------------------------------===// 2354 // Initialization 2355 //===----------------------------------------------------------------------===// 2356 2357 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 2358 LLVMOpInfoCallback /*GetOpInfo*/, 2359 LLVMSymbolLookupCallback /*SymbolLookUp*/, 2360 void *DisInfo, 2361 MCContext *Ctx, 2362 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 2363 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 2364 } 2365 2366 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 2367 const MCSubtargetInfo &STI, 2368 MCContext &Ctx) { 2369 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 2370 } 2371 2372 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 2373 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 2374 createAMDGPUDisassembler); 2375 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 2376 createAMDGPUSymbolizer); 2377 } 2378