1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 //===----------------------------------------------------------------------===// 11 // 12 /// \file 13 /// 14 /// This file contains definition for AMDGPU ISA disassembler 15 // 16 //===----------------------------------------------------------------------===// 17 18 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 19 20 #include "Disassembler/AMDGPUDisassembler.h" 21 #include "AMDGPU.h" 22 #include "AMDGPURegisterInfo.h" 23 #include "SIDefines.h" 24 #include "Utils/AMDGPUBaseInfo.h" 25 #include "llvm-c/Disassembler.h" 26 #include "llvm/ADT/APInt.h" 27 #include "llvm/ADT/ArrayRef.h" 28 #include "llvm/ADT/Twine.h" 29 #include "llvm/BinaryFormat/ELF.h" 30 #include "llvm/MC/MCContext.h" 31 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 32 #include "llvm/MC/MCExpr.h" 33 #include "llvm/MC/MCFixedLenDisassembler.h" 34 #include "llvm/MC/MCInst.h" 35 #include "llvm/MC/MCSubtargetInfo.h" 36 #include "llvm/Support/Endian.h" 37 #include "llvm/Support/ErrorHandling.h" 38 #include "llvm/Support/MathExtras.h" 39 #include "llvm/Support/TargetRegistry.h" 40 #include "llvm/Support/raw_ostream.h" 41 #include <algorithm> 42 #include <cassert> 43 #include <cstddef> 44 #include <cstdint> 45 #include <iterator> 46 #include <tuple> 47 #include <vector> 48 49 using namespace llvm; 50 51 #define DEBUG_TYPE "amdgpu-disassembler" 52 53 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 54 55 inline static MCDisassembler::DecodeStatus 56 addOperand(MCInst &Inst, const MCOperand& Opnd) { 57 Inst.addOperand(Opnd); 58 return Opnd.isValid() ? 59 MCDisassembler::Success : 60 MCDisassembler::SoftFail; 61 } 62 63 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 64 uint16_t NameIdx) { 65 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 66 if (OpIdx != -1) { 67 auto I = MI.begin(); 68 std::advance(I, OpIdx); 69 MI.insert(I, Op); 70 } 71 return OpIdx; 72 } 73 74 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, 75 uint64_t Addr, const void *Decoder) { 76 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 77 78 APInt SignedOffset(18, Imm * 4, true); 79 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 80 81 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2)) 82 return MCDisassembler::Success; 83 return addOperand(Inst, MCOperand::createImm(Imm)); 84 } 85 86 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 87 static DecodeStatus StaticDecoderName(MCInst &Inst, \ 88 unsigned Imm, \ 89 uint64_t /*Addr*/, \ 90 const void *Decoder) { \ 91 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \ 92 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 93 } 94 95 #define DECODE_OPERAND_REG(RegClass) \ 96 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass) 97 98 DECODE_OPERAND_REG(VGPR_32) 99 DECODE_OPERAND_REG(VS_32) 100 DECODE_OPERAND_REG(VS_64) 101 DECODE_OPERAND_REG(VS_128) 102 103 DECODE_OPERAND_REG(VReg_64) 104 DECODE_OPERAND_REG(VReg_96) 105 DECODE_OPERAND_REG(VReg_128) 106 107 DECODE_OPERAND_REG(SReg_32) 108 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC) 109 DECODE_OPERAND_REG(SReg_32_XEXEC_HI) 110 DECODE_OPERAND_REG(SReg_64) 111 DECODE_OPERAND_REG(SReg_64_XEXEC) 112 DECODE_OPERAND_REG(SReg_128) 113 DECODE_OPERAND_REG(SReg_256) 114 DECODE_OPERAND_REG(SReg_512) 115 116 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, 117 unsigned Imm, 118 uint64_t Addr, 119 const void *Decoder) { 120 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 121 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 122 } 123 124 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, 125 unsigned Imm, 126 uint64_t Addr, 127 const void *Decoder) { 128 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 129 return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm)); 130 } 131 132 #define DECODE_SDWA(DecName) \ 133 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 134 135 DECODE_SDWA(Src32) 136 DECODE_SDWA(Src16) 137 DECODE_SDWA(VopcDst) 138 139 #include "AMDGPUGenDisassemblerTables.inc" 140 141 //===----------------------------------------------------------------------===// 142 // 143 //===----------------------------------------------------------------------===// 144 145 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 146 assert(Bytes.size() >= sizeof(T)); 147 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data()); 148 Bytes = Bytes.slice(sizeof(T)); 149 return Res; 150 } 151 152 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table, 153 MCInst &MI, 154 uint64_t Inst, 155 uint64_t Address) const { 156 assert(MI.getOpcode() == 0); 157 assert(MI.getNumOperands() == 0); 158 MCInst TmpInst; 159 HasLiteral = false; 160 const auto SavedBytes = Bytes; 161 if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) { 162 MI = TmpInst; 163 return MCDisassembler::Success; 164 } 165 Bytes = SavedBytes; 166 return MCDisassembler::Fail; 167 } 168 169 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 170 ArrayRef<uint8_t> Bytes_, 171 uint64_t Address, 172 raw_ostream &WS, 173 raw_ostream &CS) const { 174 CommentStream = &CS; 175 bool IsSDWA = false; 176 177 // ToDo: AMDGPUDisassembler supports only VI ISA. 178 if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding]) 179 report_fatal_error("Disassembly not yet supported for subtarget"); 180 181 const unsigned MaxInstBytesNum = (std::min)((size_t)8, Bytes_.size()); 182 Bytes = Bytes_.slice(0, MaxInstBytesNum); 183 184 DecodeStatus Res = MCDisassembler::Fail; 185 do { 186 // ToDo: better to switch encoding length using some bit predicate 187 // but it is unknown yet, so try all we can 188 189 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 190 // encodings 191 if (Bytes.size() >= 8) { 192 const uint64_t QW = eatBytes<uint64_t>(Bytes); 193 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address); 194 if (Res) break; 195 196 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address); 197 if (Res) { IsSDWA = true; break; } 198 199 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address); 200 if (Res) { IsSDWA = true; break; } 201 202 if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) { 203 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address); 204 if (Res) break; 205 } 206 } 207 208 // Reinitialize Bytes as DPP64 could have eaten too much 209 Bytes = Bytes_.slice(0, MaxInstBytesNum); 210 211 // Try decode 32-bit instruction 212 if (Bytes.size() < 4) break; 213 const uint32_t DW = eatBytes<uint32_t>(Bytes); 214 Res = tryDecodeInst(DecoderTableVI32, MI, DW, Address); 215 if (Res) break; 216 217 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address); 218 if (Res) break; 219 220 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address); 221 if (Res) break; 222 223 if (Bytes.size() < 4) break; 224 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 225 Res = tryDecodeInst(DecoderTableVI64, MI, QW, Address); 226 if (Res) break; 227 228 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address); 229 if (Res) break; 230 231 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address); 232 } while (false); 233 234 if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi || 235 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_si || 236 MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi)) { 237 // Insert dummy unused src2_modifiers. 238 insertNamedMCOperand(MI, MCOperand::createImm(0), 239 AMDGPU::OpName::src2_modifiers); 240 } 241 242 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 243 Res = convertMIMGInst(MI); 244 } 245 246 if (Res && IsSDWA) 247 Res = convertSDWAInst(MI); 248 249 Size = Res ? (MaxInstBytesNum - Bytes.size()) : 0; 250 return Res; 251 } 252 253 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 254 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9]) { 255 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1) 256 // VOPC - insert clamp 257 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 258 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 259 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 260 if (SDst != -1) { 261 // VOPC - insert VCC register as sdst 262 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 263 AMDGPU::OpName::sdst); 264 } else { 265 // VOP1/2 - insert omod if present in instruction 266 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 267 } 268 } 269 return MCDisassembler::Success; 270 } 271 272 // Note that MIMG format provides no information about VADDR size. 273 // Consequently, decoded instructions always show address 274 // as if it has 1 dword, which could be not really so. 275 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 276 277 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4) { 278 return MCDisassembler::Success; 279 } 280 281 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 282 AMDGPU::OpName::vdst); 283 284 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 285 AMDGPU::OpName::vdata); 286 287 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 288 AMDGPU::OpName::dmask); 289 290 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 291 AMDGPU::OpName::tfe); 292 293 assert(VDataIdx != -1); 294 assert(DMaskIdx != -1); 295 assert(TFEIdx != -1); 296 297 bool IsAtomic = (VDstIdx != -1); 298 299 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 300 if (DMask == 0) 301 return MCDisassembler::Success; 302 303 unsigned DstSize = countPopulation(DMask); 304 if (DstSize == 1) 305 return MCDisassembler::Success; 306 307 bool D16 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::D16; 308 if (D16 && AMDGPU::hasPackedD16(STI)) { 309 DstSize = (DstSize + 1) / 2; 310 } 311 312 // FIXME: Add tfe support 313 if (MI.getOperand(TFEIdx).getImm()) 314 return MCDisassembler::Success; 315 316 int NewOpcode = -1; 317 318 if (IsAtomic) { 319 if (DMask == 0x1 || DMask == 0x3 || DMask == 0xF) { 320 NewOpcode = AMDGPU::getMaskedMIMGAtomicOp(*MCII, MI.getOpcode(), DstSize); 321 } 322 if (NewOpcode == -1) return MCDisassembler::Success; 323 } else { 324 NewOpcode = AMDGPU::getMaskedMIMGOp(*MCII, MI.getOpcode(), DstSize); 325 assert(NewOpcode != -1 && "could not find matching mimg channel instruction"); 326 } 327 328 auto RCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; 329 330 // Get first subregister of VData 331 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 332 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 333 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 334 335 // Widen the register to the correct number of enabled channels. 336 auto NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 337 &MRI.getRegClass(RCID)); 338 if (NewVdata == AMDGPU::NoRegister) { 339 // It's possible to encode this such that the low register + enabled 340 // components exceeds the register count. 341 return MCDisassembler::Success; 342 } 343 344 MI.setOpcode(NewOpcode); 345 // vaddr will be always appear as a single VGPR. This will look different than 346 // how it is usually emitted because the number of register components is not 347 // in the instruction encoding. 348 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 349 350 if (IsAtomic) { 351 // Atomic operations have an additional operand (a copy of data) 352 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 353 } 354 355 return MCDisassembler::Success; 356 } 357 358 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 359 return getContext().getRegisterInfo()-> 360 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 361 } 362 363 inline 364 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 365 const Twine& ErrMsg) const { 366 *CommentStream << "Error: " + ErrMsg; 367 368 // ToDo: add support for error operands to MCInst.h 369 // return MCOperand::createError(V); 370 return MCOperand(); 371 } 372 373 inline 374 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 375 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 376 } 377 378 inline 379 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 380 unsigned Val) const { 381 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 382 if (Val >= RegCl.getNumRegs()) 383 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 384 ": unknown register " + Twine(Val)); 385 return createRegOperand(RegCl.getRegister(Val)); 386 } 387 388 inline 389 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 390 unsigned Val) const { 391 // ToDo: SI/CI have 104 SGPRs, VI - 102 392 // Valery: here we accepting as much as we can, let assembler sort it out 393 int shift = 0; 394 switch (SRegClassID) { 395 case AMDGPU::SGPR_32RegClassID: 396 case AMDGPU::TTMP_32RegClassID: 397 break; 398 case AMDGPU::SGPR_64RegClassID: 399 case AMDGPU::TTMP_64RegClassID: 400 shift = 1; 401 break; 402 case AMDGPU::SGPR_128RegClassID: 403 case AMDGPU::TTMP_128RegClassID: 404 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 405 // this bundle? 406 case AMDGPU::SGPR_256RegClassID: 407 case AMDGPU::TTMP_256RegClassID: 408 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 409 // this bundle? 410 case AMDGPU::SGPR_512RegClassID: 411 case AMDGPU::TTMP_512RegClassID: 412 shift = 2; 413 break; 414 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 415 // this bundle? 416 default: 417 llvm_unreachable("unhandled register class"); 418 } 419 420 if (Val % (1 << shift)) { 421 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 422 << ": scalar reg isn't aligned " << Val; 423 } 424 425 return createRegOperand(SRegClassID, Val >> shift); 426 } 427 428 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { 429 return decodeSrcOp(OPW32, Val); 430 } 431 432 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { 433 return decodeSrcOp(OPW64, Val); 434 } 435 436 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const { 437 return decodeSrcOp(OPW128, Val); 438 } 439 440 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const { 441 return decodeSrcOp(OPW16, Val); 442 } 443 444 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const { 445 return decodeSrcOp(OPWV216, Val); 446 } 447 448 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { 449 // Some instructions have operand restrictions beyond what the encoding 450 // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra 451 // high bit. 452 Val &= 255; 453 454 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); 455 } 456 457 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { 458 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); 459 } 460 461 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { 462 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); 463 } 464 465 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { 466 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); 467 } 468 469 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { 470 // table-gen generated disassembler doesn't care about operand types 471 // leaving only registry class so SSrc_32 operand turns into SReg_32 472 // and therefore we accept immediates and literals here as well 473 return decodeSrcOp(OPW32, Val); 474 } 475 476 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC( 477 unsigned Val) const { 478 // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI 479 return decodeOperand_SReg_32(Val); 480 } 481 482 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI( 483 unsigned Val) const { 484 // SReg_32_XM0 is SReg_32 without EXEC_HI 485 return decodeOperand_SReg_32(Val); 486 } 487 488 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { 489 return decodeSrcOp(OPW64, Val); 490 } 491 492 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const { 493 return decodeSrcOp(OPW64, Val); 494 } 495 496 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { 497 return decodeSrcOp(OPW128, Val); 498 } 499 500 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { 501 return decodeDstOp(OPW256, Val); 502 } 503 504 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { 505 return decodeDstOp(OPW512, Val); 506 } 507 508 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { 509 // For now all literal constants are supposed to be unsigned integer 510 // ToDo: deal with signed/unsigned 64-bit integer constants 511 // ToDo: deal with float/double constants 512 if (!HasLiteral) { 513 if (Bytes.size() < 4) { 514 return errOperand(0, "cannot read literal, inst bytes left " + 515 Twine(Bytes.size())); 516 } 517 HasLiteral = true; 518 Literal = eatBytes<uint32_t>(Bytes); 519 } 520 return MCOperand::createImm(Literal); 521 } 522 523 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 524 using namespace AMDGPU::EncValues; 525 526 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 527 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 528 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 529 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 530 // Cast prevents negative overflow. 531 } 532 533 static int64_t getInlineImmVal32(unsigned Imm) { 534 switch (Imm) { 535 case 240: 536 return FloatToBits(0.5f); 537 case 241: 538 return FloatToBits(-0.5f); 539 case 242: 540 return FloatToBits(1.0f); 541 case 243: 542 return FloatToBits(-1.0f); 543 case 244: 544 return FloatToBits(2.0f); 545 case 245: 546 return FloatToBits(-2.0f); 547 case 246: 548 return FloatToBits(4.0f); 549 case 247: 550 return FloatToBits(-4.0f); 551 case 248: // 1 / (2 * PI) 552 return 0x3e22f983; 553 default: 554 llvm_unreachable("invalid fp inline imm"); 555 } 556 } 557 558 static int64_t getInlineImmVal64(unsigned Imm) { 559 switch (Imm) { 560 case 240: 561 return DoubleToBits(0.5); 562 case 241: 563 return DoubleToBits(-0.5); 564 case 242: 565 return DoubleToBits(1.0); 566 case 243: 567 return DoubleToBits(-1.0); 568 case 244: 569 return DoubleToBits(2.0); 570 case 245: 571 return DoubleToBits(-2.0); 572 case 246: 573 return DoubleToBits(4.0); 574 case 247: 575 return DoubleToBits(-4.0); 576 case 248: // 1 / (2 * PI) 577 return 0x3fc45f306dc9c882; 578 default: 579 llvm_unreachable("invalid fp inline imm"); 580 } 581 } 582 583 static int64_t getInlineImmVal16(unsigned Imm) { 584 switch (Imm) { 585 case 240: 586 return 0x3800; 587 case 241: 588 return 0xB800; 589 case 242: 590 return 0x3C00; 591 case 243: 592 return 0xBC00; 593 case 244: 594 return 0x4000; 595 case 245: 596 return 0xC000; 597 case 246: 598 return 0x4400; 599 case 247: 600 return 0xC400; 601 case 248: // 1 / (2 * PI) 602 return 0x3118; 603 default: 604 llvm_unreachable("invalid fp inline imm"); 605 } 606 } 607 608 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) { 609 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 610 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 611 612 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 613 switch (Width) { 614 case OPW32: 615 return MCOperand::createImm(getInlineImmVal32(Imm)); 616 case OPW64: 617 return MCOperand::createImm(getInlineImmVal64(Imm)); 618 case OPW16: 619 case OPWV216: 620 return MCOperand::createImm(getInlineImmVal16(Imm)); 621 default: 622 llvm_unreachable("implement me"); 623 } 624 } 625 626 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 627 using namespace AMDGPU; 628 629 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 630 switch (Width) { 631 default: // fall 632 case OPW32: 633 case OPW16: 634 case OPWV216: 635 return VGPR_32RegClassID; 636 case OPW64: return VReg_64RegClassID; 637 case OPW128: return VReg_128RegClassID; 638 } 639 } 640 641 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 642 using namespace AMDGPU; 643 644 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 645 switch (Width) { 646 default: // fall 647 case OPW32: 648 case OPW16: 649 case OPWV216: 650 return SGPR_32RegClassID; 651 case OPW64: return SGPR_64RegClassID; 652 case OPW128: return SGPR_128RegClassID; 653 case OPW256: return SGPR_256RegClassID; 654 case OPW512: return SGPR_512RegClassID; 655 } 656 } 657 658 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 659 using namespace AMDGPU; 660 661 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 662 switch (Width) { 663 default: // fall 664 case OPW32: 665 case OPW16: 666 case OPWV216: 667 return TTMP_32RegClassID; 668 case OPW64: return TTMP_64RegClassID; 669 case OPW128: return TTMP_128RegClassID; 670 case OPW256: return TTMP_256RegClassID; 671 case OPW512: return TTMP_512RegClassID; 672 } 673 } 674 675 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 676 using namespace AMDGPU::EncValues; 677 678 unsigned TTmpMin = isGFX9() ? TTMP_GFX9_MIN : TTMP_VI_MIN; 679 unsigned TTmpMax = isGFX9() ? TTMP_GFX9_MAX : TTMP_VI_MAX; 680 681 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 682 } 683 684 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const { 685 using namespace AMDGPU::EncValues; 686 687 assert(Val < 512); // enum9 688 689 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 690 return createRegOperand(getVgprClassId(Width), Val - VGPR_MIN); 691 } 692 if (Val <= SGPR_MAX) { 693 assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning. 694 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 695 } 696 697 int TTmpIdx = getTTmpIdx(Val); 698 if (TTmpIdx >= 0) { 699 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 700 } 701 702 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 703 return decodeIntImmed(Val); 704 705 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 706 return decodeFPImmed(Width, Val); 707 708 if (Val == LITERAL_CONST) 709 return decodeLiteralConstant(); 710 711 switch (Width) { 712 case OPW32: 713 case OPW16: 714 case OPWV216: 715 return decodeSpecialReg32(Val); 716 case OPW64: 717 return decodeSpecialReg64(Val); 718 default: 719 llvm_unreachable("unexpected immediate type"); 720 } 721 } 722 723 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const { 724 using namespace AMDGPU::EncValues; 725 726 assert(Val < 128); 727 assert(Width == OPW256 || Width == OPW512); 728 729 if (Val <= SGPR_MAX) { 730 assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning. 731 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 732 } 733 734 int TTmpIdx = getTTmpIdx(Val); 735 if (TTmpIdx >= 0) { 736 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 737 } 738 739 llvm_unreachable("unknown dst register"); 740 } 741 742 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 743 using namespace AMDGPU; 744 745 switch (Val) { 746 case 102: return createRegOperand(FLAT_SCR_LO); 747 case 103: return createRegOperand(FLAT_SCR_HI); 748 case 104: return createRegOperand(XNACK_MASK_LO); 749 case 105: return createRegOperand(XNACK_MASK_HI); 750 case 106: return createRegOperand(VCC_LO); 751 case 107: return createRegOperand(VCC_HI); 752 case 108: assert(!isGFX9()); return createRegOperand(TBA_LO); 753 case 109: assert(!isGFX9()); return createRegOperand(TBA_HI); 754 case 110: assert(!isGFX9()); return createRegOperand(TMA_LO); 755 case 111: assert(!isGFX9()); return createRegOperand(TMA_HI); 756 case 124: return createRegOperand(M0); 757 case 126: return createRegOperand(EXEC_LO); 758 case 127: return createRegOperand(EXEC_HI); 759 case 235: return createRegOperand(SRC_SHARED_BASE); 760 case 236: return createRegOperand(SRC_SHARED_LIMIT); 761 case 237: return createRegOperand(SRC_PRIVATE_BASE); 762 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 763 // TODO: SRC_POPS_EXITING_WAVE_ID 764 // ToDo: no support for vccz register 765 case 251: break; 766 // ToDo: no support for execz register 767 case 252: break; 768 case 253: return createRegOperand(SCC); 769 default: break; 770 } 771 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 772 } 773 774 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 775 using namespace AMDGPU; 776 777 switch (Val) { 778 case 102: return createRegOperand(FLAT_SCR); 779 case 104: return createRegOperand(XNACK_MASK); 780 case 106: return createRegOperand(VCC); 781 case 108: assert(!isGFX9()); return createRegOperand(TBA); 782 case 110: assert(!isGFX9()); return createRegOperand(TMA); 783 case 126: return createRegOperand(EXEC); 784 default: break; 785 } 786 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 787 } 788 789 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 790 const unsigned Val) const { 791 using namespace AMDGPU::SDWA; 792 using namespace AMDGPU::EncValues; 793 794 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9]) { 795 // XXX: static_cast<int> is needed to avoid stupid warning: 796 // compare with unsigned is always true 797 if (SDWA9EncValues::SRC_VGPR_MIN <= static_cast<int>(Val) && 798 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 799 return createRegOperand(getVgprClassId(Width), 800 Val - SDWA9EncValues::SRC_VGPR_MIN); 801 } 802 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 803 Val <= SDWA9EncValues::SRC_SGPR_MAX) { 804 return createSRegOperand(getSgprClassId(Width), 805 Val - SDWA9EncValues::SRC_SGPR_MIN); 806 } 807 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 808 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 809 return createSRegOperand(getTtmpClassId(Width), 810 Val - SDWA9EncValues::SRC_TTMP_MIN); 811 } 812 813 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 814 815 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 816 return decodeIntImmed(SVal); 817 818 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 819 return decodeFPImmed(Width, SVal); 820 821 return decodeSpecialReg32(SVal); 822 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 823 return createRegOperand(getVgprClassId(Width), Val); 824 } 825 llvm_unreachable("unsupported target"); 826 } 827 828 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 829 return decodeSDWASrc(OPW16, Val); 830 } 831 832 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 833 return decodeSDWASrc(OPW32, Val); 834 } 835 836 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 837 using namespace AMDGPU::SDWA; 838 839 assert(STI.getFeatureBits()[AMDGPU::FeatureGFX9] && 840 "SDWAVopcDst should be present only on GFX9"); 841 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 842 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 843 844 int TTmpIdx = getTTmpIdx(Val); 845 if (TTmpIdx >= 0) { 846 return createSRegOperand(getTtmpClassId(OPW64), TTmpIdx); 847 } else if (Val > AMDGPU::EncValues::SGPR_MAX) { 848 return decodeSpecialReg64(Val); 849 } else { 850 return createSRegOperand(getSgprClassId(OPW64), Val); 851 } 852 } else { 853 return createRegOperand(AMDGPU::VCC); 854 } 855 } 856 857 bool AMDGPUDisassembler::isVI() const { 858 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]; 859 } 860 861 bool AMDGPUDisassembler::isGFX9() const { 862 return STI.getFeatureBits()[AMDGPU::FeatureGFX9]; 863 } 864 865 //===----------------------------------------------------------------------===// 866 // AMDGPUSymbolizer 867 //===----------------------------------------------------------------------===// 868 869 // Try to find symbol name for specified label 870 bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst, 871 raw_ostream &/*cStream*/, int64_t Value, 872 uint64_t /*Address*/, bool IsBranch, 873 uint64_t /*Offset*/, uint64_t /*InstSize*/) { 874 using SymbolInfoTy = std::tuple<uint64_t, StringRef, uint8_t>; 875 using SectionSymbolsTy = std::vector<SymbolInfoTy>; 876 877 if (!IsBranch) { 878 return false; 879 } 880 881 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 882 auto Result = std::find_if(Symbols->begin(), Symbols->end(), 883 [Value](const SymbolInfoTy& Val) { 884 return std::get<0>(Val) == static_cast<uint64_t>(Value) 885 && std::get<2>(Val) == ELF::STT_NOTYPE; 886 }); 887 if (Result != Symbols->end()) { 888 auto *Sym = Ctx.getOrCreateSymbol(std::get<1>(*Result)); 889 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 890 Inst.addOperand(MCOperand::createExpr(Add)); 891 return true; 892 } 893 return false; 894 } 895 896 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 897 int64_t Value, 898 uint64_t Address) { 899 llvm_unreachable("unimplemented"); 900 } 901 902 //===----------------------------------------------------------------------===// 903 // Initialization 904 //===----------------------------------------------------------------------===// 905 906 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 907 LLVMOpInfoCallback /*GetOpInfo*/, 908 LLVMSymbolLookupCallback /*SymbolLookUp*/, 909 void *DisInfo, 910 MCContext *Ctx, 911 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 912 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 913 } 914 915 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 916 const MCSubtargetInfo &STI, 917 MCContext &Ctx) { 918 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 919 } 920 921 extern "C" void LLVMInitializeAMDGPUDisassembler() { 922 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 923 createAMDGPUDisassembler); 924 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 925 createAMDGPUSymbolizer); 926 } 927