xref: /llvm-project/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp (revision d625b4b081f9ea2d96d5bdfc1f05925b30d8b1a3) 
1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //===----------------------------------------------------------------------===//
10 //
11 /// \file
12 ///
13 /// This file contains definition for AMDGPU ISA disassembler
14 //
15 //===----------------------------------------------------------------------===//
16 
17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)?
18 
19 #include "Disassembler/AMDGPUDisassembler.h"
20 #include "AMDGPU.h"
21 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
22 #include "SIDefines.h"
23 #include "TargetInfo/AMDGPUTargetInfo.h"
24 #include "Utils/AMDGPUBaseInfo.h"
25 #include "llvm-c/Disassembler.h"
26 #include "llvm/ADT/APInt.h"
27 #include "llvm/ADT/ArrayRef.h"
28 #include "llvm/ADT/Twine.h"
29 #include "llvm/BinaryFormat/ELF.h"
30 #include "llvm/MC/MCAsmInfo.h"
31 #include "llvm/MC/MCContext.h"
32 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
33 #include "llvm/MC/MCExpr.h"
34 #include "llvm/MC/MCFixedLenDisassembler.h"
35 #include "llvm/MC/MCInst.h"
36 #include "llvm/MC/MCSubtargetInfo.h"
37 #include "llvm/Support/Endian.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/TargetRegistry.h"
41 #include "llvm/Support/raw_ostream.h"
42 #include <algorithm>
43 #include <cassert>
44 #include <cstddef>
45 #include <cstdint>
46 #include <iterator>
47 #include <tuple>
48 #include <vector>
49 
50 using namespace llvm;
51 
52 #define DEBUG_TYPE "amdgpu-disassembler"
53 
54 #define SGPR_MAX (isGFX10() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \
55                             : AMDGPU::EncValues::SGPR_MAX_SI)
56 
57 using DecodeStatus = llvm::MCDisassembler::DecodeStatus;
58 
59 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI,
60                                        MCContext &Ctx,
61                                        MCInstrInfo const *MCII) :
62   MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()),
63   TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) {
64 
65   // ToDo: AMDGPUDisassembler supports only VI ISA.
66   if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10())
67     report_fatal_error("Disassembly not yet supported for subtarget");
68 }
69 
70 inline static MCDisassembler::DecodeStatus
71 addOperand(MCInst &Inst, const MCOperand& Opnd) {
72   Inst.addOperand(Opnd);
73   return Opnd.isValid() ?
74     MCDisassembler::Success :
75     MCDisassembler::Fail;
76 }
77 
78 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op,
79                                 uint16_t NameIdx) {
80   int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx);
81   if (OpIdx != -1) {
82     auto I = MI.begin();
83     std::advance(I, OpIdx);
84     MI.insert(I, Op);
85   }
86   return OpIdx;
87 }
88 
89 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm,
90                                        uint64_t Addr, const void *Decoder) {
91   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
92 
93   // Our branches take a simm16, but we need two extra bits to account for the
94   // factor of 4.
95   APInt SignedOffset(18, Imm * 4, true);
96   int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue();
97 
98   if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2))
99     return MCDisassembler::Success;
100   return addOperand(Inst, MCOperand::createImm(Imm));
101 }
102 
103 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val,
104                                   uint64_t Addr, const void *Decoder) {
105   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
106   return addOperand(Inst, DAsm->decodeBoolReg(Val));
107 }
108 
109 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \
110 static DecodeStatus StaticDecoderName(MCInst &Inst, \
111                                        unsigned Imm, \
112                                        uint64_t /*Addr*/, \
113                                        const void *Decoder) { \
114   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \
115   return addOperand(Inst, DAsm->DecoderName(Imm)); \
116 }
117 
118 #define DECODE_OPERAND_REG(RegClass) \
119 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass)
120 
121 DECODE_OPERAND_REG(VGPR_32)
122 DECODE_OPERAND_REG(VRegOrLds_32)
123 DECODE_OPERAND_REG(VS_32)
124 DECODE_OPERAND_REG(VS_64)
125 DECODE_OPERAND_REG(VS_128)
126 
127 DECODE_OPERAND_REG(VReg_64)
128 DECODE_OPERAND_REG(VReg_96)
129 DECODE_OPERAND_REG(VReg_128)
130 
131 DECODE_OPERAND_REG(SReg_32)
132 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC)
133 DECODE_OPERAND_REG(SReg_32_XEXEC_HI)
134 DECODE_OPERAND_REG(SRegOrLds_32)
135 DECODE_OPERAND_REG(SReg_64)
136 DECODE_OPERAND_REG(SReg_64_XEXEC)
137 DECODE_OPERAND_REG(SReg_128)
138 DECODE_OPERAND_REG(SReg_256)
139 DECODE_OPERAND_REG(SReg_512)
140 
141 DECODE_OPERAND_REG(AGPR_32)
142 DECODE_OPERAND_REG(AReg_128)
143 DECODE_OPERAND_REG(AReg_512)
144 DECODE_OPERAND_REG(AReg_1024)
145 DECODE_OPERAND_REG(AV_32)
146 DECODE_OPERAND_REG(AV_64)
147 
148 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst,
149                                          unsigned Imm,
150                                          uint64_t Addr,
151                                          const void *Decoder) {
152   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
153   return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm));
154 }
155 
156 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst,
157                                          unsigned Imm,
158                                          uint64_t Addr,
159                                          const void *Decoder) {
160   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
161   return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm));
162 }
163 
164 static DecodeStatus decodeOperand_VS_16(MCInst &Inst,
165                                         unsigned Imm,
166                                         uint64_t Addr,
167                                         const void *Decoder) {
168   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
169   return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm));
170 }
171 
172 static DecodeStatus decodeOperand_VS_32(MCInst &Inst,
173                                         unsigned Imm,
174                                         uint64_t Addr,
175                                         const void *Decoder) {
176   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
177   return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm));
178 }
179 
180 static DecodeStatus decodeOperand_AReg_128(MCInst &Inst,
181                                            unsigned Imm,
182                                            uint64_t Addr,
183                                            const void *Decoder) {
184   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
185   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512));
186 }
187 
188 static DecodeStatus decodeOperand_AReg_512(MCInst &Inst,
189                                            unsigned Imm,
190                                            uint64_t Addr,
191                                            const void *Decoder) {
192   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
193   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512));
194 }
195 
196 static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst,
197                                             unsigned Imm,
198                                             uint64_t Addr,
199                                             const void *Decoder) {
200   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
201   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512));
202 }
203 
204 static DecodeStatus decodeOperand_SReg_32(MCInst &Inst,
205                                           unsigned Imm,
206                                           uint64_t Addr,
207                                           const void *Decoder) {
208   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
209   return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm));
210 }
211 
212 static DecodeStatus decodeOperand_VGPR_32(MCInst &Inst,
213                                          unsigned Imm,
214                                          uint64_t Addr,
215                                          const void *Decoder) {
216   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
217   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW32, Imm));
218 }
219 
220 #define DECODE_SDWA(DecName) \
221 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName)
222 
223 DECODE_SDWA(Src32)
224 DECODE_SDWA(Src16)
225 DECODE_SDWA(VopcDst)
226 
227 #include "AMDGPUGenDisassemblerTables.inc"
228 
229 //===----------------------------------------------------------------------===//
230 //
231 //===----------------------------------------------------------------------===//
232 
233 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) {
234   assert(Bytes.size() >= sizeof(T));
235   const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data());
236   Bytes = Bytes.slice(sizeof(T));
237   return Res;
238 }
239 
240 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table,
241                                                MCInst &MI,
242                                                uint64_t Inst,
243                                                uint64_t Address) const {
244   assert(MI.getOpcode() == 0);
245   assert(MI.getNumOperands() == 0);
246   MCInst TmpInst;
247   HasLiteral = false;
248   const auto SavedBytes = Bytes;
249   if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) {
250     MI = TmpInst;
251     return MCDisassembler::Success;
252   }
253   Bytes = SavedBytes;
254   return MCDisassembler::Fail;
255 }
256 
257 static bool isValidDPP8(const MCInst &MI) {
258   using namespace llvm::AMDGPU::DPP;
259   int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi);
260   assert(FiIdx != -1);
261   if ((unsigned)FiIdx >= MI.getNumOperands())
262     return false;
263   unsigned Fi = MI.getOperand(FiIdx).getImm();
264   return Fi == DPP8_FI_0 || Fi == DPP8_FI_1;
265 }
266 
267 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
268                                                 ArrayRef<uint8_t> Bytes_,
269                                                 uint64_t Address,
270                                                 raw_ostream &CS) const {
271   CommentStream = &CS;
272   bool IsSDWA = false;
273 
274   unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size());
275   Bytes = Bytes_.slice(0, MaxInstBytesNum);
276 
277   DecodeStatus Res = MCDisassembler::Fail;
278   do {
279     // ToDo: better to switch encoding length using some bit predicate
280     // but it is unknown yet, so try all we can
281 
282     // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2
283     // encodings
284     if (Bytes.size() >= 8) {
285       const uint64_t QW = eatBytes<uint64_t>(Bytes);
286 
287       Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address);
288       if (Res && convertDPP8Inst(MI) == MCDisassembler::Success)
289         break;
290 
291       MI = MCInst(); // clear
292 
293       Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address);
294       if (Res) break;
295 
296       Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address);
297       if (Res) { IsSDWA = true;  break; }
298 
299       Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address);
300       if (Res) { IsSDWA = true;  break; }
301 
302       Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address);
303       if (Res) { IsSDWA = true;  break; }
304 
305       if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) {
306         Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address);
307         if (Res)
308           break;
309       }
310 
311       // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and
312       // v_mad_mixhi_f16 for FMA variants. Try to decode using this special
313       // table first so we print the correct name.
314       if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) {
315         Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address);
316         if (Res)
317           break;
318       }
319     }
320 
321     // Reinitialize Bytes as DPP64 could have eaten too much
322     Bytes = Bytes_.slice(0, MaxInstBytesNum);
323 
324     // Try decode 32-bit instruction
325     if (Bytes.size() < 4) break;
326     const uint32_t DW = eatBytes<uint32_t>(Bytes);
327     Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address);
328     if (Res) break;
329 
330     Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address);
331     if (Res) break;
332 
333     Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address);
334     if (Res) break;
335 
336     Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address);
337     if (Res) break;
338 
339     if (Bytes.size() < 4) break;
340     const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW;
341     Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address);
342     if (Res) break;
343 
344     Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address);
345     if (Res) break;
346 
347     Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address);
348     if (Res) break;
349 
350     Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address);
351   } while (false);
352 
353   if (Res && (MaxInstBytesNum - Bytes.size()) == 12 && (!HasLiteral ||
354         !(MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3))) {
355     MaxInstBytesNum = 8;
356     Bytes = Bytes_.slice(0, MaxInstBytesNum);
357     eatBytes<uint64_t>(Bytes);
358   }
359 
360   if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi ||
361               MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 ||
362               MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 ||
363               MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi ||
364               MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi ||
365               MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 ||
366               MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10)) {
367     // Insert dummy unused src2_modifiers.
368     insertNamedMCOperand(MI, MCOperand::createImm(0),
369                          AMDGPU::OpName::src2_modifiers);
370   }
371 
372   if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) {
373     int VAddr0Idx =
374         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
375     int RsrcIdx =
376         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc);
377     unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1;
378     if (VAddr0Idx >= 0 && NSAArgs > 0) {
379       unsigned NSAWords = (NSAArgs + 3) / 4;
380       if (Bytes.size() < 4 * NSAWords) {
381         Res = MCDisassembler::Fail;
382       } else {
383         for (unsigned i = 0; i < NSAArgs; ++i) {
384           MI.insert(MI.begin() + VAddr0Idx + 1 + i,
385                     decodeOperand_VGPR_32(Bytes[i]));
386         }
387         Bytes = Bytes.slice(4 * NSAWords);
388       }
389     }
390 
391     if (Res)
392       Res = convertMIMGInst(MI);
393   }
394 
395   if (Res && IsSDWA)
396     Res = convertSDWAInst(MI);
397 
398   int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
399                                               AMDGPU::OpName::vdst_in);
400   if (VDstIn_Idx != -1) {
401     int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx,
402                            MCOI::OperandConstraint::TIED_TO);
403     if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx ||
404          !MI.getOperand(VDstIn_Idx).isReg() ||
405          MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) {
406       if (MI.getNumOperands() > (unsigned)VDstIn_Idx)
407         MI.erase(&MI.getOperand(VDstIn_Idx));
408       insertNamedMCOperand(MI,
409         MCOperand::createReg(MI.getOperand(Tied).getReg()),
410         AMDGPU::OpName::vdst_in);
411     }
412   }
413 
414   // if the opcode was not recognized we'll assume a Size of 4 bytes
415   // (unless there are fewer bytes left)
416   Size = Res ? (MaxInstBytesNum - Bytes.size())
417              : std::min((size_t)4, Bytes_.size());
418   return Res;
419 }
420 
421 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const {
422   if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
423       STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
424     if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1)
425       // VOPC - insert clamp
426       insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp);
427   } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
428     int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst);
429     if (SDst != -1) {
430       // VOPC - insert VCC register as sdst
431       insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC),
432                            AMDGPU::OpName::sdst);
433     } else {
434       // VOP1/2 - insert omod if present in instruction
435       insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod);
436     }
437   }
438   return MCDisassembler::Success;
439 }
440 
441 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const {
442   unsigned Opc = MI.getOpcode();
443   unsigned DescNumOps = MCII->get(Opc).getNumOperands();
444 
445   // Insert dummy unused src modifiers.
446   if (MI.getNumOperands() < DescNumOps &&
447       AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1)
448     insertNamedMCOperand(MI, MCOperand::createImm(0),
449                          AMDGPU::OpName::src0_modifiers);
450 
451   if (MI.getNumOperands() < DescNumOps &&
452       AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1)
453     insertNamedMCOperand(MI, MCOperand::createImm(0),
454                          AMDGPU::OpName::src1_modifiers);
455 
456   return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail;
457 }
458 
459 // Note that before gfx10, the MIMG encoding provided no information about
460 // VADDR size. Consequently, decoded instructions always show address as if it
461 // has 1 dword, which could be not really so.
462 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {
463 
464   int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
465                                            AMDGPU::OpName::vdst);
466 
467   int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
468                                             AMDGPU::OpName::vdata);
469   int VAddr0Idx =
470       AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
471   int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
472                                             AMDGPU::OpName::dmask);
473 
474   int TFEIdx   = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
475                                             AMDGPU::OpName::tfe);
476   int D16Idx   = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
477                                             AMDGPU::OpName::d16);
478 
479   assert(VDataIdx != -1);
480   assert(DMaskIdx != -1);
481   assert(TFEIdx != -1);
482 
483   const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode());
484   bool IsAtomic = (VDstIdx != -1);
485   bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4;
486 
487   bool IsNSA = false;
488   unsigned AddrSize = Info->VAddrDwords;
489 
490   if (STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
491     unsigned DimIdx =
492         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim);
493     const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
494         AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);
495     const AMDGPU::MIMGDimInfo *Dim =
496         AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm());
497 
498     AddrSize = BaseOpcode->NumExtraArgs +
499                (BaseOpcode->Gradients ? Dim->NumGradients : 0) +
500                (BaseOpcode->Coordinates ? Dim->NumCoords : 0) +
501                (BaseOpcode->LodOrClampOrMip ? 1 : 0);
502     IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA;
503     if (!IsNSA) {
504       if (AddrSize > 8)
505         AddrSize = 16;
506       else if (AddrSize > 4)
507         AddrSize = 8;
508     } else {
509       if (AddrSize > Info->VAddrDwords) {
510         // The NSA encoding does not contain enough operands for the combination
511         // of base opcode / dimension. Should this be an error?
512         return MCDisassembler::Success;
513       }
514     }
515   }
516 
517   unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf;
518   unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u);
519 
520   bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm();
521   if (D16 && AMDGPU::hasPackedD16(STI)) {
522     DstSize = (DstSize + 1) / 2;
523   }
524 
525   // FIXME: Add tfe support
526   if (MI.getOperand(TFEIdx).getImm())
527     return MCDisassembler::Success;
528 
529   if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords)
530     return MCDisassembler::Success;
531 
532   int NewOpcode =
533       AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize);
534   if (NewOpcode == -1)
535     return MCDisassembler::Success;
536 
537   // Widen the register to the correct number of enabled channels.
538   unsigned NewVdata = AMDGPU::NoRegister;
539   if (DstSize != Info->VDataDwords) {
540     auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass;
541 
542     // Get first subregister of VData
543     unsigned Vdata0 = MI.getOperand(VDataIdx).getReg();
544     unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0);
545     Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0;
546 
547     NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0,
548                                        &MRI.getRegClass(DataRCID));
549     if (NewVdata == AMDGPU::NoRegister) {
550       // It's possible to encode this such that the low register + enabled
551       // components exceeds the register count.
552       return MCDisassembler::Success;
553     }
554   }
555 
556   unsigned NewVAddr0 = AMDGPU::NoRegister;
557   if (STI.getFeatureBits()[AMDGPU::FeatureGFX10] && !IsNSA &&
558       AddrSize != Info->VAddrDwords) {
559     unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg();
560     unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0);
561     VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0;
562 
563     auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass;
564     NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0,
565                                         &MRI.getRegClass(AddrRCID));
566     if (NewVAddr0 == AMDGPU::NoRegister)
567       return MCDisassembler::Success;
568   }
569 
570   MI.setOpcode(NewOpcode);
571 
572   if (NewVdata != AMDGPU::NoRegister) {
573     MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata);
574 
575     if (IsAtomic) {
576       // Atomic operations have an additional operand (a copy of data)
577       MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata);
578     }
579   }
580 
581   if (NewVAddr0 != AMDGPU::NoRegister) {
582     MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0);
583   } else if (IsNSA) {
584     assert(AddrSize <= Info->VAddrDwords);
585     MI.erase(MI.begin() + VAddr0Idx + AddrSize,
586              MI.begin() + VAddr0Idx + Info->VAddrDwords);
587   }
588 
589   return MCDisassembler::Success;
590 }
591 
592 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const {
593   return getContext().getRegisterInfo()->
594     getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]);
595 }
596 
597 inline
598 MCOperand AMDGPUDisassembler::errOperand(unsigned V,
599                                          const Twine& ErrMsg) const {
600   *CommentStream << "Error: " + ErrMsg;
601 
602   // ToDo: add support for error operands to MCInst.h
603   // return MCOperand::createError(V);
604   return MCOperand();
605 }
606 
607 inline
608 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const {
609   return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI));
610 }
611 
612 inline
613 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID,
614                                                unsigned Val) const {
615   const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID];
616   if (Val >= RegCl.getNumRegs())
617     return errOperand(Val, Twine(getRegClassName(RegClassID)) +
618                            ": unknown register " + Twine(Val));
619   return createRegOperand(RegCl.getRegister(Val));
620 }
621 
622 inline
623 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID,
624                                                 unsigned Val) const {
625   // ToDo: SI/CI have 104 SGPRs, VI - 102
626   // Valery: here we accepting as much as we can, let assembler sort it out
627   int shift = 0;
628   switch (SRegClassID) {
629   case AMDGPU::SGPR_32RegClassID:
630   case AMDGPU::TTMP_32RegClassID:
631     break;
632   case AMDGPU::SGPR_64RegClassID:
633   case AMDGPU::TTMP_64RegClassID:
634     shift = 1;
635     break;
636   case AMDGPU::SGPR_128RegClassID:
637   case AMDGPU::TTMP_128RegClassID:
638   // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in
639   // this bundle?
640   case AMDGPU::SGPR_256RegClassID:
641   case AMDGPU::TTMP_256RegClassID:
642     // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in
643   // this bundle?
644   case AMDGPU::SGPR_512RegClassID:
645   case AMDGPU::TTMP_512RegClassID:
646     shift = 2;
647     break;
648   // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in
649   // this bundle?
650   default:
651     llvm_unreachable("unhandled register class");
652   }
653 
654   if (Val % (1 << shift)) {
655     *CommentStream << "Warning: " << getRegClassName(SRegClassID)
656                    << ": scalar reg isn't aligned " << Val;
657   }
658 
659   return createRegOperand(SRegClassID, Val >> shift);
660 }
661 
662 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const {
663   return decodeSrcOp(OPW32, Val);
664 }
665 
666 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const {
667   return decodeSrcOp(OPW64, Val);
668 }
669 
670 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const {
671   return decodeSrcOp(OPW128, Val);
672 }
673 
674 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const {
675   return decodeSrcOp(OPW16, Val);
676 }
677 
678 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const {
679   return decodeSrcOp(OPWV216, Val);
680 }
681 
682 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const {
683   // Some instructions have operand restrictions beyond what the encoding
684   // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra
685   // high bit.
686   Val &= 255;
687 
688   return createRegOperand(AMDGPU::VGPR_32RegClassID, Val);
689 }
690 
691 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const {
692   return decodeSrcOp(OPW32, Val);
693 }
694 
695 MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const {
696   return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255);
697 }
698 
699 MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const {
700   return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255);
701 }
702 
703 MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const {
704   return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255);
705 }
706 
707 MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const {
708   return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255);
709 }
710 
711 MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const {
712   return decodeSrcOp(OPW32, Val);
713 }
714 
715 MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const {
716   return decodeSrcOp(OPW64, Val);
717 }
718 
719 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const {
720   return createRegOperand(AMDGPU::VReg_64RegClassID, Val);
721 }
722 
723 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const {
724   return createRegOperand(AMDGPU::VReg_96RegClassID, Val);
725 }
726 
727 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const {
728   return createRegOperand(AMDGPU::VReg_128RegClassID, Val);
729 }
730 
731 MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const {
732   return createRegOperand(AMDGPU::VReg_256RegClassID, Val);
733 }
734 
735 MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const {
736   return createRegOperand(AMDGPU::VReg_512RegClassID, Val);
737 }
738 
739 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const {
740   // table-gen generated disassembler doesn't care about operand types
741   // leaving only registry class so SSrc_32 operand turns into SReg_32
742   // and therefore we accept immediates and literals here as well
743   return decodeSrcOp(OPW32, Val);
744 }
745 
746 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC(
747   unsigned Val) const {
748   // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI
749   return decodeOperand_SReg_32(Val);
750 }
751 
752 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI(
753   unsigned Val) const {
754   // SReg_32_XM0 is SReg_32 without EXEC_HI
755   return decodeOperand_SReg_32(Val);
756 }
757 
758 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const {
759   // table-gen generated disassembler doesn't care about operand types
760   // leaving only registry class so SSrc_32 operand turns into SReg_32
761   // and therefore we accept immediates and literals here as well
762   return decodeSrcOp(OPW32, Val);
763 }
764 
765 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const {
766   return decodeSrcOp(OPW64, Val);
767 }
768 
769 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const {
770   return decodeSrcOp(OPW64, Val);
771 }
772 
773 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const {
774   return decodeSrcOp(OPW128, Val);
775 }
776 
777 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const {
778   return decodeDstOp(OPW256, Val);
779 }
780 
781 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const {
782   return decodeDstOp(OPW512, Val);
783 }
784 
785 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const {
786   // For now all literal constants are supposed to be unsigned integer
787   // ToDo: deal with signed/unsigned 64-bit integer constants
788   // ToDo: deal with float/double constants
789   if (!HasLiteral) {
790     if (Bytes.size() < 4) {
791       return errOperand(0, "cannot read literal, inst bytes left " +
792                         Twine(Bytes.size()));
793     }
794     HasLiteral = true;
795     Literal = eatBytes<uint32_t>(Bytes);
796   }
797   return MCOperand::createImm(Literal);
798 }
799 
800 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) {
801   using namespace AMDGPU::EncValues;
802 
803   assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX);
804   return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ?
805     (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) :
806     (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm)));
807       // Cast prevents negative overflow.
808 }
809 
810 static int64_t getInlineImmVal32(unsigned Imm) {
811   switch (Imm) {
812   case 240:
813     return FloatToBits(0.5f);
814   case 241:
815     return FloatToBits(-0.5f);
816   case 242:
817     return FloatToBits(1.0f);
818   case 243:
819     return FloatToBits(-1.0f);
820   case 244:
821     return FloatToBits(2.0f);
822   case 245:
823     return FloatToBits(-2.0f);
824   case 246:
825     return FloatToBits(4.0f);
826   case 247:
827     return FloatToBits(-4.0f);
828   case 248: // 1 / (2 * PI)
829     return 0x3e22f983;
830   default:
831     llvm_unreachable("invalid fp inline imm");
832   }
833 }
834 
835 static int64_t getInlineImmVal64(unsigned Imm) {
836   switch (Imm) {
837   case 240:
838     return DoubleToBits(0.5);
839   case 241:
840     return DoubleToBits(-0.5);
841   case 242:
842     return DoubleToBits(1.0);
843   case 243:
844     return DoubleToBits(-1.0);
845   case 244:
846     return DoubleToBits(2.0);
847   case 245:
848     return DoubleToBits(-2.0);
849   case 246:
850     return DoubleToBits(4.0);
851   case 247:
852     return DoubleToBits(-4.0);
853   case 248: // 1 / (2 * PI)
854     return 0x3fc45f306dc9c882;
855   default:
856     llvm_unreachable("invalid fp inline imm");
857   }
858 }
859 
860 static int64_t getInlineImmVal16(unsigned Imm) {
861   switch (Imm) {
862   case 240:
863     return 0x3800;
864   case 241:
865     return 0xB800;
866   case 242:
867     return 0x3C00;
868   case 243:
869     return 0xBC00;
870   case 244:
871     return 0x4000;
872   case 245:
873     return 0xC000;
874   case 246:
875     return 0x4400;
876   case 247:
877     return 0xC400;
878   case 248: // 1 / (2 * PI)
879     return 0x3118;
880   default:
881     llvm_unreachable("invalid fp inline imm");
882   }
883 }
884 
885 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) {
886   assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN
887       && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX);
888 
889   // ToDo: case 248: 1/(2*PI) - is allowed only on VI
890   switch (Width) {
891   case OPW32:
892   case OPW128: // splat constants
893   case OPW512:
894   case OPW1024:
895     return MCOperand::createImm(getInlineImmVal32(Imm));
896   case OPW64:
897     return MCOperand::createImm(getInlineImmVal64(Imm));
898   case OPW16:
899   case OPWV216:
900     return MCOperand::createImm(getInlineImmVal16(Imm));
901   default:
902     llvm_unreachable("implement me");
903   }
904 }
905 
906 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const {
907   using namespace AMDGPU;
908 
909   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
910   switch (Width) {
911   default: // fall
912   case OPW32:
913   case OPW16:
914   case OPWV216:
915     return VGPR_32RegClassID;
916   case OPW64: return VReg_64RegClassID;
917   case OPW128: return VReg_128RegClassID;
918   }
919 }
920 
921 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const {
922   using namespace AMDGPU;
923 
924   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
925   switch (Width) {
926   default: // fall
927   case OPW32:
928   case OPW16:
929   case OPWV216:
930     return AGPR_32RegClassID;
931   case OPW64: return AReg_64RegClassID;
932   case OPW128: return AReg_128RegClassID;
933   case OPW256: return AReg_256RegClassID;
934   case OPW512: return AReg_512RegClassID;
935   case OPW1024: return AReg_1024RegClassID;
936   }
937 }
938 
939 
940 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const {
941   using namespace AMDGPU;
942 
943   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
944   switch (Width) {
945   default: // fall
946   case OPW32:
947   case OPW16:
948   case OPWV216:
949     return SGPR_32RegClassID;
950   case OPW64: return SGPR_64RegClassID;
951   case OPW128: return SGPR_128RegClassID;
952   case OPW256: return SGPR_256RegClassID;
953   case OPW512: return SGPR_512RegClassID;
954   }
955 }
956 
957 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const {
958   using namespace AMDGPU;
959 
960   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
961   switch (Width) {
962   default: // fall
963   case OPW32:
964   case OPW16:
965   case OPWV216:
966     return TTMP_32RegClassID;
967   case OPW64: return TTMP_64RegClassID;
968   case OPW128: return TTMP_128RegClassID;
969   case OPW256: return TTMP_256RegClassID;
970   case OPW512: return TTMP_512RegClassID;
971   }
972 }
973 
974 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const {
975   using namespace AMDGPU::EncValues;
976 
977   unsigned TTmpMin =
978       (isGFX9() || isGFX10()) ? TTMP_GFX9_GFX10_MIN : TTMP_VI_MIN;
979   unsigned TTmpMax =
980       (isGFX9() || isGFX10()) ? TTMP_GFX9_GFX10_MAX : TTMP_VI_MAX;
981 
982   return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1;
983 }
984 
985 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const {
986   using namespace AMDGPU::EncValues;
987 
988   assert(Val < 1024); // enum10
989 
990   bool IsAGPR = Val & 512;
991   Val &= 511;
992 
993   if (VGPR_MIN <= Val && Val <= VGPR_MAX) {
994     return createRegOperand(IsAGPR ? getAgprClassId(Width)
995                                    : getVgprClassId(Width), Val - VGPR_MIN);
996   }
997   if (Val <= SGPR_MAX) {
998     assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning.
999     return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);
1000   }
1001 
1002   int TTmpIdx = getTTmpIdx(Val);
1003   if (TTmpIdx >= 0) {
1004     return createSRegOperand(getTtmpClassId(Width), TTmpIdx);
1005   }
1006 
1007   if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX)
1008     return decodeIntImmed(Val);
1009 
1010   if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX)
1011     return decodeFPImmed(Width, Val);
1012 
1013   if (Val == LITERAL_CONST)
1014     return decodeLiteralConstant();
1015 
1016   switch (Width) {
1017   case OPW32:
1018   case OPW16:
1019   case OPWV216:
1020     return decodeSpecialReg32(Val);
1021   case OPW64:
1022     return decodeSpecialReg64(Val);
1023   default:
1024     llvm_unreachable("unexpected immediate type");
1025   }
1026 }
1027 
1028 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const {
1029   using namespace AMDGPU::EncValues;
1030 
1031   assert(Val < 128);
1032   assert(Width == OPW256 || Width == OPW512);
1033 
1034   if (Val <= SGPR_MAX) {
1035     assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning.
1036     return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);
1037   }
1038 
1039   int TTmpIdx = getTTmpIdx(Val);
1040   if (TTmpIdx >= 0) {
1041     return createSRegOperand(getTtmpClassId(Width), TTmpIdx);
1042   }
1043 
1044   llvm_unreachable("unknown dst register");
1045 }
1046 
1047 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const {
1048   using namespace AMDGPU;
1049 
1050   switch (Val) {
1051   case 102: return createRegOperand(FLAT_SCR_LO);
1052   case 103: return createRegOperand(FLAT_SCR_HI);
1053   case 104: return createRegOperand(XNACK_MASK_LO);
1054   case 105: return createRegOperand(XNACK_MASK_HI);
1055   case 106: return createRegOperand(VCC_LO);
1056   case 107: return createRegOperand(VCC_HI);
1057   case 108: return createRegOperand(TBA_LO);
1058   case 109: return createRegOperand(TBA_HI);
1059   case 110: return createRegOperand(TMA_LO);
1060   case 111: return createRegOperand(TMA_HI);
1061   case 124: return createRegOperand(M0);
1062   case 125: return createRegOperand(SGPR_NULL);
1063   case 126: return createRegOperand(EXEC_LO);
1064   case 127: return createRegOperand(EXEC_HI);
1065   case 235: return createRegOperand(SRC_SHARED_BASE);
1066   case 236: return createRegOperand(SRC_SHARED_LIMIT);
1067   case 237: return createRegOperand(SRC_PRIVATE_BASE);
1068   case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
1069   case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
1070   case 251: return createRegOperand(SRC_VCCZ);
1071   case 252: return createRegOperand(SRC_EXECZ);
1072   case 253: return createRegOperand(SRC_SCC);
1073   case 254: return createRegOperand(LDS_DIRECT);
1074   default: break;
1075   }
1076   return errOperand(Val, "unknown operand encoding " + Twine(Val));
1077 }
1078 
1079 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const {
1080   using namespace AMDGPU;
1081 
1082   switch (Val) {
1083   case 102: return createRegOperand(FLAT_SCR);
1084   case 104: return createRegOperand(XNACK_MASK);
1085   case 106: return createRegOperand(VCC);
1086   case 108: return createRegOperand(TBA);
1087   case 110: return createRegOperand(TMA);
1088   case 125: return createRegOperand(SGPR_NULL);
1089   case 126: return createRegOperand(EXEC);
1090   case 235: return createRegOperand(SRC_SHARED_BASE);
1091   case 236: return createRegOperand(SRC_SHARED_LIMIT);
1092   case 237: return createRegOperand(SRC_PRIVATE_BASE);
1093   case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
1094   case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
1095   case 251: return createRegOperand(SRC_VCCZ);
1096   case 252: return createRegOperand(SRC_EXECZ);
1097   case 253: return createRegOperand(SRC_SCC);
1098   default: break;
1099   }
1100   return errOperand(Val, "unknown operand encoding " + Twine(Val));
1101 }
1102 
1103 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width,
1104                                             const unsigned Val) const {
1105   using namespace AMDGPU::SDWA;
1106   using namespace AMDGPU::EncValues;
1107 
1108   if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
1109       STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
1110     // XXX: cast to int is needed to avoid stupid warning:
1111     // compare with unsigned is always true
1112     if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) &&
1113         Val <= SDWA9EncValues::SRC_VGPR_MAX) {
1114       return createRegOperand(getVgprClassId(Width),
1115                               Val - SDWA9EncValues::SRC_VGPR_MIN);
1116     }
1117     if (SDWA9EncValues::SRC_SGPR_MIN <= Val &&
1118         Val <= (isGFX10() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10
1119                           : SDWA9EncValues::SRC_SGPR_MAX_SI)) {
1120       return createSRegOperand(getSgprClassId(Width),
1121                                Val - SDWA9EncValues::SRC_SGPR_MIN);
1122     }
1123     if (SDWA9EncValues::SRC_TTMP_MIN <= Val &&
1124         Val <= SDWA9EncValues::SRC_TTMP_MAX) {
1125       return createSRegOperand(getTtmpClassId(Width),
1126                                Val - SDWA9EncValues::SRC_TTMP_MIN);
1127     }
1128 
1129     const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN;
1130 
1131     if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX)
1132       return decodeIntImmed(SVal);
1133 
1134     if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX)
1135       return decodeFPImmed(Width, SVal);
1136 
1137     return decodeSpecialReg32(SVal);
1138   } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
1139     return createRegOperand(getVgprClassId(Width), Val);
1140   }
1141   llvm_unreachable("unsupported target");
1142 }
1143 
1144 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const {
1145   return decodeSDWASrc(OPW16, Val);
1146 }
1147 
1148 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const {
1149   return decodeSDWASrc(OPW32, Val);
1150 }
1151 
1152 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const {
1153   using namespace AMDGPU::SDWA;
1154 
1155   assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
1156           STI.getFeatureBits()[AMDGPU::FeatureGFX10]) &&
1157          "SDWAVopcDst should be present only on GFX9+");
1158 
1159   bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64];
1160 
1161   if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) {
1162     Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK;
1163 
1164     int TTmpIdx = getTTmpIdx(Val);
1165     if (TTmpIdx >= 0) {
1166       auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32);
1167       return createSRegOperand(TTmpClsId, TTmpIdx);
1168     } else if (Val > SGPR_MAX) {
1169       return IsWave64 ? decodeSpecialReg64(Val)
1170                       : decodeSpecialReg32(Val);
1171     } else {
1172       return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val);
1173     }
1174   } else {
1175     return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO);
1176   }
1177 }
1178 
1179 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const {
1180   return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ?
1181     decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val);
1182 }
1183 
1184 bool AMDGPUDisassembler::isVI() const {
1185   return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
1186 }
1187 
1188 bool AMDGPUDisassembler::isGFX9() const {
1189   return STI.getFeatureBits()[AMDGPU::FeatureGFX9];
1190 }
1191 
1192 bool AMDGPUDisassembler::isGFX10() const {
1193   return STI.getFeatureBits()[AMDGPU::FeatureGFX10];
1194 }
1195 
1196 //===----------------------------------------------------------------------===//
1197 // AMDGPUSymbolizer
1198 //===----------------------------------------------------------------------===//
1199 
1200 // Try to find symbol name for specified label
1201 bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst,
1202                                 raw_ostream &/*cStream*/, int64_t Value,
1203                                 uint64_t /*Address*/, bool IsBranch,
1204                                 uint64_t /*Offset*/, uint64_t /*InstSize*/) {
1205 
1206   if (!IsBranch) {
1207     return false;
1208   }
1209 
1210   auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo);
1211   if (!Symbols)
1212     return false;
1213 
1214   auto Result = std::find_if(Symbols->begin(), Symbols->end(),
1215                              [Value](const SymbolInfoTy& Val) {
1216                                 return Val.Addr == static_cast<uint64_t>(Value)
1217                                     && Val.Type == ELF::STT_NOTYPE;
1218                              });
1219   if (Result != Symbols->end()) {
1220     auto *Sym = Ctx.getOrCreateSymbol(Result->Name);
1221     const auto *Add = MCSymbolRefExpr::create(Sym, Ctx);
1222     Inst.addOperand(MCOperand::createExpr(Add));
1223     return true;
1224   }
1225   return false;
1226 }
1227 
1228 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream,
1229                                                        int64_t Value,
1230                                                        uint64_t Address) {
1231   llvm_unreachable("unimplemented");
1232 }
1233 
1234 //===----------------------------------------------------------------------===//
1235 // Initialization
1236 //===----------------------------------------------------------------------===//
1237 
1238 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/,
1239                               LLVMOpInfoCallback /*GetOpInfo*/,
1240                               LLVMSymbolLookupCallback /*SymbolLookUp*/,
1241                               void *DisInfo,
1242                               MCContext *Ctx,
1243                               std::unique_ptr<MCRelocationInfo> &&RelInfo) {
1244   return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo);
1245 }
1246 
1247 static MCDisassembler *createAMDGPUDisassembler(const Target &T,
1248                                                 const MCSubtargetInfo &STI,
1249                                                 MCContext &Ctx) {
1250   return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo());
1251 }
1252 
1253 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() {
1254   TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(),
1255                                          createAMDGPUDisassembler);
1256   TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(),
1257                                        createAMDGPUSymbolizer);
1258 }
1259