1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "TargetInfo/AMDGPUTargetInfo.h" 22 #include "Utils/AMDGPUBaseInfo.h" 23 #include "llvm-c/DisassemblerTypes.h" 24 #include "llvm/BinaryFormat/ELF.h" 25 #include "llvm/MC/MCAsmInfo.h" 26 #include "llvm/MC/MCContext.h" 27 #include "llvm/MC/MCDecoderOps.h" 28 #include "llvm/MC/MCExpr.h" 29 #include "llvm/MC/MCInstrDesc.h" 30 #include "llvm/MC/MCRegisterInfo.h" 31 #include "llvm/MC/MCSubtargetInfo.h" 32 #include "llvm/MC/TargetRegistry.h" 33 #include "llvm/Support/AMDHSAKernelDescriptor.h" 34 35 using namespace llvm; 36 37 #define DEBUG_TYPE "amdgpu-disassembler" 38 39 #define SGPR_MAX \ 40 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 41 : AMDGPU::EncValues::SGPR_MAX_SI) 42 43 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 44 45 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 46 MCContext &Ctx, 47 MCInstrInfo const *MCII) : 48 MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), 49 TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) { 50 51 // ToDo: AMDGPUDisassembler supports only VI ISA. 52 if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10Plus()) 53 report_fatal_error("Disassembly not yet supported for subtarget"); 54 } 55 56 inline static MCDisassembler::DecodeStatus 57 addOperand(MCInst &Inst, const MCOperand& Opnd) { 58 Inst.addOperand(Opnd); 59 return Opnd.isValid() ? 60 MCDisassembler::Success : 61 MCDisassembler::Fail; 62 } 63 64 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 65 uint16_t NameIdx) { 66 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 67 if (OpIdx != -1) { 68 auto I = MI.begin(); 69 std::advance(I, OpIdx); 70 MI.insert(I, Op); 71 } 72 return OpIdx; 73 } 74 75 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, 76 uint64_t Addr, 77 const MCDisassembler *Decoder) { 78 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 79 80 // Our branches take a simm16, but we need two extra bits to account for the 81 // factor of 4. 82 APInt SignedOffset(18, Imm * 4, true); 83 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 84 85 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2, 0)) 86 return MCDisassembler::Success; 87 return addOperand(Inst, MCOperand::createImm(Imm)); 88 } 89 90 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, 91 const MCDisassembler *Decoder) { 92 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 93 int64_t Offset; 94 if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 95 Offset = Imm & 0xFFFFF; 96 } else { // GFX9+ supports 21-bit signed offsets. 97 Offset = SignExtend64<21>(Imm); 98 } 99 return addOperand(Inst, MCOperand::createImm(Offset)); 100 } 101 102 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, 103 const MCDisassembler *Decoder) { 104 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 105 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 106 } 107 108 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 109 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \ 110 uint64_t /*Addr*/, \ 111 const MCDisassembler *Decoder) { \ 112 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 113 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 114 } 115 116 #define DECODE_OPERAND_REG(RegClass) \ 117 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass) 118 119 DECODE_OPERAND_REG(VGPR_32) 120 DECODE_OPERAND_REG(VRegOrLds_32) 121 DECODE_OPERAND_REG(VS_32) 122 DECODE_OPERAND_REG(VS_64) 123 DECODE_OPERAND_REG(VS_128) 124 125 DECODE_OPERAND_REG(VReg_64) 126 DECODE_OPERAND_REG(VReg_96) 127 DECODE_OPERAND_REG(VReg_128) 128 DECODE_OPERAND_REG(VReg_256) 129 DECODE_OPERAND_REG(VReg_512) 130 DECODE_OPERAND_REG(VReg_1024) 131 132 DECODE_OPERAND_REG(SReg_32) 133 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC) 134 DECODE_OPERAND_REG(SReg_32_XEXEC_HI) 135 DECODE_OPERAND_REG(SRegOrLds_32) 136 DECODE_OPERAND_REG(SReg_64) 137 DECODE_OPERAND_REG(SReg_64_XEXEC) 138 DECODE_OPERAND_REG(SReg_128) 139 DECODE_OPERAND_REG(SReg_256) 140 DECODE_OPERAND_REG(SReg_512) 141 142 DECODE_OPERAND_REG(AGPR_32) 143 DECODE_OPERAND_REG(AReg_64) 144 DECODE_OPERAND_REG(AReg_128) 145 DECODE_OPERAND_REG(AReg_256) 146 DECODE_OPERAND_REG(AReg_512) 147 DECODE_OPERAND_REG(AReg_1024) 148 DECODE_OPERAND_REG(AV_32) 149 DECODE_OPERAND_REG(AV_64) 150 DECODE_OPERAND_REG(AV_128) 151 DECODE_OPERAND_REG(AVDst_128) 152 DECODE_OPERAND_REG(AVDst_512) 153 154 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, unsigned Imm, 155 uint64_t Addr, 156 const MCDisassembler *Decoder) { 157 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 158 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 159 } 160 161 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, unsigned Imm, 162 uint64_t Addr, 163 const MCDisassembler *Decoder) { 164 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 165 return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm)); 166 } 167 168 static DecodeStatus decodeOperand_VSrcV232(MCInst &Inst, unsigned Imm, 169 uint64_t Addr, 170 const MCDisassembler *Decoder) { 171 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 172 return addOperand(Inst, DAsm->decodeOperand_VSrcV232(Imm)); 173 } 174 175 static DecodeStatus decodeOperand_VS_16(MCInst &Inst, unsigned Imm, 176 uint64_t Addr, 177 const MCDisassembler *Decoder) { 178 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 179 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 180 } 181 182 static DecodeStatus decodeOperand_VS_32(MCInst &Inst, unsigned Imm, 183 uint64_t Addr, 184 const MCDisassembler *Decoder) { 185 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 186 return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm)); 187 } 188 189 static DecodeStatus decodeOperand_AReg_64(MCInst &Inst, unsigned Imm, 190 uint64_t Addr, 191 const MCDisassembler *Decoder) { 192 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 193 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm | 512)); 194 } 195 196 static DecodeStatus decodeOperand_AReg_128(MCInst &Inst, unsigned Imm, 197 uint64_t Addr, 198 const MCDisassembler *Decoder) { 199 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 200 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512)); 201 } 202 203 static DecodeStatus decodeOperand_AReg_256(MCInst &Inst, unsigned Imm, 204 uint64_t Addr, 205 const MCDisassembler *Decoder) { 206 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 207 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm | 512)); 208 } 209 210 static DecodeStatus decodeOperand_AReg_512(MCInst &Inst, unsigned Imm, 211 uint64_t Addr, 212 const MCDisassembler *Decoder) { 213 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 214 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512)); 215 } 216 217 static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst, unsigned Imm, 218 uint64_t Addr, 219 const MCDisassembler *Decoder) { 220 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 221 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512)); 222 } 223 224 static DecodeStatus decodeOperand_VReg_64(MCInst &Inst, unsigned Imm, 225 uint64_t Addr, 226 const MCDisassembler *Decoder) { 227 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 228 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm)); 229 } 230 231 static DecodeStatus decodeOperand_VReg_128(MCInst &Inst, unsigned Imm, 232 uint64_t Addr, 233 const MCDisassembler *Decoder) { 234 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 235 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm)); 236 } 237 238 static DecodeStatus decodeOperand_VReg_256(MCInst &Inst, unsigned Imm, 239 uint64_t Addr, 240 const MCDisassembler *Decoder) { 241 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 242 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm)); 243 } 244 245 static DecodeStatus decodeOperand_VReg_512(MCInst &Inst, unsigned Imm, 246 uint64_t Addr, 247 const MCDisassembler *Decoder) { 248 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 249 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm)); 250 } 251 252 static DecodeStatus decodeOperand_VReg_1024(MCInst &Inst, unsigned Imm, 253 uint64_t Addr, 254 const MCDisassembler *Decoder) { 255 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 256 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm)); 257 } 258 259 static DecodeStatus decodeOperand_f32kimm(MCInst &Inst, unsigned Imm, 260 uint64_t Addr, 261 const MCDisassembler *Decoder) { 262 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 263 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 264 } 265 266 static DecodeStatus decodeOperand_f16kimm(MCInst &Inst, unsigned Imm, 267 uint64_t Addr, 268 const MCDisassembler *Decoder) { 269 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 270 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 271 } 272 273 static DecodeStatus 274 decodeOperand_VS_16_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, 275 const MCDisassembler *Decoder) { 276 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 277 return addOperand( 278 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW16, Imm, true)); 279 } 280 281 static DecodeStatus 282 decodeOperand_VS_32_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, 283 const MCDisassembler *Decoder) { 284 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 285 return addOperand( 286 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW32, Imm, true)); 287 } 288 289 static bool IsAGPROperand(const MCInst &Inst, int OpIdx, 290 const MCRegisterInfo *MRI) { 291 if (OpIdx < 0) 292 return false; 293 294 const MCOperand &Op = Inst.getOperand(OpIdx); 295 if (!Op.isReg()) 296 return false; 297 298 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); 299 auto Reg = Sub ? Sub : Op.getReg(); 300 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; 301 } 302 303 static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, unsigned Imm, 304 AMDGPUDisassembler::OpWidthTy Opw, 305 const MCDisassembler *Decoder) { 306 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 307 if (!DAsm->isGFX90A()) { 308 Imm &= 511; 309 } else { 310 // If atomic has both vdata and vdst their register classes are tied. 311 // The bit is decoded along with the vdst, first operand. We need to 312 // change register class to AGPR if vdst was AGPR. 313 // If a DS instruction has both data0 and data1 their register classes 314 // are also tied. 315 unsigned Opc = Inst.getOpcode(); 316 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; 317 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 318 : AMDGPU::OpName::vdata; 319 const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo(); 320 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); 321 if ((int)Inst.getNumOperands() == DataIdx) { 322 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); 323 if (IsAGPROperand(Inst, DstIdx, MRI)) 324 Imm |= 512; 325 } 326 327 if (TSFlags & SIInstrFlags::DS) { 328 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); 329 if ((int)Inst.getNumOperands() == Data2Idx && 330 IsAGPROperand(Inst, DataIdx, MRI)) 331 Imm |= 512; 332 } 333 } 334 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); 335 } 336 337 static DecodeStatus 338 DecodeAVLdSt_32RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 339 const MCDisassembler *Decoder) { 340 return decodeOperand_AVLdSt_Any(Inst, Imm, 341 AMDGPUDisassembler::OPW32, Decoder); 342 } 343 344 static DecodeStatus 345 DecodeAVLdSt_64RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 346 const MCDisassembler *Decoder) { 347 return decodeOperand_AVLdSt_Any(Inst, Imm, 348 AMDGPUDisassembler::OPW64, Decoder); 349 } 350 351 static DecodeStatus 352 DecodeAVLdSt_96RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 353 const MCDisassembler *Decoder) { 354 return decodeOperand_AVLdSt_Any(Inst, Imm, 355 AMDGPUDisassembler::OPW96, Decoder); 356 } 357 358 static DecodeStatus 359 DecodeAVLdSt_128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 360 const MCDisassembler *Decoder) { 361 return decodeOperand_AVLdSt_Any(Inst, Imm, 362 AMDGPUDisassembler::OPW128, Decoder); 363 } 364 365 static DecodeStatus decodeOperand_SReg_32(MCInst &Inst, unsigned Imm, 366 uint64_t Addr, 367 const MCDisassembler *Decoder) { 368 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 369 return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm)); 370 } 371 372 #define DECODE_SDWA(DecName) \ 373 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 374 375 DECODE_SDWA(Src32) 376 DECODE_SDWA(Src16) 377 DECODE_SDWA(VopcDst) 378 379 #include "AMDGPUGenDisassemblerTables.inc" 380 381 //===----------------------------------------------------------------------===// 382 // 383 //===----------------------------------------------------------------------===// 384 385 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 386 assert(Bytes.size() >= sizeof(T)); 387 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data()); 388 Bytes = Bytes.slice(sizeof(T)); 389 return Res; 390 } 391 392 // The disassembler is greedy, so we need to check FI operand value to 393 // not parse a dpp if the correct literal is not set. For dpp16 the 394 // autogenerated decoder checks the dpp literal 395 static bool isValidDPP8(const MCInst &MI) { 396 using namespace llvm::AMDGPU::DPP; 397 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi); 398 assert(FiIdx != -1); 399 if ((unsigned)FiIdx >= MI.getNumOperands()) 400 return false; 401 unsigned Fi = MI.getOperand(FiIdx).getImm(); 402 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1; 403 } 404 405 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 406 ArrayRef<uint8_t> Bytes_, 407 uint64_t Address, 408 raw_ostream &CS) const { 409 CommentStream = &CS; 410 bool IsSDWA = false; 411 412 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 413 Bytes = Bytes_.slice(0, MaxInstBytesNum); 414 415 DecodeStatus Res = MCDisassembler::Fail; 416 do { 417 // ToDo: better to switch encoding length using some bit predicate 418 // but it is unknown yet, so try all we can 419 420 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 421 // encodings 422 if (Bytes.size() >= 8) { 423 const uint64_t QW = eatBytes<uint64_t>(Bytes); 424 425 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 426 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address); 427 if (Res) { 428 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) 429 == -1) 430 break; 431 if (convertDPP8Inst(MI) == MCDisassembler::Success) 432 break; 433 MI = MCInst(); // clear 434 } 435 } 436 437 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address); 438 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 439 break; 440 441 MI = MCInst(); // clear 442 443 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address); 444 if (Res) break; 445 446 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address); 447 if (Res) { IsSDWA = true; break; } 448 449 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address); 450 if (Res) { IsSDWA = true; break; } 451 452 Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address); 453 if (Res) { IsSDWA = true; break; } 454 455 if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) { 456 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address); 457 if (Res) 458 break; 459 } 460 461 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 462 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 463 // table first so we print the correct name. 464 if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) { 465 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address); 466 if (Res) 467 break; 468 } 469 } 470 471 // Reinitialize Bytes as DPP64 could have eaten too much 472 Bytes = Bytes_.slice(0, MaxInstBytesNum); 473 474 // Try decode 32-bit instruction 475 if (Bytes.size() < 4) break; 476 const uint32_t DW = eatBytes<uint32_t>(Bytes); 477 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address); 478 if (Res) break; 479 480 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address); 481 if (Res) break; 482 483 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address); 484 if (Res) break; 485 486 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 487 Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address); 488 if (Res) 489 break; 490 } 491 492 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 493 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address); 494 if (Res) break; 495 } 496 497 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address); 498 if (Res) break; 499 500 Res = tryDecodeInst(DecoderTableGFX1132, MI, DW, Address); 501 if (Res) break; 502 503 if (Bytes.size() < 4) break; 504 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 505 506 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 507 Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address); 508 if (Res) 509 break; 510 } 511 512 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address); 513 if (Res) break; 514 515 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address); 516 if (Res) break; 517 518 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address); 519 if (Res) break; 520 521 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address); 522 if (Res) break; 523 524 Res = tryDecodeInst(DecoderTableGFX1164, MI, QW, Address); 525 } while (false); 526 527 if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi || 528 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 || 529 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 || 530 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 || 531 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 || 532 MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi || 533 MI.getOpcode() == AMDGPU::V_FMAC_F64_e64_gfx90a || 534 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi || 535 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 || 536 MI.getOpcode() == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 || 537 MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10)) { 538 // Insert dummy unused src2_modifiers. 539 insertNamedMCOperand(MI, MCOperand::createImm(0), 540 AMDGPU::OpName::src2_modifiers); 541 } 542 543 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 544 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT | SIInstrFlags::SMRD))) { 545 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 546 AMDGPU::OpName::cpol); 547 if (CPolPos != -1) { 548 unsigned CPol = 549 (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ? 550 AMDGPU::CPol::GLC : 0; 551 if (MI.getNumOperands() <= (unsigned)CPolPos) { 552 insertNamedMCOperand(MI, MCOperand::createImm(CPol), 553 AMDGPU::OpName::cpol); 554 } else if (CPol) { 555 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); 556 } 557 } 558 } 559 560 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 561 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) && 562 (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts])) { 563 // GFX90A lost TFE, its place is occupied by ACC. 564 int TFEOpIdx = 565 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); 566 if (TFEOpIdx != -1) { 567 auto TFEIter = MI.begin(); 568 std::advance(TFEIter, TFEOpIdx); 569 MI.insert(TFEIter, MCOperand::createImm(0)); 570 } 571 } 572 573 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 574 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF))) { 575 int SWZOpIdx = 576 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); 577 if (SWZOpIdx != -1) { 578 auto SWZIter = MI.begin(); 579 std::advance(SWZIter, SWZOpIdx); 580 MI.insert(SWZIter, MCOperand::createImm(0)); 581 } 582 } 583 584 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 585 int VAddr0Idx = 586 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 587 int RsrcIdx = 588 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 589 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 590 if (VAddr0Idx >= 0 && NSAArgs > 0) { 591 unsigned NSAWords = (NSAArgs + 3) / 4; 592 if (Bytes.size() < 4 * NSAWords) { 593 Res = MCDisassembler::Fail; 594 } else { 595 for (unsigned i = 0; i < NSAArgs; ++i) { 596 MI.insert(MI.begin() + VAddr0Idx + 1 + i, 597 decodeOperand_VGPR_32(Bytes[i])); 598 } 599 Bytes = Bytes.slice(4 * NSAWords); 600 } 601 } 602 603 if (Res) 604 Res = convertMIMGInst(MI); 605 } 606 607 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::EXP)) 608 Res = convertEXPInst(MI); 609 610 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VINTERP)) 611 Res = convertVINTERPInst(MI); 612 613 if (Res && IsSDWA) 614 Res = convertSDWAInst(MI); 615 616 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 617 AMDGPU::OpName::vdst_in); 618 if (VDstIn_Idx != -1) { 619 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 620 MCOI::OperandConstraint::TIED_TO); 621 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 622 !MI.getOperand(VDstIn_Idx).isReg() || 623 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 624 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 625 MI.erase(&MI.getOperand(VDstIn_Idx)); 626 insertNamedMCOperand(MI, 627 MCOperand::createReg(MI.getOperand(Tied).getReg()), 628 AMDGPU::OpName::vdst_in); 629 } 630 } 631 632 int ImmLitIdx = 633 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm); 634 if (Res && ImmLitIdx != -1) 635 Res = convertFMAanyK(MI, ImmLitIdx); 636 637 // if the opcode was not recognized we'll assume a Size of 4 bytes 638 // (unless there are fewer bytes left) 639 Size = Res ? (MaxInstBytesNum - Bytes.size()) 640 : std::min((size_t)4, Bytes_.size()); 641 return Res; 642 } 643 644 DecodeStatus AMDGPUDisassembler::convertEXPInst(MCInst &MI) const { 645 if (STI.getFeatureBits()[AMDGPU::FeatureGFX11]) { 646 // The MCInst still has these fields even though they are no longer encoded 647 // in the GFX11 instruction. 648 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vm); 649 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::compr); 650 } 651 return MCDisassembler::Success; 652 } 653 654 DecodeStatus AMDGPUDisassembler::convertVINTERPInst(MCInst &MI) const { 655 if (MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx11 || 656 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx11 || 657 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx11 || 658 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx11) { 659 // The MCInst has this field that is not directly encoded in the 660 // instruction. 661 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::op_sel); 662 } 663 return MCDisassembler::Success; 664 } 665 666 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 667 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 668 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 669 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1) 670 // VOPC - insert clamp 671 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 672 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 673 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 674 if (SDst != -1) { 675 // VOPC - insert VCC register as sdst 676 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 677 AMDGPU::OpName::sdst); 678 } else { 679 // VOP1/2 - insert omod if present in instruction 680 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 681 } 682 } 683 return MCDisassembler::Success; 684 } 685 686 // We must check FI == literal to reject not genuine dpp8 insts, and we must 687 // first add optional MI operands to check FI 688 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 689 unsigned Opc = MI.getOpcode(); 690 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 691 692 // Insert dummy unused src modifiers. 693 if (MI.getNumOperands() < DescNumOps && 694 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1) 695 insertNamedMCOperand(MI, MCOperand::createImm(0), 696 AMDGPU::OpName::src0_modifiers); 697 698 if (MI.getNumOperands() < DescNumOps && 699 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1) 700 insertNamedMCOperand(MI, MCOperand::createImm(0), 701 AMDGPU::OpName::src1_modifiers); 702 703 return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail; 704 } 705 706 // Note that before gfx10, the MIMG encoding provided no information about 707 // VADDR size. Consequently, decoded instructions always show address as if it 708 // has 1 dword, which could be not really so. 709 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 710 711 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 712 AMDGPU::OpName::vdst); 713 714 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 715 AMDGPU::OpName::vdata); 716 int VAddr0Idx = 717 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 718 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 719 AMDGPU::OpName::dmask); 720 721 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 722 AMDGPU::OpName::tfe); 723 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 724 AMDGPU::OpName::d16); 725 726 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 727 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 728 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 729 730 assert(VDataIdx != -1); 731 if (BaseOpcode->BVH) { 732 // Add A16 operand for intersect_ray instructions 733 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16) > -1) { 734 addOperand(MI, MCOperand::createImm(1)); 735 } 736 return MCDisassembler::Success; 737 } 738 739 bool IsAtomic = (VDstIdx != -1); 740 bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4; 741 bool IsNSA = false; 742 unsigned AddrSize = Info->VAddrDwords; 743 744 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 745 unsigned DimIdx = 746 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 747 int A16Idx = 748 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16); 749 const AMDGPU::MIMGDimInfo *Dim = 750 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 751 const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm()); 752 753 AddrSize = 754 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); 755 756 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA; 757 if (!IsNSA) { 758 if (AddrSize > 8) 759 AddrSize = 16; 760 } else { 761 if (AddrSize > Info->VAddrDwords) { 762 // The NSA encoding does not contain enough operands for the combination 763 // of base opcode / dimension. Should this be an error? 764 return MCDisassembler::Success; 765 } 766 } 767 } 768 769 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 770 unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u); 771 772 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 773 if (D16 && AMDGPU::hasPackedD16(STI)) { 774 DstSize = (DstSize + 1) / 2; 775 } 776 777 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm()) 778 DstSize += 1; 779 780 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 781 return MCDisassembler::Success; 782 783 int NewOpcode = 784 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 785 if (NewOpcode == -1) 786 return MCDisassembler::Success; 787 788 // Widen the register to the correct number of enabled channels. 789 unsigned NewVdata = AMDGPU::NoRegister; 790 if (DstSize != Info->VDataDwords) { 791 auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; 792 793 // Get first subregister of VData 794 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 795 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 796 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 797 798 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 799 &MRI.getRegClass(DataRCID)); 800 if (NewVdata == AMDGPU::NoRegister) { 801 // It's possible to encode this such that the low register + enabled 802 // components exceeds the register count. 803 return MCDisassembler::Success; 804 } 805 } 806 807 unsigned NewVAddr0 = AMDGPU::NoRegister; 808 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10] && !IsNSA && 809 AddrSize != Info->VAddrDwords) { 810 unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg(); 811 unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0); 812 VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0; 813 814 auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass; 815 NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0, 816 &MRI.getRegClass(AddrRCID)); 817 if (NewVAddr0 == AMDGPU::NoRegister) 818 return MCDisassembler::Success; 819 } 820 821 MI.setOpcode(NewOpcode); 822 823 if (NewVdata != AMDGPU::NoRegister) { 824 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 825 826 if (IsAtomic) { 827 // Atomic operations have an additional operand (a copy of data) 828 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 829 } 830 } 831 832 if (NewVAddr0 != AMDGPU::NoRegister) { 833 MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0); 834 } else if (IsNSA) { 835 assert(AddrSize <= Info->VAddrDwords); 836 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 837 MI.begin() + VAddr0Idx + Info->VAddrDwords); 838 } 839 840 return MCDisassembler::Success; 841 } 842 843 DecodeStatus AMDGPUDisassembler::convertFMAanyK(MCInst &MI, 844 int ImmLitIdx) const { 845 assert(HasLiteral && "Should have decoded a literal"); 846 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 847 unsigned DescNumOps = Desc.getNumOperands(); 848 assert(DescNumOps == MI.getNumOperands()); 849 for (unsigned I = 0; I < DescNumOps; ++I) { 850 auto &Op = MI.getOperand(I); 851 auto OpType = Desc.OpInfo[I].OperandType; 852 bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED || 853 OpType == AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED); 854 if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST && 855 IsDeferredOp) 856 Op.setImm(Literal); 857 } 858 return MCDisassembler::Success; 859 } 860 861 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 862 return getContext().getRegisterInfo()-> 863 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 864 } 865 866 inline 867 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 868 const Twine& ErrMsg) const { 869 *CommentStream << "Error: " + ErrMsg; 870 871 // ToDo: add support for error operands to MCInst.h 872 // return MCOperand::createError(V); 873 return MCOperand(); 874 } 875 876 inline 877 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 878 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 879 } 880 881 inline 882 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 883 unsigned Val) const { 884 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 885 if (Val >= RegCl.getNumRegs()) 886 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 887 ": unknown register " + Twine(Val)); 888 return createRegOperand(RegCl.getRegister(Val)); 889 } 890 891 inline 892 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 893 unsigned Val) const { 894 // ToDo: SI/CI have 104 SGPRs, VI - 102 895 // Valery: here we accepting as much as we can, let assembler sort it out 896 int shift = 0; 897 switch (SRegClassID) { 898 case AMDGPU::SGPR_32RegClassID: 899 case AMDGPU::TTMP_32RegClassID: 900 break; 901 case AMDGPU::SGPR_64RegClassID: 902 case AMDGPU::TTMP_64RegClassID: 903 shift = 1; 904 break; 905 case AMDGPU::SGPR_128RegClassID: 906 case AMDGPU::TTMP_128RegClassID: 907 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 908 // this bundle? 909 case AMDGPU::SGPR_256RegClassID: 910 case AMDGPU::TTMP_256RegClassID: 911 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 912 // this bundle? 913 case AMDGPU::SGPR_512RegClassID: 914 case AMDGPU::TTMP_512RegClassID: 915 shift = 2; 916 break; 917 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 918 // this bundle? 919 default: 920 llvm_unreachable("unhandled register class"); 921 } 922 923 if (Val % (1 << shift)) { 924 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 925 << ": scalar reg isn't aligned " << Val; 926 } 927 928 return createRegOperand(SRegClassID, Val >> shift); 929 } 930 931 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { 932 return decodeSrcOp(OPW32, Val); 933 } 934 935 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { 936 return decodeSrcOp(OPW64, Val); 937 } 938 939 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const { 940 return decodeSrcOp(OPW128, Val); 941 } 942 943 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const { 944 return decodeSrcOp(OPW16, Val); 945 } 946 947 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const { 948 return decodeSrcOp(OPWV216, Val); 949 } 950 951 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV232(unsigned Val) const { 952 return decodeSrcOp(OPWV232, Val); 953 } 954 955 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { 956 // Some instructions have operand restrictions beyond what the encoding 957 // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra 958 // high bit. 959 Val &= 255; 960 961 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); 962 } 963 964 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const { 965 return decodeSrcOp(OPW32, Val); 966 } 967 968 MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const { 969 return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255); 970 } 971 972 MCOperand AMDGPUDisassembler::decodeOperand_AReg_64(unsigned Val) const { 973 return createRegOperand(AMDGPU::AReg_64RegClassID, Val & 255); 974 } 975 976 MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const { 977 return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255); 978 } 979 980 MCOperand AMDGPUDisassembler::decodeOperand_AReg_256(unsigned Val) const { 981 return createRegOperand(AMDGPU::AReg_256RegClassID, Val & 255); 982 } 983 984 MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const { 985 return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255); 986 } 987 988 MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const { 989 return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255); 990 } 991 992 MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const { 993 return decodeSrcOp(OPW32, Val); 994 } 995 996 MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const { 997 return decodeSrcOp(OPW64, Val); 998 } 999 1000 MCOperand AMDGPUDisassembler::decodeOperand_AV_128(unsigned Val) const { 1001 return decodeSrcOp(OPW128, Val); 1002 } 1003 1004 MCOperand AMDGPUDisassembler::decodeOperand_AVDst_128(unsigned Val) const { 1005 using namespace AMDGPU::EncValues; 1006 assert((Val & IS_VGPR) == 0); // Val{8} is not encoded but assumed to be 1. 1007 return decodeSrcOp(OPW128, Val | IS_VGPR); 1008 } 1009 1010 MCOperand AMDGPUDisassembler::decodeOperand_AVDst_512(unsigned Val) const { 1011 using namespace AMDGPU::EncValues; 1012 assert((Val & IS_VGPR) == 0); // Val{8} is not encoded but assumed to be 1. 1013 return decodeSrcOp(OPW512, Val | IS_VGPR); 1014 } 1015 1016 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { 1017 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); 1018 } 1019 1020 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { 1021 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); 1022 } 1023 1024 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { 1025 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); 1026 } 1027 1028 MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const { 1029 return createRegOperand(AMDGPU::VReg_256RegClassID, Val); 1030 } 1031 1032 MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const { 1033 return createRegOperand(AMDGPU::VReg_512RegClassID, Val); 1034 } 1035 1036 MCOperand AMDGPUDisassembler::decodeOperand_VReg_1024(unsigned Val) const { 1037 return createRegOperand(AMDGPU::VReg_1024RegClassID, Val); 1038 } 1039 1040 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { 1041 // table-gen generated disassembler doesn't care about operand types 1042 // leaving only registry class so SSrc_32 operand turns into SReg_32 1043 // and therefore we accept immediates and literals here as well 1044 return decodeSrcOp(OPW32, Val); 1045 } 1046 1047 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC( 1048 unsigned Val) const { 1049 // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI 1050 return decodeOperand_SReg_32(Val); 1051 } 1052 1053 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI( 1054 unsigned Val) const { 1055 // SReg_32_XM0 is SReg_32 without EXEC_HI 1056 return decodeOperand_SReg_32(Val); 1057 } 1058 1059 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const { 1060 // table-gen generated disassembler doesn't care about operand types 1061 // leaving only registry class so SSrc_32 operand turns into SReg_32 1062 // and therefore we accept immediates and literals here as well 1063 return decodeSrcOp(OPW32, Val); 1064 } 1065 1066 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { 1067 return decodeSrcOp(OPW64, Val); 1068 } 1069 1070 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const { 1071 return decodeSrcOp(OPW64, Val); 1072 } 1073 1074 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { 1075 return decodeSrcOp(OPW128, Val); 1076 } 1077 1078 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { 1079 return decodeDstOp(OPW256, Val); 1080 } 1081 1082 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { 1083 return decodeDstOp(OPW512, Val); 1084 } 1085 1086 // Decode Literals for insts which always have a literal in the encoding 1087 MCOperand 1088 AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const { 1089 if (HasLiteral) { 1090 if (Literal != Val) 1091 return errOperand(Val, "More than one unique literal is illegal"); 1092 } 1093 HasLiteral = true; 1094 Literal = Val; 1095 return MCOperand::createImm(Literal); 1096 } 1097 1098 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { 1099 // For now all literal constants are supposed to be unsigned integer 1100 // ToDo: deal with signed/unsigned 64-bit integer constants 1101 // ToDo: deal with float/double constants 1102 if (!HasLiteral) { 1103 if (Bytes.size() < 4) { 1104 return errOperand(0, "cannot read literal, inst bytes left " + 1105 Twine(Bytes.size())); 1106 } 1107 HasLiteral = true; 1108 Literal = eatBytes<uint32_t>(Bytes); 1109 } 1110 return MCOperand::createImm(Literal); 1111 } 1112 1113 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 1114 using namespace AMDGPU::EncValues; 1115 1116 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 1117 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 1118 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 1119 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 1120 // Cast prevents negative overflow. 1121 } 1122 1123 static int64_t getInlineImmVal32(unsigned Imm) { 1124 switch (Imm) { 1125 case 240: 1126 return FloatToBits(0.5f); 1127 case 241: 1128 return FloatToBits(-0.5f); 1129 case 242: 1130 return FloatToBits(1.0f); 1131 case 243: 1132 return FloatToBits(-1.0f); 1133 case 244: 1134 return FloatToBits(2.0f); 1135 case 245: 1136 return FloatToBits(-2.0f); 1137 case 246: 1138 return FloatToBits(4.0f); 1139 case 247: 1140 return FloatToBits(-4.0f); 1141 case 248: // 1 / (2 * PI) 1142 return 0x3e22f983; 1143 default: 1144 llvm_unreachable("invalid fp inline imm"); 1145 } 1146 } 1147 1148 static int64_t getInlineImmVal64(unsigned Imm) { 1149 switch (Imm) { 1150 case 240: 1151 return DoubleToBits(0.5); 1152 case 241: 1153 return DoubleToBits(-0.5); 1154 case 242: 1155 return DoubleToBits(1.0); 1156 case 243: 1157 return DoubleToBits(-1.0); 1158 case 244: 1159 return DoubleToBits(2.0); 1160 case 245: 1161 return DoubleToBits(-2.0); 1162 case 246: 1163 return DoubleToBits(4.0); 1164 case 247: 1165 return DoubleToBits(-4.0); 1166 case 248: // 1 / (2 * PI) 1167 return 0x3fc45f306dc9c882; 1168 default: 1169 llvm_unreachable("invalid fp inline imm"); 1170 } 1171 } 1172 1173 static int64_t getInlineImmVal16(unsigned Imm) { 1174 switch (Imm) { 1175 case 240: 1176 return 0x3800; 1177 case 241: 1178 return 0xB800; 1179 case 242: 1180 return 0x3C00; 1181 case 243: 1182 return 0xBC00; 1183 case 244: 1184 return 0x4000; 1185 case 245: 1186 return 0xC000; 1187 case 246: 1188 return 0x4400; 1189 case 247: 1190 return 0xC400; 1191 case 248: // 1 / (2 * PI) 1192 return 0x3118; 1193 default: 1194 llvm_unreachable("invalid fp inline imm"); 1195 } 1196 } 1197 1198 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) { 1199 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 1200 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 1201 1202 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 1203 switch (Width) { 1204 case OPW32: 1205 case OPW128: // splat constants 1206 case OPW512: 1207 case OPW1024: 1208 case OPWV232: 1209 return MCOperand::createImm(getInlineImmVal32(Imm)); 1210 case OPW64: 1211 case OPW256: 1212 return MCOperand::createImm(getInlineImmVal64(Imm)); 1213 case OPW16: 1214 case OPWV216: 1215 return MCOperand::createImm(getInlineImmVal16(Imm)); 1216 default: 1217 llvm_unreachable("implement me"); 1218 } 1219 } 1220 1221 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 1222 using namespace AMDGPU; 1223 1224 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1225 switch (Width) { 1226 default: // fall 1227 case OPW32: 1228 case OPW16: 1229 case OPWV216: 1230 return VGPR_32RegClassID; 1231 case OPW64: 1232 case OPWV232: return VReg_64RegClassID; 1233 case OPW96: return VReg_96RegClassID; 1234 case OPW128: return VReg_128RegClassID; 1235 case OPW160: return VReg_160RegClassID; 1236 case OPW256: return VReg_256RegClassID; 1237 case OPW512: return VReg_512RegClassID; 1238 case OPW1024: return VReg_1024RegClassID; 1239 } 1240 } 1241 1242 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 1243 using namespace AMDGPU; 1244 1245 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1246 switch (Width) { 1247 default: // fall 1248 case OPW32: 1249 case OPW16: 1250 case OPWV216: 1251 return AGPR_32RegClassID; 1252 case OPW64: 1253 case OPWV232: return AReg_64RegClassID; 1254 case OPW96: return AReg_96RegClassID; 1255 case OPW128: return AReg_128RegClassID; 1256 case OPW160: return AReg_160RegClassID; 1257 case OPW256: return AReg_256RegClassID; 1258 case OPW512: return AReg_512RegClassID; 1259 case OPW1024: return AReg_1024RegClassID; 1260 } 1261 } 1262 1263 1264 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 1265 using namespace AMDGPU; 1266 1267 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1268 switch (Width) { 1269 default: // fall 1270 case OPW32: 1271 case OPW16: 1272 case OPWV216: 1273 return SGPR_32RegClassID; 1274 case OPW64: 1275 case OPWV232: return SGPR_64RegClassID; 1276 case OPW96: return SGPR_96RegClassID; 1277 case OPW128: return SGPR_128RegClassID; 1278 case OPW160: return SGPR_160RegClassID; 1279 case OPW256: return SGPR_256RegClassID; 1280 case OPW512: return SGPR_512RegClassID; 1281 } 1282 } 1283 1284 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 1285 using namespace AMDGPU; 1286 1287 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1288 switch (Width) { 1289 default: // fall 1290 case OPW32: 1291 case OPW16: 1292 case OPWV216: 1293 return TTMP_32RegClassID; 1294 case OPW64: 1295 case OPWV232: return TTMP_64RegClassID; 1296 case OPW128: return TTMP_128RegClassID; 1297 case OPW256: return TTMP_256RegClassID; 1298 case OPW512: return TTMP_512RegClassID; 1299 } 1300 } 1301 1302 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 1303 using namespace AMDGPU::EncValues; 1304 1305 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN; 1306 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX; 1307 1308 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1309 } 1310 1311 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val, 1312 bool MandatoryLiteral) const { 1313 using namespace AMDGPU::EncValues; 1314 1315 assert(Val < 1024); // enum10 1316 1317 bool IsAGPR = Val & 512; 1318 Val &= 511; 1319 1320 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1321 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1322 : getVgprClassId(Width), Val - VGPR_MIN); 1323 } 1324 if (Val <= SGPR_MAX) { 1325 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1326 static_assert(SGPR_MIN == 0, ""); 1327 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1328 } 1329 1330 int TTmpIdx = getTTmpIdx(Val); 1331 if (TTmpIdx >= 0) { 1332 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1333 } 1334 1335 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1336 return decodeIntImmed(Val); 1337 1338 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1339 return decodeFPImmed(Width, Val); 1340 1341 if (Val == LITERAL_CONST) { 1342 if (MandatoryLiteral) 1343 // Keep a sentinel value for deferred setting 1344 return MCOperand::createImm(LITERAL_CONST); 1345 else 1346 return decodeLiteralConstant(); 1347 } 1348 1349 switch (Width) { 1350 case OPW32: 1351 case OPW16: 1352 case OPWV216: 1353 return decodeSpecialReg32(Val); 1354 case OPW64: 1355 case OPWV232: 1356 return decodeSpecialReg64(Val); 1357 default: 1358 llvm_unreachable("unexpected immediate type"); 1359 } 1360 } 1361 1362 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const { 1363 using namespace AMDGPU::EncValues; 1364 1365 assert(Val < 128); 1366 assert(Width == OPW256 || Width == OPW512); 1367 1368 if (Val <= SGPR_MAX) { 1369 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1370 static_assert(SGPR_MIN == 0, ""); 1371 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1372 } 1373 1374 int TTmpIdx = getTTmpIdx(Val); 1375 if (TTmpIdx >= 0) { 1376 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1377 } 1378 1379 llvm_unreachable("unknown dst register"); 1380 } 1381 1382 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1383 using namespace AMDGPU; 1384 1385 switch (Val) { 1386 case 102: return createRegOperand(FLAT_SCR_LO); 1387 case 103: return createRegOperand(FLAT_SCR_HI); 1388 case 104: return createRegOperand(XNACK_MASK_LO); 1389 case 105: return createRegOperand(XNACK_MASK_HI); 1390 case 106: return createRegOperand(VCC_LO); 1391 case 107: return createRegOperand(VCC_HI); 1392 case 108: return createRegOperand(TBA_LO); 1393 case 109: return createRegOperand(TBA_HI); 1394 case 110: return createRegOperand(TMA_LO); 1395 case 111: return createRegOperand(TMA_HI); 1396 case 124: 1397 return isGFX11Plus() ? createRegOperand(SGPR_NULL) : createRegOperand(M0); 1398 case 125: 1399 return isGFX11Plus() ? createRegOperand(M0) : createRegOperand(SGPR_NULL); 1400 case 126: return createRegOperand(EXEC_LO); 1401 case 127: return createRegOperand(EXEC_HI); 1402 case 235: return createRegOperand(SRC_SHARED_BASE); 1403 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1404 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1405 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1406 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1407 case 251: return createRegOperand(SRC_VCCZ); 1408 case 252: return createRegOperand(SRC_EXECZ); 1409 case 253: return createRegOperand(SRC_SCC); 1410 case 254: return createRegOperand(LDS_DIRECT); 1411 default: break; 1412 } 1413 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1414 } 1415 1416 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1417 using namespace AMDGPU; 1418 1419 switch (Val) { 1420 case 102: return createRegOperand(FLAT_SCR); 1421 case 104: return createRegOperand(XNACK_MASK); 1422 case 106: return createRegOperand(VCC); 1423 case 108: return createRegOperand(TBA); 1424 case 110: return createRegOperand(TMA); 1425 case 124: 1426 if (isGFX11Plus()) 1427 return createRegOperand(SGPR_NULL); 1428 break; 1429 case 125: 1430 if (!isGFX11Plus()) 1431 return createRegOperand(SGPR_NULL); 1432 break; 1433 case 126: return createRegOperand(EXEC); 1434 case 235: return createRegOperand(SRC_SHARED_BASE); 1435 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1436 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1437 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1438 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1439 case 251: return createRegOperand(SRC_VCCZ); 1440 case 252: return createRegOperand(SRC_EXECZ); 1441 case 253: return createRegOperand(SRC_SCC); 1442 default: break; 1443 } 1444 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1445 } 1446 1447 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 1448 const unsigned Val) const { 1449 using namespace AMDGPU::SDWA; 1450 using namespace AMDGPU::EncValues; 1451 1452 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1453 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 1454 // XXX: cast to int is needed to avoid stupid warning: 1455 // compare with unsigned is always true 1456 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1457 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1458 return createRegOperand(getVgprClassId(Width), 1459 Val - SDWA9EncValues::SRC_VGPR_MIN); 1460 } 1461 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1462 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1463 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1464 return createSRegOperand(getSgprClassId(Width), 1465 Val - SDWA9EncValues::SRC_SGPR_MIN); 1466 } 1467 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1468 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1469 return createSRegOperand(getTtmpClassId(Width), 1470 Val - SDWA9EncValues::SRC_TTMP_MIN); 1471 } 1472 1473 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1474 1475 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1476 return decodeIntImmed(SVal); 1477 1478 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1479 return decodeFPImmed(Width, SVal); 1480 1481 return decodeSpecialReg32(SVal); 1482 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 1483 return createRegOperand(getVgprClassId(Width), Val); 1484 } 1485 llvm_unreachable("unsupported target"); 1486 } 1487 1488 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1489 return decodeSDWASrc(OPW16, Val); 1490 } 1491 1492 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1493 return decodeSDWASrc(OPW32, Val); 1494 } 1495 1496 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1497 using namespace AMDGPU::SDWA; 1498 1499 assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1500 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) && 1501 "SDWAVopcDst should be present only on GFX9+"); 1502 1503 bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64]; 1504 1505 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1506 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1507 1508 int TTmpIdx = getTTmpIdx(Val); 1509 if (TTmpIdx >= 0) { 1510 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1511 return createSRegOperand(TTmpClsId, TTmpIdx); 1512 } else if (Val > SGPR_MAX) { 1513 return IsWave64 ? decodeSpecialReg64(Val) 1514 : decodeSpecialReg32(Val); 1515 } else { 1516 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1517 } 1518 } else { 1519 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1520 } 1521 } 1522 1523 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1524 return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ? 1525 decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val); 1526 } 1527 1528 bool AMDGPUDisassembler::isVI() const { 1529 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]; 1530 } 1531 1532 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } 1533 1534 bool AMDGPUDisassembler::isGFX90A() const { 1535 return STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]; 1536 } 1537 1538 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } 1539 1540 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } 1541 1542 bool AMDGPUDisassembler::isGFX10Plus() const { 1543 return AMDGPU::isGFX10Plus(STI); 1544 } 1545 1546 bool AMDGPUDisassembler::isGFX11() const { 1547 return STI.getFeatureBits()[AMDGPU::FeatureGFX11]; 1548 } 1549 1550 bool AMDGPUDisassembler::isGFX11Plus() const { 1551 return AMDGPU::isGFX11Plus(STI); 1552 } 1553 1554 1555 bool AMDGPUDisassembler::hasArchitectedFlatScratch() const { 1556 return STI.getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch]; 1557 } 1558 1559 //===----------------------------------------------------------------------===// 1560 // AMDGPU specific symbol handling 1561 //===----------------------------------------------------------------------===// 1562 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1563 do { \ 1564 KdStream << Indent << DIRECTIVE " " \ 1565 << ((FourByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1566 } while (0) 1567 1568 // NOLINTNEXTLINE(readability-identifier-naming) 1569 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1570 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1571 using namespace amdhsa; 1572 StringRef Indent = "\t"; 1573 1574 // We cannot accurately backward compute #VGPRs used from 1575 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1576 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1577 // simply calculate the inverse of what the assembler does. 1578 1579 uint32_t GranulatedWorkitemVGPRCount = 1580 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT) >> 1581 COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT; 1582 1583 uint32_t NextFreeVGPR = (GranulatedWorkitemVGPRCount + 1) * 1584 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI); 1585 1586 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1587 1588 // We cannot backward compute values used to calculate 1589 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1590 // directives can't be computed: 1591 // .amdhsa_reserve_vcc 1592 // .amdhsa_reserve_flat_scratch 1593 // .amdhsa_reserve_xnack_mask 1594 // They take their respective default values if not specified in the assembly. 1595 // 1596 // GRANULATED_WAVEFRONT_SGPR_COUNT 1597 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1598 // 1599 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1600 // are set to 0. So while disassembling we consider that: 1601 // 1602 // GRANULATED_WAVEFRONT_SGPR_COUNT 1603 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1604 // 1605 // The disassembler cannot recover the original values of those 3 directives. 1606 1607 uint32_t GranulatedWavefrontSGPRCount = 1608 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT) >> 1609 COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT; 1610 1611 if (isGFX10Plus() && GranulatedWavefrontSGPRCount) 1612 return MCDisassembler::Fail; 1613 1614 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1615 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1616 1617 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1618 if (!hasArchitectedFlatScratch()) 1619 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1620 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1621 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1622 1623 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY) 1624 return MCDisassembler::Fail; 1625 1626 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1627 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1628 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1629 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1630 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1631 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1632 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1633 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1634 1635 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) 1636 return MCDisassembler::Fail; 1637 1638 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 1639 1640 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) 1641 return MCDisassembler::Fail; 1642 1643 PRINT_DIRECTIVE(".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 1644 1645 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) 1646 return MCDisassembler::Fail; 1647 1648 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER) 1649 return MCDisassembler::Fail; 1650 1651 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_FP16_OVFL); 1652 1653 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED0) 1654 return MCDisassembler::Fail; 1655 1656 if (isGFX10Plus()) { 1657 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1658 COMPUTE_PGM_RSRC1_WGP_MODE); 1659 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_MEM_ORDERED); 1660 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_FWD_PROGRESS); 1661 } 1662 return MCDisassembler::Success; 1663 } 1664 1665 // NOLINTNEXTLINE(readability-identifier-naming) 1666 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 1667 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1668 using namespace amdhsa; 1669 StringRef Indent = "\t"; 1670 if (hasArchitectedFlatScratch()) 1671 PRINT_DIRECTIVE(".amdhsa_enable_private_segment", 1672 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1673 else 1674 PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset", 1675 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1676 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 1677 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 1678 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 1679 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 1680 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 1681 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 1682 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 1683 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 1684 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 1685 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 1686 1687 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH) 1688 return MCDisassembler::Fail; 1689 1690 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY) 1691 return MCDisassembler::Fail; 1692 1693 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE) 1694 return MCDisassembler::Fail; 1695 1696 PRINT_DIRECTIVE( 1697 ".amdhsa_exception_fp_ieee_invalid_op", 1698 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 1699 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 1700 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 1701 PRINT_DIRECTIVE( 1702 ".amdhsa_exception_fp_ieee_div_zero", 1703 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 1704 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 1705 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 1706 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 1707 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 1708 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 1709 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 1710 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 1711 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 1712 1713 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0) 1714 return MCDisassembler::Fail; 1715 1716 return MCDisassembler::Success; 1717 } 1718 1719 #undef PRINT_DIRECTIVE 1720 1721 MCDisassembler::DecodeStatus 1722 AMDGPUDisassembler::decodeKernelDescriptorDirective( 1723 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 1724 raw_string_ostream &KdStream) const { 1725 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1726 do { \ 1727 KdStream << Indent << DIRECTIVE " " \ 1728 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1729 } while (0) 1730 1731 uint16_t TwoByteBuffer = 0; 1732 uint32_t FourByteBuffer = 0; 1733 1734 StringRef ReservedBytes; 1735 StringRef Indent = "\t"; 1736 1737 assert(Bytes.size() == 64); 1738 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 1739 1740 switch (Cursor.tell()) { 1741 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 1742 FourByteBuffer = DE.getU32(Cursor); 1743 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 1744 << '\n'; 1745 return MCDisassembler::Success; 1746 1747 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 1748 FourByteBuffer = DE.getU32(Cursor); 1749 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 1750 << FourByteBuffer << '\n'; 1751 return MCDisassembler::Success; 1752 1753 case amdhsa::KERNARG_SIZE_OFFSET: 1754 FourByteBuffer = DE.getU32(Cursor); 1755 KdStream << Indent << ".amdhsa_kernarg_size " 1756 << FourByteBuffer << '\n'; 1757 return MCDisassembler::Success; 1758 1759 case amdhsa::RESERVED0_OFFSET: 1760 // 4 reserved bytes, must be 0. 1761 ReservedBytes = DE.getBytes(Cursor, 4); 1762 for (int I = 0; I < 4; ++I) { 1763 if (ReservedBytes[I] != 0) { 1764 return MCDisassembler::Fail; 1765 } 1766 } 1767 return MCDisassembler::Success; 1768 1769 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 1770 // KERNEL_CODE_ENTRY_BYTE_OFFSET 1771 // So far no directive controls this for Code Object V3, so simply skip for 1772 // disassembly. 1773 DE.skip(Cursor, 8); 1774 return MCDisassembler::Success; 1775 1776 case amdhsa::RESERVED1_OFFSET: 1777 // 20 reserved bytes, must be 0. 1778 ReservedBytes = DE.getBytes(Cursor, 20); 1779 for (int I = 0; I < 20; ++I) { 1780 if (ReservedBytes[I] != 0) { 1781 return MCDisassembler::Fail; 1782 } 1783 } 1784 return MCDisassembler::Success; 1785 1786 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 1787 // COMPUTE_PGM_RSRC3 1788 // - Only set for GFX10, GFX6-9 have this to be 0. 1789 // - Currently no directives directly control this. 1790 FourByteBuffer = DE.getU32(Cursor); 1791 if (!isGFX10Plus() && FourByteBuffer) { 1792 return MCDisassembler::Fail; 1793 } 1794 return MCDisassembler::Success; 1795 1796 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 1797 FourByteBuffer = DE.getU32(Cursor); 1798 if (decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream) == 1799 MCDisassembler::Fail) { 1800 return MCDisassembler::Fail; 1801 } 1802 return MCDisassembler::Success; 1803 1804 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 1805 FourByteBuffer = DE.getU32(Cursor); 1806 if (decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream) == 1807 MCDisassembler::Fail) { 1808 return MCDisassembler::Fail; 1809 } 1810 return MCDisassembler::Success; 1811 1812 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 1813 using namespace amdhsa; 1814 TwoByteBuffer = DE.getU16(Cursor); 1815 1816 if (!hasArchitectedFlatScratch()) 1817 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 1818 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 1819 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 1820 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 1821 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 1822 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 1823 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 1824 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 1825 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 1826 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 1827 if (!hasArchitectedFlatScratch()) 1828 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 1829 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 1830 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 1831 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 1832 1833 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 1834 return MCDisassembler::Fail; 1835 1836 // Reserved for GFX9 1837 if (isGFX9() && 1838 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 1839 return MCDisassembler::Fail; 1840 } else if (isGFX10Plus()) { 1841 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 1842 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 1843 } 1844 1845 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) 1846 return MCDisassembler::Fail; 1847 1848 return MCDisassembler::Success; 1849 1850 case amdhsa::RESERVED2_OFFSET: 1851 // 6 bytes from here are reserved, must be 0. 1852 ReservedBytes = DE.getBytes(Cursor, 6); 1853 for (int I = 0; I < 6; ++I) { 1854 if (ReservedBytes[I] != 0) 1855 return MCDisassembler::Fail; 1856 } 1857 return MCDisassembler::Success; 1858 1859 default: 1860 llvm_unreachable("Unhandled index. Case statements cover everything."); 1861 return MCDisassembler::Fail; 1862 } 1863 #undef PRINT_DIRECTIVE 1864 } 1865 1866 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( 1867 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 1868 // CP microcode requires the kernel descriptor to be 64 aligned. 1869 if (Bytes.size() != 64 || KdAddress % 64 != 0) 1870 return MCDisassembler::Fail; 1871 1872 std::string Kd; 1873 raw_string_ostream KdStream(Kd); 1874 KdStream << ".amdhsa_kernel " << KdName << '\n'; 1875 1876 DataExtractor::Cursor C(0); 1877 while (C && C.tell() < Bytes.size()) { 1878 MCDisassembler::DecodeStatus Status = 1879 decodeKernelDescriptorDirective(C, Bytes, KdStream); 1880 1881 cantFail(C.takeError()); 1882 1883 if (Status == MCDisassembler::Fail) 1884 return MCDisassembler::Fail; 1885 } 1886 KdStream << ".end_amdhsa_kernel\n"; 1887 outs() << KdStream.str(); 1888 return MCDisassembler::Success; 1889 } 1890 1891 Optional<MCDisassembler::DecodeStatus> 1892 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 1893 ArrayRef<uint8_t> Bytes, uint64_t Address, 1894 raw_ostream &CStream) const { 1895 // Right now only kernel descriptor needs to be handled. 1896 // We ignore all other symbols for target specific handling. 1897 // TODO: 1898 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 1899 // Object V2 and V3 when symbols are marked protected. 1900 1901 // amd_kernel_code_t for Code Object V2. 1902 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 1903 Size = 256; 1904 return MCDisassembler::Fail; 1905 } 1906 1907 // Code Object V3 kernel descriptors. 1908 StringRef Name = Symbol.Name; 1909 if (Symbol.Type == ELF::STT_OBJECT && Name.endswith(StringRef(".kd"))) { 1910 Size = 64; // Size = 64 regardless of success or failure. 1911 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 1912 } 1913 return None; 1914 } 1915 1916 //===----------------------------------------------------------------------===// 1917 // AMDGPUSymbolizer 1918 //===----------------------------------------------------------------------===// 1919 1920 // Try to find symbol name for specified label 1921 bool AMDGPUSymbolizer::tryAddingSymbolicOperand( 1922 MCInst &Inst, raw_ostream & /*cStream*/, int64_t Value, 1923 uint64_t /*Address*/, bool IsBranch, uint64_t /*Offset*/, 1924 uint64_t /*OpSize*/, uint64_t /*InstSize*/) { 1925 1926 if (!IsBranch) { 1927 return false; 1928 } 1929 1930 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 1931 if (!Symbols) 1932 return false; 1933 1934 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { 1935 return Val.Addr == static_cast<uint64_t>(Value) && 1936 Val.Type == ELF::STT_NOTYPE; 1937 }); 1938 if (Result != Symbols->end()) { 1939 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 1940 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 1941 Inst.addOperand(MCOperand::createExpr(Add)); 1942 return true; 1943 } 1944 // Add to list of referenced addresses, so caller can synthesize a label. 1945 ReferencedAddresses.push_back(static_cast<uint64_t>(Value)); 1946 return false; 1947 } 1948 1949 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 1950 int64_t Value, 1951 uint64_t Address) { 1952 llvm_unreachable("unimplemented"); 1953 } 1954 1955 //===----------------------------------------------------------------------===// 1956 // Initialization 1957 //===----------------------------------------------------------------------===// 1958 1959 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 1960 LLVMOpInfoCallback /*GetOpInfo*/, 1961 LLVMSymbolLookupCallback /*SymbolLookUp*/, 1962 void *DisInfo, 1963 MCContext *Ctx, 1964 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 1965 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 1966 } 1967 1968 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 1969 const MCSubtargetInfo &STI, 1970 MCContext &Ctx) { 1971 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 1972 } 1973 1974 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 1975 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 1976 createAMDGPUDisassembler); 1977 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 1978 createAMDGPUSymbolizer); 1979 } 1980