1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "SIDefines.h" 22 #include "SIRegisterInfo.h" 23 #include "TargetInfo/AMDGPUTargetInfo.h" 24 #include "Utils/AMDGPUBaseInfo.h" 25 #include "llvm-c/DisassemblerTypes.h" 26 #include "llvm/BinaryFormat/ELF.h" 27 #include "llvm/MC/MCAsmInfo.h" 28 #include "llvm/MC/MCContext.h" 29 #include "llvm/MC/MCDecoderOps.h" 30 #include "llvm/MC/MCExpr.h" 31 #include "llvm/MC/MCInstrDesc.h" 32 #include "llvm/MC/MCRegisterInfo.h" 33 #include "llvm/MC/MCSubtargetInfo.h" 34 #include "llvm/MC/TargetRegistry.h" 35 #include "llvm/Support/AMDHSAKernelDescriptor.h" 36 37 using namespace llvm; 38 39 #define DEBUG_TYPE "amdgpu-disassembler" 40 41 #define SGPR_MAX \ 42 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 43 : AMDGPU::EncValues::SGPR_MAX_SI) 44 45 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 46 47 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 48 MCContext &Ctx, MCInstrInfo const *MCII) 49 : MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), 50 MAI(*Ctx.getAsmInfo()), TargetMaxInstBytes(MAI.getMaxInstLength(&STI)), 51 CodeObjectVersion(AMDGPU::getDefaultAMDHSACodeObjectVersion()) { 52 // ToDo: AMDGPUDisassembler supports only VI ISA. 53 if (!STI.hasFeature(AMDGPU::FeatureGCN3Encoding) && !isGFX10Plus()) 54 report_fatal_error("Disassembly not yet supported for subtarget"); 55 } 56 57 void AMDGPUDisassembler::setABIVersion(unsigned Version) { 58 CodeObjectVersion = AMDGPU::getAMDHSACodeObjectVersion(Version); 59 } 60 61 inline static MCDisassembler::DecodeStatus 62 addOperand(MCInst &Inst, const MCOperand& Opnd) { 63 Inst.addOperand(Opnd); 64 return Opnd.isValid() ? 65 MCDisassembler::Success : 66 MCDisassembler::Fail; 67 } 68 69 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 70 uint16_t NameIdx) { 71 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 72 if (OpIdx != -1) { 73 auto I = MI.begin(); 74 std::advance(I, OpIdx); 75 MI.insert(I, Op); 76 } 77 return OpIdx; 78 } 79 80 static DecodeStatus decodeSOPPBrTarget(MCInst &Inst, unsigned Imm, 81 uint64_t Addr, 82 const MCDisassembler *Decoder) { 83 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 84 85 // Our branches take a simm16, but we need two extra bits to account for the 86 // factor of 4. 87 APInt SignedOffset(18, Imm * 4, true); 88 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 89 90 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2, 0)) 91 return MCDisassembler::Success; 92 return addOperand(Inst, MCOperand::createImm(Imm)); 93 } 94 95 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, 96 const MCDisassembler *Decoder) { 97 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 98 int64_t Offset; 99 if (DAsm->isGFX12Plus()) { // GFX12 supports 24-bit signed offsets. 100 Offset = SignExtend64<24>(Imm); 101 } else if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 102 Offset = Imm & 0xFFFFF; 103 } else { // GFX9+ supports 21-bit signed offsets. 104 Offset = SignExtend64<21>(Imm); 105 } 106 return addOperand(Inst, MCOperand::createImm(Offset)); 107 } 108 109 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, 110 const MCDisassembler *Decoder) { 111 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 112 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 113 } 114 115 static DecodeStatus decodeSplitBarrier(MCInst &Inst, unsigned Val, 116 uint64_t Addr, 117 const MCDisassembler *Decoder) { 118 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 119 return addOperand(Inst, DAsm->decodeSplitBarrier(Val)); 120 } 121 122 static DecodeStatus decodeDpp8FI(MCInst &Inst, unsigned Val, uint64_t Addr, 123 const MCDisassembler *Decoder) { 124 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 125 return addOperand(Inst, DAsm->decodeDpp8FI(Val)); 126 } 127 128 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 129 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \ 130 uint64_t /*Addr*/, \ 131 const MCDisassembler *Decoder) { \ 132 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 133 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 134 } 135 136 // Decoder for registers, decode directly using RegClassID. Imm(8-bit) is 137 // number of register. Used by VGPR only and AGPR only operands. 138 #define DECODE_OPERAND_REG_8(RegClass) \ 139 static DecodeStatus Decode##RegClass##RegisterClass( \ 140 MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \ 141 const MCDisassembler *Decoder) { \ 142 assert(Imm < (1 << 8) && "8-bit encoding"); \ 143 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 144 return addOperand( \ 145 Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm)); \ 146 } 147 148 #define DECODE_SrcOp(Name, EncSize, OpWidth, EncImm, MandatoryLiteral, \ 149 ImmWidth) \ 150 static DecodeStatus Name(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \ 151 const MCDisassembler *Decoder) { \ 152 assert(Imm < (1 << EncSize) && #EncSize "-bit encoding"); \ 153 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 154 return addOperand(Inst, \ 155 DAsm->decodeSrcOp(AMDGPUDisassembler::OpWidth, EncImm, \ 156 MandatoryLiteral, ImmWidth)); \ 157 } 158 159 static DecodeStatus decodeSrcOp(MCInst &Inst, unsigned EncSize, 160 AMDGPUDisassembler::OpWidthTy OpWidth, 161 unsigned Imm, unsigned EncImm, 162 bool MandatoryLiteral, unsigned ImmWidth, 163 AMDGPU::OperandSemantics Sema, 164 const MCDisassembler *Decoder) { 165 assert(Imm < (1U << EncSize) && "Operand doesn't fit encoding!"); 166 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 167 return addOperand(Inst, DAsm->decodeSrcOp(OpWidth, EncImm, MandatoryLiteral, 168 ImmWidth, Sema)); 169 } 170 171 // Decoder for registers. Imm(7-bit) is number of register, uses decodeSrcOp to 172 // get register class. Used by SGPR only operands. 173 #define DECODE_OPERAND_REG_7(RegClass, OpWidth) \ 174 DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0) 175 176 // Decoder for registers. Imm(10-bit): Imm{7-0} is number of register, 177 // Imm{9} is acc(agpr or vgpr) Imm{8} should be 0 (see VOP3Pe_SMFMAC). 178 // Set Imm{8} to 1 (IS_VGPR) to decode using 'enum10' from decodeSrcOp. 179 // Used by AV_ register classes (AGPR or VGPR only register operands). 180 template <AMDGPUDisassembler::OpWidthTy OpWidth> 181 static DecodeStatus decodeAV10(MCInst &Inst, unsigned Imm, uint64_t /* Addr */, 182 const MCDisassembler *Decoder) { 183 return decodeSrcOp(Inst, 10, OpWidth, Imm, Imm | AMDGPU::EncValues::IS_VGPR, 184 false, 0, AMDGPU::OperandSemantics::INT, Decoder); 185 } 186 187 // Decoder for Src(9-bit encoding) registers only. 188 template <AMDGPUDisassembler::OpWidthTy OpWidth> 189 static DecodeStatus decodeSrcReg9(MCInst &Inst, unsigned Imm, 190 uint64_t /* Addr */, 191 const MCDisassembler *Decoder) { 192 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, false, 0, 193 AMDGPU::OperandSemantics::INT, Decoder); 194 } 195 196 // Decoder for Src(9-bit encoding) AGPR, register number encoded in 9bits, set 197 // Imm{9} to 1 (set acc) and decode using 'enum10' from decodeSrcOp, registers 198 // only. 199 template <AMDGPUDisassembler::OpWidthTy OpWidth> 200 static DecodeStatus decodeSrcA9(MCInst &Inst, unsigned Imm, uint64_t /* Addr */, 201 const MCDisassembler *Decoder) { 202 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm | 512, false, 0, 203 AMDGPU::OperandSemantics::INT, Decoder); 204 } 205 206 // Decoder for 'enum10' from decodeSrcOp, Imm{0-8} is 9-bit Src encoding 207 // Imm{9} is acc, registers only. 208 template <AMDGPUDisassembler::OpWidthTy OpWidth> 209 static DecodeStatus decodeSrcAV10(MCInst &Inst, unsigned Imm, 210 uint64_t /* Addr */, 211 const MCDisassembler *Decoder) { 212 return decodeSrcOp(Inst, 10, OpWidth, Imm, Imm, false, 0, 213 AMDGPU::OperandSemantics::INT, Decoder); 214 } 215 216 // Decoder for RegisterOperands using 9-bit Src encoding. Operand can be 217 // register from RegClass or immediate. Registers that don't belong to RegClass 218 // will be decoded and InstPrinter will report warning. Immediate will be 219 // decoded into constant of size ImmWidth, should match width of immediate used 220 // by OperandType (important for floating point types). 221 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth, 222 unsigned OperandSemantics> 223 static DecodeStatus decodeSrcRegOrImm9(MCInst &Inst, unsigned Imm, 224 uint64_t /* Addr */, 225 const MCDisassembler *Decoder) { 226 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, false, ImmWidth, 227 (AMDGPU::OperandSemantics)OperandSemantics, Decoder); 228 } 229 230 // Decoder for Src(9-bit encoding) AGPR or immediate. Set Imm{9} to 1 (set acc) 231 // and decode using 'enum10' from decodeSrcOp. 232 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth, 233 unsigned OperandSemantics> 234 static DecodeStatus decodeSrcRegOrImmA9(MCInst &Inst, unsigned Imm, 235 uint64_t /* Addr */, 236 const MCDisassembler *Decoder) { 237 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm | 512, false, ImmWidth, 238 (AMDGPU::OperandSemantics)OperandSemantics, Decoder); 239 } 240 241 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth, 242 unsigned OperandSemantics> 243 static DecodeStatus decodeSrcRegOrImmDeferred9(MCInst &Inst, unsigned Imm, 244 uint64_t /* Addr */, 245 const MCDisassembler *Decoder) { 246 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, true, ImmWidth, 247 (AMDGPU::OperandSemantics)OperandSemantics, Decoder); 248 } 249 250 // Default decoders generated by tablegen: 'Decode<RegClass>RegisterClass' 251 // when RegisterClass is used as an operand. Most often used for destination 252 // operands. 253 254 DECODE_OPERAND_REG_8(VGPR_32) 255 DECODE_OPERAND_REG_8(VGPR_32_Lo128) 256 DECODE_OPERAND_REG_8(VReg_64) 257 DECODE_OPERAND_REG_8(VReg_96) 258 DECODE_OPERAND_REG_8(VReg_128) 259 DECODE_OPERAND_REG_8(VReg_256) 260 DECODE_OPERAND_REG_8(VReg_288) 261 DECODE_OPERAND_REG_8(VReg_352) 262 DECODE_OPERAND_REG_8(VReg_384) 263 DECODE_OPERAND_REG_8(VReg_512) 264 DECODE_OPERAND_REG_8(VReg_1024) 265 266 DECODE_OPERAND_REG_7(SReg_32, OPW32) 267 DECODE_OPERAND_REG_7(SReg_32_XEXEC, OPW32) 268 DECODE_OPERAND_REG_7(SReg_32_XM0_XEXEC, OPW32) 269 DECODE_OPERAND_REG_7(SReg_32_XEXEC_HI, OPW32) 270 DECODE_OPERAND_REG_7(SReg_64, OPW64) 271 DECODE_OPERAND_REG_7(SReg_64_XEXEC, OPW64) 272 DECODE_OPERAND_REG_7(SReg_96, OPW96) 273 DECODE_OPERAND_REG_7(SReg_128, OPW128) 274 DECODE_OPERAND_REG_7(SReg_256, OPW256) 275 DECODE_OPERAND_REG_7(SReg_512, OPW512) 276 277 DECODE_OPERAND_REG_8(AGPR_32) 278 DECODE_OPERAND_REG_8(AReg_64) 279 DECODE_OPERAND_REG_8(AReg_128) 280 DECODE_OPERAND_REG_8(AReg_256) 281 DECODE_OPERAND_REG_8(AReg_512) 282 DECODE_OPERAND_REG_8(AReg_1024) 283 284 static DecodeStatus DecodeVGPR_16RegisterClass(MCInst &Inst, unsigned Imm, 285 uint64_t /*Addr*/, 286 const MCDisassembler *Decoder) { 287 assert(isUInt<10>(Imm) && "10-bit encoding expected"); 288 assert((Imm & (1 << 8)) == 0 && "Imm{8} should not be used"); 289 290 bool IsHi = Imm & (1 << 9); 291 unsigned RegIdx = Imm & 0xff; 292 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 293 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 294 } 295 296 static DecodeStatus 297 DecodeVGPR_16_Lo128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, 298 const MCDisassembler *Decoder) { 299 assert(isUInt<8>(Imm) && "8-bit encoding expected"); 300 301 bool IsHi = Imm & (1 << 7); 302 unsigned RegIdx = Imm & 0x7f; 303 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 304 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 305 } 306 307 static DecodeStatus decodeOperand_VSrcT16_Lo128(MCInst &Inst, unsigned Imm, 308 uint64_t /*Addr*/, 309 const MCDisassembler *Decoder) { 310 assert(isUInt<9>(Imm) && "9-bit encoding expected"); 311 312 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 313 bool IsVGPR = Imm & (1 << 8); 314 if (IsVGPR) { 315 bool IsHi = Imm & (1 << 7); 316 unsigned RegIdx = Imm & 0x7f; 317 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 318 } 319 return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(AMDGPUDisassembler::OPW16, 320 Imm & 0xFF, false, 16)); 321 } 322 323 static DecodeStatus decodeOperand_VSrcT16(MCInst &Inst, unsigned Imm, 324 uint64_t /*Addr*/, 325 const MCDisassembler *Decoder) { 326 assert(isUInt<10>(Imm) && "10-bit encoding expected"); 327 328 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 329 bool IsVGPR = Imm & (1 << 8); 330 if (IsVGPR) { 331 bool IsHi = Imm & (1 << 9); 332 unsigned RegIdx = Imm & 0xff; 333 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 334 } 335 return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(AMDGPUDisassembler::OPW16, 336 Imm & 0xFF, false, 16)); 337 } 338 339 static DecodeStatus decodeOperand_KImmFP(MCInst &Inst, unsigned Imm, 340 uint64_t Addr, 341 const MCDisassembler *Decoder) { 342 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 343 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 344 } 345 346 static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val, 347 uint64_t Addr, const void *Decoder) { 348 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 349 return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val)); 350 } 351 352 static bool IsAGPROperand(const MCInst &Inst, int OpIdx, 353 const MCRegisterInfo *MRI) { 354 if (OpIdx < 0) 355 return false; 356 357 const MCOperand &Op = Inst.getOperand(OpIdx); 358 if (!Op.isReg()) 359 return false; 360 361 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); 362 auto Reg = Sub ? Sub : Op.getReg(); 363 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; 364 } 365 366 static DecodeStatus decodeAVLdSt(MCInst &Inst, unsigned Imm, 367 AMDGPUDisassembler::OpWidthTy Opw, 368 const MCDisassembler *Decoder) { 369 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 370 if (!DAsm->isGFX90A()) { 371 Imm &= 511; 372 } else { 373 // If atomic has both vdata and vdst their register classes are tied. 374 // The bit is decoded along with the vdst, first operand. We need to 375 // change register class to AGPR if vdst was AGPR. 376 // If a DS instruction has both data0 and data1 their register classes 377 // are also tied. 378 unsigned Opc = Inst.getOpcode(); 379 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; 380 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 381 : AMDGPU::OpName::vdata; 382 const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo(); 383 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); 384 if ((int)Inst.getNumOperands() == DataIdx) { 385 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); 386 if (IsAGPROperand(Inst, DstIdx, MRI)) 387 Imm |= 512; 388 } 389 390 if (TSFlags & SIInstrFlags::DS) { 391 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); 392 if ((int)Inst.getNumOperands() == Data2Idx && 393 IsAGPROperand(Inst, DataIdx, MRI)) 394 Imm |= 512; 395 } 396 } 397 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); 398 } 399 400 template <AMDGPUDisassembler::OpWidthTy Opw> 401 static DecodeStatus decodeAVLdSt(MCInst &Inst, unsigned Imm, 402 uint64_t /* Addr */, 403 const MCDisassembler *Decoder) { 404 return decodeAVLdSt(Inst, Imm, Opw, Decoder); 405 } 406 407 static DecodeStatus decodeOperand_VSrc_f64(MCInst &Inst, unsigned Imm, 408 uint64_t Addr, 409 const MCDisassembler *Decoder) { 410 assert(Imm < (1 << 9) && "9-bit encoding"); 411 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 412 return addOperand(Inst, 413 DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm, false, 64, 414 AMDGPU::OperandSemantics::FP64)); 415 } 416 417 #define DECODE_SDWA(DecName) \ 418 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 419 420 DECODE_SDWA(Src32) 421 DECODE_SDWA(Src16) 422 DECODE_SDWA(VopcDst) 423 424 #include "AMDGPUGenDisassemblerTables.inc" 425 426 //===----------------------------------------------------------------------===// 427 // 428 //===----------------------------------------------------------------------===// 429 430 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 431 assert(Bytes.size() >= sizeof(T)); 432 const auto Res = 433 support::endian::read<T, llvm::endianness::little>(Bytes.data()); 434 Bytes = Bytes.slice(sizeof(T)); 435 return Res; 436 } 437 438 static inline DecoderUInt128 eat12Bytes(ArrayRef<uint8_t> &Bytes) { 439 assert(Bytes.size() >= 12); 440 uint64_t Lo = 441 support::endian::read<uint64_t, llvm::endianness::little>(Bytes.data()); 442 Bytes = Bytes.slice(8); 443 uint64_t Hi = 444 support::endian::read<uint32_t, llvm::endianness::little>(Bytes.data()); 445 Bytes = Bytes.slice(4); 446 return DecoderUInt128(Lo, Hi); 447 } 448 449 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 450 ArrayRef<uint8_t> Bytes_, 451 uint64_t Address, 452 raw_ostream &CS) const { 453 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 454 Bytes = Bytes_.slice(0, MaxInstBytesNum); 455 456 DecodeStatus Res = MCDisassembler::Fail; 457 do { 458 // ToDo: better to switch encoding length using some bit predicate 459 // but it is unknown yet, so try all we can 460 461 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 462 // encodings 463 if (isGFX11Plus() && Bytes.size() >= 12 ) { 464 DecoderUInt128 DecW = eat12Bytes(Bytes); 465 Res = 466 tryDecodeInst(DecoderTableDPP8GFX1196, DecoderTableDPP8GFX11_FAKE1696, 467 MI, DecW, Address, CS); 468 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 469 break; 470 Res = 471 tryDecodeInst(DecoderTableDPP8GFX1296, DecoderTableDPP8GFX12_FAKE1696, 472 MI, DecW, Address, CS); 473 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 474 break; 475 476 const auto convertVOPDPP = [&]() { 477 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3P) { 478 convertVOP3PDPPInst(MI); 479 } else if (AMDGPU::isVOPC64DPP(MI.getOpcode())) { 480 convertVOPCDPPInst(MI); // Special VOP3 case 481 } else { 482 assert(MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3); 483 convertVOP3DPPInst(MI); // Regular VOP3 case 484 } 485 }; 486 Res = tryDecodeInst(DecoderTableDPPGFX1196, DecoderTableDPPGFX11_FAKE1696, 487 MI, DecW, Address, CS); 488 if (Res) { 489 convertVOPDPP(); 490 break; 491 } 492 Res = tryDecodeInst(DecoderTableDPPGFX1296, DecoderTableDPPGFX12_FAKE1696, 493 MI, DecW, Address, CS); 494 if (Res) { 495 convertVOPDPP(); 496 break; 497 } 498 Res = tryDecodeInst(DecoderTableGFX1196, MI, DecW, Address, CS); 499 if (Res) 500 break; 501 502 Res = tryDecodeInst(DecoderTableGFX1296, MI, DecW, Address, CS); 503 if (Res) 504 break; 505 506 Res = tryDecodeInst(DecoderTableGFX12W6496, MI, DecW, Address, CS); 507 if (Res) 508 break; 509 } 510 // Reinitialize Bytes 511 Bytes = Bytes_.slice(0, MaxInstBytesNum); 512 513 if (Bytes.size() >= 8) { 514 const uint64_t QW = eatBytes<uint64_t>(Bytes); 515 516 if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding)) { 517 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address, CS); 518 if (Res) { 519 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) 520 == -1) 521 break; 522 if (convertDPP8Inst(MI) == MCDisassembler::Success) 523 break; 524 } 525 } 526 527 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address, CS); 528 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 529 break; 530 531 Res = tryDecodeInst(DecoderTableDPP8GFX1164, 532 DecoderTableDPP8GFX11_FAKE1664, MI, QW, Address, CS); 533 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 534 break; 535 536 Res = tryDecodeInst(DecoderTableDPP8GFX1264, 537 DecoderTableDPP8GFX12_FAKE1664, MI, QW, Address, CS); 538 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 539 break; 540 541 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address, CS); 542 if (Res) break; 543 544 Res = tryDecodeInst(DecoderTableDPPGFX1164, DecoderTableDPPGFX11_FAKE1664, 545 MI, QW, Address, CS); 546 if (Res) { 547 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC) 548 convertVOPCDPPInst(MI); 549 break; 550 } 551 552 Res = tryDecodeInst(DecoderTableDPPGFX1264, DecoderTableDPPGFX12_FAKE1664, 553 MI, QW, Address, CS); 554 if (Res) { 555 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC) 556 convertVOPCDPPInst(MI); 557 break; 558 } 559 560 if (STI.hasFeature(AMDGPU::FeatureUnpackedD16VMem)) { 561 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address, CS); 562 if (Res) 563 break; 564 } 565 566 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 567 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 568 // table first so we print the correct name. 569 if (STI.hasFeature(AMDGPU::FeatureFmaMixInsts)) { 570 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address, CS); 571 if (Res) 572 break; 573 } 574 575 if (STI.hasFeature(AMDGPU::FeatureGFX940Insts)) { 576 Res = tryDecodeInst(DecoderTableGFX94064, MI, QW, Address, CS); 577 if (Res) 578 break; 579 } 580 581 if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts)) { 582 Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address, CS); 583 if (Res) 584 break; 585 } 586 587 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address, CS); 588 if (Res) 589 break; 590 591 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address, CS); 592 if (Res) 593 break; 594 595 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address, CS); 596 if (Res) 597 break; 598 599 Res = tryDecodeInst(DecoderTableGFX1264, DecoderTableGFX12_FAKE1664, MI, 600 QW, Address, CS); 601 if (Res) 602 break; 603 604 Res = tryDecodeInst(DecoderTableGFX1164, DecoderTableGFX11_FAKE1664, MI, 605 QW, Address, CS); 606 if (Res) 607 break; 608 609 Res = tryDecodeInst(DecoderTableGFX11W6464, MI, QW, Address, CS); 610 if (Res) 611 break; 612 613 Res = tryDecodeInst(DecoderTableGFX12W6464, MI, QW, Address, CS); 614 if (Res) 615 break; 616 } 617 618 // Reinitialize Bytes as DPP64 could have eaten too much 619 Bytes = Bytes_.slice(0, MaxInstBytesNum); 620 621 // Try decode 32-bit instruction 622 if (Bytes.size() < 4) break; 623 const uint32_t DW = eatBytes<uint32_t>(Bytes); 624 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address, CS); 625 if (Res) break; 626 627 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address, CS); 628 if (Res) break; 629 630 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address, CS); 631 if (Res) break; 632 633 if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts)) { 634 Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address, CS); 635 if (Res) 636 break; 637 } 638 639 if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding)) { 640 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address, CS); 641 if (Res) break; 642 } 643 644 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address, CS); 645 if (Res) break; 646 647 Res = tryDecodeInst(DecoderTableGFX1132, DecoderTableGFX11_FAKE1632, MI, DW, 648 Address, CS); 649 if (Res) break; 650 651 Res = tryDecodeInst(DecoderTableGFX1232, DecoderTableGFX12_FAKE1632, MI, DW, 652 Address, CS); 653 } while (false); 654 655 if (Res && AMDGPU::isMAC(MI.getOpcode())) { 656 // Insert dummy unused src2_modifiers. 657 insertNamedMCOperand(MI, MCOperand::createImm(0), 658 AMDGPU::OpName::src2_modifiers); 659 } 660 661 if (Res && (MI.getOpcode() == AMDGPU::V_CVT_SR_BF8_F32_e64_dpp || 662 MI.getOpcode() == AMDGPU::V_CVT_SR_FP8_F32_e64_dpp)) { 663 // Insert dummy unused src2_modifiers. 664 insertNamedMCOperand(MI, MCOperand::createImm(0), 665 AMDGPU::OpName::src2_modifiers); 666 } 667 668 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::DS) && 669 !AMDGPU::hasGDS(STI)) { 670 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::gds); 671 } 672 673 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 674 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT | SIInstrFlags::SMRD))) { 675 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 676 AMDGPU::OpName::cpol); 677 if (CPolPos != -1) { 678 unsigned CPol = 679 (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ? 680 AMDGPU::CPol::GLC : 0; 681 if (MI.getNumOperands() <= (unsigned)CPolPos) { 682 insertNamedMCOperand(MI, MCOperand::createImm(CPol), 683 AMDGPU::OpName::cpol); 684 } else if (CPol) { 685 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); 686 } 687 } 688 } 689 690 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 691 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) && 692 (STI.hasFeature(AMDGPU::FeatureGFX90AInsts))) { 693 // GFX90A lost TFE, its place is occupied by ACC. 694 int TFEOpIdx = 695 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); 696 if (TFEOpIdx != -1) { 697 auto TFEIter = MI.begin(); 698 std::advance(TFEIter, TFEOpIdx); 699 MI.insert(TFEIter, MCOperand::createImm(0)); 700 } 701 } 702 703 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 704 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF))) { 705 int SWZOpIdx = 706 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); 707 if (SWZOpIdx != -1) { 708 auto SWZIter = MI.begin(); 709 std::advance(SWZIter, SWZOpIdx); 710 MI.insert(SWZIter, MCOperand::createImm(0)); 711 } 712 } 713 714 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 715 int VAddr0Idx = 716 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 717 int RsrcIdx = 718 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 719 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 720 if (VAddr0Idx >= 0 && NSAArgs > 0) { 721 unsigned NSAWords = (NSAArgs + 3) / 4; 722 if (Bytes.size() < 4 * NSAWords) { 723 Res = MCDisassembler::Fail; 724 } else { 725 for (unsigned i = 0; i < NSAArgs; ++i) { 726 const unsigned VAddrIdx = VAddr0Idx + 1 + i; 727 auto VAddrRCID = 728 MCII->get(MI.getOpcode()).operands()[VAddrIdx].RegClass; 729 MI.insert(MI.begin() + VAddrIdx, 730 createRegOperand(VAddrRCID, Bytes[i])); 731 } 732 Bytes = Bytes.slice(4 * NSAWords); 733 } 734 } 735 736 if (Res) 737 Res = convertMIMGInst(MI); 738 } 739 740 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 741 (SIInstrFlags::VIMAGE | SIInstrFlags::VSAMPLE))) 742 Res = convertMIMGInst(MI); 743 744 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::EXP)) 745 Res = convertEXPInst(MI); 746 747 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VINTERP)) 748 Res = convertVINTERPInst(MI); 749 750 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::SDWA)) 751 Res = convertSDWAInst(MI); 752 753 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 754 AMDGPU::OpName::vdst_in); 755 if (VDstIn_Idx != -1) { 756 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 757 MCOI::OperandConstraint::TIED_TO); 758 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 759 !MI.getOperand(VDstIn_Idx).isReg() || 760 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 761 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 762 MI.erase(&MI.getOperand(VDstIn_Idx)); 763 insertNamedMCOperand(MI, 764 MCOperand::createReg(MI.getOperand(Tied).getReg()), 765 AMDGPU::OpName::vdst_in); 766 } 767 } 768 769 int ImmLitIdx = 770 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm); 771 bool IsSOPK = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::SOPK; 772 if (Res && ImmLitIdx != -1 && !IsSOPK) 773 Res = convertFMAanyK(MI, ImmLitIdx); 774 775 // if the opcode was not recognized we'll assume a Size of 4 bytes 776 // (unless there are fewer bytes left) 777 Size = Res ? (MaxInstBytesNum - Bytes.size()) 778 : std::min((size_t)4, Bytes_.size()); 779 return Res; 780 } 781 782 DecodeStatus AMDGPUDisassembler::convertEXPInst(MCInst &MI) const { 783 if (STI.hasFeature(AMDGPU::FeatureGFX11Insts)) { 784 // The MCInst still has these fields even though they are no longer encoded 785 // in the GFX11 instruction. 786 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vm); 787 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::compr); 788 } 789 return MCDisassembler::Success; 790 } 791 792 DecodeStatus AMDGPUDisassembler::convertVINTERPInst(MCInst &MI) const { 793 if (MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx11 || 794 MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx12 || 795 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx11 || 796 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx12 || 797 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx11 || 798 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx12 || 799 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx11 || 800 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx12) { 801 // The MCInst has this field that is not directly encoded in the 802 // instruction. 803 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::op_sel); 804 } 805 return MCDisassembler::Success; 806 } 807 808 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 809 if (STI.hasFeature(AMDGPU::FeatureGFX9) || 810 STI.hasFeature(AMDGPU::FeatureGFX10)) { 811 if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::sdst)) 812 // VOPC - insert clamp 813 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 814 } else if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) { 815 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 816 if (SDst != -1) { 817 // VOPC - insert VCC register as sdst 818 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 819 AMDGPU::OpName::sdst); 820 } else { 821 // VOP1/2 - insert omod if present in instruction 822 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 823 } 824 } 825 return MCDisassembler::Success; 826 } 827 828 struct VOPModifiers { 829 unsigned OpSel = 0; 830 unsigned OpSelHi = 0; 831 unsigned NegLo = 0; 832 unsigned NegHi = 0; 833 }; 834 835 // Reconstruct values of VOP3/VOP3P operands such as op_sel. 836 // Note that these values do not affect disassembler output, 837 // so this is only necessary for consistency with src_modifiers. 838 static VOPModifiers collectVOPModifiers(const MCInst &MI, 839 bool IsVOP3P = false) { 840 VOPModifiers Modifiers; 841 unsigned Opc = MI.getOpcode(); 842 const int ModOps[] = {AMDGPU::OpName::src0_modifiers, 843 AMDGPU::OpName::src1_modifiers, 844 AMDGPU::OpName::src2_modifiers}; 845 for (int J = 0; J < 3; ++J) { 846 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]); 847 if (OpIdx == -1) 848 continue; 849 850 unsigned Val = MI.getOperand(OpIdx).getImm(); 851 852 Modifiers.OpSel |= !!(Val & SISrcMods::OP_SEL_0) << J; 853 if (IsVOP3P) { 854 Modifiers.OpSelHi |= !!(Val & SISrcMods::OP_SEL_1) << J; 855 Modifiers.NegLo |= !!(Val & SISrcMods::NEG) << J; 856 Modifiers.NegHi |= !!(Val & SISrcMods::NEG_HI) << J; 857 } else if (J == 0) { 858 Modifiers.OpSel |= !!(Val & SISrcMods::DST_OP_SEL) << 3; 859 } 860 } 861 862 return Modifiers; 863 } 864 865 // Instructions decode the op_sel/suffix bits into the src_modifier 866 // operands. Copy those bits into the src operands for true16 VGPRs. 867 void AMDGPUDisassembler::convertTrue16OpSel(MCInst &MI) const { 868 const unsigned Opc = MI.getOpcode(); 869 const MCRegisterClass &ConversionRC = 870 MRI.getRegClass(AMDGPU::VGPR_16RegClassID); 871 constexpr std::array<std::tuple<int, int, unsigned>, 4> OpAndOpMods = { 872 {{AMDGPU::OpName::src0, AMDGPU::OpName::src0_modifiers, 873 SISrcMods::OP_SEL_0}, 874 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_modifiers, 875 SISrcMods::OP_SEL_0}, 876 {AMDGPU::OpName::src2, AMDGPU::OpName::src2_modifiers, 877 SISrcMods::OP_SEL_0}, 878 {AMDGPU::OpName::vdst, AMDGPU::OpName::src0_modifiers, 879 SISrcMods::DST_OP_SEL}}}; 880 for (const auto &[OpName, OpModsName, OpSelMask] : OpAndOpMods) { 881 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, OpName); 882 int OpModsIdx = AMDGPU::getNamedOperandIdx(Opc, OpModsName); 883 if (OpIdx == -1 || OpModsIdx == -1) 884 continue; 885 MCOperand &Op = MI.getOperand(OpIdx); 886 if (!Op.isReg()) 887 continue; 888 if (!ConversionRC.contains(Op.getReg())) 889 continue; 890 unsigned OpEnc = MRI.getEncodingValue(Op.getReg()); 891 const MCOperand &OpMods = MI.getOperand(OpModsIdx); 892 unsigned ModVal = OpMods.getImm(); 893 if (ModVal & OpSelMask) { // isHi 894 unsigned RegIdx = OpEnc & AMDGPU::HWEncoding::REG_IDX_MASK; 895 Op.setReg(ConversionRC.getRegister(RegIdx * 2 + 1)); 896 } 897 } 898 } 899 900 // MAC opcodes have special old and src2 operands. 901 // src2 is tied to dst, while old is not tied (but assumed to be). 902 bool AMDGPUDisassembler::isMacDPP(MCInst &MI) const { 903 constexpr int DST_IDX = 0; 904 auto Opcode = MI.getOpcode(); 905 const auto &Desc = MCII->get(Opcode); 906 auto OldIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::old); 907 908 if (OldIdx != -1 && Desc.getOperandConstraint( 909 OldIdx, MCOI::OperandConstraint::TIED_TO) == -1) { 910 assert(AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src2)); 911 assert(Desc.getOperandConstraint( 912 AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2), 913 MCOI::OperandConstraint::TIED_TO) == DST_IDX); 914 (void)DST_IDX; 915 return true; 916 } 917 918 return false; 919 } 920 921 // Create dummy old operand and insert dummy unused src2_modifiers 922 void AMDGPUDisassembler::convertMacDPPInst(MCInst &MI) const { 923 assert(MI.getNumOperands() + 1 < MCII->get(MI.getOpcode()).getNumOperands()); 924 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 925 insertNamedMCOperand(MI, MCOperand::createImm(0), 926 AMDGPU::OpName::src2_modifiers); 927 } 928 929 // We must check FI == literal to reject not genuine dpp8 insts, and we must 930 // first add optional MI operands to check FI 931 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 932 unsigned Opc = MI.getOpcode(); 933 934 if (MCII->get(Opc).TSFlags & SIInstrFlags::VOP3P) { 935 convertVOP3PDPPInst(MI); 936 } else if ((MCII->get(Opc).TSFlags & SIInstrFlags::VOPC) || 937 AMDGPU::isVOPC64DPP(Opc)) { 938 convertVOPCDPPInst(MI); 939 } else { 940 if (isMacDPP(MI)) 941 convertMacDPPInst(MI); 942 943 int VDstInIdx = 944 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst_in); 945 if (VDstInIdx != -1) 946 insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::vdst_in); 947 948 if (MI.getOpcode() == AMDGPU::V_CVT_SR_BF8_F32_e64_dpp8_gfx12 || 949 MI.getOpcode() == AMDGPU::V_CVT_SR_FP8_F32_e64_dpp8_gfx12) 950 insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::src2); 951 952 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 953 if (MI.getNumOperands() < DescNumOps && 954 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { 955 convertTrue16OpSel(MI); 956 auto Mods = collectVOPModifiers(MI); 957 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 958 AMDGPU::OpName::op_sel); 959 } else { 960 // Insert dummy unused src modifiers. 961 if (MI.getNumOperands() < DescNumOps && 962 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) 963 insertNamedMCOperand(MI, MCOperand::createImm(0), 964 AMDGPU::OpName::src0_modifiers); 965 966 if (MI.getNumOperands() < DescNumOps && 967 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers)) 968 insertNamedMCOperand(MI, MCOperand::createImm(0), 969 AMDGPU::OpName::src1_modifiers); 970 } 971 } 972 return MCDisassembler::Success; 973 } 974 975 DecodeStatus AMDGPUDisassembler::convertVOP3DPPInst(MCInst &MI) const { 976 if (isMacDPP(MI)) 977 convertMacDPPInst(MI); 978 979 convertTrue16OpSel(MI); 980 981 int VDstInIdx = 982 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst_in); 983 if (VDstInIdx != -1) 984 insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::vdst_in); 985 986 if (MI.getOpcode() == AMDGPU::V_CVT_SR_BF8_F32_e64_dpp_gfx12 || 987 MI.getOpcode() == AMDGPU::V_CVT_SR_FP8_F32_e64_dpp_gfx12) 988 insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::src2); 989 990 unsigned Opc = MI.getOpcode(); 991 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 992 if (MI.getNumOperands() < DescNumOps && 993 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { 994 auto Mods = collectVOPModifiers(MI); 995 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 996 AMDGPU::OpName::op_sel); 997 } 998 return MCDisassembler::Success; 999 } 1000 1001 // Note that before gfx10, the MIMG encoding provided no information about 1002 // VADDR size. Consequently, decoded instructions always show address as if it 1003 // has 1 dword, which could be not really so. 1004 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 1005 auto TSFlags = MCII->get(MI.getOpcode()).TSFlags; 1006 1007 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 1008 AMDGPU::OpName::vdst); 1009 1010 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 1011 AMDGPU::OpName::vdata); 1012 int VAddr0Idx = 1013 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 1014 int RsrcOpName = TSFlags & SIInstrFlags::MIMG ? AMDGPU::OpName::srsrc 1015 : AMDGPU::OpName::rsrc; 1016 int RsrcIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), RsrcOpName); 1017 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 1018 AMDGPU::OpName::dmask); 1019 1020 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 1021 AMDGPU::OpName::tfe); 1022 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 1023 AMDGPU::OpName::d16); 1024 1025 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 1026 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 1027 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 1028 1029 assert(VDataIdx != -1); 1030 if (BaseOpcode->BVH) { 1031 // Add A16 operand for intersect_ray instructions 1032 addOperand(MI, MCOperand::createImm(BaseOpcode->A16)); 1033 return MCDisassembler::Success; 1034 } 1035 1036 bool IsAtomic = (VDstIdx != -1); 1037 bool IsGather4 = TSFlags & SIInstrFlags::Gather4; 1038 bool IsVSample = TSFlags & SIInstrFlags::VSAMPLE; 1039 bool IsNSA = false; 1040 bool IsPartialNSA = false; 1041 unsigned AddrSize = Info->VAddrDwords; 1042 1043 if (isGFX10Plus()) { 1044 unsigned DimIdx = 1045 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 1046 int A16Idx = 1047 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16); 1048 const AMDGPU::MIMGDimInfo *Dim = 1049 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 1050 const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm()); 1051 1052 AddrSize = 1053 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); 1054 1055 // VSAMPLE insts that do not use vaddr3 behave the same as NSA forms. 1056 // VIMAGE insts other than BVH never use vaddr4. 1057 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA || 1058 Info->MIMGEncoding == AMDGPU::MIMGEncGfx11NSA || 1059 Info->MIMGEncoding == AMDGPU::MIMGEncGfx12; 1060 if (!IsNSA) { 1061 if (!IsVSample && AddrSize > 12) 1062 AddrSize = 16; 1063 } else { 1064 if (AddrSize > Info->VAddrDwords) { 1065 if (!STI.hasFeature(AMDGPU::FeaturePartialNSAEncoding)) { 1066 // The NSA encoding does not contain enough operands for the 1067 // combination of base opcode / dimension. Should this be an error? 1068 return MCDisassembler::Success; 1069 } 1070 IsPartialNSA = true; 1071 } 1072 } 1073 } 1074 1075 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 1076 unsigned DstSize = IsGather4 ? 4 : std::max(llvm::popcount(DMask), 1); 1077 1078 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 1079 if (D16 && AMDGPU::hasPackedD16(STI)) { 1080 DstSize = (DstSize + 1) / 2; 1081 } 1082 1083 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm()) 1084 DstSize += 1; 1085 1086 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 1087 return MCDisassembler::Success; 1088 1089 int NewOpcode = 1090 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 1091 if (NewOpcode == -1) 1092 return MCDisassembler::Success; 1093 1094 // Widen the register to the correct number of enabled channels. 1095 unsigned NewVdata = AMDGPU::NoRegister; 1096 if (DstSize != Info->VDataDwords) { 1097 auto DataRCID = MCII->get(NewOpcode).operands()[VDataIdx].RegClass; 1098 1099 // Get first subregister of VData 1100 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 1101 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 1102 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 1103 1104 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 1105 &MRI.getRegClass(DataRCID)); 1106 if (NewVdata == AMDGPU::NoRegister) { 1107 // It's possible to encode this such that the low register + enabled 1108 // components exceeds the register count. 1109 return MCDisassembler::Success; 1110 } 1111 } 1112 1113 // If not using NSA on GFX10+, widen vaddr0 address register to correct size. 1114 // If using partial NSA on GFX11+ widen last address register. 1115 int VAddrSAIdx = IsPartialNSA ? (RsrcIdx - 1) : VAddr0Idx; 1116 unsigned NewVAddrSA = AMDGPU::NoRegister; 1117 if (STI.hasFeature(AMDGPU::FeatureNSAEncoding) && (!IsNSA || IsPartialNSA) && 1118 AddrSize != Info->VAddrDwords) { 1119 unsigned VAddrSA = MI.getOperand(VAddrSAIdx).getReg(); 1120 unsigned VAddrSubSA = MRI.getSubReg(VAddrSA, AMDGPU::sub0); 1121 VAddrSA = VAddrSubSA ? VAddrSubSA : VAddrSA; 1122 1123 auto AddrRCID = MCII->get(NewOpcode).operands()[VAddrSAIdx].RegClass; 1124 NewVAddrSA = MRI.getMatchingSuperReg(VAddrSA, AMDGPU::sub0, 1125 &MRI.getRegClass(AddrRCID)); 1126 if (!NewVAddrSA) 1127 return MCDisassembler::Success; 1128 } 1129 1130 MI.setOpcode(NewOpcode); 1131 1132 if (NewVdata != AMDGPU::NoRegister) { 1133 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 1134 1135 if (IsAtomic) { 1136 // Atomic operations have an additional operand (a copy of data) 1137 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 1138 } 1139 } 1140 1141 if (NewVAddrSA) { 1142 MI.getOperand(VAddrSAIdx) = MCOperand::createReg(NewVAddrSA); 1143 } else if (IsNSA) { 1144 assert(AddrSize <= Info->VAddrDwords); 1145 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 1146 MI.begin() + VAddr0Idx + Info->VAddrDwords); 1147 } 1148 1149 return MCDisassembler::Success; 1150 } 1151 1152 // Opsel and neg bits are used in src_modifiers and standalone operands. Autogen 1153 // decoder only adds to src_modifiers, so manually add the bits to the other 1154 // operands. 1155 DecodeStatus AMDGPUDisassembler::convertVOP3PDPPInst(MCInst &MI) const { 1156 unsigned Opc = MI.getOpcode(); 1157 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1158 auto Mods = collectVOPModifiers(MI, true); 1159 1160 if (MI.getNumOperands() < DescNumOps && 1161 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vdst_in)) 1162 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vdst_in); 1163 1164 if (MI.getNumOperands() < DescNumOps && 1165 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) 1166 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 1167 AMDGPU::OpName::op_sel); 1168 if (MI.getNumOperands() < DescNumOps && 1169 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel_hi)) 1170 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSelHi), 1171 AMDGPU::OpName::op_sel_hi); 1172 if (MI.getNumOperands() < DescNumOps && 1173 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_lo)) 1174 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegLo), 1175 AMDGPU::OpName::neg_lo); 1176 if (MI.getNumOperands() < DescNumOps && 1177 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_hi)) 1178 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegHi), 1179 AMDGPU::OpName::neg_hi); 1180 1181 return MCDisassembler::Success; 1182 } 1183 1184 // Create dummy old operand and insert optional operands 1185 DecodeStatus AMDGPUDisassembler::convertVOPCDPPInst(MCInst &MI) const { 1186 unsigned Opc = MI.getOpcode(); 1187 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1188 1189 if (MI.getNumOperands() < DescNumOps && 1190 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::old)) 1191 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 1192 1193 if (MI.getNumOperands() < DescNumOps && 1194 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) 1195 insertNamedMCOperand(MI, MCOperand::createImm(0), 1196 AMDGPU::OpName::src0_modifiers); 1197 1198 if (MI.getNumOperands() < DescNumOps && 1199 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers)) 1200 insertNamedMCOperand(MI, MCOperand::createImm(0), 1201 AMDGPU::OpName::src1_modifiers); 1202 return MCDisassembler::Success; 1203 } 1204 1205 DecodeStatus AMDGPUDisassembler::convertFMAanyK(MCInst &MI, 1206 int ImmLitIdx) const { 1207 assert(HasLiteral && "Should have decoded a literal"); 1208 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 1209 unsigned DescNumOps = Desc.getNumOperands(); 1210 insertNamedMCOperand(MI, MCOperand::createImm(Literal), 1211 AMDGPU::OpName::immDeferred); 1212 assert(DescNumOps == MI.getNumOperands()); 1213 for (unsigned I = 0; I < DescNumOps; ++I) { 1214 auto &Op = MI.getOperand(I); 1215 auto OpType = Desc.operands()[I].OperandType; 1216 bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED || 1217 OpType == AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED); 1218 if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST && 1219 IsDeferredOp) 1220 Op.setImm(Literal); 1221 } 1222 return MCDisassembler::Success; 1223 } 1224 1225 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 1226 return getContext().getRegisterInfo()-> 1227 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 1228 } 1229 1230 inline 1231 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 1232 const Twine& ErrMsg) const { 1233 *CommentStream << "Error: " + ErrMsg; 1234 1235 // ToDo: add support for error operands to MCInst.h 1236 // return MCOperand::createError(V); 1237 return MCOperand(); 1238 } 1239 1240 inline 1241 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 1242 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 1243 } 1244 1245 inline 1246 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 1247 unsigned Val) const { 1248 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 1249 if (Val >= RegCl.getNumRegs()) 1250 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 1251 ": unknown register " + Twine(Val)); 1252 return createRegOperand(RegCl.getRegister(Val)); 1253 } 1254 1255 inline 1256 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 1257 unsigned Val) const { 1258 // ToDo: SI/CI have 104 SGPRs, VI - 102 1259 // Valery: here we accepting as much as we can, let assembler sort it out 1260 int shift = 0; 1261 switch (SRegClassID) { 1262 case AMDGPU::SGPR_32RegClassID: 1263 case AMDGPU::TTMP_32RegClassID: 1264 break; 1265 case AMDGPU::SGPR_64RegClassID: 1266 case AMDGPU::TTMP_64RegClassID: 1267 shift = 1; 1268 break; 1269 case AMDGPU::SGPR_96RegClassID: 1270 case AMDGPU::TTMP_96RegClassID: 1271 case AMDGPU::SGPR_128RegClassID: 1272 case AMDGPU::TTMP_128RegClassID: 1273 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 1274 // this bundle? 1275 case AMDGPU::SGPR_256RegClassID: 1276 case AMDGPU::TTMP_256RegClassID: 1277 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 1278 // this bundle? 1279 case AMDGPU::SGPR_288RegClassID: 1280 case AMDGPU::TTMP_288RegClassID: 1281 case AMDGPU::SGPR_320RegClassID: 1282 case AMDGPU::TTMP_320RegClassID: 1283 case AMDGPU::SGPR_352RegClassID: 1284 case AMDGPU::TTMP_352RegClassID: 1285 case AMDGPU::SGPR_384RegClassID: 1286 case AMDGPU::TTMP_384RegClassID: 1287 case AMDGPU::SGPR_512RegClassID: 1288 case AMDGPU::TTMP_512RegClassID: 1289 shift = 2; 1290 break; 1291 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 1292 // this bundle? 1293 default: 1294 llvm_unreachable("unhandled register class"); 1295 } 1296 1297 if (Val % (1 << shift)) { 1298 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 1299 << ": scalar reg isn't aligned " << Val; 1300 } 1301 1302 return createRegOperand(SRegClassID, Val >> shift); 1303 } 1304 1305 MCOperand AMDGPUDisassembler::createVGPR16Operand(unsigned RegIdx, 1306 bool IsHi) const { 1307 unsigned RegIdxInVGPR16 = RegIdx * 2 + (IsHi ? 1 : 0); 1308 return createRegOperand(AMDGPU::VGPR_16RegClassID, RegIdxInVGPR16); 1309 } 1310 1311 // Decode Literals for insts which always have a literal in the encoding 1312 MCOperand 1313 AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const { 1314 if (HasLiteral) { 1315 assert( 1316 AMDGPU::hasVOPD(STI) && 1317 "Should only decode multiple kimm with VOPD, check VSrc operand types"); 1318 if (Literal != Val) 1319 return errOperand(Val, "More than one unique literal is illegal"); 1320 } 1321 HasLiteral = true; 1322 Literal = Val; 1323 return MCOperand::createImm(Literal); 1324 } 1325 1326 MCOperand AMDGPUDisassembler::decodeLiteralConstant(bool ExtendFP64) const { 1327 // For now all literal constants are supposed to be unsigned integer 1328 // ToDo: deal with signed/unsigned 64-bit integer constants 1329 // ToDo: deal with float/double constants 1330 if (!HasLiteral) { 1331 if (Bytes.size() < 4) { 1332 return errOperand(0, "cannot read literal, inst bytes left " + 1333 Twine(Bytes.size())); 1334 } 1335 HasLiteral = true; 1336 Literal = Literal64 = eatBytes<uint32_t>(Bytes); 1337 if (ExtendFP64) 1338 Literal64 <<= 32; 1339 } 1340 return MCOperand::createImm(ExtendFP64 ? Literal64 : Literal); 1341 } 1342 1343 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 1344 using namespace AMDGPU::EncValues; 1345 1346 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 1347 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 1348 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 1349 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 1350 // Cast prevents negative overflow. 1351 } 1352 1353 static int64_t getInlineImmVal32(unsigned Imm) { 1354 switch (Imm) { 1355 case 240: 1356 return llvm::bit_cast<uint32_t>(0.5f); 1357 case 241: 1358 return llvm::bit_cast<uint32_t>(-0.5f); 1359 case 242: 1360 return llvm::bit_cast<uint32_t>(1.0f); 1361 case 243: 1362 return llvm::bit_cast<uint32_t>(-1.0f); 1363 case 244: 1364 return llvm::bit_cast<uint32_t>(2.0f); 1365 case 245: 1366 return llvm::bit_cast<uint32_t>(-2.0f); 1367 case 246: 1368 return llvm::bit_cast<uint32_t>(4.0f); 1369 case 247: 1370 return llvm::bit_cast<uint32_t>(-4.0f); 1371 case 248: // 1 / (2 * PI) 1372 return 0x3e22f983; 1373 default: 1374 llvm_unreachable("invalid fp inline imm"); 1375 } 1376 } 1377 1378 static int64_t getInlineImmVal64(unsigned Imm) { 1379 switch (Imm) { 1380 case 240: 1381 return llvm::bit_cast<uint64_t>(0.5); 1382 case 241: 1383 return llvm::bit_cast<uint64_t>(-0.5); 1384 case 242: 1385 return llvm::bit_cast<uint64_t>(1.0); 1386 case 243: 1387 return llvm::bit_cast<uint64_t>(-1.0); 1388 case 244: 1389 return llvm::bit_cast<uint64_t>(2.0); 1390 case 245: 1391 return llvm::bit_cast<uint64_t>(-2.0); 1392 case 246: 1393 return llvm::bit_cast<uint64_t>(4.0); 1394 case 247: 1395 return llvm::bit_cast<uint64_t>(-4.0); 1396 case 248: // 1 / (2 * PI) 1397 return 0x3fc45f306dc9c882; 1398 default: 1399 llvm_unreachable("invalid fp inline imm"); 1400 } 1401 } 1402 1403 static int64_t getInlineImmValF16(unsigned Imm) { 1404 switch (Imm) { 1405 case 240: 1406 return 0x3800; 1407 case 241: 1408 return 0xB800; 1409 case 242: 1410 return 0x3C00; 1411 case 243: 1412 return 0xBC00; 1413 case 244: 1414 return 0x4000; 1415 case 245: 1416 return 0xC000; 1417 case 246: 1418 return 0x4400; 1419 case 247: 1420 return 0xC400; 1421 case 248: // 1 / (2 * PI) 1422 return 0x3118; 1423 default: 1424 llvm_unreachable("invalid fp inline imm"); 1425 } 1426 } 1427 1428 static int64_t getInlineImmValBF16(unsigned Imm) { 1429 switch (Imm) { 1430 case 240: 1431 return 0x3F00; 1432 case 241: 1433 return 0xBF00; 1434 case 242: 1435 return 0x3F80; 1436 case 243: 1437 return 0xBF80; 1438 case 244: 1439 return 0x4000; 1440 case 245: 1441 return 0xC000; 1442 case 246: 1443 return 0x4080; 1444 case 247: 1445 return 0xC080; 1446 case 248: // 1 / (2 * PI) 1447 return 0x3E22; 1448 default: 1449 llvm_unreachable("invalid fp inline imm"); 1450 } 1451 } 1452 1453 static int64_t getInlineImmVal16(unsigned Imm, AMDGPU::OperandSemantics Sema) { 1454 return (Sema == AMDGPU::OperandSemantics::BF16) ? getInlineImmValBF16(Imm) 1455 : getInlineImmValF16(Imm); 1456 } 1457 1458 MCOperand AMDGPUDisassembler::decodeFPImmed(unsigned ImmWidth, unsigned Imm, 1459 AMDGPU::OperandSemantics Sema) { 1460 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN && 1461 Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 1462 1463 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 1464 // ImmWidth 0 is a default case where operand should not allow immediates. 1465 // Imm value is still decoded into 32 bit immediate operand, inst printer will 1466 // use it to print verbose error message. 1467 switch (ImmWidth) { 1468 case 0: 1469 case 32: 1470 return MCOperand::createImm(getInlineImmVal32(Imm)); 1471 case 64: 1472 return MCOperand::createImm(getInlineImmVal64(Imm)); 1473 case 16: 1474 return MCOperand::createImm(getInlineImmVal16(Imm, Sema)); 1475 default: 1476 llvm_unreachable("implement me"); 1477 } 1478 } 1479 1480 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 1481 using namespace AMDGPU; 1482 1483 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1484 switch (Width) { 1485 default: // fall 1486 case OPW32: 1487 case OPW16: 1488 case OPWV216: 1489 return VGPR_32RegClassID; 1490 case OPW64: 1491 case OPWV232: return VReg_64RegClassID; 1492 case OPW96: return VReg_96RegClassID; 1493 case OPW128: return VReg_128RegClassID; 1494 case OPW160: return VReg_160RegClassID; 1495 case OPW256: return VReg_256RegClassID; 1496 case OPW288: return VReg_288RegClassID; 1497 case OPW320: return VReg_320RegClassID; 1498 case OPW352: return VReg_352RegClassID; 1499 case OPW384: return VReg_384RegClassID; 1500 case OPW512: return VReg_512RegClassID; 1501 case OPW1024: return VReg_1024RegClassID; 1502 } 1503 } 1504 1505 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 1506 using namespace AMDGPU; 1507 1508 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1509 switch (Width) { 1510 default: // fall 1511 case OPW32: 1512 case OPW16: 1513 case OPWV216: 1514 return AGPR_32RegClassID; 1515 case OPW64: 1516 case OPWV232: return AReg_64RegClassID; 1517 case OPW96: return AReg_96RegClassID; 1518 case OPW128: return AReg_128RegClassID; 1519 case OPW160: return AReg_160RegClassID; 1520 case OPW256: return AReg_256RegClassID; 1521 case OPW288: return AReg_288RegClassID; 1522 case OPW320: return AReg_320RegClassID; 1523 case OPW352: return AReg_352RegClassID; 1524 case OPW384: return AReg_384RegClassID; 1525 case OPW512: return AReg_512RegClassID; 1526 case OPW1024: return AReg_1024RegClassID; 1527 } 1528 } 1529 1530 1531 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 1532 using namespace AMDGPU; 1533 1534 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1535 switch (Width) { 1536 default: // fall 1537 case OPW32: 1538 case OPW16: 1539 case OPWV216: 1540 return SGPR_32RegClassID; 1541 case OPW64: 1542 case OPWV232: return SGPR_64RegClassID; 1543 case OPW96: return SGPR_96RegClassID; 1544 case OPW128: return SGPR_128RegClassID; 1545 case OPW160: return SGPR_160RegClassID; 1546 case OPW256: return SGPR_256RegClassID; 1547 case OPW288: return SGPR_288RegClassID; 1548 case OPW320: return SGPR_320RegClassID; 1549 case OPW352: return SGPR_352RegClassID; 1550 case OPW384: return SGPR_384RegClassID; 1551 case OPW512: return SGPR_512RegClassID; 1552 } 1553 } 1554 1555 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 1556 using namespace AMDGPU; 1557 1558 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1559 switch (Width) { 1560 default: // fall 1561 case OPW32: 1562 case OPW16: 1563 case OPWV216: 1564 return TTMP_32RegClassID; 1565 case OPW64: 1566 case OPWV232: return TTMP_64RegClassID; 1567 case OPW128: return TTMP_128RegClassID; 1568 case OPW256: return TTMP_256RegClassID; 1569 case OPW288: return TTMP_288RegClassID; 1570 case OPW320: return TTMP_320RegClassID; 1571 case OPW352: return TTMP_352RegClassID; 1572 case OPW384: return TTMP_384RegClassID; 1573 case OPW512: return TTMP_512RegClassID; 1574 } 1575 } 1576 1577 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 1578 using namespace AMDGPU::EncValues; 1579 1580 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN; 1581 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX; 1582 1583 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1584 } 1585 1586 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val, 1587 bool MandatoryLiteral, 1588 unsigned ImmWidth, 1589 AMDGPU::OperandSemantics Sema) const { 1590 using namespace AMDGPU::EncValues; 1591 1592 assert(Val < 1024); // enum10 1593 1594 bool IsAGPR = Val & 512; 1595 Val &= 511; 1596 1597 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1598 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1599 : getVgprClassId(Width), Val - VGPR_MIN); 1600 } 1601 return decodeNonVGPRSrcOp(Width, Val & 0xFF, MandatoryLiteral, ImmWidth, 1602 Sema); 1603 } 1604 1605 MCOperand 1606 AMDGPUDisassembler::decodeNonVGPRSrcOp(const OpWidthTy Width, unsigned Val, 1607 bool MandatoryLiteral, unsigned ImmWidth, 1608 AMDGPU::OperandSemantics Sema) const { 1609 // Cases when Val{8} is 1 (vgpr, agpr or true 16 vgpr) should have been 1610 // decoded earlier. 1611 assert(Val < (1 << 8) && "9-bit Src encoding when Val{8} is 0"); 1612 using namespace AMDGPU::EncValues; 1613 1614 if (Val <= SGPR_MAX) { 1615 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1616 static_assert(SGPR_MIN == 0); 1617 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1618 } 1619 1620 int TTmpIdx = getTTmpIdx(Val); 1621 if (TTmpIdx >= 0) { 1622 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1623 } 1624 1625 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1626 return decodeIntImmed(Val); 1627 1628 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1629 return decodeFPImmed(ImmWidth, Val, Sema); 1630 1631 if (Val == LITERAL_CONST) { 1632 if (MandatoryLiteral) 1633 // Keep a sentinel value for deferred setting 1634 return MCOperand::createImm(LITERAL_CONST); 1635 else 1636 return decodeLiteralConstant(Sema == AMDGPU::OperandSemantics::FP64); 1637 } 1638 1639 switch (Width) { 1640 case OPW32: 1641 case OPW16: 1642 case OPWV216: 1643 return decodeSpecialReg32(Val); 1644 case OPW64: 1645 case OPWV232: 1646 return decodeSpecialReg64(Val); 1647 default: 1648 llvm_unreachable("unexpected immediate type"); 1649 } 1650 } 1651 1652 // Bit 0 of DstY isn't stored in the instruction, because it's always the 1653 // opposite of bit 0 of DstX. 1654 MCOperand AMDGPUDisassembler::decodeVOPDDstYOp(MCInst &Inst, 1655 unsigned Val) const { 1656 int VDstXInd = 1657 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::vdstX); 1658 assert(VDstXInd != -1); 1659 assert(Inst.getOperand(VDstXInd).isReg()); 1660 unsigned XDstReg = MRI.getEncodingValue(Inst.getOperand(VDstXInd).getReg()); 1661 Val |= ~XDstReg & 1; 1662 auto Width = llvm::AMDGPUDisassembler::OPW32; 1663 return createRegOperand(getVgprClassId(Width), Val); 1664 } 1665 1666 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1667 using namespace AMDGPU; 1668 1669 switch (Val) { 1670 // clang-format off 1671 case 102: return createRegOperand(FLAT_SCR_LO); 1672 case 103: return createRegOperand(FLAT_SCR_HI); 1673 case 104: return createRegOperand(XNACK_MASK_LO); 1674 case 105: return createRegOperand(XNACK_MASK_HI); 1675 case 106: return createRegOperand(VCC_LO); 1676 case 107: return createRegOperand(VCC_HI); 1677 case 108: return createRegOperand(TBA_LO); 1678 case 109: return createRegOperand(TBA_HI); 1679 case 110: return createRegOperand(TMA_LO); 1680 case 111: return createRegOperand(TMA_HI); 1681 case 124: 1682 return isGFX11Plus() ? createRegOperand(SGPR_NULL) : createRegOperand(M0); 1683 case 125: 1684 return isGFX11Plus() ? createRegOperand(M0) : createRegOperand(SGPR_NULL); 1685 case 126: return createRegOperand(EXEC_LO); 1686 case 127: return createRegOperand(EXEC_HI); 1687 case 235: return createRegOperand(SRC_SHARED_BASE_LO); 1688 case 236: return createRegOperand(SRC_SHARED_LIMIT_LO); 1689 case 237: return createRegOperand(SRC_PRIVATE_BASE_LO); 1690 case 238: return createRegOperand(SRC_PRIVATE_LIMIT_LO); 1691 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1692 case 251: return createRegOperand(SRC_VCCZ); 1693 case 252: return createRegOperand(SRC_EXECZ); 1694 case 253: return createRegOperand(SRC_SCC); 1695 case 254: return createRegOperand(LDS_DIRECT); 1696 default: break; 1697 // clang-format on 1698 } 1699 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1700 } 1701 1702 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1703 using namespace AMDGPU; 1704 1705 switch (Val) { 1706 case 102: return createRegOperand(FLAT_SCR); 1707 case 104: return createRegOperand(XNACK_MASK); 1708 case 106: return createRegOperand(VCC); 1709 case 108: return createRegOperand(TBA); 1710 case 110: return createRegOperand(TMA); 1711 case 124: 1712 if (isGFX11Plus()) 1713 return createRegOperand(SGPR_NULL); 1714 break; 1715 case 125: 1716 if (!isGFX11Plus()) 1717 return createRegOperand(SGPR_NULL); 1718 break; 1719 case 126: return createRegOperand(EXEC); 1720 case 235: return createRegOperand(SRC_SHARED_BASE); 1721 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1722 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1723 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1724 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1725 case 251: return createRegOperand(SRC_VCCZ); 1726 case 252: return createRegOperand(SRC_EXECZ); 1727 case 253: return createRegOperand(SRC_SCC); 1728 default: break; 1729 } 1730 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1731 } 1732 1733 MCOperand 1734 AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, const unsigned Val, 1735 unsigned ImmWidth, 1736 AMDGPU::OperandSemantics Sema) const { 1737 using namespace AMDGPU::SDWA; 1738 using namespace AMDGPU::EncValues; 1739 1740 if (STI.hasFeature(AMDGPU::FeatureGFX9) || 1741 STI.hasFeature(AMDGPU::FeatureGFX10)) { 1742 // XXX: cast to int is needed to avoid stupid warning: 1743 // compare with unsigned is always true 1744 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1745 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1746 return createRegOperand(getVgprClassId(Width), 1747 Val - SDWA9EncValues::SRC_VGPR_MIN); 1748 } 1749 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1750 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1751 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1752 return createSRegOperand(getSgprClassId(Width), 1753 Val - SDWA9EncValues::SRC_SGPR_MIN); 1754 } 1755 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1756 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1757 return createSRegOperand(getTtmpClassId(Width), 1758 Val - SDWA9EncValues::SRC_TTMP_MIN); 1759 } 1760 1761 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1762 1763 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1764 return decodeIntImmed(SVal); 1765 1766 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1767 return decodeFPImmed(ImmWidth, SVal, Sema); 1768 1769 return decodeSpecialReg32(SVal); 1770 } else if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) { 1771 return createRegOperand(getVgprClassId(Width), Val); 1772 } 1773 llvm_unreachable("unsupported target"); 1774 } 1775 1776 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1777 return decodeSDWASrc(OPW16, Val, 16, AMDGPU::OperandSemantics::FP16); 1778 } 1779 1780 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1781 return decodeSDWASrc(OPW32, Val, 32, AMDGPU::OperandSemantics::FP32); 1782 } 1783 1784 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1785 using namespace AMDGPU::SDWA; 1786 1787 assert((STI.hasFeature(AMDGPU::FeatureGFX9) || 1788 STI.hasFeature(AMDGPU::FeatureGFX10)) && 1789 "SDWAVopcDst should be present only on GFX9+"); 1790 1791 bool IsWave64 = STI.hasFeature(AMDGPU::FeatureWavefrontSize64); 1792 1793 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1794 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1795 1796 int TTmpIdx = getTTmpIdx(Val); 1797 if (TTmpIdx >= 0) { 1798 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1799 return createSRegOperand(TTmpClsId, TTmpIdx); 1800 } else if (Val > SGPR_MAX) { 1801 return IsWave64 ? decodeSpecialReg64(Val) 1802 : decodeSpecialReg32(Val); 1803 } else { 1804 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1805 } 1806 } else { 1807 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1808 } 1809 } 1810 1811 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1812 return STI.hasFeature(AMDGPU::FeatureWavefrontSize64) 1813 ? decodeSrcOp(OPW64, Val) 1814 : decodeSrcOp(OPW32, Val); 1815 } 1816 1817 MCOperand AMDGPUDisassembler::decodeSplitBarrier(unsigned Val) const { 1818 return decodeSrcOp(OPW32, Val); 1819 } 1820 1821 MCOperand AMDGPUDisassembler::decodeDpp8FI(unsigned Val) const { 1822 if (Val != AMDGPU::DPP::DPP8_FI_0 && Val != AMDGPU::DPP::DPP8_FI_1) 1823 return MCOperand(); 1824 return MCOperand::createImm(Val); 1825 } 1826 1827 bool AMDGPUDisassembler::isVI() const { 1828 return STI.hasFeature(AMDGPU::FeatureVolcanicIslands); 1829 } 1830 1831 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } 1832 1833 bool AMDGPUDisassembler::isGFX90A() const { 1834 return STI.hasFeature(AMDGPU::FeatureGFX90AInsts); 1835 } 1836 1837 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } 1838 1839 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } 1840 1841 bool AMDGPUDisassembler::isGFX10Plus() const { 1842 return AMDGPU::isGFX10Plus(STI); 1843 } 1844 1845 bool AMDGPUDisassembler::isGFX11() const { 1846 return STI.hasFeature(AMDGPU::FeatureGFX11); 1847 } 1848 1849 bool AMDGPUDisassembler::isGFX11Plus() const { 1850 return AMDGPU::isGFX11Plus(STI); 1851 } 1852 1853 bool AMDGPUDisassembler::isGFX12Plus() const { 1854 return AMDGPU::isGFX12Plus(STI); 1855 } 1856 1857 bool AMDGPUDisassembler::hasArchitectedFlatScratch() const { 1858 return STI.hasFeature(AMDGPU::FeatureArchitectedFlatScratch); 1859 } 1860 1861 bool AMDGPUDisassembler::hasKernargPreload() const { 1862 return AMDGPU::hasKernargPreload(STI); 1863 } 1864 1865 //===----------------------------------------------------------------------===// 1866 // AMDGPU specific symbol handling 1867 //===----------------------------------------------------------------------===// 1868 #define GET_FIELD(MASK) (AMDHSA_BITS_GET(FourByteBuffer, MASK)) 1869 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1870 do { \ 1871 KdStream << Indent << DIRECTIVE " " << GET_FIELD(MASK) << '\n'; \ 1872 } while (0) 1873 #define PRINT_PSEUDO_DIRECTIVE_COMMENT(DIRECTIVE, MASK) \ 1874 do { \ 1875 KdStream << Indent << MAI.getCommentString() << ' ' << DIRECTIVE " " \ 1876 << GET_FIELD(MASK) << '\n'; \ 1877 } while (0) 1878 1879 // NOLINTNEXTLINE(readability-identifier-naming) 1880 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1881 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1882 using namespace amdhsa; 1883 StringRef Indent = "\t"; 1884 1885 // We cannot accurately backward compute #VGPRs used from 1886 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1887 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1888 // simply calculate the inverse of what the assembler does. 1889 1890 uint32_t GranulatedWorkitemVGPRCount = 1891 GET_FIELD(COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT); 1892 1893 uint32_t NextFreeVGPR = 1894 (GranulatedWorkitemVGPRCount + 1) * 1895 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI, EnableWavefrontSize32); 1896 1897 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1898 1899 // We cannot backward compute values used to calculate 1900 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1901 // directives can't be computed: 1902 // .amdhsa_reserve_vcc 1903 // .amdhsa_reserve_flat_scratch 1904 // .amdhsa_reserve_xnack_mask 1905 // They take their respective default values if not specified in the assembly. 1906 // 1907 // GRANULATED_WAVEFRONT_SGPR_COUNT 1908 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1909 // 1910 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1911 // are set to 0. So while disassembling we consider that: 1912 // 1913 // GRANULATED_WAVEFRONT_SGPR_COUNT 1914 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1915 // 1916 // The disassembler cannot recover the original values of those 3 directives. 1917 1918 uint32_t GranulatedWavefrontSGPRCount = 1919 GET_FIELD(COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT); 1920 1921 if (isGFX10Plus() && GranulatedWavefrontSGPRCount) 1922 return MCDisassembler::Fail; 1923 1924 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1925 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1926 1927 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1928 if (!hasArchitectedFlatScratch()) 1929 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1930 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1931 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1932 1933 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY) 1934 return MCDisassembler::Fail; 1935 1936 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1937 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1938 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1939 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1940 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1941 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1942 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1943 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1944 1945 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) 1946 return MCDisassembler::Fail; 1947 1948 if (!isGFX12Plus()) 1949 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", 1950 COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP); 1951 1952 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) 1953 return MCDisassembler::Fail; 1954 1955 if (!isGFX12Plus()) 1956 PRINT_DIRECTIVE(".amdhsa_ieee_mode", 1957 COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE); 1958 1959 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) 1960 return MCDisassembler::Fail; 1961 1962 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER) 1963 return MCDisassembler::Fail; 1964 1965 if (isGFX9Plus()) 1966 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL); 1967 1968 if (!isGFX9Plus()) 1969 if (FourByteBuffer & COMPUTE_PGM_RSRC1_GFX6_GFX8_RESERVED0) 1970 return MCDisassembler::Fail; 1971 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED1) 1972 return MCDisassembler::Fail; 1973 if (!isGFX10Plus()) 1974 if (FourByteBuffer & COMPUTE_PGM_RSRC1_GFX6_GFX9_RESERVED2) 1975 return MCDisassembler::Fail; 1976 1977 if (isGFX10Plus()) { 1978 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1979 COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE); 1980 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED); 1981 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS); 1982 } 1983 1984 if (isGFX12Plus()) 1985 PRINT_DIRECTIVE(".amdhsa_round_robin_scheduling", 1986 COMPUTE_PGM_RSRC1_GFX12_PLUS_ENABLE_WG_RR_EN); 1987 1988 return MCDisassembler::Success; 1989 } 1990 1991 // NOLINTNEXTLINE(readability-identifier-naming) 1992 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 1993 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1994 using namespace amdhsa; 1995 StringRef Indent = "\t"; 1996 if (hasArchitectedFlatScratch()) 1997 PRINT_DIRECTIVE(".amdhsa_enable_private_segment", 1998 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1999 else 2000 PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset", 2001 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 2002 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 2003 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 2004 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 2005 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 2006 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 2007 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 2008 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 2009 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 2010 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 2011 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 2012 2013 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH) 2014 return MCDisassembler::Fail; 2015 2016 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY) 2017 return MCDisassembler::Fail; 2018 2019 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE) 2020 return MCDisassembler::Fail; 2021 2022 PRINT_DIRECTIVE( 2023 ".amdhsa_exception_fp_ieee_invalid_op", 2024 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 2025 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 2026 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 2027 PRINT_DIRECTIVE( 2028 ".amdhsa_exception_fp_ieee_div_zero", 2029 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 2030 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 2031 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 2032 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 2033 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 2034 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 2035 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 2036 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 2037 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 2038 2039 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0) 2040 return MCDisassembler::Fail; 2041 2042 return MCDisassembler::Success; 2043 } 2044 2045 // NOLINTNEXTLINE(readability-identifier-naming) 2046 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC3( 2047 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 2048 using namespace amdhsa; 2049 StringRef Indent = "\t"; 2050 if (isGFX90A()) { 2051 KdStream << Indent << ".amdhsa_accum_offset " 2052 << (GET_FIELD(COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET) + 1) * 4 2053 << '\n'; 2054 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX90A_RESERVED0) 2055 return MCDisassembler::Fail; 2056 PRINT_DIRECTIVE(".amdhsa_tg_split", COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT); 2057 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX90A_RESERVED1) 2058 return MCDisassembler::Fail; 2059 } else if (isGFX10Plus()) { 2060 // Bits [0-3]. 2061 if (!isGFX12Plus()) { 2062 if (!EnableWavefrontSize32 || !*EnableWavefrontSize32) { 2063 PRINT_DIRECTIVE(".amdhsa_shared_vgpr_count", 2064 COMPUTE_PGM_RSRC3_GFX10_GFX11_SHARED_VGPR_COUNT); 2065 } else { 2066 PRINT_PSEUDO_DIRECTIVE_COMMENT( 2067 "SHARED_VGPR_COUNT", 2068 COMPUTE_PGM_RSRC3_GFX10_GFX11_SHARED_VGPR_COUNT); 2069 } 2070 } else { 2071 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX12_PLUS_RESERVED0) 2072 return MCDisassembler::Fail; 2073 } 2074 2075 // Bits [4-11]. 2076 if (isGFX11()) { 2077 PRINT_PSEUDO_DIRECTIVE_COMMENT("INST_PREF_SIZE", 2078 COMPUTE_PGM_RSRC3_GFX11_INST_PREF_SIZE); 2079 PRINT_PSEUDO_DIRECTIVE_COMMENT("TRAP_ON_START", 2080 COMPUTE_PGM_RSRC3_GFX11_TRAP_ON_START); 2081 PRINT_PSEUDO_DIRECTIVE_COMMENT("TRAP_ON_END", 2082 COMPUTE_PGM_RSRC3_GFX11_TRAP_ON_END); 2083 } else if (isGFX12Plus()) { 2084 PRINT_PSEUDO_DIRECTIVE_COMMENT( 2085 "INST_PREF_SIZE", COMPUTE_PGM_RSRC3_GFX12_PLUS_INST_PREF_SIZE); 2086 } else { 2087 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_RESERVED1) 2088 return MCDisassembler::Fail; 2089 } 2090 2091 // Bits [12]. 2092 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_PLUS_RESERVED2) 2093 return MCDisassembler::Fail; 2094 2095 // Bits [13]. 2096 if (isGFX12Plus()) { 2097 PRINT_PSEUDO_DIRECTIVE_COMMENT("GLG_EN", 2098 COMPUTE_PGM_RSRC3_GFX12_PLUS_GLG_EN); 2099 } else { 2100 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_GFX11_RESERVED3) 2101 return MCDisassembler::Fail; 2102 } 2103 2104 // Bits [14-30]. 2105 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_PLUS_RESERVED4) 2106 return MCDisassembler::Fail; 2107 2108 // Bits [31]. 2109 if (isGFX11Plus()) { 2110 PRINT_PSEUDO_DIRECTIVE_COMMENT("IMAGE_OP", 2111 COMPUTE_PGM_RSRC3_GFX11_PLUS_IMAGE_OP); 2112 } else { 2113 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_RESERVED5) 2114 return MCDisassembler::Fail; 2115 } 2116 } else if (FourByteBuffer) { 2117 return MCDisassembler::Fail; 2118 } 2119 return MCDisassembler::Success; 2120 } 2121 #undef PRINT_PSEUDO_DIRECTIVE_COMMENT 2122 #undef PRINT_DIRECTIVE 2123 #undef GET_FIELD 2124 2125 MCDisassembler::DecodeStatus 2126 AMDGPUDisassembler::decodeKernelDescriptorDirective( 2127 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 2128 raw_string_ostream &KdStream) const { 2129 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 2130 do { \ 2131 KdStream << Indent << DIRECTIVE " " \ 2132 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 2133 } while (0) 2134 2135 uint16_t TwoByteBuffer = 0; 2136 uint32_t FourByteBuffer = 0; 2137 2138 StringRef ReservedBytes; 2139 StringRef Indent = "\t"; 2140 2141 assert(Bytes.size() == 64); 2142 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 2143 2144 switch (Cursor.tell()) { 2145 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 2146 FourByteBuffer = DE.getU32(Cursor); 2147 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 2148 << '\n'; 2149 return MCDisassembler::Success; 2150 2151 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 2152 FourByteBuffer = DE.getU32(Cursor); 2153 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 2154 << FourByteBuffer << '\n'; 2155 return MCDisassembler::Success; 2156 2157 case amdhsa::KERNARG_SIZE_OFFSET: 2158 FourByteBuffer = DE.getU32(Cursor); 2159 KdStream << Indent << ".amdhsa_kernarg_size " 2160 << FourByteBuffer << '\n'; 2161 return MCDisassembler::Success; 2162 2163 case amdhsa::RESERVED0_OFFSET: 2164 // 4 reserved bytes, must be 0. 2165 ReservedBytes = DE.getBytes(Cursor, 4); 2166 for (int I = 0; I < 4; ++I) { 2167 if (ReservedBytes[I] != 0) { 2168 return MCDisassembler::Fail; 2169 } 2170 } 2171 return MCDisassembler::Success; 2172 2173 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 2174 // KERNEL_CODE_ENTRY_BYTE_OFFSET 2175 // So far no directive controls this for Code Object V3, so simply skip for 2176 // disassembly. 2177 DE.skip(Cursor, 8); 2178 return MCDisassembler::Success; 2179 2180 case amdhsa::RESERVED1_OFFSET: 2181 // 20 reserved bytes, must be 0. 2182 ReservedBytes = DE.getBytes(Cursor, 20); 2183 for (int I = 0; I < 20; ++I) { 2184 if (ReservedBytes[I] != 0) { 2185 return MCDisassembler::Fail; 2186 } 2187 } 2188 return MCDisassembler::Success; 2189 2190 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 2191 FourByteBuffer = DE.getU32(Cursor); 2192 return decodeCOMPUTE_PGM_RSRC3(FourByteBuffer, KdStream); 2193 2194 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 2195 FourByteBuffer = DE.getU32(Cursor); 2196 return decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream); 2197 2198 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 2199 FourByteBuffer = DE.getU32(Cursor); 2200 return decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream); 2201 2202 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 2203 using namespace amdhsa; 2204 TwoByteBuffer = DE.getU16(Cursor); 2205 2206 if (!hasArchitectedFlatScratch()) 2207 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 2208 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 2209 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 2210 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 2211 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 2212 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 2213 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 2214 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 2215 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 2216 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 2217 if (!hasArchitectedFlatScratch()) 2218 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 2219 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 2220 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 2221 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 2222 2223 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 2224 return MCDisassembler::Fail; 2225 2226 // Reserved for GFX9 2227 if (isGFX9() && 2228 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 2229 return MCDisassembler::Fail; 2230 } else if (isGFX10Plus()) { 2231 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 2232 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 2233 } 2234 2235 if (CodeObjectVersion >= AMDGPU::AMDHSA_COV5) 2236 PRINT_DIRECTIVE(".amdhsa_uses_dynamic_stack", 2237 KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK); 2238 2239 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) 2240 return MCDisassembler::Fail; 2241 2242 return MCDisassembler::Success; 2243 2244 case amdhsa::KERNARG_PRELOAD_OFFSET: 2245 using namespace amdhsa; 2246 TwoByteBuffer = DE.getU16(Cursor); 2247 if (TwoByteBuffer & KERNARG_PRELOAD_SPEC_LENGTH) { 2248 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_preload_length", 2249 KERNARG_PRELOAD_SPEC_LENGTH); 2250 } 2251 2252 if (TwoByteBuffer & KERNARG_PRELOAD_SPEC_OFFSET) { 2253 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_preload_offset", 2254 KERNARG_PRELOAD_SPEC_OFFSET); 2255 } 2256 return MCDisassembler::Success; 2257 2258 case amdhsa::RESERVED3_OFFSET: 2259 // 4 bytes from here are reserved, must be 0. 2260 ReservedBytes = DE.getBytes(Cursor, 4); 2261 for (int I = 0; I < 4; ++I) { 2262 if (ReservedBytes[I] != 0) 2263 return MCDisassembler::Fail; 2264 } 2265 return MCDisassembler::Success; 2266 2267 default: 2268 llvm_unreachable("Unhandled index. Case statements cover everything."); 2269 return MCDisassembler::Fail; 2270 } 2271 #undef PRINT_DIRECTIVE 2272 } 2273 2274 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( 2275 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 2276 // CP microcode requires the kernel descriptor to be 64 aligned. 2277 if (Bytes.size() != 64 || KdAddress % 64 != 0) 2278 return MCDisassembler::Fail; 2279 2280 // FIXME: We can't actually decode "in order" as is done below, as e.g. GFX10 2281 // requires us to know the setting of .amdhsa_wavefront_size32 in order to 2282 // accurately produce .amdhsa_next_free_vgpr, and they appear in the wrong 2283 // order. Workaround this by first looking up .amdhsa_wavefront_size32 here 2284 // when required. 2285 if (isGFX10Plus()) { 2286 uint16_t KernelCodeProperties = 2287 support::endian::read16(&Bytes[amdhsa::KERNEL_CODE_PROPERTIES_OFFSET], 2288 llvm::endianness::little); 2289 EnableWavefrontSize32 = 2290 AMDHSA_BITS_GET(KernelCodeProperties, 2291 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 2292 } 2293 2294 std::string Kd; 2295 raw_string_ostream KdStream(Kd); 2296 KdStream << ".amdhsa_kernel " << KdName << '\n'; 2297 2298 DataExtractor::Cursor C(0); 2299 while (C && C.tell() < Bytes.size()) { 2300 MCDisassembler::DecodeStatus Status = 2301 decodeKernelDescriptorDirective(C, Bytes, KdStream); 2302 2303 cantFail(C.takeError()); 2304 2305 if (Status == MCDisassembler::Fail) 2306 return MCDisassembler::Fail; 2307 } 2308 KdStream << ".end_amdhsa_kernel\n"; 2309 outs() << KdStream.str(); 2310 return MCDisassembler::Success; 2311 } 2312 2313 std::optional<MCDisassembler::DecodeStatus> 2314 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 2315 ArrayRef<uint8_t> Bytes, uint64_t Address, 2316 raw_ostream &CStream) const { 2317 // Right now only kernel descriptor needs to be handled. 2318 // We ignore all other symbols for target specific handling. 2319 // TODO: 2320 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 2321 // Object V2 and V3 when symbols are marked protected. 2322 2323 // amd_kernel_code_t for Code Object V2. 2324 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 2325 Size = 256; 2326 return MCDisassembler::Fail; 2327 } 2328 2329 // Code Object V3 kernel descriptors. 2330 StringRef Name = Symbol.Name; 2331 if (Symbol.Type == ELF::STT_OBJECT && Name.ends_with(StringRef(".kd"))) { 2332 Size = 64; // Size = 64 regardless of success or failure. 2333 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 2334 } 2335 return std::nullopt; 2336 } 2337 2338 //===----------------------------------------------------------------------===// 2339 // AMDGPUSymbolizer 2340 //===----------------------------------------------------------------------===// 2341 2342 // Try to find symbol name for specified label 2343 bool AMDGPUSymbolizer::tryAddingSymbolicOperand( 2344 MCInst &Inst, raw_ostream & /*cStream*/, int64_t Value, 2345 uint64_t /*Address*/, bool IsBranch, uint64_t /*Offset*/, 2346 uint64_t /*OpSize*/, uint64_t /*InstSize*/) { 2347 2348 if (!IsBranch) { 2349 return false; 2350 } 2351 2352 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 2353 if (!Symbols) 2354 return false; 2355 2356 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { 2357 return Val.Addr == static_cast<uint64_t>(Value) && 2358 Val.Type == ELF::STT_NOTYPE; 2359 }); 2360 if (Result != Symbols->end()) { 2361 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 2362 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 2363 Inst.addOperand(MCOperand::createExpr(Add)); 2364 return true; 2365 } 2366 // Add to list of referenced addresses, so caller can synthesize a label. 2367 ReferencedAddresses.push_back(static_cast<uint64_t>(Value)); 2368 return false; 2369 } 2370 2371 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 2372 int64_t Value, 2373 uint64_t Address) { 2374 llvm_unreachable("unimplemented"); 2375 } 2376 2377 //===----------------------------------------------------------------------===// 2378 // Initialization 2379 //===----------------------------------------------------------------------===// 2380 2381 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 2382 LLVMOpInfoCallback /*GetOpInfo*/, 2383 LLVMSymbolLookupCallback /*SymbolLookUp*/, 2384 void *DisInfo, 2385 MCContext *Ctx, 2386 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 2387 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 2388 } 2389 2390 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 2391 const MCSubtargetInfo &STI, 2392 MCContext &Ctx) { 2393 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 2394 } 2395 2396 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 2397 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 2398 createAMDGPUDisassembler); 2399 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 2400 createAMDGPUSymbolizer); 2401 } 2402