1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "SIDefines.h" 22 #include "SIRegisterInfo.h" 23 #include "TargetInfo/AMDGPUTargetInfo.h" 24 #include "Utils/AMDGPUBaseInfo.h" 25 #include "llvm-c/DisassemblerTypes.h" 26 #include "llvm/BinaryFormat/ELF.h" 27 #include "llvm/MC/MCAsmInfo.h" 28 #include "llvm/MC/MCContext.h" 29 #include "llvm/MC/MCDecoderOps.h" 30 #include "llvm/MC/MCExpr.h" 31 #include "llvm/MC/MCInstrDesc.h" 32 #include "llvm/MC/MCRegisterInfo.h" 33 #include "llvm/MC/MCSubtargetInfo.h" 34 #include "llvm/MC/TargetRegistry.h" 35 #include "llvm/Support/AMDHSAKernelDescriptor.h" 36 37 using namespace llvm; 38 39 #define DEBUG_TYPE "amdgpu-disassembler" 40 41 #define SGPR_MAX \ 42 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 43 : AMDGPU::EncValues::SGPR_MAX_SI) 44 45 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 46 47 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 48 MCContext &Ctx, MCInstrInfo const *MCII) 49 : MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), 50 MAI(*Ctx.getAsmInfo()), TargetMaxInstBytes(MAI.getMaxInstLength(&STI)), 51 CodeObjectVersion(AMDGPU::getDefaultAMDHSACodeObjectVersion()) { 52 // ToDo: AMDGPUDisassembler supports only VI ISA. 53 if (!STI.hasFeature(AMDGPU::FeatureGCN3Encoding) && !isGFX10Plus()) 54 report_fatal_error("Disassembly not yet supported for subtarget"); 55 } 56 57 void AMDGPUDisassembler::setABIVersion(unsigned Version) { 58 CodeObjectVersion = AMDGPU::getAMDHSACodeObjectVersion(Version); 59 } 60 61 inline static MCDisassembler::DecodeStatus 62 addOperand(MCInst &Inst, const MCOperand& Opnd) { 63 Inst.addOperand(Opnd); 64 return Opnd.isValid() ? 65 MCDisassembler::Success : 66 MCDisassembler::Fail; 67 } 68 69 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 70 uint16_t NameIdx) { 71 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 72 if (OpIdx != -1) { 73 auto I = MI.begin(); 74 std::advance(I, OpIdx); 75 MI.insert(I, Op); 76 } 77 return OpIdx; 78 } 79 80 static DecodeStatus decodeSOPPBrTarget(MCInst &Inst, unsigned Imm, 81 uint64_t Addr, 82 const MCDisassembler *Decoder) { 83 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 84 85 // Our branches take a simm16, but we need two extra bits to account for the 86 // factor of 4. 87 APInt SignedOffset(18, Imm * 4, true); 88 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 89 90 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2, 0)) 91 return MCDisassembler::Success; 92 return addOperand(Inst, MCOperand::createImm(Imm)); 93 } 94 95 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, 96 const MCDisassembler *Decoder) { 97 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 98 int64_t Offset; 99 if (DAsm->isGFX12Plus()) { // GFX12 supports 24-bit signed offsets. 100 Offset = SignExtend64<24>(Imm); 101 } else if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 102 Offset = Imm & 0xFFFFF; 103 } else { // GFX9+ supports 21-bit signed offsets. 104 Offset = SignExtend64<21>(Imm); 105 } 106 return addOperand(Inst, MCOperand::createImm(Offset)); 107 } 108 109 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, 110 const MCDisassembler *Decoder) { 111 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 112 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 113 } 114 115 static DecodeStatus decodeSplitBarrier(MCInst &Inst, unsigned Val, 116 uint64_t Addr, 117 const MCDisassembler *Decoder) { 118 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 119 return addOperand(Inst, DAsm->decodeSplitBarrier(Val)); 120 } 121 122 static DecodeStatus decodeDpp8FI(MCInst &Inst, unsigned Val, uint64_t Addr, 123 const MCDisassembler *Decoder) { 124 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 125 return addOperand(Inst, DAsm->decodeDpp8FI(Val)); 126 } 127 128 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 129 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \ 130 uint64_t /*Addr*/, \ 131 const MCDisassembler *Decoder) { \ 132 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 133 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 134 } 135 136 // Decoder for registers, decode directly using RegClassID. Imm(8-bit) is 137 // number of register. Used by VGPR only and AGPR only operands. 138 #define DECODE_OPERAND_REG_8(RegClass) \ 139 static DecodeStatus Decode##RegClass##RegisterClass( \ 140 MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \ 141 const MCDisassembler *Decoder) { \ 142 assert(Imm < (1 << 8) && "8-bit encoding"); \ 143 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 144 return addOperand( \ 145 Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm)); \ 146 } 147 148 #define DECODE_SrcOp(Name, EncSize, OpWidth, EncImm, MandatoryLiteral, \ 149 ImmWidth) \ 150 static DecodeStatus Name(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \ 151 const MCDisassembler *Decoder) { \ 152 assert(Imm < (1 << EncSize) && #EncSize "-bit encoding"); \ 153 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 154 return addOperand(Inst, \ 155 DAsm->decodeSrcOp(AMDGPUDisassembler::OpWidth, EncImm, \ 156 MandatoryLiteral, ImmWidth)); \ 157 } 158 159 static DecodeStatus decodeSrcOp(MCInst &Inst, unsigned EncSize, 160 AMDGPUDisassembler::OpWidthTy OpWidth, 161 unsigned Imm, unsigned EncImm, 162 bool MandatoryLiteral, unsigned ImmWidth, 163 AMDGPU::OperandSemantics Sema, 164 const MCDisassembler *Decoder) { 165 assert(Imm < (1U << EncSize) && "Operand doesn't fit encoding!"); 166 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 167 return addOperand(Inst, DAsm->decodeSrcOp(OpWidth, EncImm, MandatoryLiteral, 168 ImmWidth, Sema)); 169 } 170 171 // Decoder for registers. Imm(7-bit) is number of register, uses decodeSrcOp to 172 // get register class. Used by SGPR only operands. 173 #define DECODE_OPERAND_REG_7(RegClass, OpWidth) \ 174 DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0) 175 176 // Decoder for registers. Imm(10-bit): Imm{7-0} is number of register, 177 // Imm{9} is acc(agpr or vgpr) Imm{8} should be 0 (see VOP3Pe_SMFMAC). 178 // Set Imm{8} to 1 (IS_VGPR) to decode using 'enum10' from decodeSrcOp. 179 // Used by AV_ register classes (AGPR or VGPR only register operands). 180 template <AMDGPUDisassembler::OpWidthTy OpWidth> 181 static DecodeStatus decodeAV10(MCInst &Inst, unsigned Imm, uint64_t /* Addr */, 182 const MCDisassembler *Decoder) { 183 return decodeSrcOp(Inst, 10, OpWidth, Imm, Imm | AMDGPU::EncValues::IS_VGPR, 184 false, 0, AMDGPU::OperandSemantics::INT, Decoder); 185 } 186 187 // Decoder for Src(9-bit encoding) registers only. 188 template <AMDGPUDisassembler::OpWidthTy OpWidth> 189 static DecodeStatus decodeSrcReg9(MCInst &Inst, unsigned Imm, 190 uint64_t /* Addr */, 191 const MCDisassembler *Decoder) { 192 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, false, 0, 193 AMDGPU::OperandSemantics::INT, Decoder); 194 } 195 196 // Decoder for Src(9-bit encoding) AGPR, register number encoded in 9bits, set 197 // Imm{9} to 1 (set acc) and decode using 'enum10' from decodeSrcOp, registers 198 // only. 199 template <AMDGPUDisassembler::OpWidthTy OpWidth> 200 static DecodeStatus decodeSrcA9(MCInst &Inst, unsigned Imm, uint64_t /* Addr */, 201 const MCDisassembler *Decoder) { 202 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm | 512, false, 0, 203 AMDGPU::OperandSemantics::INT, Decoder); 204 } 205 206 // Decoder for 'enum10' from decodeSrcOp, Imm{0-8} is 9-bit Src encoding 207 // Imm{9} is acc, registers only. 208 template <AMDGPUDisassembler::OpWidthTy OpWidth> 209 static DecodeStatus decodeSrcAV10(MCInst &Inst, unsigned Imm, 210 uint64_t /* Addr */, 211 const MCDisassembler *Decoder) { 212 return decodeSrcOp(Inst, 10, OpWidth, Imm, Imm, false, 0, 213 AMDGPU::OperandSemantics::INT, Decoder); 214 } 215 216 // Decoder for RegisterOperands using 9-bit Src encoding. Operand can be 217 // register from RegClass or immediate. Registers that don't belong to RegClass 218 // will be decoded and InstPrinter will report warning. Immediate will be 219 // decoded into constant of size ImmWidth, should match width of immediate used 220 // by OperandType (important for floating point types). 221 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth, 222 unsigned OperandSemantics> 223 static DecodeStatus decodeSrcRegOrImm9(MCInst &Inst, unsigned Imm, 224 uint64_t /* Addr */, 225 const MCDisassembler *Decoder) { 226 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, false, ImmWidth, 227 (AMDGPU::OperandSemantics)OperandSemantics, Decoder); 228 } 229 230 // Decoder for Src(9-bit encoding) AGPR or immediate. Set Imm{9} to 1 (set acc) 231 // and decode using 'enum10' from decodeSrcOp. 232 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth, 233 unsigned OperandSemantics> 234 static DecodeStatus decodeSrcRegOrImmA9(MCInst &Inst, unsigned Imm, 235 uint64_t /* Addr */, 236 const MCDisassembler *Decoder) { 237 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm | 512, false, ImmWidth, 238 (AMDGPU::OperandSemantics)OperandSemantics, Decoder); 239 } 240 241 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth, 242 unsigned OperandSemantics> 243 static DecodeStatus decodeSrcRegOrImmDeferred9(MCInst &Inst, unsigned Imm, 244 uint64_t /* Addr */, 245 const MCDisassembler *Decoder) { 246 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, true, ImmWidth, 247 (AMDGPU::OperandSemantics)OperandSemantics, Decoder); 248 } 249 250 // Default decoders generated by tablegen: 'Decode<RegClass>RegisterClass' 251 // when RegisterClass is used as an operand. Most often used for destination 252 // operands. 253 254 DECODE_OPERAND_REG_8(VGPR_32) 255 DECODE_OPERAND_REG_8(VGPR_32_Lo128) 256 DECODE_OPERAND_REG_8(VReg_64) 257 DECODE_OPERAND_REG_8(VReg_96) 258 DECODE_OPERAND_REG_8(VReg_128) 259 DECODE_OPERAND_REG_8(VReg_256) 260 DECODE_OPERAND_REG_8(VReg_288) 261 DECODE_OPERAND_REG_8(VReg_352) 262 DECODE_OPERAND_REG_8(VReg_384) 263 DECODE_OPERAND_REG_8(VReg_512) 264 DECODE_OPERAND_REG_8(VReg_1024) 265 266 DECODE_OPERAND_REG_7(SReg_32, OPW32) 267 DECODE_OPERAND_REG_7(SReg_32_XEXEC, OPW32) 268 DECODE_OPERAND_REG_7(SReg_32_XM0_XEXEC, OPW32) 269 DECODE_OPERAND_REG_7(SReg_32_XEXEC_HI, OPW32) 270 DECODE_OPERAND_REG_7(SReg_64, OPW64) 271 DECODE_OPERAND_REG_7(SReg_64_XEXEC, OPW64) 272 DECODE_OPERAND_REG_7(SReg_96, OPW96) 273 DECODE_OPERAND_REG_7(SReg_128, OPW128) 274 DECODE_OPERAND_REG_7(SReg_256, OPW256) 275 DECODE_OPERAND_REG_7(SReg_512, OPW512) 276 277 DECODE_OPERAND_REG_8(AGPR_32) 278 DECODE_OPERAND_REG_8(AReg_64) 279 DECODE_OPERAND_REG_8(AReg_128) 280 DECODE_OPERAND_REG_8(AReg_256) 281 DECODE_OPERAND_REG_8(AReg_512) 282 DECODE_OPERAND_REG_8(AReg_1024) 283 284 static DecodeStatus DecodeVGPR_16RegisterClass(MCInst &Inst, unsigned Imm, 285 uint64_t /*Addr*/, 286 const MCDisassembler *Decoder) { 287 assert(isUInt<10>(Imm) && "10-bit encoding expected"); 288 assert((Imm & (1 << 8)) == 0 && "Imm{8} should not be used"); 289 290 bool IsHi = Imm & (1 << 9); 291 unsigned RegIdx = Imm & 0xff; 292 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 293 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 294 } 295 296 static DecodeStatus 297 DecodeVGPR_16_Lo128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, 298 const MCDisassembler *Decoder) { 299 assert(isUInt<8>(Imm) && "8-bit encoding expected"); 300 301 bool IsHi = Imm & (1 << 7); 302 unsigned RegIdx = Imm & 0x7f; 303 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 304 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 305 } 306 307 static DecodeStatus decodeOperand_VSrcT16_Lo128(MCInst &Inst, unsigned Imm, 308 uint64_t /*Addr*/, 309 const MCDisassembler *Decoder) { 310 assert(isUInt<9>(Imm) && "9-bit encoding expected"); 311 312 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 313 bool IsVGPR = Imm & (1 << 8); 314 if (IsVGPR) { 315 bool IsHi = Imm & (1 << 7); 316 unsigned RegIdx = Imm & 0x7f; 317 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 318 } 319 return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(AMDGPUDisassembler::OPW16, 320 Imm & 0xFF, false, 16)); 321 } 322 323 static DecodeStatus decodeOperand_VSrcT16(MCInst &Inst, unsigned Imm, 324 uint64_t /*Addr*/, 325 const MCDisassembler *Decoder) { 326 assert(isUInt<10>(Imm) && "10-bit encoding expected"); 327 328 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 329 bool IsVGPR = Imm & (1 << 8); 330 if (IsVGPR) { 331 bool IsHi = Imm & (1 << 9); 332 unsigned RegIdx = Imm & 0xff; 333 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 334 } 335 return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(AMDGPUDisassembler::OPW16, 336 Imm & 0xFF, false, 16)); 337 } 338 339 static DecodeStatus decodeOperand_KImmFP(MCInst &Inst, unsigned Imm, 340 uint64_t Addr, 341 const MCDisassembler *Decoder) { 342 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 343 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 344 } 345 346 static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val, 347 uint64_t Addr, const void *Decoder) { 348 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 349 return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val)); 350 } 351 352 static bool IsAGPROperand(const MCInst &Inst, int OpIdx, 353 const MCRegisterInfo *MRI) { 354 if (OpIdx < 0) 355 return false; 356 357 const MCOperand &Op = Inst.getOperand(OpIdx); 358 if (!Op.isReg()) 359 return false; 360 361 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); 362 auto Reg = Sub ? Sub : Op.getReg(); 363 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; 364 } 365 366 static DecodeStatus decodeAVLdSt(MCInst &Inst, unsigned Imm, 367 AMDGPUDisassembler::OpWidthTy Opw, 368 const MCDisassembler *Decoder) { 369 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 370 if (!DAsm->isGFX90A()) { 371 Imm &= 511; 372 } else { 373 // If atomic has both vdata and vdst their register classes are tied. 374 // The bit is decoded along with the vdst, first operand. We need to 375 // change register class to AGPR if vdst was AGPR. 376 // If a DS instruction has both data0 and data1 their register classes 377 // are also tied. 378 unsigned Opc = Inst.getOpcode(); 379 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; 380 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 381 : AMDGPU::OpName::vdata; 382 const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo(); 383 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); 384 if ((int)Inst.getNumOperands() == DataIdx) { 385 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); 386 if (IsAGPROperand(Inst, DstIdx, MRI)) 387 Imm |= 512; 388 } 389 390 if (TSFlags & SIInstrFlags::DS) { 391 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); 392 if ((int)Inst.getNumOperands() == Data2Idx && 393 IsAGPROperand(Inst, DataIdx, MRI)) 394 Imm |= 512; 395 } 396 } 397 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); 398 } 399 400 template <AMDGPUDisassembler::OpWidthTy Opw> 401 static DecodeStatus decodeAVLdSt(MCInst &Inst, unsigned Imm, 402 uint64_t /* Addr */, 403 const MCDisassembler *Decoder) { 404 return decodeAVLdSt(Inst, Imm, Opw, Decoder); 405 } 406 407 static DecodeStatus decodeOperand_VSrc_f64(MCInst &Inst, unsigned Imm, 408 uint64_t Addr, 409 const MCDisassembler *Decoder) { 410 assert(Imm < (1 << 9) && "9-bit encoding"); 411 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 412 return addOperand(Inst, 413 DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm, false, 64, 414 AMDGPU::OperandSemantics::FP64)); 415 } 416 417 #define DECODE_SDWA(DecName) \ 418 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 419 420 DECODE_SDWA(Src32) 421 DECODE_SDWA(Src16) 422 DECODE_SDWA(VopcDst) 423 424 #include "AMDGPUGenDisassemblerTables.inc" 425 426 //===----------------------------------------------------------------------===// 427 // 428 //===----------------------------------------------------------------------===// 429 430 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 431 assert(Bytes.size() >= sizeof(T)); 432 const auto Res = 433 support::endian::read<T, llvm::endianness::little>(Bytes.data()); 434 Bytes = Bytes.slice(sizeof(T)); 435 return Res; 436 } 437 438 static inline DecoderUInt128 eat12Bytes(ArrayRef<uint8_t> &Bytes) { 439 assert(Bytes.size() >= 12); 440 uint64_t Lo = 441 support::endian::read<uint64_t, llvm::endianness::little>(Bytes.data()); 442 Bytes = Bytes.slice(8); 443 uint64_t Hi = 444 support::endian::read<uint32_t, llvm::endianness::little>(Bytes.data()); 445 Bytes = Bytes.slice(4); 446 return DecoderUInt128(Lo, Hi); 447 } 448 449 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 450 ArrayRef<uint8_t> Bytes_, 451 uint64_t Address, 452 raw_ostream &CS) const { 453 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 454 Bytes = Bytes_.slice(0, MaxInstBytesNum); 455 456 DecodeStatus Res = MCDisassembler::Fail; 457 do { 458 // ToDo: better to switch encoding length using some bit predicate 459 // but it is unknown yet, so try all we can 460 461 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 462 // encodings 463 if (isGFX11Plus() && Bytes.size() >= 12 ) { 464 DecoderUInt128 DecW = eat12Bytes(Bytes); 465 Res = 466 tryDecodeInst(DecoderTableDPP8GFX1196, DecoderTableDPP8GFX11_FAKE1696, 467 MI, DecW, Address, CS); 468 if (Res) 469 break; 470 471 Res = 472 tryDecodeInst(DecoderTableDPP8GFX1296, DecoderTableDPP8GFX12_FAKE1696, 473 MI, DecW, Address, CS); 474 if (Res) 475 break; 476 477 Res = tryDecodeInst(DecoderTableDPPGFX1196, DecoderTableDPPGFX11_FAKE1696, 478 MI, DecW, Address, CS); 479 if (Res) 480 break; 481 482 Res = tryDecodeInst(DecoderTableDPPGFX1296, DecoderTableDPPGFX12_FAKE1696, 483 MI, DecW, Address, CS); 484 if (Res) 485 break; 486 487 Res = tryDecodeInst(DecoderTableGFX1196, MI, DecW, Address, CS); 488 if (Res) 489 break; 490 491 Res = tryDecodeInst(DecoderTableGFX1296, MI, DecW, Address, CS); 492 if (Res) 493 break; 494 495 Res = tryDecodeInst(DecoderTableGFX12W6496, MI, DecW, Address, CS); 496 if (Res) 497 break; 498 } 499 // Reinitialize Bytes 500 Bytes = Bytes_.slice(0, MaxInstBytesNum); 501 502 if (Bytes.size() >= 8) { 503 const uint64_t QW = eatBytes<uint64_t>(Bytes); 504 505 if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding)) { 506 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address, CS); 507 if (Res) 508 break; 509 } 510 511 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address, CS); 512 if (Res) 513 break; 514 515 Res = tryDecodeInst(DecoderTableDPP8GFX1164, 516 DecoderTableDPP8GFX11_FAKE1664, MI, QW, Address, CS); 517 if (Res) 518 break; 519 520 Res = tryDecodeInst(DecoderTableDPP8GFX1264, 521 DecoderTableDPP8GFX12_FAKE1664, MI, QW, Address, CS); 522 if (Res) 523 break; 524 525 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address, CS); 526 if (Res) break; 527 528 Res = tryDecodeInst(DecoderTableDPPGFX1164, DecoderTableDPPGFX11_FAKE1664, 529 MI, QW, Address, CS); 530 if (Res) 531 break; 532 533 Res = tryDecodeInst(DecoderTableDPPGFX1264, DecoderTableDPPGFX12_FAKE1664, 534 MI, QW, Address, CS); 535 if (Res) 536 break; 537 538 if (STI.hasFeature(AMDGPU::FeatureUnpackedD16VMem)) { 539 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address, CS); 540 if (Res) 541 break; 542 } 543 544 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 545 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 546 // table first so we print the correct name. 547 if (STI.hasFeature(AMDGPU::FeatureFmaMixInsts)) { 548 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address, CS); 549 if (Res) 550 break; 551 } 552 553 if (STI.hasFeature(AMDGPU::FeatureGFX940Insts)) { 554 Res = tryDecodeInst(DecoderTableGFX94064, MI, QW, Address, CS); 555 if (Res) 556 break; 557 } 558 559 if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts)) { 560 Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address, CS); 561 if (Res) 562 break; 563 } 564 565 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address, CS); 566 if (Res) 567 break; 568 569 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address, CS); 570 if (Res) 571 break; 572 573 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address, CS); 574 if (Res) 575 break; 576 577 Res = tryDecodeInst(DecoderTableGFX1264, DecoderTableGFX12_FAKE1664, MI, 578 QW, Address, CS); 579 if (Res) 580 break; 581 582 Res = tryDecodeInst(DecoderTableGFX1164, DecoderTableGFX11_FAKE1664, MI, 583 QW, Address, CS); 584 if (Res) 585 break; 586 587 Res = tryDecodeInst(DecoderTableGFX11W6464, MI, QW, Address, CS); 588 if (Res) 589 break; 590 591 Res = tryDecodeInst(DecoderTableGFX12W6464, MI, QW, Address, CS); 592 if (Res) 593 break; 594 } 595 596 // Reinitialize Bytes as DPP64 could have eaten too much 597 Bytes = Bytes_.slice(0, MaxInstBytesNum); 598 599 // Try decode 32-bit instruction 600 if (Bytes.size() < 4) break; 601 const uint32_t DW = eatBytes<uint32_t>(Bytes); 602 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address, CS); 603 if (Res) break; 604 605 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address, CS); 606 if (Res) break; 607 608 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address, CS); 609 if (Res) break; 610 611 if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts)) { 612 Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address, CS); 613 if (Res) 614 break; 615 } 616 617 if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding)) { 618 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address, CS); 619 if (Res) break; 620 } 621 622 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address, CS); 623 if (Res) break; 624 625 Res = tryDecodeInst(DecoderTableGFX1132, DecoderTableGFX11_FAKE1632, MI, DW, 626 Address, CS); 627 if (Res) break; 628 629 Res = tryDecodeInst(DecoderTableGFX1232, DecoderTableGFX12_FAKE1632, MI, DW, 630 Address, CS); 631 } while (false); 632 633 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::DPP)) { 634 if (isMacDPP(MI)) 635 convertMacDPPInst(MI); 636 637 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3P) 638 convertVOP3PDPPInst(MI); 639 else if ((MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC) || 640 AMDGPU::isVOPC64DPP(MI.getOpcode())) 641 convertVOPCDPPInst(MI); // Special VOP3 case 642 else if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) != 643 -1) 644 convertDPP8Inst(MI); 645 else if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3) 646 convertVOP3DPPInst(MI); // Regular VOP3 case 647 } 648 649 if (Res && AMDGPU::isMAC(MI.getOpcode())) { 650 // Insert dummy unused src2_modifiers. 651 insertNamedMCOperand(MI, MCOperand::createImm(0), 652 AMDGPU::OpName::src2_modifiers); 653 } 654 655 if (Res && (MI.getOpcode() == AMDGPU::V_CVT_SR_BF8_F32_e64_dpp || 656 MI.getOpcode() == AMDGPU::V_CVT_SR_FP8_F32_e64_dpp)) { 657 // Insert dummy unused src2_modifiers. 658 insertNamedMCOperand(MI, MCOperand::createImm(0), 659 AMDGPU::OpName::src2_modifiers); 660 } 661 662 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::DS) && 663 !AMDGPU::hasGDS(STI)) { 664 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::gds); 665 } 666 667 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 668 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT | SIInstrFlags::SMRD))) { 669 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 670 AMDGPU::OpName::cpol); 671 if (CPolPos != -1) { 672 unsigned CPol = 673 (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ? 674 AMDGPU::CPol::GLC : 0; 675 if (MI.getNumOperands() <= (unsigned)CPolPos) { 676 insertNamedMCOperand(MI, MCOperand::createImm(CPol), 677 AMDGPU::OpName::cpol); 678 } else if (CPol) { 679 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); 680 } 681 } 682 } 683 684 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 685 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) && 686 (STI.hasFeature(AMDGPU::FeatureGFX90AInsts))) { 687 // GFX90A lost TFE, its place is occupied by ACC. 688 int TFEOpIdx = 689 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); 690 if (TFEOpIdx != -1) { 691 auto TFEIter = MI.begin(); 692 std::advance(TFEIter, TFEOpIdx); 693 MI.insert(TFEIter, MCOperand::createImm(0)); 694 } 695 } 696 697 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 698 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF))) { 699 int SWZOpIdx = 700 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); 701 if (SWZOpIdx != -1) { 702 auto SWZIter = MI.begin(); 703 std::advance(SWZIter, SWZOpIdx); 704 MI.insert(SWZIter, MCOperand::createImm(0)); 705 } 706 } 707 708 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 709 int VAddr0Idx = 710 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 711 int RsrcIdx = 712 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 713 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 714 if (VAddr0Idx >= 0 && NSAArgs > 0) { 715 unsigned NSAWords = (NSAArgs + 3) / 4; 716 if (Bytes.size() < 4 * NSAWords) { 717 Res = MCDisassembler::Fail; 718 } else { 719 for (unsigned i = 0; i < NSAArgs; ++i) { 720 const unsigned VAddrIdx = VAddr0Idx + 1 + i; 721 auto VAddrRCID = 722 MCII->get(MI.getOpcode()).operands()[VAddrIdx].RegClass; 723 MI.insert(MI.begin() + VAddrIdx, 724 createRegOperand(VAddrRCID, Bytes[i])); 725 } 726 Bytes = Bytes.slice(4 * NSAWords); 727 } 728 } 729 730 if (Res) 731 Res = convertMIMGInst(MI); 732 } 733 734 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 735 (SIInstrFlags::VIMAGE | SIInstrFlags::VSAMPLE))) 736 Res = convertMIMGInst(MI); 737 738 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::EXP)) 739 Res = convertEXPInst(MI); 740 741 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VINTERP)) 742 Res = convertVINTERPInst(MI); 743 744 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::SDWA)) 745 Res = convertSDWAInst(MI); 746 747 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 748 AMDGPU::OpName::vdst_in); 749 if (VDstIn_Idx != -1) { 750 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 751 MCOI::OperandConstraint::TIED_TO); 752 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 753 !MI.getOperand(VDstIn_Idx).isReg() || 754 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 755 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 756 MI.erase(&MI.getOperand(VDstIn_Idx)); 757 insertNamedMCOperand(MI, 758 MCOperand::createReg(MI.getOperand(Tied).getReg()), 759 AMDGPU::OpName::vdst_in); 760 } 761 } 762 763 int ImmLitIdx = 764 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm); 765 bool IsSOPK = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::SOPK; 766 if (Res && ImmLitIdx != -1 && !IsSOPK) 767 Res = convertFMAanyK(MI, ImmLitIdx); 768 769 // if the opcode was not recognized we'll assume a Size of 4 bytes 770 // (unless there are fewer bytes left) 771 Size = Res ? (MaxInstBytesNum - Bytes.size()) 772 : std::min((size_t)4, Bytes_.size()); 773 return Res; 774 } 775 776 DecodeStatus AMDGPUDisassembler::convertEXPInst(MCInst &MI) const { 777 if (STI.hasFeature(AMDGPU::FeatureGFX11Insts)) { 778 // The MCInst still has these fields even though they are no longer encoded 779 // in the GFX11 instruction. 780 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vm); 781 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::compr); 782 } 783 return MCDisassembler::Success; 784 } 785 786 DecodeStatus AMDGPUDisassembler::convertVINTERPInst(MCInst &MI) const { 787 if (MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx11 || 788 MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx12 || 789 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx11 || 790 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx12 || 791 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx11 || 792 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx12 || 793 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx11 || 794 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx12) { 795 // The MCInst has this field that is not directly encoded in the 796 // instruction. 797 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::op_sel); 798 } 799 return MCDisassembler::Success; 800 } 801 802 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 803 if (STI.hasFeature(AMDGPU::FeatureGFX9) || 804 STI.hasFeature(AMDGPU::FeatureGFX10)) { 805 if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::sdst)) 806 // VOPC - insert clamp 807 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 808 } else if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) { 809 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 810 if (SDst != -1) { 811 // VOPC - insert VCC register as sdst 812 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 813 AMDGPU::OpName::sdst); 814 } else { 815 // VOP1/2 - insert omod if present in instruction 816 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 817 } 818 } 819 return MCDisassembler::Success; 820 } 821 822 struct VOPModifiers { 823 unsigned OpSel = 0; 824 unsigned OpSelHi = 0; 825 unsigned NegLo = 0; 826 unsigned NegHi = 0; 827 }; 828 829 // Reconstruct values of VOP3/VOP3P operands such as op_sel. 830 // Note that these values do not affect disassembler output, 831 // so this is only necessary for consistency with src_modifiers. 832 static VOPModifiers collectVOPModifiers(const MCInst &MI, 833 bool IsVOP3P = false) { 834 VOPModifiers Modifiers; 835 unsigned Opc = MI.getOpcode(); 836 const int ModOps[] = {AMDGPU::OpName::src0_modifiers, 837 AMDGPU::OpName::src1_modifiers, 838 AMDGPU::OpName::src2_modifiers}; 839 for (int J = 0; J < 3; ++J) { 840 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]); 841 if (OpIdx == -1) 842 continue; 843 844 unsigned Val = MI.getOperand(OpIdx).getImm(); 845 846 Modifiers.OpSel |= !!(Val & SISrcMods::OP_SEL_0) << J; 847 if (IsVOP3P) { 848 Modifiers.OpSelHi |= !!(Val & SISrcMods::OP_SEL_1) << J; 849 Modifiers.NegLo |= !!(Val & SISrcMods::NEG) << J; 850 Modifiers.NegHi |= !!(Val & SISrcMods::NEG_HI) << J; 851 } else if (J == 0) { 852 Modifiers.OpSel |= !!(Val & SISrcMods::DST_OP_SEL) << 3; 853 } 854 } 855 856 return Modifiers; 857 } 858 859 // Instructions decode the op_sel/suffix bits into the src_modifier 860 // operands. Copy those bits into the src operands for true16 VGPRs. 861 void AMDGPUDisassembler::convertTrue16OpSel(MCInst &MI) const { 862 const unsigned Opc = MI.getOpcode(); 863 const MCRegisterClass &ConversionRC = 864 MRI.getRegClass(AMDGPU::VGPR_16RegClassID); 865 constexpr std::array<std::tuple<int, int, unsigned>, 4> OpAndOpMods = { 866 {{AMDGPU::OpName::src0, AMDGPU::OpName::src0_modifiers, 867 SISrcMods::OP_SEL_0}, 868 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_modifiers, 869 SISrcMods::OP_SEL_0}, 870 {AMDGPU::OpName::src2, AMDGPU::OpName::src2_modifiers, 871 SISrcMods::OP_SEL_0}, 872 {AMDGPU::OpName::vdst, AMDGPU::OpName::src0_modifiers, 873 SISrcMods::DST_OP_SEL}}}; 874 for (const auto &[OpName, OpModsName, OpSelMask] : OpAndOpMods) { 875 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, OpName); 876 int OpModsIdx = AMDGPU::getNamedOperandIdx(Opc, OpModsName); 877 if (OpIdx == -1 || OpModsIdx == -1) 878 continue; 879 MCOperand &Op = MI.getOperand(OpIdx); 880 if (!Op.isReg()) 881 continue; 882 if (!ConversionRC.contains(Op.getReg())) 883 continue; 884 unsigned OpEnc = MRI.getEncodingValue(Op.getReg()); 885 const MCOperand &OpMods = MI.getOperand(OpModsIdx); 886 unsigned ModVal = OpMods.getImm(); 887 if (ModVal & OpSelMask) { // isHi 888 unsigned RegIdx = OpEnc & AMDGPU::HWEncoding::REG_IDX_MASK; 889 Op.setReg(ConversionRC.getRegister(RegIdx * 2 + 1)); 890 } 891 } 892 } 893 894 // MAC opcodes have special old and src2 operands. 895 // src2 is tied to dst, while old is not tied (but assumed to be). 896 bool AMDGPUDisassembler::isMacDPP(MCInst &MI) const { 897 constexpr int DST_IDX = 0; 898 auto Opcode = MI.getOpcode(); 899 const auto &Desc = MCII->get(Opcode); 900 auto OldIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::old); 901 902 if (OldIdx != -1 && Desc.getOperandConstraint( 903 OldIdx, MCOI::OperandConstraint::TIED_TO) == -1) { 904 assert(AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src2)); 905 assert(Desc.getOperandConstraint( 906 AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2), 907 MCOI::OperandConstraint::TIED_TO) == DST_IDX); 908 (void)DST_IDX; 909 return true; 910 } 911 912 return false; 913 } 914 915 // Create dummy old operand and insert dummy unused src2_modifiers 916 void AMDGPUDisassembler::convertMacDPPInst(MCInst &MI) const { 917 assert(MI.getNumOperands() + 1 < MCII->get(MI.getOpcode()).getNumOperands()); 918 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 919 insertNamedMCOperand(MI, MCOperand::createImm(0), 920 AMDGPU::OpName::src2_modifiers); 921 } 922 923 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 924 unsigned Opc = MI.getOpcode(); 925 926 int VDstInIdx = 927 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst_in); 928 if (VDstInIdx != -1) 929 insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::vdst_in); 930 931 if (MI.getOpcode() == AMDGPU::V_CVT_SR_BF8_F32_e64_dpp8_gfx12 || 932 MI.getOpcode() == AMDGPU::V_CVT_SR_FP8_F32_e64_dpp8_gfx12) 933 insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::src2); 934 935 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 936 if (MI.getNumOperands() < DescNumOps && 937 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { 938 convertTrue16OpSel(MI); 939 auto Mods = collectVOPModifiers(MI); 940 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 941 AMDGPU::OpName::op_sel); 942 } else { 943 // Insert dummy unused src modifiers. 944 if (MI.getNumOperands() < DescNumOps && 945 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) 946 insertNamedMCOperand(MI, MCOperand::createImm(0), 947 AMDGPU::OpName::src0_modifiers); 948 949 if (MI.getNumOperands() < DescNumOps && 950 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers)) 951 insertNamedMCOperand(MI, MCOperand::createImm(0), 952 AMDGPU::OpName::src1_modifiers); 953 } 954 return MCDisassembler::Success; 955 } 956 957 DecodeStatus AMDGPUDisassembler::convertVOP3DPPInst(MCInst &MI) const { 958 convertTrue16OpSel(MI); 959 960 int VDstInIdx = 961 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst_in); 962 if (VDstInIdx != -1) 963 insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::vdst_in); 964 965 if (MI.getOpcode() == AMDGPU::V_CVT_SR_BF8_F32_e64_dpp_gfx12 || 966 MI.getOpcode() == AMDGPU::V_CVT_SR_FP8_F32_e64_dpp_gfx12) 967 insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::src2); 968 969 unsigned Opc = MI.getOpcode(); 970 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 971 if (MI.getNumOperands() < DescNumOps && 972 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { 973 auto Mods = collectVOPModifiers(MI); 974 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 975 AMDGPU::OpName::op_sel); 976 } 977 return MCDisassembler::Success; 978 } 979 980 // Note that before gfx10, the MIMG encoding provided no information about 981 // VADDR size. Consequently, decoded instructions always show address as if it 982 // has 1 dword, which could be not really so. 983 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 984 auto TSFlags = MCII->get(MI.getOpcode()).TSFlags; 985 986 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 987 AMDGPU::OpName::vdst); 988 989 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 990 AMDGPU::OpName::vdata); 991 int VAddr0Idx = 992 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 993 int RsrcOpName = TSFlags & SIInstrFlags::MIMG ? AMDGPU::OpName::srsrc 994 : AMDGPU::OpName::rsrc; 995 int RsrcIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), RsrcOpName); 996 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 997 AMDGPU::OpName::dmask); 998 999 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 1000 AMDGPU::OpName::tfe); 1001 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 1002 AMDGPU::OpName::d16); 1003 1004 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 1005 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 1006 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 1007 1008 assert(VDataIdx != -1); 1009 if (BaseOpcode->BVH) { 1010 // Add A16 operand for intersect_ray instructions 1011 addOperand(MI, MCOperand::createImm(BaseOpcode->A16)); 1012 return MCDisassembler::Success; 1013 } 1014 1015 bool IsAtomic = (VDstIdx != -1); 1016 bool IsGather4 = TSFlags & SIInstrFlags::Gather4; 1017 bool IsVSample = TSFlags & SIInstrFlags::VSAMPLE; 1018 bool IsNSA = false; 1019 bool IsPartialNSA = false; 1020 unsigned AddrSize = Info->VAddrDwords; 1021 1022 if (isGFX10Plus()) { 1023 unsigned DimIdx = 1024 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 1025 int A16Idx = 1026 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16); 1027 const AMDGPU::MIMGDimInfo *Dim = 1028 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 1029 const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm()); 1030 1031 AddrSize = 1032 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); 1033 1034 // VSAMPLE insts that do not use vaddr3 behave the same as NSA forms. 1035 // VIMAGE insts other than BVH never use vaddr4. 1036 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA || 1037 Info->MIMGEncoding == AMDGPU::MIMGEncGfx11NSA || 1038 Info->MIMGEncoding == AMDGPU::MIMGEncGfx12; 1039 if (!IsNSA) { 1040 if (!IsVSample && AddrSize > 12) 1041 AddrSize = 16; 1042 } else { 1043 if (AddrSize > Info->VAddrDwords) { 1044 if (!STI.hasFeature(AMDGPU::FeaturePartialNSAEncoding)) { 1045 // The NSA encoding does not contain enough operands for the 1046 // combination of base opcode / dimension. Should this be an error? 1047 return MCDisassembler::Success; 1048 } 1049 IsPartialNSA = true; 1050 } 1051 } 1052 } 1053 1054 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 1055 unsigned DstSize = IsGather4 ? 4 : std::max(llvm::popcount(DMask), 1); 1056 1057 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 1058 if (D16 && AMDGPU::hasPackedD16(STI)) { 1059 DstSize = (DstSize + 1) / 2; 1060 } 1061 1062 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm()) 1063 DstSize += 1; 1064 1065 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 1066 return MCDisassembler::Success; 1067 1068 int NewOpcode = 1069 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 1070 if (NewOpcode == -1) 1071 return MCDisassembler::Success; 1072 1073 // Widen the register to the correct number of enabled channels. 1074 unsigned NewVdata = AMDGPU::NoRegister; 1075 if (DstSize != Info->VDataDwords) { 1076 auto DataRCID = MCII->get(NewOpcode).operands()[VDataIdx].RegClass; 1077 1078 // Get first subregister of VData 1079 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 1080 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 1081 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 1082 1083 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 1084 &MRI.getRegClass(DataRCID)); 1085 if (NewVdata == AMDGPU::NoRegister) { 1086 // It's possible to encode this such that the low register + enabled 1087 // components exceeds the register count. 1088 return MCDisassembler::Success; 1089 } 1090 } 1091 1092 // If not using NSA on GFX10+, widen vaddr0 address register to correct size. 1093 // If using partial NSA on GFX11+ widen last address register. 1094 int VAddrSAIdx = IsPartialNSA ? (RsrcIdx - 1) : VAddr0Idx; 1095 unsigned NewVAddrSA = AMDGPU::NoRegister; 1096 if (STI.hasFeature(AMDGPU::FeatureNSAEncoding) && (!IsNSA || IsPartialNSA) && 1097 AddrSize != Info->VAddrDwords) { 1098 unsigned VAddrSA = MI.getOperand(VAddrSAIdx).getReg(); 1099 unsigned VAddrSubSA = MRI.getSubReg(VAddrSA, AMDGPU::sub0); 1100 VAddrSA = VAddrSubSA ? VAddrSubSA : VAddrSA; 1101 1102 auto AddrRCID = MCII->get(NewOpcode).operands()[VAddrSAIdx].RegClass; 1103 NewVAddrSA = MRI.getMatchingSuperReg(VAddrSA, AMDGPU::sub0, 1104 &MRI.getRegClass(AddrRCID)); 1105 if (!NewVAddrSA) 1106 return MCDisassembler::Success; 1107 } 1108 1109 MI.setOpcode(NewOpcode); 1110 1111 if (NewVdata != AMDGPU::NoRegister) { 1112 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 1113 1114 if (IsAtomic) { 1115 // Atomic operations have an additional operand (a copy of data) 1116 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 1117 } 1118 } 1119 1120 if (NewVAddrSA) { 1121 MI.getOperand(VAddrSAIdx) = MCOperand::createReg(NewVAddrSA); 1122 } else if (IsNSA) { 1123 assert(AddrSize <= Info->VAddrDwords); 1124 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 1125 MI.begin() + VAddr0Idx + Info->VAddrDwords); 1126 } 1127 1128 return MCDisassembler::Success; 1129 } 1130 1131 // Opsel and neg bits are used in src_modifiers and standalone operands. Autogen 1132 // decoder only adds to src_modifiers, so manually add the bits to the other 1133 // operands. 1134 DecodeStatus AMDGPUDisassembler::convertVOP3PDPPInst(MCInst &MI) const { 1135 unsigned Opc = MI.getOpcode(); 1136 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1137 auto Mods = collectVOPModifiers(MI, true); 1138 1139 if (MI.getNumOperands() < DescNumOps && 1140 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vdst_in)) 1141 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vdst_in); 1142 1143 if (MI.getNumOperands() < DescNumOps && 1144 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) 1145 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 1146 AMDGPU::OpName::op_sel); 1147 if (MI.getNumOperands() < DescNumOps && 1148 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel_hi)) 1149 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSelHi), 1150 AMDGPU::OpName::op_sel_hi); 1151 if (MI.getNumOperands() < DescNumOps && 1152 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_lo)) 1153 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegLo), 1154 AMDGPU::OpName::neg_lo); 1155 if (MI.getNumOperands() < DescNumOps && 1156 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_hi)) 1157 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegHi), 1158 AMDGPU::OpName::neg_hi); 1159 1160 return MCDisassembler::Success; 1161 } 1162 1163 // Create dummy old operand and insert optional operands 1164 DecodeStatus AMDGPUDisassembler::convertVOPCDPPInst(MCInst &MI) const { 1165 unsigned Opc = MI.getOpcode(); 1166 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1167 1168 if (MI.getNumOperands() < DescNumOps && 1169 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::old)) 1170 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 1171 1172 if (MI.getNumOperands() < DescNumOps && 1173 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) 1174 insertNamedMCOperand(MI, MCOperand::createImm(0), 1175 AMDGPU::OpName::src0_modifiers); 1176 1177 if (MI.getNumOperands() < DescNumOps && 1178 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers)) 1179 insertNamedMCOperand(MI, MCOperand::createImm(0), 1180 AMDGPU::OpName::src1_modifiers); 1181 return MCDisassembler::Success; 1182 } 1183 1184 DecodeStatus AMDGPUDisassembler::convertFMAanyK(MCInst &MI, 1185 int ImmLitIdx) const { 1186 assert(HasLiteral && "Should have decoded a literal"); 1187 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 1188 unsigned DescNumOps = Desc.getNumOperands(); 1189 insertNamedMCOperand(MI, MCOperand::createImm(Literal), 1190 AMDGPU::OpName::immDeferred); 1191 assert(DescNumOps == MI.getNumOperands()); 1192 for (unsigned I = 0; I < DescNumOps; ++I) { 1193 auto &Op = MI.getOperand(I); 1194 auto OpType = Desc.operands()[I].OperandType; 1195 bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED || 1196 OpType == AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED); 1197 if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST && 1198 IsDeferredOp) 1199 Op.setImm(Literal); 1200 } 1201 return MCDisassembler::Success; 1202 } 1203 1204 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 1205 return getContext().getRegisterInfo()-> 1206 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 1207 } 1208 1209 inline 1210 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 1211 const Twine& ErrMsg) const { 1212 *CommentStream << "Error: " + ErrMsg; 1213 1214 // ToDo: add support for error operands to MCInst.h 1215 // return MCOperand::createError(V); 1216 return MCOperand(); 1217 } 1218 1219 inline 1220 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 1221 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 1222 } 1223 1224 inline 1225 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 1226 unsigned Val) const { 1227 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 1228 if (Val >= RegCl.getNumRegs()) 1229 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 1230 ": unknown register " + Twine(Val)); 1231 return createRegOperand(RegCl.getRegister(Val)); 1232 } 1233 1234 inline 1235 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 1236 unsigned Val) const { 1237 // ToDo: SI/CI have 104 SGPRs, VI - 102 1238 // Valery: here we accepting as much as we can, let assembler sort it out 1239 int shift = 0; 1240 switch (SRegClassID) { 1241 case AMDGPU::SGPR_32RegClassID: 1242 case AMDGPU::TTMP_32RegClassID: 1243 break; 1244 case AMDGPU::SGPR_64RegClassID: 1245 case AMDGPU::TTMP_64RegClassID: 1246 shift = 1; 1247 break; 1248 case AMDGPU::SGPR_96RegClassID: 1249 case AMDGPU::TTMP_96RegClassID: 1250 case AMDGPU::SGPR_128RegClassID: 1251 case AMDGPU::TTMP_128RegClassID: 1252 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 1253 // this bundle? 1254 case AMDGPU::SGPR_256RegClassID: 1255 case AMDGPU::TTMP_256RegClassID: 1256 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 1257 // this bundle? 1258 case AMDGPU::SGPR_288RegClassID: 1259 case AMDGPU::TTMP_288RegClassID: 1260 case AMDGPU::SGPR_320RegClassID: 1261 case AMDGPU::TTMP_320RegClassID: 1262 case AMDGPU::SGPR_352RegClassID: 1263 case AMDGPU::TTMP_352RegClassID: 1264 case AMDGPU::SGPR_384RegClassID: 1265 case AMDGPU::TTMP_384RegClassID: 1266 case AMDGPU::SGPR_512RegClassID: 1267 case AMDGPU::TTMP_512RegClassID: 1268 shift = 2; 1269 break; 1270 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 1271 // this bundle? 1272 default: 1273 llvm_unreachable("unhandled register class"); 1274 } 1275 1276 if (Val % (1 << shift)) { 1277 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 1278 << ": scalar reg isn't aligned " << Val; 1279 } 1280 1281 return createRegOperand(SRegClassID, Val >> shift); 1282 } 1283 1284 MCOperand AMDGPUDisassembler::createVGPR16Operand(unsigned RegIdx, 1285 bool IsHi) const { 1286 unsigned RegIdxInVGPR16 = RegIdx * 2 + (IsHi ? 1 : 0); 1287 return createRegOperand(AMDGPU::VGPR_16RegClassID, RegIdxInVGPR16); 1288 } 1289 1290 // Decode Literals for insts which always have a literal in the encoding 1291 MCOperand 1292 AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const { 1293 if (HasLiteral) { 1294 assert( 1295 AMDGPU::hasVOPD(STI) && 1296 "Should only decode multiple kimm with VOPD, check VSrc operand types"); 1297 if (Literal != Val) 1298 return errOperand(Val, "More than one unique literal is illegal"); 1299 } 1300 HasLiteral = true; 1301 Literal = Val; 1302 return MCOperand::createImm(Literal); 1303 } 1304 1305 MCOperand AMDGPUDisassembler::decodeLiteralConstant(bool ExtendFP64) const { 1306 // For now all literal constants are supposed to be unsigned integer 1307 // ToDo: deal with signed/unsigned 64-bit integer constants 1308 // ToDo: deal with float/double constants 1309 if (!HasLiteral) { 1310 if (Bytes.size() < 4) { 1311 return errOperand(0, "cannot read literal, inst bytes left " + 1312 Twine(Bytes.size())); 1313 } 1314 HasLiteral = true; 1315 Literal = Literal64 = eatBytes<uint32_t>(Bytes); 1316 if (ExtendFP64) 1317 Literal64 <<= 32; 1318 } 1319 return MCOperand::createImm(ExtendFP64 ? Literal64 : Literal); 1320 } 1321 1322 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 1323 using namespace AMDGPU::EncValues; 1324 1325 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 1326 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 1327 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 1328 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 1329 // Cast prevents negative overflow. 1330 } 1331 1332 static int64_t getInlineImmVal32(unsigned Imm) { 1333 switch (Imm) { 1334 case 240: 1335 return llvm::bit_cast<uint32_t>(0.5f); 1336 case 241: 1337 return llvm::bit_cast<uint32_t>(-0.5f); 1338 case 242: 1339 return llvm::bit_cast<uint32_t>(1.0f); 1340 case 243: 1341 return llvm::bit_cast<uint32_t>(-1.0f); 1342 case 244: 1343 return llvm::bit_cast<uint32_t>(2.0f); 1344 case 245: 1345 return llvm::bit_cast<uint32_t>(-2.0f); 1346 case 246: 1347 return llvm::bit_cast<uint32_t>(4.0f); 1348 case 247: 1349 return llvm::bit_cast<uint32_t>(-4.0f); 1350 case 248: // 1 / (2 * PI) 1351 return 0x3e22f983; 1352 default: 1353 llvm_unreachable("invalid fp inline imm"); 1354 } 1355 } 1356 1357 static int64_t getInlineImmVal64(unsigned Imm) { 1358 switch (Imm) { 1359 case 240: 1360 return llvm::bit_cast<uint64_t>(0.5); 1361 case 241: 1362 return llvm::bit_cast<uint64_t>(-0.5); 1363 case 242: 1364 return llvm::bit_cast<uint64_t>(1.0); 1365 case 243: 1366 return llvm::bit_cast<uint64_t>(-1.0); 1367 case 244: 1368 return llvm::bit_cast<uint64_t>(2.0); 1369 case 245: 1370 return llvm::bit_cast<uint64_t>(-2.0); 1371 case 246: 1372 return llvm::bit_cast<uint64_t>(4.0); 1373 case 247: 1374 return llvm::bit_cast<uint64_t>(-4.0); 1375 case 248: // 1 / (2 * PI) 1376 return 0x3fc45f306dc9c882; 1377 default: 1378 llvm_unreachable("invalid fp inline imm"); 1379 } 1380 } 1381 1382 static int64_t getInlineImmValF16(unsigned Imm) { 1383 switch (Imm) { 1384 case 240: 1385 return 0x3800; 1386 case 241: 1387 return 0xB800; 1388 case 242: 1389 return 0x3C00; 1390 case 243: 1391 return 0xBC00; 1392 case 244: 1393 return 0x4000; 1394 case 245: 1395 return 0xC000; 1396 case 246: 1397 return 0x4400; 1398 case 247: 1399 return 0xC400; 1400 case 248: // 1 / (2 * PI) 1401 return 0x3118; 1402 default: 1403 llvm_unreachable("invalid fp inline imm"); 1404 } 1405 } 1406 1407 static int64_t getInlineImmValBF16(unsigned Imm) { 1408 switch (Imm) { 1409 case 240: 1410 return 0x3F00; 1411 case 241: 1412 return 0xBF00; 1413 case 242: 1414 return 0x3F80; 1415 case 243: 1416 return 0xBF80; 1417 case 244: 1418 return 0x4000; 1419 case 245: 1420 return 0xC000; 1421 case 246: 1422 return 0x4080; 1423 case 247: 1424 return 0xC080; 1425 case 248: // 1 / (2 * PI) 1426 return 0x3E22; 1427 default: 1428 llvm_unreachable("invalid fp inline imm"); 1429 } 1430 } 1431 1432 static int64_t getInlineImmVal16(unsigned Imm, AMDGPU::OperandSemantics Sema) { 1433 return (Sema == AMDGPU::OperandSemantics::BF16) ? getInlineImmValBF16(Imm) 1434 : getInlineImmValF16(Imm); 1435 } 1436 1437 MCOperand AMDGPUDisassembler::decodeFPImmed(unsigned ImmWidth, unsigned Imm, 1438 AMDGPU::OperandSemantics Sema) { 1439 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN && 1440 Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 1441 1442 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 1443 // ImmWidth 0 is a default case where operand should not allow immediates. 1444 // Imm value is still decoded into 32 bit immediate operand, inst printer will 1445 // use it to print verbose error message. 1446 switch (ImmWidth) { 1447 case 0: 1448 case 32: 1449 return MCOperand::createImm(getInlineImmVal32(Imm)); 1450 case 64: 1451 return MCOperand::createImm(getInlineImmVal64(Imm)); 1452 case 16: 1453 return MCOperand::createImm(getInlineImmVal16(Imm, Sema)); 1454 default: 1455 llvm_unreachable("implement me"); 1456 } 1457 } 1458 1459 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 1460 using namespace AMDGPU; 1461 1462 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1463 switch (Width) { 1464 default: // fall 1465 case OPW32: 1466 case OPW16: 1467 case OPWV216: 1468 return VGPR_32RegClassID; 1469 case OPW64: 1470 case OPWV232: return VReg_64RegClassID; 1471 case OPW96: return VReg_96RegClassID; 1472 case OPW128: return VReg_128RegClassID; 1473 case OPW160: return VReg_160RegClassID; 1474 case OPW256: return VReg_256RegClassID; 1475 case OPW288: return VReg_288RegClassID; 1476 case OPW320: return VReg_320RegClassID; 1477 case OPW352: return VReg_352RegClassID; 1478 case OPW384: return VReg_384RegClassID; 1479 case OPW512: return VReg_512RegClassID; 1480 case OPW1024: return VReg_1024RegClassID; 1481 } 1482 } 1483 1484 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 1485 using namespace AMDGPU; 1486 1487 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1488 switch (Width) { 1489 default: // fall 1490 case OPW32: 1491 case OPW16: 1492 case OPWV216: 1493 return AGPR_32RegClassID; 1494 case OPW64: 1495 case OPWV232: return AReg_64RegClassID; 1496 case OPW96: return AReg_96RegClassID; 1497 case OPW128: return AReg_128RegClassID; 1498 case OPW160: return AReg_160RegClassID; 1499 case OPW256: return AReg_256RegClassID; 1500 case OPW288: return AReg_288RegClassID; 1501 case OPW320: return AReg_320RegClassID; 1502 case OPW352: return AReg_352RegClassID; 1503 case OPW384: return AReg_384RegClassID; 1504 case OPW512: return AReg_512RegClassID; 1505 case OPW1024: return AReg_1024RegClassID; 1506 } 1507 } 1508 1509 1510 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 1511 using namespace AMDGPU; 1512 1513 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1514 switch (Width) { 1515 default: // fall 1516 case OPW32: 1517 case OPW16: 1518 case OPWV216: 1519 return SGPR_32RegClassID; 1520 case OPW64: 1521 case OPWV232: return SGPR_64RegClassID; 1522 case OPW96: return SGPR_96RegClassID; 1523 case OPW128: return SGPR_128RegClassID; 1524 case OPW160: return SGPR_160RegClassID; 1525 case OPW256: return SGPR_256RegClassID; 1526 case OPW288: return SGPR_288RegClassID; 1527 case OPW320: return SGPR_320RegClassID; 1528 case OPW352: return SGPR_352RegClassID; 1529 case OPW384: return SGPR_384RegClassID; 1530 case OPW512: return SGPR_512RegClassID; 1531 } 1532 } 1533 1534 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 1535 using namespace AMDGPU; 1536 1537 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1538 switch (Width) { 1539 default: // fall 1540 case OPW32: 1541 case OPW16: 1542 case OPWV216: 1543 return TTMP_32RegClassID; 1544 case OPW64: 1545 case OPWV232: return TTMP_64RegClassID; 1546 case OPW128: return TTMP_128RegClassID; 1547 case OPW256: return TTMP_256RegClassID; 1548 case OPW288: return TTMP_288RegClassID; 1549 case OPW320: return TTMP_320RegClassID; 1550 case OPW352: return TTMP_352RegClassID; 1551 case OPW384: return TTMP_384RegClassID; 1552 case OPW512: return TTMP_512RegClassID; 1553 } 1554 } 1555 1556 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 1557 using namespace AMDGPU::EncValues; 1558 1559 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN; 1560 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX; 1561 1562 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1563 } 1564 1565 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val, 1566 bool MandatoryLiteral, 1567 unsigned ImmWidth, 1568 AMDGPU::OperandSemantics Sema) const { 1569 using namespace AMDGPU::EncValues; 1570 1571 assert(Val < 1024); // enum10 1572 1573 bool IsAGPR = Val & 512; 1574 Val &= 511; 1575 1576 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1577 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1578 : getVgprClassId(Width), Val - VGPR_MIN); 1579 } 1580 return decodeNonVGPRSrcOp(Width, Val & 0xFF, MandatoryLiteral, ImmWidth, 1581 Sema); 1582 } 1583 1584 MCOperand 1585 AMDGPUDisassembler::decodeNonVGPRSrcOp(const OpWidthTy Width, unsigned Val, 1586 bool MandatoryLiteral, unsigned ImmWidth, 1587 AMDGPU::OperandSemantics Sema) const { 1588 // Cases when Val{8} is 1 (vgpr, agpr or true 16 vgpr) should have been 1589 // decoded earlier. 1590 assert(Val < (1 << 8) && "9-bit Src encoding when Val{8} is 0"); 1591 using namespace AMDGPU::EncValues; 1592 1593 if (Val <= SGPR_MAX) { 1594 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1595 static_assert(SGPR_MIN == 0); 1596 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1597 } 1598 1599 int TTmpIdx = getTTmpIdx(Val); 1600 if (TTmpIdx >= 0) { 1601 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1602 } 1603 1604 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1605 return decodeIntImmed(Val); 1606 1607 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1608 return decodeFPImmed(ImmWidth, Val, Sema); 1609 1610 if (Val == LITERAL_CONST) { 1611 if (MandatoryLiteral) 1612 // Keep a sentinel value for deferred setting 1613 return MCOperand::createImm(LITERAL_CONST); 1614 else 1615 return decodeLiteralConstant(Sema == AMDGPU::OperandSemantics::FP64); 1616 } 1617 1618 switch (Width) { 1619 case OPW32: 1620 case OPW16: 1621 case OPWV216: 1622 return decodeSpecialReg32(Val); 1623 case OPW64: 1624 case OPWV232: 1625 return decodeSpecialReg64(Val); 1626 default: 1627 llvm_unreachable("unexpected immediate type"); 1628 } 1629 } 1630 1631 // Bit 0 of DstY isn't stored in the instruction, because it's always the 1632 // opposite of bit 0 of DstX. 1633 MCOperand AMDGPUDisassembler::decodeVOPDDstYOp(MCInst &Inst, 1634 unsigned Val) const { 1635 int VDstXInd = 1636 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::vdstX); 1637 assert(VDstXInd != -1); 1638 assert(Inst.getOperand(VDstXInd).isReg()); 1639 unsigned XDstReg = MRI.getEncodingValue(Inst.getOperand(VDstXInd).getReg()); 1640 Val |= ~XDstReg & 1; 1641 auto Width = llvm::AMDGPUDisassembler::OPW32; 1642 return createRegOperand(getVgprClassId(Width), Val); 1643 } 1644 1645 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1646 using namespace AMDGPU; 1647 1648 switch (Val) { 1649 // clang-format off 1650 case 102: return createRegOperand(FLAT_SCR_LO); 1651 case 103: return createRegOperand(FLAT_SCR_HI); 1652 case 104: return createRegOperand(XNACK_MASK_LO); 1653 case 105: return createRegOperand(XNACK_MASK_HI); 1654 case 106: return createRegOperand(VCC_LO); 1655 case 107: return createRegOperand(VCC_HI); 1656 case 108: return createRegOperand(TBA_LO); 1657 case 109: return createRegOperand(TBA_HI); 1658 case 110: return createRegOperand(TMA_LO); 1659 case 111: return createRegOperand(TMA_HI); 1660 case 124: 1661 return isGFX11Plus() ? createRegOperand(SGPR_NULL) : createRegOperand(M0); 1662 case 125: 1663 return isGFX11Plus() ? createRegOperand(M0) : createRegOperand(SGPR_NULL); 1664 case 126: return createRegOperand(EXEC_LO); 1665 case 127: return createRegOperand(EXEC_HI); 1666 case 235: return createRegOperand(SRC_SHARED_BASE_LO); 1667 case 236: return createRegOperand(SRC_SHARED_LIMIT_LO); 1668 case 237: return createRegOperand(SRC_PRIVATE_BASE_LO); 1669 case 238: return createRegOperand(SRC_PRIVATE_LIMIT_LO); 1670 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1671 case 251: return createRegOperand(SRC_VCCZ); 1672 case 252: return createRegOperand(SRC_EXECZ); 1673 case 253: return createRegOperand(SRC_SCC); 1674 case 254: return createRegOperand(LDS_DIRECT); 1675 default: break; 1676 // clang-format on 1677 } 1678 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1679 } 1680 1681 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1682 using namespace AMDGPU; 1683 1684 switch (Val) { 1685 case 102: return createRegOperand(FLAT_SCR); 1686 case 104: return createRegOperand(XNACK_MASK); 1687 case 106: return createRegOperand(VCC); 1688 case 108: return createRegOperand(TBA); 1689 case 110: return createRegOperand(TMA); 1690 case 124: 1691 if (isGFX11Plus()) 1692 return createRegOperand(SGPR_NULL); 1693 break; 1694 case 125: 1695 if (!isGFX11Plus()) 1696 return createRegOperand(SGPR_NULL); 1697 break; 1698 case 126: return createRegOperand(EXEC); 1699 case 235: return createRegOperand(SRC_SHARED_BASE); 1700 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1701 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1702 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1703 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1704 case 251: return createRegOperand(SRC_VCCZ); 1705 case 252: return createRegOperand(SRC_EXECZ); 1706 case 253: return createRegOperand(SRC_SCC); 1707 default: break; 1708 } 1709 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1710 } 1711 1712 MCOperand 1713 AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, const unsigned Val, 1714 unsigned ImmWidth, 1715 AMDGPU::OperandSemantics Sema) const { 1716 using namespace AMDGPU::SDWA; 1717 using namespace AMDGPU::EncValues; 1718 1719 if (STI.hasFeature(AMDGPU::FeatureGFX9) || 1720 STI.hasFeature(AMDGPU::FeatureGFX10)) { 1721 // XXX: cast to int is needed to avoid stupid warning: 1722 // compare with unsigned is always true 1723 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1724 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1725 return createRegOperand(getVgprClassId(Width), 1726 Val - SDWA9EncValues::SRC_VGPR_MIN); 1727 } 1728 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1729 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1730 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1731 return createSRegOperand(getSgprClassId(Width), 1732 Val - SDWA9EncValues::SRC_SGPR_MIN); 1733 } 1734 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1735 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1736 return createSRegOperand(getTtmpClassId(Width), 1737 Val - SDWA9EncValues::SRC_TTMP_MIN); 1738 } 1739 1740 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1741 1742 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1743 return decodeIntImmed(SVal); 1744 1745 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1746 return decodeFPImmed(ImmWidth, SVal, Sema); 1747 1748 return decodeSpecialReg32(SVal); 1749 } else if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) { 1750 return createRegOperand(getVgprClassId(Width), Val); 1751 } 1752 llvm_unreachable("unsupported target"); 1753 } 1754 1755 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1756 return decodeSDWASrc(OPW16, Val, 16, AMDGPU::OperandSemantics::FP16); 1757 } 1758 1759 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1760 return decodeSDWASrc(OPW32, Val, 32, AMDGPU::OperandSemantics::FP32); 1761 } 1762 1763 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1764 using namespace AMDGPU::SDWA; 1765 1766 assert((STI.hasFeature(AMDGPU::FeatureGFX9) || 1767 STI.hasFeature(AMDGPU::FeatureGFX10)) && 1768 "SDWAVopcDst should be present only on GFX9+"); 1769 1770 bool IsWave64 = STI.hasFeature(AMDGPU::FeatureWavefrontSize64); 1771 1772 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1773 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1774 1775 int TTmpIdx = getTTmpIdx(Val); 1776 if (TTmpIdx >= 0) { 1777 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1778 return createSRegOperand(TTmpClsId, TTmpIdx); 1779 } else if (Val > SGPR_MAX) { 1780 return IsWave64 ? decodeSpecialReg64(Val) 1781 : decodeSpecialReg32(Val); 1782 } else { 1783 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1784 } 1785 } else { 1786 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1787 } 1788 } 1789 1790 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1791 return STI.hasFeature(AMDGPU::FeatureWavefrontSize64) 1792 ? decodeSrcOp(OPW64, Val) 1793 : decodeSrcOp(OPW32, Val); 1794 } 1795 1796 MCOperand AMDGPUDisassembler::decodeSplitBarrier(unsigned Val) const { 1797 return decodeSrcOp(OPW32, Val); 1798 } 1799 1800 MCOperand AMDGPUDisassembler::decodeDpp8FI(unsigned Val) const { 1801 if (Val != AMDGPU::DPP::DPP8_FI_0 && Val != AMDGPU::DPP::DPP8_FI_1) 1802 return MCOperand(); 1803 return MCOperand::createImm(Val); 1804 } 1805 1806 bool AMDGPUDisassembler::isVI() const { 1807 return STI.hasFeature(AMDGPU::FeatureVolcanicIslands); 1808 } 1809 1810 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } 1811 1812 bool AMDGPUDisassembler::isGFX90A() const { 1813 return STI.hasFeature(AMDGPU::FeatureGFX90AInsts); 1814 } 1815 1816 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } 1817 1818 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } 1819 1820 bool AMDGPUDisassembler::isGFX10Plus() const { 1821 return AMDGPU::isGFX10Plus(STI); 1822 } 1823 1824 bool AMDGPUDisassembler::isGFX11() const { 1825 return STI.hasFeature(AMDGPU::FeatureGFX11); 1826 } 1827 1828 bool AMDGPUDisassembler::isGFX11Plus() const { 1829 return AMDGPU::isGFX11Plus(STI); 1830 } 1831 1832 bool AMDGPUDisassembler::isGFX12Plus() const { 1833 return AMDGPU::isGFX12Plus(STI); 1834 } 1835 1836 bool AMDGPUDisassembler::hasArchitectedFlatScratch() const { 1837 return STI.hasFeature(AMDGPU::FeatureArchitectedFlatScratch); 1838 } 1839 1840 bool AMDGPUDisassembler::hasKernargPreload() const { 1841 return AMDGPU::hasKernargPreload(STI); 1842 } 1843 1844 //===----------------------------------------------------------------------===// 1845 // AMDGPU specific symbol handling 1846 //===----------------------------------------------------------------------===// 1847 #define GET_FIELD(MASK) (AMDHSA_BITS_GET(FourByteBuffer, MASK)) 1848 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1849 do { \ 1850 KdStream << Indent << DIRECTIVE " " << GET_FIELD(MASK) << '\n'; \ 1851 } while (0) 1852 #define PRINT_PSEUDO_DIRECTIVE_COMMENT(DIRECTIVE, MASK) \ 1853 do { \ 1854 KdStream << Indent << MAI.getCommentString() << ' ' << DIRECTIVE " " \ 1855 << GET_FIELD(MASK) << '\n'; \ 1856 } while (0) 1857 1858 // NOLINTNEXTLINE(readability-identifier-naming) 1859 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1860 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1861 using namespace amdhsa; 1862 StringRef Indent = "\t"; 1863 1864 // We cannot accurately backward compute #VGPRs used from 1865 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1866 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1867 // simply calculate the inverse of what the assembler does. 1868 1869 uint32_t GranulatedWorkitemVGPRCount = 1870 GET_FIELD(COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT); 1871 1872 uint32_t NextFreeVGPR = 1873 (GranulatedWorkitemVGPRCount + 1) * 1874 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI, EnableWavefrontSize32); 1875 1876 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1877 1878 // We cannot backward compute values used to calculate 1879 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1880 // directives can't be computed: 1881 // .amdhsa_reserve_vcc 1882 // .amdhsa_reserve_flat_scratch 1883 // .amdhsa_reserve_xnack_mask 1884 // They take their respective default values if not specified in the assembly. 1885 // 1886 // GRANULATED_WAVEFRONT_SGPR_COUNT 1887 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1888 // 1889 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1890 // are set to 0. So while disassembling we consider that: 1891 // 1892 // GRANULATED_WAVEFRONT_SGPR_COUNT 1893 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1894 // 1895 // The disassembler cannot recover the original values of those 3 directives. 1896 1897 uint32_t GranulatedWavefrontSGPRCount = 1898 GET_FIELD(COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT); 1899 1900 if (isGFX10Plus() && GranulatedWavefrontSGPRCount) 1901 return MCDisassembler::Fail; 1902 1903 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1904 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1905 1906 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1907 if (!hasArchitectedFlatScratch()) 1908 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1909 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1910 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1911 1912 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY) 1913 return MCDisassembler::Fail; 1914 1915 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1916 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1917 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1918 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1919 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1920 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1921 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1922 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1923 1924 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) 1925 return MCDisassembler::Fail; 1926 1927 if (!isGFX12Plus()) 1928 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", 1929 COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP); 1930 1931 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) 1932 return MCDisassembler::Fail; 1933 1934 if (!isGFX12Plus()) 1935 PRINT_DIRECTIVE(".amdhsa_ieee_mode", 1936 COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE); 1937 1938 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) 1939 return MCDisassembler::Fail; 1940 1941 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER) 1942 return MCDisassembler::Fail; 1943 1944 if (isGFX9Plus()) 1945 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL); 1946 1947 if (!isGFX9Plus()) 1948 if (FourByteBuffer & COMPUTE_PGM_RSRC1_GFX6_GFX8_RESERVED0) 1949 return MCDisassembler::Fail; 1950 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED1) 1951 return MCDisassembler::Fail; 1952 if (!isGFX10Plus()) 1953 if (FourByteBuffer & COMPUTE_PGM_RSRC1_GFX6_GFX9_RESERVED2) 1954 return MCDisassembler::Fail; 1955 1956 if (isGFX10Plus()) { 1957 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1958 COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE); 1959 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED); 1960 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS); 1961 } 1962 1963 if (isGFX12Plus()) 1964 PRINT_DIRECTIVE(".amdhsa_round_robin_scheduling", 1965 COMPUTE_PGM_RSRC1_GFX12_PLUS_ENABLE_WG_RR_EN); 1966 1967 return MCDisassembler::Success; 1968 } 1969 1970 // NOLINTNEXTLINE(readability-identifier-naming) 1971 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 1972 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1973 using namespace amdhsa; 1974 StringRef Indent = "\t"; 1975 if (hasArchitectedFlatScratch()) 1976 PRINT_DIRECTIVE(".amdhsa_enable_private_segment", 1977 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1978 else 1979 PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset", 1980 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1981 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 1982 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 1983 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 1984 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 1985 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 1986 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 1987 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 1988 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 1989 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 1990 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 1991 1992 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH) 1993 return MCDisassembler::Fail; 1994 1995 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY) 1996 return MCDisassembler::Fail; 1997 1998 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE) 1999 return MCDisassembler::Fail; 2000 2001 PRINT_DIRECTIVE( 2002 ".amdhsa_exception_fp_ieee_invalid_op", 2003 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 2004 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 2005 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 2006 PRINT_DIRECTIVE( 2007 ".amdhsa_exception_fp_ieee_div_zero", 2008 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 2009 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 2010 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 2011 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 2012 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 2013 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 2014 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 2015 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 2016 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 2017 2018 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0) 2019 return MCDisassembler::Fail; 2020 2021 return MCDisassembler::Success; 2022 } 2023 2024 // NOLINTNEXTLINE(readability-identifier-naming) 2025 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC3( 2026 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 2027 using namespace amdhsa; 2028 StringRef Indent = "\t"; 2029 if (isGFX90A()) { 2030 KdStream << Indent << ".amdhsa_accum_offset " 2031 << (GET_FIELD(COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET) + 1) * 4 2032 << '\n'; 2033 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX90A_RESERVED0) 2034 return MCDisassembler::Fail; 2035 PRINT_DIRECTIVE(".amdhsa_tg_split", COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT); 2036 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX90A_RESERVED1) 2037 return MCDisassembler::Fail; 2038 } else if (isGFX10Plus()) { 2039 // Bits [0-3]. 2040 if (!isGFX12Plus()) { 2041 if (!EnableWavefrontSize32 || !*EnableWavefrontSize32) { 2042 PRINT_DIRECTIVE(".amdhsa_shared_vgpr_count", 2043 COMPUTE_PGM_RSRC3_GFX10_GFX11_SHARED_VGPR_COUNT); 2044 } else { 2045 PRINT_PSEUDO_DIRECTIVE_COMMENT( 2046 "SHARED_VGPR_COUNT", 2047 COMPUTE_PGM_RSRC3_GFX10_GFX11_SHARED_VGPR_COUNT); 2048 } 2049 } else { 2050 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX12_PLUS_RESERVED0) 2051 return MCDisassembler::Fail; 2052 } 2053 2054 // Bits [4-11]. 2055 if (isGFX11()) { 2056 PRINT_PSEUDO_DIRECTIVE_COMMENT("INST_PREF_SIZE", 2057 COMPUTE_PGM_RSRC3_GFX11_INST_PREF_SIZE); 2058 PRINT_PSEUDO_DIRECTIVE_COMMENT("TRAP_ON_START", 2059 COMPUTE_PGM_RSRC3_GFX11_TRAP_ON_START); 2060 PRINT_PSEUDO_DIRECTIVE_COMMENT("TRAP_ON_END", 2061 COMPUTE_PGM_RSRC3_GFX11_TRAP_ON_END); 2062 } else if (isGFX12Plus()) { 2063 PRINT_PSEUDO_DIRECTIVE_COMMENT( 2064 "INST_PREF_SIZE", COMPUTE_PGM_RSRC3_GFX12_PLUS_INST_PREF_SIZE); 2065 } else { 2066 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_RESERVED1) 2067 return MCDisassembler::Fail; 2068 } 2069 2070 // Bits [12]. 2071 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_PLUS_RESERVED2) 2072 return MCDisassembler::Fail; 2073 2074 // Bits [13]. 2075 if (isGFX12Plus()) { 2076 PRINT_PSEUDO_DIRECTIVE_COMMENT("GLG_EN", 2077 COMPUTE_PGM_RSRC3_GFX12_PLUS_GLG_EN); 2078 } else { 2079 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_GFX11_RESERVED3) 2080 return MCDisassembler::Fail; 2081 } 2082 2083 // Bits [14-30]. 2084 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_PLUS_RESERVED4) 2085 return MCDisassembler::Fail; 2086 2087 // Bits [31]. 2088 if (isGFX11Plus()) { 2089 PRINT_PSEUDO_DIRECTIVE_COMMENT("IMAGE_OP", 2090 COMPUTE_PGM_RSRC3_GFX11_PLUS_IMAGE_OP); 2091 } else { 2092 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_RESERVED5) 2093 return MCDisassembler::Fail; 2094 } 2095 } else if (FourByteBuffer) { 2096 return MCDisassembler::Fail; 2097 } 2098 return MCDisassembler::Success; 2099 } 2100 #undef PRINT_PSEUDO_DIRECTIVE_COMMENT 2101 #undef PRINT_DIRECTIVE 2102 #undef GET_FIELD 2103 2104 MCDisassembler::DecodeStatus 2105 AMDGPUDisassembler::decodeKernelDescriptorDirective( 2106 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 2107 raw_string_ostream &KdStream) const { 2108 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 2109 do { \ 2110 KdStream << Indent << DIRECTIVE " " \ 2111 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 2112 } while (0) 2113 2114 uint16_t TwoByteBuffer = 0; 2115 uint32_t FourByteBuffer = 0; 2116 2117 StringRef ReservedBytes; 2118 StringRef Indent = "\t"; 2119 2120 assert(Bytes.size() == 64); 2121 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 2122 2123 switch (Cursor.tell()) { 2124 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 2125 FourByteBuffer = DE.getU32(Cursor); 2126 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 2127 << '\n'; 2128 return MCDisassembler::Success; 2129 2130 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 2131 FourByteBuffer = DE.getU32(Cursor); 2132 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 2133 << FourByteBuffer << '\n'; 2134 return MCDisassembler::Success; 2135 2136 case amdhsa::KERNARG_SIZE_OFFSET: 2137 FourByteBuffer = DE.getU32(Cursor); 2138 KdStream << Indent << ".amdhsa_kernarg_size " 2139 << FourByteBuffer << '\n'; 2140 return MCDisassembler::Success; 2141 2142 case amdhsa::RESERVED0_OFFSET: 2143 // 4 reserved bytes, must be 0. 2144 ReservedBytes = DE.getBytes(Cursor, 4); 2145 for (int I = 0; I < 4; ++I) { 2146 if (ReservedBytes[I] != 0) { 2147 return MCDisassembler::Fail; 2148 } 2149 } 2150 return MCDisassembler::Success; 2151 2152 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 2153 // KERNEL_CODE_ENTRY_BYTE_OFFSET 2154 // So far no directive controls this for Code Object V3, so simply skip for 2155 // disassembly. 2156 DE.skip(Cursor, 8); 2157 return MCDisassembler::Success; 2158 2159 case amdhsa::RESERVED1_OFFSET: 2160 // 20 reserved bytes, must be 0. 2161 ReservedBytes = DE.getBytes(Cursor, 20); 2162 for (int I = 0; I < 20; ++I) { 2163 if (ReservedBytes[I] != 0) { 2164 return MCDisassembler::Fail; 2165 } 2166 } 2167 return MCDisassembler::Success; 2168 2169 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 2170 FourByteBuffer = DE.getU32(Cursor); 2171 return decodeCOMPUTE_PGM_RSRC3(FourByteBuffer, KdStream); 2172 2173 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 2174 FourByteBuffer = DE.getU32(Cursor); 2175 return decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream); 2176 2177 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 2178 FourByteBuffer = DE.getU32(Cursor); 2179 return decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream); 2180 2181 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 2182 using namespace amdhsa; 2183 TwoByteBuffer = DE.getU16(Cursor); 2184 2185 if (!hasArchitectedFlatScratch()) 2186 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 2187 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 2188 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 2189 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 2190 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 2191 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 2192 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 2193 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 2194 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 2195 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 2196 if (!hasArchitectedFlatScratch()) 2197 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 2198 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 2199 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 2200 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 2201 2202 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 2203 return MCDisassembler::Fail; 2204 2205 // Reserved for GFX9 2206 if (isGFX9() && 2207 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 2208 return MCDisassembler::Fail; 2209 } else if (isGFX10Plus()) { 2210 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 2211 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 2212 } 2213 2214 if (CodeObjectVersion >= AMDGPU::AMDHSA_COV5) 2215 PRINT_DIRECTIVE(".amdhsa_uses_dynamic_stack", 2216 KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK); 2217 2218 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) 2219 return MCDisassembler::Fail; 2220 2221 return MCDisassembler::Success; 2222 2223 case amdhsa::KERNARG_PRELOAD_OFFSET: 2224 using namespace amdhsa; 2225 TwoByteBuffer = DE.getU16(Cursor); 2226 if (TwoByteBuffer & KERNARG_PRELOAD_SPEC_LENGTH) { 2227 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_preload_length", 2228 KERNARG_PRELOAD_SPEC_LENGTH); 2229 } 2230 2231 if (TwoByteBuffer & KERNARG_PRELOAD_SPEC_OFFSET) { 2232 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_preload_offset", 2233 KERNARG_PRELOAD_SPEC_OFFSET); 2234 } 2235 return MCDisassembler::Success; 2236 2237 case amdhsa::RESERVED3_OFFSET: 2238 // 4 bytes from here are reserved, must be 0. 2239 ReservedBytes = DE.getBytes(Cursor, 4); 2240 for (int I = 0; I < 4; ++I) { 2241 if (ReservedBytes[I] != 0) 2242 return MCDisassembler::Fail; 2243 } 2244 return MCDisassembler::Success; 2245 2246 default: 2247 llvm_unreachable("Unhandled index. Case statements cover everything."); 2248 return MCDisassembler::Fail; 2249 } 2250 #undef PRINT_DIRECTIVE 2251 } 2252 2253 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( 2254 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 2255 // CP microcode requires the kernel descriptor to be 64 aligned. 2256 if (Bytes.size() != 64 || KdAddress % 64 != 0) 2257 return MCDisassembler::Fail; 2258 2259 // FIXME: We can't actually decode "in order" as is done below, as e.g. GFX10 2260 // requires us to know the setting of .amdhsa_wavefront_size32 in order to 2261 // accurately produce .amdhsa_next_free_vgpr, and they appear in the wrong 2262 // order. Workaround this by first looking up .amdhsa_wavefront_size32 here 2263 // when required. 2264 if (isGFX10Plus()) { 2265 uint16_t KernelCodeProperties = 2266 support::endian::read16(&Bytes[amdhsa::KERNEL_CODE_PROPERTIES_OFFSET], 2267 llvm::endianness::little); 2268 EnableWavefrontSize32 = 2269 AMDHSA_BITS_GET(KernelCodeProperties, 2270 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 2271 } 2272 2273 std::string Kd; 2274 raw_string_ostream KdStream(Kd); 2275 KdStream << ".amdhsa_kernel " << KdName << '\n'; 2276 2277 DataExtractor::Cursor C(0); 2278 while (C && C.tell() < Bytes.size()) { 2279 MCDisassembler::DecodeStatus Status = 2280 decodeKernelDescriptorDirective(C, Bytes, KdStream); 2281 2282 cantFail(C.takeError()); 2283 2284 if (Status == MCDisassembler::Fail) 2285 return MCDisassembler::Fail; 2286 } 2287 KdStream << ".end_amdhsa_kernel\n"; 2288 outs() << KdStream.str(); 2289 return MCDisassembler::Success; 2290 } 2291 2292 std::optional<MCDisassembler::DecodeStatus> 2293 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 2294 ArrayRef<uint8_t> Bytes, uint64_t Address, 2295 raw_ostream &CStream) const { 2296 // Right now only kernel descriptor needs to be handled. 2297 // We ignore all other symbols for target specific handling. 2298 // TODO: 2299 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 2300 // Object V2 and V3 when symbols are marked protected. 2301 2302 // amd_kernel_code_t for Code Object V2. 2303 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 2304 Size = 256; 2305 return MCDisassembler::Fail; 2306 } 2307 2308 // Code Object V3 kernel descriptors. 2309 StringRef Name = Symbol.Name; 2310 if (Symbol.Type == ELF::STT_OBJECT && Name.ends_with(StringRef(".kd"))) { 2311 Size = 64; // Size = 64 regardless of success or failure. 2312 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 2313 } 2314 return std::nullopt; 2315 } 2316 2317 //===----------------------------------------------------------------------===// 2318 // AMDGPUSymbolizer 2319 //===----------------------------------------------------------------------===// 2320 2321 // Try to find symbol name for specified label 2322 bool AMDGPUSymbolizer::tryAddingSymbolicOperand( 2323 MCInst &Inst, raw_ostream & /*cStream*/, int64_t Value, 2324 uint64_t /*Address*/, bool IsBranch, uint64_t /*Offset*/, 2325 uint64_t /*OpSize*/, uint64_t /*InstSize*/) { 2326 2327 if (!IsBranch) { 2328 return false; 2329 } 2330 2331 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 2332 if (!Symbols) 2333 return false; 2334 2335 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { 2336 return Val.Addr == static_cast<uint64_t>(Value) && 2337 Val.Type == ELF::STT_NOTYPE; 2338 }); 2339 if (Result != Symbols->end()) { 2340 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 2341 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 2342 Inst.addOperand(MCOperand::createExpr(Add)); 2343 return true; 2344 } 2345 // Add to list of referenced addresses, so caller can synthesize a label. 2346 ReferencedAddresses.push_back(static_cast<uint64_t>(Value)); 2347 return false; 2348 } 2349 2350 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 2351 int64_t Value, 2352 uint64_t Address) { 2353 llvm_unreachable("unimplemented"); 2354 } 2355 2356 //===----------------------------------------------------------------------===// 2357 // Initialization 2358 //===----------------------------------------------------------------------===// 2359 2360 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 2361 LLVMOpInfoCallback /*GetOpInfo*/, 2362 LLVMSymbolLookupCallback /*SymbolLookUp*/, 2363 void *DisInfo, 2364 MCContext *Ctx, 2365 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 2366 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 2367 } 2368 2369 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 2370 const MCSubtargetInfo &STI, 2371 MCContext &Ctx) { 2372 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 2373 } 2374 2375 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 2376 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 2377 createAMDGPUDisassembler); 2378 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 2379 createAMDGPUSymbolizer); 2380 } 2381