1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "SIDefines.h" 22 #include "SIRegisterInfo.h" 23 #include "TargetInfo/AMDGPUTargetInfo.h" 24 #include "Utils/AMDGPUAsmUtils.h" 25 #include "Utils/AMDGPUBaseInfo.h" 26 #include "llvm-c/DisassemblerTypes.h" 27 #include "llvm/BinaryFormat/ELF.h" 28 #include "llvm/MC/MCAsmInfo.h" 29 #include "llvm/MC/MCContext.h" 30 #include "llvm/MC/MCDecoderOps.h" 31 #include "llvm/MC/MCExpr.h" 32 #include "llvm/MC/MCInstrDesc.h" 33 #include "llvm/MC/MCRegisterInfo.h" 34 #include "llvm/MC/MCSubtargetInfo.h" 35 #include "llvm/MC/TargetRegistry.h" 36 #include "llvm/Support/AMDHSAKernelDescriptor.h" 37 38 using namespace llvm; 39 40 #define DEBUG_TYPE "amdgpu-disassembler" 41 42 #define SGPR_MAX \ 43 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 44 : AMDGPU::EncValues::SGPR_MAX_SI) 45 46 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 47 48 static const MCSubtargetInfo &addDefaultWaveSize(const MCSubtargetInfo &STI, 49 MCContext &Ctx) { 50 if (!STI.hasFeature(AMDGPU::FeatureWavefrontSize64) && 51 !STI.hasFeature(AMDGPU::FeatureWavefrontSize32)) { 52 MCSubtargetInfo &STICopy = Ctx.getSubtargetCopy(STI); 53 // If there is no default wave size it must be a generation before gfx10, 54 // these have FeatureWavefrontSize64 in their definition already. For gfx10+ 55 // set wave32 as a default. 56 STICopy.ToggleFeature(AMDGPU::FeatureWavefrontSize32); 57 return STICopy; 58 } 59 60 return STI; 61 } 62 63 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 64 MCContext &Ctx, MCInstrInfo const *MCII) 65 : MCDisassembler(addDefaultWaveSize(STI, Ctx), Ctx), MCII(MCII), 66 MRI(*Ctx.getRegisterInfo()), MAI(*Ctx.getAsmInfo()), 67 TargetMaxInstBytes(MAI.getMaxInstLength(&STI)), 68 CodeObjectVersion(AMDGPU::getDefaultAMDHSACodeObjectVersion()) { 69 // ToDo: AMDGPUDisassembler supports only VI ISA. 70 if (!STI.hasFeature(AMDGPU::FeatureGCN3Encoding) && !isGFX10Plus()) 71 report_fatal_error("Disassembly not yet supported for subtarget"); 72 73 for (auto [Symbol, Code] : AMDGPU::UCVersion::getGFXVersions()) 74 createConstantSymbolExpr(Symbol, Code); 75 76 UCVersionW64Expr = createConstantSymbolExpr("UC_VERSION_W64_BIT", 0x2000); 77 UCVersionW32Expr = createConstantSymbolExpr("UC_VERSION_W32_BIT", 0x4000); 78 UCVersionMDPExpr = createConstantSymbolExpr("UC_VERSION_MDP_BIT", 0x8000); 79 } 80 81 void AMDGPUDisassembler::setABIVersion(unsigned Version) { 82 CodeObjectVersion = AMDGPU::getAMDHSACodeObjectVersion(Version); 83 } 84 85 inline static MCDisassembler::DecodeStatus 86 addOperand(MCInst &Inst, const MCOperand& Opnd) { 87 Inst.addOperand(Opnd); 88 return Opnd.isValid() ? 89 MCDisassembler::Success : 90 MCDisassembler::Fail; 91 } 92 93 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 94 uint16_t NameIdx) { 95 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 96 if (OpIdx != -1) { 97 auto *I = MI.begin(); 98 std::advance(I, OpIdx); 99 MI.insert(I, Op); 100 } 101 return OpIdx; 102 } 103 104 static DecodeStatus decodeSOPPBrTarget(MCInst &Inst, unsigned Imm, 105 uint64_t Addr, 106 const MCDisassembler *Decoder) { 107 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 108 109 // Our branches take a simm16. 110 int64_t Offset = SignExtend64<16>(Imm) * 4 + 4 + Addr; 111 112 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2, 0)) 113 return MCDisassembler::Success; 114 return addOperand(Inst, MCOperand::createImm(Imm)); 115 } 116 117 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, 118 const MCDisassembler *Decoder) { 119 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 120 int64_t Offset; 121 if (DAsm->isGFX12Plus()) { // GFX12 supports 24-bit signed offsets. 122 Offset = SignExtend64<24>(Imm); 123 } else if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 124 Offset = Imm & 0xFFFFF; 125 } else { // GFX9+ supports 21-bit signed offsets. 126 Offset = SignExtend64<21>(Imm); 127 } 128 return addOperand(Inst, MCOperand::createImm(Offset)); 129 } 130 131 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, 132 const MCDisassembler *Decoder) { 133 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 134 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 135 } 136 137 static DecodeStatus decodeSplitBarrier(MCInst &Inst, unsigned Val, 138 uint64_t Addr, 139 const MCDisassembler *Decoder) { 140 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 141 return addOperand(Inst, DAsm->decodeSplitBarrier(Val)); 142 } 143 144 static DecodeStatus decodeDpp8FI(MCInst &Inst, unsigned Val, uint64_t Addr, 145 const MCDisassembler *Decoder) { 146 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 147 return addOperand(Inst, DAsm->decodeDpp8FI(Val)); 148 } 149 150 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 151 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \ 152 uint64_t /*Addr*/, \ 153 const MCDisassembler *Decoder) { \ 154 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 155 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 156 } 157 158 // Decoder for registers, decode directly using RegClassID. Imm(8-bit) is 159 // number of register. Used by VGPR only and AGPR only operands. 160 #define DECODE_OPERAND_REG_8(RegClass) \ 161 static DecodeStatus Decode##RegClass##RegisterClass( \ 162 MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \ 163 const MCDisassembler *Decoder) { \ 164 assert(Imm < (1 << 8) && "8-bit encoding"); \ 165 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 166 return addOperand( \ 167 Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm)); \ 168 } 169 170 #define DECODE_SrcOp(Name, EncSize, OpWidth, EncImm, MandatoryLiteral, \ 171 ImmWidth) \ 172 static DecodeStatus Name(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \ 173 const MCDisassembler *Decoder) { \ 174 assert(Imm < (1 << EncSize) && #EncSize "-bit encoding"); \ 175 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 176 return addOperand(Inst, \ 177 DAsm->decodeSrcOp(AMDGPUDisassembler::OpWidth, EncImm, \ 178 MandatoryLiteral, ImmWidth)); \ 179 } 180 181 static DecodeStatus decodeSrcOp(MCInst &Inst, unsigned EncSize, 182 AMDGPUDisassembler::OpWidthTy OpWidth, 183 unsigned Imm, unsigned EncImm, 184 bool MandatoryLiteral, unsigned ImmWidth, 185 AMDGPU::OperandSemantics Sema, 186 const MCDisassembler *Decoder) { 187 assert(Imm < (1U << EncSize) && "Operand doesn't fit encoding!"); 188 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 189 return addOperand(Inst, DAsm->decodeSrcOp(OpWidth, EncImm, MandatoryLiteral, 190 ImmWidth, Sema)); 191 } 192 193 // Decoder for registers. Imm(7-bit) is number of register, uses decodeSrcOp to 194 // get register class. Used by SGPR only operands. 195 #define DECODE_OPERAND_REG_7(RegClass, OpWidth) \ 196 DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0) 197 198 // Decoder for registers. Imm(10-bit): Imm{7-0} is number of register, 199 // Imm{9} is acc(agpr or vgpr) Imm{8} should be 0 (see VOP3Pe_SMFMAC). 200 // Set Imm{8} to 1 (IS_VGPR) to decode using 'enum10' from decodeSrcOp. 201 // Used by AV_ register classes (AGPR or VGPR only register operands). 202 template <AMDGPUDisassembler::OpWidthTy OpWidth> 203 static DecodeStatus decodeAV10(MCInst &Inst, unsigned Imm, uint64_t /* Addr */, 204 const MCDisassembler *Decoder) { 205 return decodeSrcOp(Inst, 10, OpWidth, Imm, Imm | AMDGPU::EncValues::IS_VGPR, 206 false, 0, AMDGPU::OperandSemantics::INT, Decoder); 207 } 208 209 // Decoder for Src(9-bit encoding) registers only. 210 template <AMDGPUDisassembler::OpWidthTy OpWidth> 211 static DecodeStatus decodeSrcReg9(MCInst &Inst, unsigned Imm, 212 uint64_t /* Addr */, 213 const MCDisassembler *Decoder) { 214 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, false, 0, 215 AMDGPU::OperandSemantics::INT, Decoder); 216 } 217 218 // Decoder for Src(9-bit encoding) AGPR, register number encoded in 9bits, set 219 // Imm{9} to 1 (set acc) and decode using 'enum10' from decodeSrcOp, registers 220 // only. 221 template <AMDGPUDisassembler::OpWidthTy OpWidth> 222 static DecodeStatus decodeSrcA9(MCInst &Inst, unsigned Imm, uint64_t /* Addr */, 223 const MCDisassembler *Decoder) { 224 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm | 512, false, 0, 225 AMDGPU::OperandSemantics::INT, Decoder); 226 } 227 228 // Decoder for 'enum10' from decodeSrcOp, Imm{0-8} is 9-bit Src encoding 229 // Imm{9} is acc, registers only. 230 template <AMDGPUDisassembler::OpWidthTy OpWidth> 231 static DecodeStatus decodeSrcAV10(MCInst &Inst, unsigned Imm, 232 uint64_t /* Addr */, 233 const MCDisassembler *Decoder) { 234 return decodeSrcOp(Inst, 10, OpWidth, Imm, Imm, false, 0, 235 AMDGPU::OperandSemantics::INT, Decoder); 236 } 237 238 // Decoder for RegisterOperands using 9-bit Src encoding. Operand can be 239 // register from RegClass or immediate. Registers that don't belong to RegClass 240 // will be decoded and InstPrinter will report warning. Immediate will be 241 // decoded into constant of size ImmWidth, should match width of immediate used 242 // by OperandType (important for floating point types). 243 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth, 244 unsigned OperandSemantics> 245 static DecodeStatus decodeSrcRegOrImm9(MCInst &Inst, unsigned Imm, 246 uint64_t /* Addr */, 247 const MCDisassembler *Decoder) { 248 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, false, ImmWidth, 249 (AMDGPU::OperandSemantics)OperandSemantics, Decoder); 250 } 251 252 // Decoder for Src(9-bit encoding) AGPR or immediate. Set Imm{9} to 1 (set acc) 253 // and decode using 'enum10' from decodeSrcOp. 254 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth, 255 unsigned OperandSemantics> 256 static DecodeStatus decodeSrcRegOrImmA9(MCInst &Inst, unsigned Imm, 257 uint64_t /* Addr */, 258 const MCDisassembler *Decoder) { 259 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm | 512, false, ImmWidth, 260 (AMDGPU::OperandSemantics)OperandSemantics, Decoder); 261 } 262 263 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth, 264 unsigned OperandSemantics> 265 static DecodeStatus decodeSrcRegOrImmDeferred9(MCInst &Inst, unsigned Imm, 266 uint64_t /* Addr */, 267 const MCDisassembler *Decoder) { 268 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, true, ImmWidth, 269 (AMDGPU::OperandSemantics)OperandSemantics, Decoder); 270 } 271 272 // Default decoders generated by tablegen: 'Decode<RegClass>RegisterClass' 273 // when RegisterClass is used as an operand. Most often used for destination 274 // operands. 275 276 DECODE_OPERAND_REG_8(VGPR_32) 277 DECODE_OPERAND_REG_8(VGPR_32_Lo128) 278 DECODE_OPERAND_REG_8(VReg_64) 279 DECODE_OPERAND_REG_8(VReg_96) 280 DECODE_OPERAND_REG_8(VReg_128) 281 DECODE_OPERAND_REG_8(VReg_256) 282 DECODE_OPERAND_REG_8(VReg_288) 283 DECODE_OPERAND_REG_8(VReg_352) 284 DECODE_OPERAND_REG_8(VReg_384) 285 DECODE_OPERAND_REG_8(VReg_512) 286 DECODE_OPERAND_REG_8(VReg_1024) 287 288 DECODE_OPERAND_REG_7(SReg_32, OPW32) 289 DECODE_OPERAND_REG_7(SReg_32_XEXEC, OPW32) 290 DECODE_OPERAND_REG_7(SReg_32_XM0_XEXEC, OPW32) 291 DECODE_OPERAND_REG_7(SReg_32_XEXEC_HI, OPW32) 292 DECODE_OPERAND_REG_7(SReg_64, OPW64) 293 DECODE_OPERAND_REG_7(SReg_64_XEXEC, OPW64) 294 DECODE_OPERAND_REG_7(SReg_64_XEXEC_XNULL, OPW64) 295 DECODE_OPERAND_REG_7(SReg_96, OPW96) 296 DECODE_OPERAND_REG_7(SReg_128, OPW128) 297 DECODE_OPERAND_REG_7(SReg_256, OPW256) 298 DECODE_OPERAND_REG_7(SReg_512, OPW512) 299 300 DECODE_OPERAND_REG_8(AGPR_32) 301 DECODE_OPERAND_REG_8(AReg_64) 302 DECODE_OPERAND_REG_8(AReg_128) 303 DECODE_OPERAND_REG_8(AReg_256) 304 DECODE_OPERAND_REG_8(AReg_512) 305 DECODE_OPERAND_REG_8(AReg_1024) 306 307 static DecodeStatus DecodeVGPR_16RegisterClass(MCInst &Inst, unsigned Imm, 308 uint64_t /*Addr*/, 309 const MCDisassembler *Decoder) { 310 assert(isUInt<10>(Imm) && "10-bit encoding expected"); 311 assert((Imm & (1 << 8)) == 0 && "Imm{8} should not be used"); 312 313 bool IsHi = Imm & (1 << 9); 314 unsigned RegIdx = Imm & 0xff; 315 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 316 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 317 } 318 319 static DecodeStatus 320 DecodeVGPR_16_Lo128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, 321 const MCDisassembler *Decoder) { 322 assert(isUInt<8>(Imm) && "8-bit encoding expected"); 323 324 bool IsHi = Imm & (1 << 7); 325 unsigned RegIdx = Imm & 0x7f; 326 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 327 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 328 } 329 330 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth, 331 unsigned OperandSemantics> 332 static DecodeStatus decodeOperand_VSrcT16_Lo128(MCInst &Inst, unsigned Imm, 333 uint64_t /*Addr*/, 334 const MCDisassembler *Decoder) { 335 assert(isUInt<9>(Imm) && "9-bit encoding expected"); 336 337 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 338 if (Imm & AMDGPU::EncValues::IS_VGPR) { 339 bool IsHi = Imm & (1 << 7); 340 unsigned RegIdx = Imm & 0x7f; 341 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 342 } 343 return addOperand(Inst, DAsm->decodeNonVGPRSrcOp( 344 OpWidth, Imm & 0xFF, false, ImmWidth, 345 (AMDGPU::OperandSemantics)OperandSemantics)); 346 } 347 348 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth, 349 unsigned OperandSemantics> 350 static DecodeStatus decodeOperand_VSrcT16(MCInst &Inst, unsigned Imm, 351 uint64_t /*Addr*/, 352 const MCDisassembler *Decoder) { 353 assert(isUInt<10>(Imm) && "10-bit encoding expected"); 354 355 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 356 if (Imm & AMDGPU::EncValues::IS_VGPR) { 357 bool IsHi = Imm & (1 << 9); 358 unsigned RegIdx = Imm & 0xff; 359 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 360 } 361 return addOperand(Inst, DAsm->decodeNonVGPRSrcOp( 362 OpWidth, Imm & 0xFF, false, ImmWidth, 363 (AMDGPU::OperandSemantics)OperandSemantics)); 364 } 365 366 static DecodeStatus decodeOperand_VGPR_16(MCInst &Inst, unsigned Imm, 367 uint64_t /*Addr*/, 368 const MCDisassembler *Decoder) { 369 assert(isUInt<10>(Imm) && "10-bit encoding expected"); 370 assert(Imm & AMDGPU::EncValues::IS_VGPR && "VGPR expected"); 371 372 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 373 374 bool IsHi = Imm & (1 << 9); 375 unsigned RegIdx = Imm & 0xff; 376 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 377 } 378 379 static DecodeStatus decodeOperand_KImmFP(MCInst &Inst, unsigned Imm, 380 uint64_t Addr, 381 const MCDisassembler *Decoder) { 382 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 383 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 384 } 385 386 static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val, 387 uint64_t Addr, const void *Decoder) { 388 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 389 return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val)); 390 } 391 392 static bool IsAGPROperand(const MCInst &Inst, int OpIdx, 393 const MCRegisterInfo *MRI) { 394 if (OpIdx < 0) 395 return false; 396 397 const MCOperand &Op = Inst.getOperand(OpIdx); 398 if (!Op.isReg()) 399 return false; 400 401 MCRegister Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); 402 auto Reg = Sub ? Sub : Op.getReg(); 403 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; 404 } 405 406 static DecodeStatus decodeAVLdSt(MCInst &Inst, unsigned Imm, 407 AMDGPUDisassembler::OpWidthTy Opw, 408 const MCDisassembler *Decoder) { 409 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 410 if (!DAsm->isGFX90A()) { 411 Imm &= 511; 412 } else { 413 // If atomic has both vdata and vdst their register classes are tied. 414 // The bit is decoded along with the vdst, first operand. We need to 415 // change register class to AGPR if vdst was AGPR. 416 // If a DS instruction has both data0 and data1 their register classes 417 // are also tied. 418 unsigned Opc = Inst.getOpcode(); 419 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; 420 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 421 : AMDGPU::OpName::vdata; 422 const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo(); 423 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); 424 if ((int)Inst.getNumOperands() == DataIdx) { 425 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); 426 if (IsAGPROperand(Inst, DstIdx, MRI)) 427 Imm |= 512; 428 } 429 430 if (TSFlags & SIInstrFlags::DS) { 431 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); 432 if ((int)Inst.getNumOperands() == Data2Idx && 433 IsAGPROperand(Inst, DataIdx, MRI)) 434 Imm |= 512; 435 } 436 } 437 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); 438 } 439 440 template <AMDGPUDisassembler::OpWidthTy Opw> 441 static DecodeStatus decodeAVLdSt(MCInst &Inst, unsigned Imm, 442 uint64_t /* Addr */, 443 const MCDisassembler *Decoder) { 444 return decodeAVLdSt(Inst, Imm, Opw, Decoder); 445 } 446 447 static DecodeStatus decodeOperand_VSrc_f64(MCInst &Inst, unsigned Imm, 448 uint64_t Addr, 449 const MCDisassembler *Decoder) { 450 assert(Imm < (1 << 9) && "9-bit encoding"); 451 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 452 return addOperand(Inst, 453 DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm, false, 64, 454 AMDGPU::OperandSemantics::FP64)); 455 } 456 457 #define DECODE_SDWA(DecName) \ 458 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 459 460 DECODE_SDWA(Src32) 461 DECODE_SDWA(Src16) 462 DECODE_SDWA(VopcDst) 463 464 static DecodeStatus decodeVersionImm(MCInst &Inst, unsigned Imm, 465 uint64_t /* Addr */, 466 const MCDisassembler *Decoder) { 467 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 468 return addOperand(Inst, DAsm->decodeVersionImm(Imm)); 469 } 470 471 #include "AMDGPUGenDisassemblerTables.inc" 472 473 //===----------------------------------------------------------------------===// 474 // 475 //===----------------------------------------------------------------------===// 476 477 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 478 assert(Bytes.size() >= sizeof(T)); 479 const auto Res = 480 support::endian::read<T, llvm::endianness::little>(Bytes.data()); 481 Bytes = Bytes.slice(sizeof(T)); 482 return Res; 483 } 484 485 static inline DecoderUInt128 eat12Bytes(ArrayRef<uint8_t> &Bytes) { 486 assert(Bytes.size() >= 12); 487 uint64_t Lo = 488 support::endian::read<uint64_t, llvm::endianness::little>(Bytes.data()); 489 Bytes = Bytes.slice(8); 490 uint64_t Hi = 491 support::endian::read<uint32_t, llvm::endianness::little>(Bytes.data()); 492 Bytes = Bytes.slice(4); 493 return DecoderUInt128(Lo, Hi); 494 } 495 496 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 497 ArrayRef<uint8_t> Bytes_, 498 uint64_t Address, 499 raw_ostream &CS) const { 500 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 501 Bytes = Bytes_.slice(0, MaxInstBytesNum); 502 503 // In case the opcode is not recognized we'll assume a Size of 4 bytes (unless 504 // there are fewer bytes left). This will be overridden on success. 505 Size = std::min((size_t)4, Bytes_.size()); 506 507 do { 508 // ToDo: better to switch encoding length using some bit predicate 509 // but it is unknown yet, so try all we can 510 511 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 512 // encodings 513 if (isGFX11Plus() && Bytes.size() >= 12 ) { 514 DecoderUInt128 DecW = eat12Bytes(Bytes); 515 516 if (isGFX11() && 517 tryDecodeInst(DecoderTableGFX1196, DecoderTableGFX11_FAKE1696, MI, 518 DecW, Address, CS)) 519 break; 520 521 if (isGFX12() && 522 tryDecodeInst(DecoderTableGFX1296, DecoderTableGFX12_FAKE1696, MI, 523 DecW, Address, CS)) 524 break; 525 526 if (isGFX12() && 527 tryDecodeInst(DecoderTableGFX12W6496, MI, DecW, Address, CS)) 528 break; 529 530 // Reinitialize Bytes 531 Bytes = Bytes_.slice(0, MaxInstBytesNum); 532 } 533 534 if (Bytes.size() >= 8) { 535 const uint64_t QW = eatBytes<uint64_t>(Bytes); 536 537 if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding) && 538 tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address, CS)) 539 break; 540 541 if (STI.hasFeature(AMDGPU::FeatureUnpackedD16VMem) && 542 tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address, CS)) 543 break; 544 545 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 546 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 547 // table first so we print the correct name. 548 if (STI.hasFeature(AMDGPU::FeatureFmaMixInsts) && 549 tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address, CS)) 550 break; 551 552 if (STI.hasFeature(AMDGPU::FeatureGFX940Insts) && 553 tryDecodeInst(DecoderTableGFX94064, MI, QW, Address, CS)) 554 break; 555 556 if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts) && 557 tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address, CS)) 558 break; 559 560 if ((isVI() || isGFX9()) && 561 tryDecodeInst(DecoderTableGFX864, MI, QW, Address, CS)) 562 break; 563 564 if (isGFX9() && tryDecodeInst(DecoderTableGFX964, MI, QW, Address, CS)) 565 break; 566 567 if (isGFX10() && tryDecodeInst(DecoderTableGFX1064, MI, QW, Address, CS)) 568 break; 569 570 if (isGFX12() && 571 tryDecodeInst(DecoderTableGFX1264, DecoderTableGFX12_FAKE1664, MI, QW, 572 Address, CS)) 573 break; 574 575 if (isGFX11() && 576 tryDecodeInst(DecoderTableGFX1164, DecoderTableGFX11_FAKE1664, MI, QW, 577 Address, CS)) 578 break; 579 580 if (isGFX11() && 581 tryDecodeInst(DecoderTableGFX11W6464, MI, QW, Address, CS)) 582 break; 583 584 if (isGFX12() && 585 tryDecodeInst(DecoderTableGFX12W6464, MI, QW, Address, CS)) 586 break; 587 588 // Reinitialize Bytes 589 Bytes = Bytes_.slice(0, MaxInstBytesNum); 590 } 591 592 // Try decode 32-bit instruction 593 if (Bytes.size() >= 4) { 594 const uint32_t DW = eatBytes<uint32_t>(Bytes); 595 596 if ((isVI() || isGFX9()) && 597 tryDecodeInst(DecoderTableGFX832, MI, DW, Address, CS)) 598 break; 599 600 if (tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address, CS)) 601 break; 602 603 if (isGFX9() && tryDecodeInst(DecoderTableGFX932, MI, DW, Address, CS)) 604 break; 605 606 if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts) && 607 tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address, CS)) 608 break; 609 610 if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding) && 611 tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address, CS)) 612 break; 613 614 if (isGFX10() && tryDecodeInst(DecoderTableGFX1032, MI, DW, Address, CS)) 615 break; 616 617 if (isGFX11() && 618 tryDecodeInst(DecoderTableGFX1132, DecoderTableGFX11_FAKE1632, MI, DW, 619 Address, CS)) 620 break; 621 622 if (isGFX12() && 623 tryDecodeInst(DecoderTableGFX1232, DecoderTableGFX12_FAKE1632, MI, DW, 624 Address, CS)) 625 break; 626 } 627 628 return MCDisassembler::Fail; 629 } while (false); 630 631 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::DPP) { 632 if (isMacDPP(MI)) 633 convertMacDPPInst(MI); 634 635 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3P) 636 convertVOP3PDPPInst(MI); 637 else if ((MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC) || 638 AMDGPU::isVOPC64DPP(MI.getOpcode())) 639 convertVOPCDPPInst(MI); // Special VOP3 case 640 else if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) != 641 -1) 642 convertDPP8Inst(MI); 643 else if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3) 644 convertVOP3DPPInst(MI); // Regular VOP3 case 645 } 646 647 convertTrue16OpSel(MI); 648 649 if (AMDGPU::isMAC(MI.getOpcode())) { 650 // Insert dummy unused src2_modifiers. 651 insertNamedMCOperand(MI, MCOperand::createImm(0), 652 AMDGPU::OpName::src2_modifiers); 653 } 654 655 if (MI.getOpcode() == AMDGPU::V_CVT_SR_BF8_F32_e64_dpp || 656 MI.getOpcode() == AMDGPU::V_CVT_SR_FP8_F32_e64_dpp) { 657 // Insert dummy unused src2_modifiers. 658 insertNamedMCOperand(MI, MCOperand::createImm(0), 659 AMDGPU::OpName::src2_modifiers); 660 } 661 662 if ((MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::DS) && 663 !AMDGPU::hasGDS(STI)) { 664 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::gds); 665 } 666 667 if (MCII->get(MI.getOpcode()).TSFlags & 668 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT | SIInstrFlags::SMRD)) { 669 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 670 AMDGPU::OpName::cpol); 671 if (CPolPos != -1) { 672 unsigned CPol = 673 (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ? 674 AMDGPU::CPol::GLC : 0; 675 if (MI.getNumOperands() <= (unsigned)CPolPos) { 676 insertNamedMCOperand(MI, MCOperand::createImm(CPol), 677 AMDGPU::OpName::cpol); 678 } else if (CPol) { 679 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); 680 } 681 } 682 } 683 684 if ((MCII->get(MI.getOpcode()).TSFlags & 685 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) && 686 (STI.hasFeature(AMDGPU::FeatureGFX90AInsts))) { 687 // GFX90A lost TFE, its place is occupied by ACC. 688 int TFEOpIdx = 689 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); 690 if (TFEOpIdx != -1) { 691 auto *TFEIter = MI.begin(); 692 std::advance(TFEIter, TFEOpIdx); 693 MI.insert(TFEIter, MCOperand::createImm(0)); 694 } 695 } 696 697 if (MCII->get(MI.getOpcode()).TSFlags & 698 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) { 699 int SWZOpIdx = 700 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); 701 if (SWZOpIdx != -1) { 702 auto *SWZIter = MI.begin(); 703 std::advance(SWZIter, SWZOpIdx); 704 MI.insert(SWZIter, MCOperand::createImm(0)); 705 } 706 } 707 708 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG) { 709 int VAddr0Idx = 710 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 711 int RsrcIdx = 712 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 713 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 714 if (VAddr0Idx >= 0 && NSAArgs > 0) { 715 unsigned NSAWords = (NSAArgs + 3) / 4; 716 if (Bytes.size() < 4 * NSAWords) 717 return MCDisassembler::Fail; 718 for (unsigned i = 0; i < NSAArgs; ++i) { 719 const unsigned VAddrIdx = VAddr0Idx + 1 + i; 720 auto VAddrRCID = 721 MCII->get(MI.getOpcode()).operands()[VAddrIdx].RegClass; 722 MI.insert(MI.begin() + VAddrIdx, createRegOperand(VAddrRCID, Bytes[i])); 723 } 724 Bytes = Bytes.slice(4 * NSAWords); 725 } 726 727 convertMIMGInst(MI); 728 } 729 730 if (MCII->get(MI.getOpcode()).TSFlags & 731 (SIInstrFlags::VIMAGE | SIInstrFlags::VSAMPLE)) 732 convertMIMGInst(MI); 733 734 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::EXP) 735 convertEXPInst(MI); 736 737 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VINTERP) 738 convertVINTERPInst(MI); 739 740 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::SDWA) 741 convertSDWAInst(MI); 742 743 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 744 AMDGPU::OpName::vdst_in); 745 if (VDstIn_Idx != -1) { 746 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 747 MCOI::OperandConstraint::TIED_TO); 748 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 749 !MI.getOperand(VDstIn_Idx).isReg() || 750 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 751 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 752 MI.erase(&MI.getOperand(VDstIn_Idx)); 753 insertNamedMCOperand(MI, 754 MCOperand::createReg(MI.getOperand(Tied).getReg()), 755 AMDGPU::OpName::vdst_in); 756 } 757 } 758 759 int ImmLitIdx = 760 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm); 761 bool IsSOPK = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::SOPK; 762 if (ImmLitIdx != -1 && !IsSOPK) 763 convertFMAanyK(MI, ImmLitIdx); 764 765 Size = MaxInstBytesNum - Bytes.size(); 766 return MCDisassembler::Success; 767 } 768 769 void AMDGPUDisassembler::convertEXPInst(MCInst &MI) const { 770 if (STI.hasFeature(AMDGPU::FeatureGFX11Insts)) { 771 // The MCInst still has these fields even though they are no longer encoded 772 // in the GFX11 instruction. 773 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vm); 774 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::compr); 775 } 776 } 777 778 void AMDGPUDisassembler::convertVINTERPInst(MCInst &MI) const { 779 convertTrue16OpSel(MI); 780 if (MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_t16_gfx11 || 781 MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_fake16_gfx11 || 782 MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_t16_gfx12 || 783 MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_fake16_gfx12 || 784 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_t16_gfx11 || 785 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_fake16_gfx11 || 786 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_t16_gfx12 || 787 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_fake16_gfx12 || 788 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_t16_gfx11 || 789 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_fake16_gfx11 || 790 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_t16_gfx12 || 791 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_fake16_gfx12 || 792 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_t16_gfx11 || 793 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_fake16_gfx11 || 794 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_t16_gfx12 || 795 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_fake16_gfx12) { 796 // The MCInst has this field that is not directly encoded in the 797 // instruction. 798 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::op_sel); 799 } 800 } 801 802 void AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 803 if (STI.hasFeature(AMDGPU::FeatureGFX9) || 804 STI.hasFeature(AMDGPU::FeatureGFX10)) { 805 if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::sdst)) 806 // VOPC - insert clamp 807 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 808 } else if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) { 809 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 810 if (SDst != -1) { 811 // VOPC - insert VCC register as sdst 812 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 813 AMDGPU::OpName::sdst); 814 } else { 815 // VOP1/2 - insert omod if present in instruction 816 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 817 } 818 } 819 } 820 821 struct VOPModifiers { 822 unsigned OpSel = 0; 823 unsigned OpSelHi = 0; 824 unsigned NegLo = 0; 825 unsigned NegHi = 0; 826 }; 827 828 // Reconstruct values of VOP3/VOP3P operands such as op_sel. 829 // Note that these values do not affect disassembler output, 830 // so this is only necessary for consistency with src_modifiers. 831 static VOPModifiers collectVOPModifiers(const MCInst &MI, 832 bool IsVOP3P = false) { 833 VOPModifiers Modifiers; 834 unsigned Opc = MI.getOpcode(); 835 const int ModOps[] = {AMDGPU::OpName::src0_modifiers, 836 AMDGPU::OpName::src1_modifiers, 837 AMDGPU::OpName::src2_modifiers}; 838 for (int J = 0; J < 3; ++J) { 839 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]); 840 if (OpIdx == -1) 841 continue; 842 843 unsigned Val = MI.getOperand(OpIdx).getImm(); 844 845 Modifiers.OpSel |= !!(Val & SISrcMods::OP_SEL_0) << J; 846 if (IsVOP3P) { 847 Modifiers.OpSelHi |= !!(Val & SISrcMods::OP_SEL_1) << J; 848 Modifiers.NegLo |= !!(Val & SISrcMods::NEG) << J; 849 Modifiers.NegHi |= !!(Val & SISrcMods::NEG_HI) << J; 850 } else if (J == 0) { 851 Modifiers.OpSel |= !!(Val & SISrcMods::DST_OP_SEL) << 3; 852 } 853 } 854 855 return Modifiers; 856 } 857 858 // Instructions decode the op_sel/suffix bits into the src_modifier 859 // operands. Copy those bits into the src operands for true16 VGPRs. 860 void AMDGPUDisassembler::convertTrue16OpSel(MCInst &MI) const { 861 const unsigned Opc = MI.getOpcode(); 862 const MCRegisterClass &ConversionRC = 863 MRI.getRegClass(AMDGPU::VGPR_16RegClassID); 864 constexpr std::array<std::tuple<int, int, unsigned>, 4> OpAndOpMods = { 865 {{AMDGPU::OpName::src0, AMDGPU::OpName::src0_modifiers, 866 SISrcMods::OP_SEL_0}, 867 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_modifiers, 868 SISrcMods::OP_SEL_0}, 869 {AMDGPU::OpName::src2, AMDGPU::OpName::src2_modifiers, 870 SISrcMods::OP_SEL_0}, 871 {AMDGPU::OpName::vdst, AMDGPU::OpName::src0_modifiers, 872 SISrcMods::DST_OP_SEL}}}; 873 for (const auto &[OpName, OpModsName, OpSelMask] : OpAndOpMods) { 874 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, OpName); 875 int OpModsIdx = AMDGPU::getNamedOperandIdx(Opc, OpModsName); 876 if (OpIdx == -1 || OpModsIdx == -1) 877 continue; 878 MCOperand &Op = MI.getOperand(OpIdx); 879 if (!Op.isReg()) 880 continue; 881 if (!ConversionRC.contains(Op.getReg())) 882 continue; 883 unsigned OpEnc = MRI.getEncodingValue(Op.getReg()); 884 const MCOperand &OpMods = MI.getOperand(OpModsIdx); 885 unsigned ModVal = OpMods.getImm(); 886 if (ModVal & OpSelMask) { // isHi 887 unsigned RegIdx = OpEnc & AMDGPU::HWEncoding::REG_IDX_MASK; 888 Op.setReg(ConversionRC.getRegister(RegIdx * 2 + 1)); 889 } 890 } 891 } 892 893 // MAC opcodes have special old and src2 operands. 894 // src2 is tied to dst, while old is not tied (but assumed to be). 895 bool AMDGPUDisassembler::isMacDPP(MCInst &MI) const { 896 constexpr int DST_IDX = 0; 897 auto Opcode = MI.getOpcode(); 898 const auto &Desc = MCII->get(Opcode); 899 auto OldIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::old); 900 901 if (OldIdx != -1 && Desc.getOperandConstraint( 902 OldIdx, MCOI::OperandConstraint::TIED_TO) == -1) { 903 assert(AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src2)); 904 assert(Desc.getOperandConstraint( 905 AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2), 906 MCOI::OperandConstraint::TIED_TO) == DST_IDX); 907 (void)DST_IDX; 908 return true; 909 } 910 911 return false; 912 } 913 914 // Create dummy old operand and insert dummy unused src2_modifiers 915 void AMDGPUDisassembler::convertMacDPPInst(MCInst &MI) const { 916 assert(MI.getNumOperands() + 1 < MCII->get(MI.getOpcode()).getNumOperands()); 917 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 918 insertNamedMCOperand(MI, MCOperand::createImm(0), 919 AMDGPU::OpName::src2_modifiers); 920 } 921 922 void AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 923 unsigned Opc = MI.getOpcode(); 924 925 int VDstInIdx = 926 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst_in); 927 if (VDstInIdx != -1) 928 insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::vdst_in); 929 930 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 931 if (MI.getNumOperands() < DescNumOps && 932 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { 933 convertTrue16OpSel(MI); 934 auto Mods = collectVOPModifiers(MI); 935 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 936 AMDGPU::OpName::op_sel); 937 } else { 938 // Insert dummy unused src modifiers. 939 if (MI.getNumOperands() < DescNumOps && 940 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) 941 insertNamedMCOperand(MI, MCOperand::createImm(0), 942 AMDGPU::OpName::src0_modifiers); 943 944 if (MI.getNumOperands() < DescNumOps && 945 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers)) 946 insertNamedMCOperand(MI, MCOperand::createImm(0), 947 AMDGPU::OpName::src1_modifiers); 948 } 949 } 950 951 void AMDGPUDisassembler::convertVOP3DPPInst(MCInst &MI) const { 952 convertTrue16OpSel(MI); 953 954 int VDstInIdx = 955 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst_in); 956 if (VDstInIdx != -1) 957 insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::vdst_in); 958 959 unsigned Opc = MI.getOpcode(); 960 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 961 if (MI.getNumOperands() < DescNumOps && 962 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { 963 auto Mods = collectVOPModifiers(MI); 964 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 965 AMDGPU::OpName::op_sel); 966 } 967 } 968 969 // Note that before gfx10, the MIMG encoding provided no information about 970 // VADDR size. Consequently, decoded instructions always show address as if it 971 // has 1 dword, which could be not really so. 972 void AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 973 auto TSFlags = MCII->get(MI.getOpcode()).TSFlags; 974 975 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 976 AMDGPU::OpName::vdst); 977 978 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 979 AMDGPU::OpName::vdata); 980 int VAddr0Idx = 981 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 982 int RsrcOpName = (TSFlags & SIInstrFlags::MIMG) ? AMDGPU::OpName::srsrc 983 : AMDGPU::OpName::rsrc; 984 int RsrcIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), RsrcOpName); 985 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 986 AMDGPU::OpName::dmask); 987 988 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 989 AMDGPU::OpName::tfe); 990 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 991 AMDGPU::OpName::d16); 992 993 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 994 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 995 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 996 997 assert(VDataIdx != -1); 998 if (BaseOpcode->BVH) { 999 // Add A16 operand for intersect_ray instructions 1000 addOperand(MI, MCOperand::createImm(BaseOpcode->A16)); 1001 return; 1002 } 1003 1004 bool IsAtomic = (VDstIdx != -1); 1005 bool IsGather4 = TSFlags & SIInstrFlags::Gather4; 1006 bool IsVSample = TSFlags & SIInstrFlags::VSAMPLE; 1007 bool IsNSA = false; 1008 bool IsPartialNSA = false; 1009 unsigned AddrSize = Info->VAddrDwords; 1010 1011 if (isGFX10Plus()) { 1012 unsigned DimIdx = 1013 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 1014 int A16Idx = 1015 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16); 1016 const AMDGPU::MIMGDimInfo *Dim = 1017 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 1018 const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm()); 1019 1020 AddrSize = 1021 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); 1022 1023 // VSAMPLE insts that do not use vaddr3 behave the same as NSA forms. 1024 // VIMAGE insts other than BVH never use vaddr4. 1025 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA || 1026 Info->MIMGEncoding == AMDGPU::MIMGEncGfx11NSA || 1027 Info->MIMGEncoding == AMDGPU::MIMGEncGfx12; 1028 if (!IsNSA) { 1029 if (!IsVSample && AddrSize > 12) 1030 AddrSize = 16; 1031 } else { 1032 if (AddrSize > Info->VAddrDwords) { 1033 if (!STI.hasFeature(AMDGPU::FeaturePartialNSAEncoding)) { 1034 // The NSA encoding does not contain enough operands for the 1035 // combination of base opcode / dimension. Should this be an error? 1036 return; 1037 } 1038 IsPartialNSA = true; 1039 } 1040 } 1041 } 1042 1043 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 1044 unsigned DstSize = IsGather4 ? 4 : std::max(llvm::popcount(DMask), 1); 1045 1046 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 1047 if (D16 && AMDGPU::hasPackedD16(STI)) { 1048 DstSize = (DstSize + 1) / 2; 1049 } 1050 1051 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm()) 1052 DstSize += 1; 1053 1054 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 1055 return; 1056 1057 int NewOpcode = 1058 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 1059 if (NewOpcode == -1) 1060 return; 1061 1062 // Widen the register to the correct number of enabled channels. 1063 MCRegister NewVdata; 1064 if (DstSize != Info->VDataDwords) { 1065 auto DataRCID = MCII->get(NewOpcode).operands()[VDataIdx].RegClass; 1066 1067 // Get first subregister of VData 1068 MCRegister Vdata0 = MI.getOperand(VDataIdx).getReg(); 1069 MCRegister VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 1070 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 1071 1072 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 1073 &MRI.getRegClass(DataRCID)); 1074 if (!NewVdata) { 1075 // It's possible to encode this such that the low register + enabled 1076 // components exceeds the register count. 1077 return; 1078 } 1079 } 1080 1081 // If not using NSA on GFX10+, widen vaddr0 address register to correct size. 1082 // If using partial NSA on GFX11+ widen last address register. 1083 int VAddrSAIdx = IsPartialNSA ? (RsrcIdx - 1) : VAddr0Idx; 1084 MCRegister NewVAddrSA; 1085 if (STI.hasFeature(AMDGPU::FeatureNSAEncoding) && (!IsNSA || IsPartialNSA) && 1086 AddrSize != Info->VAddrDwords) { 1087 MCRegister VAddrSA = MI.getOperand(VAddrSAIdx).getReg(); 1088 MCRegister VAddrSubSA = MRI.getSubReg(VAddrSA, AMDGPU::sub0); 1089 VAddrSA = VAddrSubSA ? VAddrSubSA : VAddrSA; 1090 1091 auto AddrRCID = MCII->get(NewOpcode).operands()[VAddrSAIdx].RegClass; 1092 NewVAddrSA = MRI.getMatchingSuperReg(VAddrSA, AMDGPU::sub0, 1093 &MRI.getRegClass(AddrRCID)); 1094 if (!NewVAddrSA) 1095 return; 1096 } 1097 1098 MI.setOpcode(NewOpcode); 1099 1100 if (NewVdata != AMDGPU::NoRegister) { 1101 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 1102 1103 if (IsAtomic) { 1104 // Atomic operations have an additional operand (a copy of data) 1105 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 1106 } 1107 } 1108 1109 if (NewVAddrSA) { 1110 MI.getOperand(VAddrSAIdx) = MCOperand::createReg(NewVAddrSA); 1111 } else if (IsNSA) { 1112 assert(AddrSize <= Info->VAddrDwords); 1113 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 1114 MI.begin() + VAddr0Idx + Info->VAddrDwords); 1115 } 1116 } 1117 1118 // Opsel and neg bits are used in src_modifiers and standalone operands. Autogen 1119 // decoder only adds to src_modifiers, so manually add the bits to the other 1120 // operands. 1121 void AMDGPUDisassembler::convertVOP3PDPPInst(MCInst &MI) const { 1122 unsigned Opc = MI.getOpcode(); 1123 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1124 auto Mods = collectVOPModifiers(MI, true); 1125 1126 if (MI.getNumOperands() < DescNumOps && 1127 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vdst_in)) 1128 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vdst_in); 1129 1130 if (MI.getNumOperands() < DescNumOps && 1131 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) 1132 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 1133 AMDGPU::OpName::op_sel); 1134 if (MI.getNumOperands() < DescNumOps && 1135 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel_hi)) 1136 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSelHi), 1137 AMDGPU::OpName::op_sel_hi); 1138 if (MI.getNumOperands() < DescNumOps && 1139 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_lo)) 1140 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegLo), 1141 AMDGPU::OpName::neg_lo); 1142 if (MI.getNumOperands() < DescNumOps && 1143 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_hi)) 1144 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegHi), 1145 AMDGPU::OpName::neg_hi); 1146 } 1147 1148 // Create dummy old operand and insert optional operands 1149 void AMDGPUDisassembler::convertVOPCDPPInst(MCInst &MI) const { 1150 unsigned Opc = MI.getOpcode(); 1151 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1152 1153 if (MI.getNumOperands() < DescNumOps && 1154 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::old)) 1155 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 1156 1157 if (MI.getNumOperands() < DescNumOps && 1158 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) 1159 insertNamedMCOperand(MI, MCOperand::createImm(0), 1160 AMDGPU::OpName::src0_modifiers); 1161 1162 if (MI.getNumOperands() < DescNumOps && 1163 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers)) 1164 insertNamedMCOperand(MI, MCOperand::createImm(0), 1165 AMDGPU::OpName::src1_modifiers); 1166 } 1167 1168 void AMDGPUDisassembler::convertFMAanyK(MCInst &MI, int ImmLitIdx) const { 1169 assert(HasLiteral && "Should have decoded a literal"); 1170 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 1171 unsigned DescNumOps = Desc.getNumOperands(); 1172 insertNamedMCOperand(MI, MCOperand::createImm(Literal), 1173 AMDGPU::OpName::immDeferred); 1174 assert(DescNumOps == MI.getNumOperands()); 1175 for (unsigned I = 0; I < DescNumOps; ++I) { 1176 auto &Op = MI.getOperand(I); 1177 auto OpType = Desc.operands()[I].OperandType; 1178 bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED || 1179 OpType == AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED); 1180 if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST && 1181 IsDeferredOp) 1182 Op.setImm(Literal); 1183 } 1184 } 1185 1186 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 1187 return getContext().getRegisterInfo()-> 1188 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 1189 } 1190 1191 inline 1192 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 1193 const Twine& ErrMsg) const { 1194 *CommentStream << "Error: " + ErrMsg; 1195 1196 // ToDo: add support for error operands to MCInst.h 1197 // return MCOperand::createError(V); 1198 return MCOperand(); 1199 } 1200 1201 inline 1202 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 1203 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 1204 } 1205 1206 inline 1207 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 1208 unsigned Val) const { 1209 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 1210 if (Val >= RegCl.getNumRegs()) 1211 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 1212 ": unknown register " + Twine(Val)); 1213 return createRegOperand(RegCl.getRegister(Val)); 1214 } 1215 1216 inline 1217 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 1218 unsigned Val) const { 1219 // ToDo: SI/CI have 104 SGPRs, VI - 102 1220 // Valery: here we accepting as much as we can, let assembler sort it out 1221 int shift = 0; 1222 switch (SRegClassID) { 1223 case AMDGPU::SGPR_32RegClassID: 1224 case AMDGPU::TTMP_32RegClassID: 1225 break; 1226 case AMDGPU::SGPR_64RegClassID: 1227 case AMDGPU::TTMP_64RegClassID: 1228 shift = 1; 1229 break; 1230 case AMDGPU::SGPR_96RegClassID: 1231 case AMDGPU::TTMP_96RegClassID: 1232 case AMDGPU::SGPR_128RegClassID: 1233 case AMDGPU::TTMP_128RegClassID: 1234 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 1235 // this bundle? 1236 case AMDGPU::SGPR_256RegClassID: 1237 case AMDGPU::TTMP_256RegClassID: 1238 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 1239 // this bundle? 1240 case AMDGPU::SGPR_288RegClassID: 1241 case AMDGPU::TTMP_288RegClassID: 1242 case AMDGPU::SGPR_320RegClassID: 1243 case AMDGPU::TTMP_320RegClassID: 1244 case AMDGPU::SGPR_352RegClassID: 1245 case AMDGPU::TTMP_352RegClassID: 1246 case AMDGPU::SGPR_384RegClassID: 1247 case AMDGPU::TTMP_384RegClassID: 1248 case AMDGPU::SGPR_512RegClassID: 1249 case AMDGPU::TTMP_512RegClassID: 1250 shift = 2; 1251 break; 1252 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 1253 // this bundle? 1254 default: 1255 llvm_unreachable("unhandled register class"); 1256 } 1257 1258 if (Val % (1 << shift)) { 1259 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 1260 << ": scalar reg isn't aligned " << Val; 1261 } 1262 1263 return createRegOperand(SRegClassID, Val >> shift); 1264 } 1265 1266 MCOperand AMDGPUDisassembler::createVGPR16Operand(unsigned RegIdx, 1267 bool IsHi) const { 1268 unsigned RegIdxInVGPR16 = RegIdx * 2 + (IsHi ? 1 : 0); 1269 return createRegOperand(AMDGPU::VGPR_16RegClassID, RegIdxInVGPR16); 1270 } 1271 1272 // Decode Literals for insts which always have a literal in the encoding 1273 MCOperand 1274 AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const { 1275 if (HasLiteral) { 1276 assert( 1277 AMDGPU::hasVOPD(STI) && 1278 "Should only decode multiple kimm with VOPD, check VSrc operand types"); 1279 if (Literal != Val) 1280 return errOperand(Val, "More than one unique literal is illegal"); 1281 } 1282 HasLiteral = true; 1283 Literal = Val; 1284 return MCOperand::createImm(Literal); 1285 } 1286 1287 MCOperand AMDGPUDisassembler::decodeLiteralConstant(bool ExtendFP64) const { 1288 // For now all literal constants are supposed to be unsigned integer 1289 // ToDo: deal with signed/unsigned 64-bit integer constants 1290 // ToDo: deal with float/double constants 1291 if (!HasLiteral) { 1292 if (Bytes.size() < 4) { 1293 return errOperand(0, "cannot read literal, inst bytes left " + 1294 Twine(Bytes.size())); 1295 } 1296 HasLiteral = true; 1297 Literal = Literal64 = eatBytes<uint32_t>(Bytes); 1298 if (ExtendFP64) 1299 Literal64 <<= 32; 1300 } 1301 return MCOperand::createImm(ExtendFP64 ? Literal64 : Literal); 1302 } 1303 1304 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 1305 using namespace AMDGPU::EncValues; 1306 1307 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 1308 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 1309 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 1310 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 1311 // Cast prevents negative overflow. 1312 } 1313 1314 static int64_t getInlineImmVal32(unsigned Imm) { 1315 switch (Imm) { 1316 case 240: 1317 return llvm::bit_cast<uint32_t>(0.5f); 1318 case 241: 1319 return llvm::bit_cast<uint32_t>(-0.5f); 1320 case 242: 1321 return llvm::bit_cast<uint32_t>(1.0f); 1322 case 243: 1323 return llvm::bit_cast<uint32_t>(-1.0f); 1324 case 244: 1325 return llvm::bit_cast<uint32_t>(2.0f); 1326 case 245: 1327 return llvm::bit_cast<uint32_t>(-2.0f); 1328 case 246: 1329 return llvm::bit_cast<uint32_t>(4.0f); 1330 case 247: 1331 return llvm::bit_cast<uint32_t>(-4.0f); 1332 case 248: // 1 / (2 * PI) 1333 return 0x3e22f983; 1334 default: 1335 llvm_unreachable("invalid fp inline imm"); 1336 } 1337 } 1338 1339 static int64_t getInlineImmVal64(unsigned Imm) { 1340 switch (Imm) { 1341 case 240: 1342 return llvm::bit_cast<uint64_t>(0.5); 1343 case 241: 1344 return llvm::bit_cast<uint64_t>(-0.5); 1345 case 242: 1346 return llvm::bit_cast<uint64_t>(1.0); 1347 case 243: 1348 return llvm::bit_cast<uint64_t>(-1.0); 1349 case 244: 1350 return llvm::bit_cast<uint64_t>(2.0); 1351 case 245: 1352 return llvm::bit_cast<uint64_t>(-2.0); 1353 case 246: 1354 return llvm::bit_cast<uint64_t>(4.0); 1355 case 247: 1356 return llvm::bit_cast<uint64_t>(-4.0); 1357 case 248: // 1 / (2 * PI) 1358 return 0x3fc45f306dc9c882; 1359 default: 1360 llvm_unreachable("invalid fp inline imm"); 1361 } 1362 } 1363 1364 static int64_t getInlineImmValF16(unsigned Imm) { 1365 switch (Imm) { 1366 case 240: 1367 return 0x3800; 1368 case 241: 1369 return 0xB800; 1370 case 242: 1371 return 0x3C00; 1372 case 243: 1373 return 0xBC00; 1374 case 244: 1375 return 0x4000; 1376 case 245: 1377 return 0xC000; 1378 case 246: 1379 return 0x4400; 1380 case 247: 1381 return 0xC400; 1382 case 248: // 1 / (2 * PI) 1383 return 0x3118; 1384 default: 1385 llvm_unreachable("invalid fp inline imm"); 1386 } 1387 } 1388 1389 static int64_t getInlineImmValBF16(unsigned Imm) { 1390 switch (Imm) { 1391 case 240: 1392 return 0x3F00; 1393 case 241: 1394 return 0xBF00; 1395 case 242: 1396 return 0x3F80; 1397 case 243: 1398 return 0xBF80; 1399 case 244: 1400 return 0x4000; 1401 case 245: 1402 return 0xC000; 1403 case 246: 1404 return 0x4080; 1405 case 247: 1406 return 0xC080; 1407 case 248: // 1 / (2 * PI) 1408 return 0x3E22; 1409 default: 1410 llvm_unreachable("invalid fp inline imm"); 1411 } 1412 } 1413 1414 static int64_t getInlineImmVal16(unsigned Imm, AMDGPU::OperandSemantics Sema) { 1415 return (Sema == AMDGPU::OperandSemantics::BF16) ? getInlineImmValBF16(Imm) 1416 : getInlineImmValF16(Imm); 1417 } 1418 1419 MCOperand AMDGPUDisassembler::decodeFPImmed(unsigned ImmWidth, unsigned Imm, 1420 AMDGPU::OperandSemantics Sema) { 1421 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN && 1422 Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 1423 1424 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 1425 // ImmWidth 0 is a default case where operand should not allow immediates. 1426 // Imm value is still decoded into 32 bit immediate operand, inst printer will 1427 // use it to print verbose error message. 1428 switch (ImmWidth) { 1429 case 0: 1430 case 32: 1431 return MCOperand::createImm(getInlineImmVal32(Imm)); 1432 case 64: 1433 return MCOperand::createImm(getInlineImmVal64(Imm)); 1434 case 16: 1435 return MCOperand::createImm(getInlineImmVal16(Imm, Sema)); 1436 default: 1437 llvm_unreachable("implement me"); 1438 } 1439 } 1440 1441 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 1442 using namespace AMDGPU; 1443 1444 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1445 switch (Width) { 1446 default: // fall 1447 case OPW32: 1448 case OPW16: 1449 case OPWV216: 1450 return VGPR_32RegClassID; 1451 case OPW64: 1452 case OPWV232: return VReg_64RegClassID; 1453 case OPW96: return VReg_96RegClassID; 1454 case OPW128: return VReg_128RegClassID; 1455 case OPW160: return VReg_160RegClassID; 1456 case OPW256: return VReg_256RegClassID; 1457 case OPW288: return VReg_288RegClassID; 1458 case OPW320: return VReg_320RegClassID; 1459 case OPW352: return VReg_352RegClassID; 1460 case OPW384: return VReg_384RegClassID; 1461 case OPW512: return VReg_512RegClassID; 1462 case OPW1024: return VReg_1024RegClassID; 1463 } 1464 } 1465 1466 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 1467 using namespace AMDGPU; 1468 1469 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1470 switch (Width) { 1471 default: // fall 1472 case OPW32: 1473 case OPW16: 1474 case OPWV216: 1475 return AGPR_32RegClassID; 1476 case OPW64: 1477 case OPWV232: return AReg_64RegClassID; 1478 case OPW96: return AReg_96RegClassID; 1479 case OPW128: return AReg_128RegClassID; 1480 case OPW160: return AReg_160RegClassID; 1481 case OPW256: return AReg_256RegClassID; 1482 case OPW288: return AReg_288RegClassID; 1483 case OPW320: return AReg_320RegClassID; 1484 case OPW352: return AReg_352RegClassID; 1485 case OPW384: return AReg_384RegClassID; 1486 case OPW512: return AReg_512RegClassID; 1487 case OPW1024: return AReg_1024RegClassID; 1488 } 1489 } 1490 1491 1492 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 1493 using namespace AMDGPU; 1494 1495 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1496 switch (Width) { 1497 default: // fall 1498 case OPW32: 1499 case OPW16: 1500 case OPWV216: 1501 return SGPR_32RegClassID; 1502 case OPW64: 1503 case OPWV232: return SGPR_64RegClassID; 1504 case OPW96: return SGPR_96RegClassID; 1505 case OPW128: return SGPR_128RegClassID; 1506 case OPW160: return SGPR_160RegClassID; 1507 case OPW256: return SGPR_256RegClassID; 1508 case OPW288: return SGPR_288RegClassID; 1509 case OPW320: return SGPR_320RegClassID; 1510 case OPW352: return SGPR_352RegClassID; 1511 case OPW384: return SGPR_384RegClassID; 1512 case OPW512: return SGPR_512RegClassID; 1513 } 1514 } 1515 1516 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 1517 using namespace AMDGPU; 1518 1519 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1520 switch (Width) { 1521 default: // fall 1522 case OPW32: 1523 case OPW16: 1524 case OPWV216: 1525 return TTMP_32RegClassID; 1526 case OPW64: 1527 case OPWV232: return TTMP_64RegClassID; 1528 case OPW128: return TTMP_128RegClassID; 1529 case OPW256: return TTMP_256RegClassID; 1530 case OPW288: return TTMP_288RegClassID; 1531 case OPW320: return TTMP_320RegClassID; 1532 case OPW352: return TTMP_352RegClassID; 1533 case OPW384: return TTMP_384RegClassID; 1534 case OPW512: return TTMP_512RegClassID; 1535 } 1536 } 1537 1538 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 1539 using namespace AMDGPU::EncValues; 1540 1541 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN; 1542 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX; 1543 1544 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1545 } 1546 1547 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val, 1548 bool MandatoryLiteral, 1549 unsigned ImmWidth, 1550 AMDGPU::OperandSemantics Sema) const { 1551 using namespace AMDGPU::EncValues; 1552 1553 assert(Val < 1024); // enum10 1554 1555 bool IsAGPR = Val & 512; 1556 Val &= 511; 1557 1558 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1559 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1560 : getVgprClassId(Width), Val - VGPR_MIN); 1561 } 1562 return decodeNonVGPRSrcOp(Width, Val & 0xFF, MandatoryLiteral, ImmWidth, 1563 Sema); 1564 } 1565 1566 MCOperand 1567 AMDGPUDisassembler::decodeNonVGPRSrcOp(const OpWidthTy Width, unsigned Val, 1568 bool MandatoryLiteral, unsigned ImmWidth, 1569 AMDGPU::OperandSemantics Sema) const { 1570 // Cases when Val{8} is 1 (vgpr, agpr or true 16 vgpr) should have been 1571 // decoded earlier. 1572 assert(Val < (1 << 8) && "9-bit Src encoding when Val{8} is 0"); 1573 using namespace AMDGPU::EncValues; 1574 1575 if (Val <= SGPR_MAX) { 1576 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1577 static_assert(SGPR_MIN == 0); 1578 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1579 } 1580 1581 int TTmpIdx = getTTmpIdx(Val); 1582 if (TTmpIdx >= 0) { 1583 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1584 } 1585 1586 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1587 return decodeIntImmed(Val); 1588 1589 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1590 return decodeFPImmed(ImmWidth, Val, Sema); 1591 1592 if (Val == LITERAL_CONST) { 1593 if (MandatoryLiteral) 1594 // Keep a sentinel value for deferred setting 1595 return MCOperand::createImm(LITERAL_CONST); 1596 return decodeLiteralConstant(Sema == AMDGPU::OperandSemantics::FP64); 1597 } 1598 1599 switch (Width) { 1600 case OPW32: 1601 case OPW16: 1602 case OPWV216: 1603 return decodeSpecialReg32(Val); 1604 case OPW64: 1605 case OPWV232: 1606 return decodeSpecialReg64(Val); 1607 default: 1608 llvm_unreachable("unexpected immediate type"); 1609 } 1610 } 1611 1612 // Bit 0 of DstY isn't stored in the instruction, because it's always the 1613 // opposite of bit 0 of DstX. 1614 MCOperand AMDGPUDisassembler::decodeVOPDDstYOp(MCInst &Inst, 1615 unsigned Val) const { 1616 int VDstXInd = 1617 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::vdstX); 1618 assert(VDstXInd != -1); 1619 assert(Inst.getOperand(VDstXInd).isReg()); 1620 unsigned XDstReg = MRI.getEncodingValue(Inst.getOperand(VDstXInd).getReg()); 1621 Val |= ~XDstReg & 1; 1622 auto Width = llvm::AMDGPUDisassembler::OPW32; 1623 return createRegOperand(getVgprClassId(Width), Val); 1624 } 1625 1626 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1627 using namespace AMDGPU; 1628 1629 switch (Val) { 1630 // clang-format off 1631 case 102: return createRegOperand(FLAT_SCR_LO); 1632 case 103: return createRegOperand(FLAT_SCR_HI); 1633 case 104: return createRegOperand(XNACK_MASK_LO); 1634 case 105: return createRegOperand(XNACK_MASK_HI); 1635 case 106: return createRegOperand(VCC_LO); 1636 case 107: return createRegOperand(VCC_HI); 1637 case 108: return createRegOperand(TBA_LO); 1638 case 109: return createRegOperand(TBA_HI); 1639 case 110: return createRegOperand(TMA_LO); 1640 case 111: return createRegOperand(TMA_HI); 1641 case 124: 1642 return isGFX11Plus() ? createRegOperand(SGPR_NULL) : createRegOperand(M0); 1643 case 125: 1644 return isGFX11Plus() ? createRegOperand(M0) : createRegOperand(SGPR_NULL); 1645 case 126: return createRegOperand(EXEC_LO); 1646 case 127: return createRegOperand(EXEC_HI); 1647 case 235: return createRegOperand(SRC_SHARED_BASE_LO); 1648 case 236: return createRegOperand(SRC_SHARED_LIMIT_LO); 1649 case 237: return createRegOperand(SRC_PRIVATE_BASE_LO); 1650 case 238: return createRegOperand(SRC_PRIVATE_LIMIT_LO); 1651 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1652 case 251: return createRegOperand(SRC_VCCZ); 1653 case 252: return createRegOperand(SRC_EXECZ); 1654 case 253: return createRegOperand(SRC_SCC); 1655 case 254: return createRegOperand(LDS_DIRECT); 1656 default: break; 1657 // clang-format on 1658 } 1659 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1660 } 1661 1662 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1663 using namespace AMDGPU; 1664 1665 switch (Val) { 1666 case 102: return createRegOperand(FLAT_SCR); 1667 case 104: return createRegOperand(XNACK_MASK); 1668 case 106: return createRegOperand(VCC); 1669 case 108: return createRegOperand(TBA); 1670 case 110: return createRegOperand(TMA); 1671 case 124: 1672 if (isGFX11Plus()) 1673 return createRegOperand(SGPR_NULL); 1674 break; 1675 case 125: 1676 if (!isGFX11Plus()) 1677 return createRegOperand(SGPR_NULL); 1678 break; 1679 case 126: return createRegOperand(EXEC); 1680 case 235: return createRegOperand(SRC_SHARED_BASE); 1681 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1682 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1683 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1684 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1685 case 251: return createRegOperand(SRC_VCCZ); 1686 case 252: return createRegOperand(SRC_EXECZ); 1687 case 253: return createRegOperand(SRC_SCC); 1688 default: break; 1689 } 1690 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1691 } 1692 1693 MCOperand 1694 AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, const unsigned Val, 1695 unsigned ImmWidth, 1696 AMDGPU::OperandSemantics Sema) const { 1697 using namespace AMDGPU::SDWA; 1698 using namespace AMDGPU::EncValues; 1699 1700 if (STI.hasFeature(AMDGPU::FeatureGFX9) || 1701 STI.hasFeature(AMDGPU::FeatureGFX10)) { 1702 // XXX: cast to int is needed to avoid stupid warning: 1703 // compare with unsigned is always true 1704 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1705 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1706 return createRegOperand(getVgprClassId(Width), 1707 Val - SDWA9EncValues::SRC_VGPR_MIN); 1708 } 1709 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1710 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1711 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1712 return createSRegOperand(getSgprClassId(Width), 1713 Val - SDWA9EncValues::SRC_SGPR_MIN); 1714 } 1715 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1716 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1717 return createSRegOperand(getTtmpClassId(Width), 1718 Val - SDWA9EncValues::SRC_TTMP_MIN); 1719 } 1720 1721 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1722 1723 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1724 return decodeIntImmed(SVal); 1725 1726 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1727 return decodeFPImmed(ImmWidth, SVal, Sema); 1728 1729 return decodeSpecialReg32(SVal); 1730 } 1731 if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) 1732 return createRegOperand(getVgprClassId(Width), Val); 1733 llvm_unreachable("unsupported target"); 1734 } 1735 1736 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1737 return decodeSDWASrc(OPW16, Val, 16, AMDGPU::OperandSemantics::FP16); 1738 } 1739 1740 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1741 return decodeSDWASrc(OPW32, Val, 32, AMDGPU::OperandSemantics::FP32); 1742 } 1743 1744 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1745 using namespace AMDGPU::SDWA; 1746 1747 assert((STI.hasFeature(AMDGPU::FeatureGFX9) || 1748 STI.hasFeature(AMDGPU::FeatureGFX10)) && 1749 "SDWAVopcDst should be present only on GFX9+"); 1750 1751 bool IsWave64 = STI.hasFeature(AMDGPU::FeatureWavefrontSize64); 1752 1753 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1754 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1755 1756 int TTmpIdx = getTTmpIdx(Val); 1757 if (TTmpIdx >= 0) { 1758 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1759 return createSRegOperand(TTmpClsId, TTmpIdx); 1760 } 1761 if (Val > SGPR_MAX) { 1762 return IsWave64 ? decodeSpecialReg64(Val) : decodeSpecialReg32(Val); 1763 } 1764 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1765 } 1766 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1767 } 1768 1769 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1770 return STI.hasFeature(AMDGPU::FeatureWavefrontSize64) 1771 ? decodeSrcOp(OPW64, Val) 1772 : decodeSrcOp(OPW32, Val); 1773 } 1774 1775 MCOperand AMDGPUDisassembler::decodeSplitBarrier(unsigned Val) const { 1776 return decodeSrcOp(OPW32, Val); 1777 } 1778 1779 MCOperand AMDGPUDisassembler::decodeDpp8FI(unsigned Val) const { 1780 if (Val != AMDGPU::DPP::DPP8_FI_0 && Val != AMDGPU::DPP::DPP8_FI_1) 1781 return MCOperand(); 1782 return MCOperand::createImm(Val); 1783 } 1784 1785 MCOperand AMDGPUDisassembler::decodeVersionImm(unsigned Imm) const { 1786 using VersionField = AMDGPU::EncodingField<7, 0>; 1787 using W64Bit = AMDGPU::EncodingBit<13>; 1788 using W32Bit = AMDGPU::EncodingBit<14>; 1789 using MDPBit = AMDGPU::EncodingBit<15>; 1790 using Encoding = AMDGPU::EncodingFields<VersionField, W64Bit, W32Bit, MDPBit>; 1791 1792 auto [Version, W64, W32, MDP] = Encoding::decode(Imm); 1793 1794 // Decode into a plain immediate if any unused bits are raised. 1795 if (Encoding::encode(Version, W64, W32, MDP) != Imm) 1796 return MCOperand::createImm(Imm); 1797 1798 const auto &Versions = AMDGPU::UCVersion::getGFXVersions(); 1799 const auto *I = find_if( 1800 Versions, [Version = Version](const AMDGPU::UCVersion::GFXVersion &V) { 1801 return V.Code == Version; 1802 }); 1803 MCContext &Ctx = getContext(); 1804 const MCExpr *E; 1805 if (I == Versions.end()) 1806 E = MCConstantExpr::create(Version, Ctx); 1807 else 1808 E = MCSymbolRefExpr::create(Ctx.getOrCreateSymbol(I->Symbol), Ctx); 1809 1810 if (W64) 1811 E = MCBinaryExpr::createOr(E, UCVersionW64Expr, Ctx); 1812 if (W32) 1813 E = MCBinaryExpr::createOr(E, UCVersionW32Expr, Ctx); 1814 if (MDP) 1815 E = MCBinaryExpr::createOr(E, UCVersionMDPExpr, Ctx); 1816 1817 return MCOperand::createExpr(E); 1818 } 1819 1820 bool AMDGPUDisassembler::isVI() const { 1821 return STI.hasFeature(AMDGPU::FeatureVolcanicIslands); 1822 } 1823 1824 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } 1825 1826 bool AMDGPUDisassembler::isGFX90A() const { 1827 return STI.hasFeature(AMDGPU::FeatureGFX90AInsts); 1828 } 1829 1830 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } 1831 1832 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } 1833 1834 bool AMDGPUDisassembler::isGFX10Plus() const { 1835 return AMDGPU::isGFX10Plus(STI); 1836 } 1837 1838 bool AMDGPUDisassembler::isGFX11() const { 1839 return STI.hasFeature(AMDGPU::FeatureGFX11); 1840 } 1841 1842 bool AMDGPUDisassembler::isGFX11Plus() const { 1843 return AMDGPU::isGFX11Plus(STI); 1844 } 1845 1846 bool AMDGPUDisassembler::isGFX12() const { 1847 return STI.hasFeature(AMDGPU::FeatureGFX12); 1848 } 1849 1850 bool AMDGPUDisassembler::isGFX12Plus() const { 1851 return AMDGPU::isGFX12Plus(STI); 1852 } 1853 1854 bool AMDGPUDisassembler::hasArchitectedFlatScratch() const { 1855 return STI.hasFeature(AMDGPU::FeatureArchitectedFlatScratch); 1856 } 1857 1858 bool AMDGPUDisassembler::hasKernargPreload() const { 1859 return AMDGPU::hasKernargPreload(STI); 1860 } 1861 1862 //===----------------------------------------------------------------------===// 1863 // AMDGPU specific symbol handling 1864 //===----------------------------------------------------------------------===// 1865 1866 /// Print a string describing the reserved bit range specified by Mask with 1867 /// offset BaseBytes for use in error comments. Mask is a single continuous 1868 /// range of 1s surrounded by zeros. The format here is meant to align with the 1869 /// tables that describe these bits in llvm.org/docs/AMDGPUUsage.html. 1870 static SmallString<32> getBitRangeFromMask(uint32_t Mask, unsigned BaseBytes) { 1871 SmallString<32> Result; 1872 raw_svector_ostream S(Result); 1873 1874 int TrailingZeros = llvm::countr_zero(Mask); 1875 int PopCount = llvm::popcount(Mask); 1876 1877 if (PopCount == 1) { 1878 S << "bit (" << (TrailingZeros + BaseBytes * CHAR_BIT) << ')'; 1879 } else { 1880 S << "bits in range (" 1881 << (TrailingZeros + PopCount - 1 + BaseBytes * CHAR_BIT) << ':' 1882 << (TrailingZeros + BaseBytes * CHAR_BIT) << ')'; 1883 } 1884 1885 return Result; 1886 } 1887 1888 #define GET_FIELD(MASK) (AMDHSA_BITS_GET(FourByteBuffer, MASK)) 1889 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1890 do { \ 1891 KdStream << Indent << DIRECTIVE " " << GET_FIELD(MASK) << '\n'; \ 1892 } while (0) 1893 #define PRINT_PSEUDO_DIRECTIVE_COMMENT(DIRECTIVE, MASK) \ 1894 do { \ 1895 KdStream << Indent << MAI.getCommentString() << ' ' << DIRECTIVE " " \ 1896 << GET_FIELD(MASK) << '\n'; \ 1897 } while (0) 1898 1899 #define CHECK_RESERVED_BITS_IMPL(MASK, DESC, MSG) \ 1900 do { \ 1901 if (FourByteBuffer & (MASK)) { \ 1902 return createStringError(std::errc::invalid_argument, \ 1903 "kernel descriptor " DESC \ 1904 " reserved %s set" MSG, \ 1905 getBitRangeFromMask((MASK), 0).c_str()); \ 1906 } \ 1907 } while (0) 1908 1909 #define CHECK_RESERVED_BITS(MASK) CHECK_RESERVED_BITS_IMPL(MASK, #MASK, "") 1910 #define CHECK_RESERVED_BITS_MSG(MASK, MSG) \ 1911 CHECK_RESERVED_BITS_IMPL(MASK, #MASK, ", " MSG) 1912 #define CHECK_RESERVED_BITS_DESC(MASK, DESC) \ 1913 CHECK_RESERVED_BITS_IMPL(MASK, DESC, "") 1914 #define CHECK_RESERVED_BITS_DESC_MSG(MASK, DESC, MSG) \ 1915 CHECK_RESERVED_BITS_IMPL(MASK, DESC, ", " MSG) 1916 1917 // NOLINTNEXTLINE(readability-identifier-naming) 1918 Expected<bool> AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1919 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1920 using namespace amdhsa; 1921 StringRef Indent = "\t"; 1922 1923 // We cannot accurately backward compute #VGPRs used from 1924 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1925 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1926 // simply calculate the inverse of what the assembler does. 1927 1928 uint32_t GranulatedWorkitemVGPRCount = 1929 GET_FIELD(COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT); 1930 1931 uint32_t NextFreeVGPR = 1932 (GranulatedWorkitemVGPRCount + 1) * 1933 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI, EnableWavefrontSize32); 1934 1935 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1936 1937 // We cannot backward compute values used to calculate 1938 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1939 // directives can't be computed: 1940 // .amdhsa_reserve_vcc 1941 // .amdhsa_reserve_flat_scratch 1942 // .amdhsa_reserve_xnack_mask 1943 // They take their respective default values if not specified in the assembly. 1944 // 1945 // GRANULATED_WAVEFRONT_SGPR_COUNT 1946 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1947 // 1948 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1949 // are set to 0. So while disassembling we consider that: 1950 // 1951 // GRANULATED_WAVEFRONT_SGPR_COUNT 1952 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1953 // 1954 // The disassembler cannot recover the original values of those 3 directives. 1955 1956 uint32_t GranulatedWavefrontSGPRCount = 1957 GET_FIELD(COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT); 1958 1959 if (isGFX10Plus()) 1960 CHECK_RESERVED_BITS_MSG(COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT, 1961 "must be zero on gfx10+"); 1962 1963 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1964 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1965 1966 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1967 if (!hasArchitectedFlatScratch()) 1968 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1969 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1970 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1971 1972 CHECK_RESERVED_BITS(COMPUTE_PGM_RSRC1_PRIORITY); 1973 1974 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1975 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1976 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1977 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1978 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1979 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1980 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1981 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1982 1983 CHECK_RESERVED_BITS(COMPUTE_PGM_RSRC1_PRIV); 1984 1985 if (!isGFX12Plus()) 1986 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", 1987 COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP); 1988 1989 CHECK_RESERVED_BITS(COMPUTE_PGM_RSRC1_DEBUG_MODE); 1990 1991 if (!isGFX12Plus()) 1992 PRINT_DIRECTIVE(".amdhsa_ieee_mode", 1993 COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE); 1994 1995 CHECK_RESERVED_BITS(COMPUTE_PGM_RSRC1_BULKY); 1996 CHECK_RESERVED_BITS(COMPUTE_PGM_RSRC1_CDBG_USER); 1997 1998 if (isGFX9Plus()) 1999 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL); 2000 2001 if (!isGFX9Plus()) 2002 CHECK_RESERVED_BITS_DESC_MSG(COMPUTE_PGM_RSRC1_GFX6_GFX8_RESERVED0, 2003 "COMPUTE_PGM_RSRC1", "must be zero pre-gfx9"); 2004 2005 CHECK_RESERVED_BITS_DESC(COMPUTE_PGM_RSRC1_RESERVED1, "COMPUTE_PGM_RSRC1"); 2006 2007 if (!isGFX10Plus()) 2008 CHECK_RESERVED_BITS_DESC_MSG(COMPUTE_PGM_RSRC1_GFX6_GFX9_RESERVED2, 2009 "COMPUTE_PGM_RSRC1", "must be zero pre-gfx10"); 2010 2011 if (isGFX10Plus()) { 2012 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 2013 COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE); 2014 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED); 2015 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS); 2016 } 2017 2018 if (isGFX12Plus()) 2019 PRINT_DIRECTIVE(".amdhsa_round_robin_scheduling", 2020 COMPUTE_PGM_RSRC1_GFX12_PLUS_ENABLE_WG_RR_EN); 2021 2022 return true; 2023 } 2024 2025 // NOLINTNEXTLINE(readability-identifier-naming) 2026 Expected<bool> AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 2027 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 2028 using namespace amdhsa; 2029 StringRef Indent = "\t"; 2030 if (hasArchitectedFlatScratch()) 2031 PRINT_DIRECTIVE(".amdhsa_enable_private_segment", 2032 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 2033 else 2034 PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset", 2035 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 2036 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 2037 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 2038 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 2039 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 2040 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 2041 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 2042 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 2043 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 2044 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 2045 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 2046 2047 CHECK_RESERVED_BITS(COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH); 2048 CHECK_RESERVED_BITS(COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY); 2049 CHECK_RESERVED_BITS(COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE); 2050 2051 PRINT_DIRECTIVE( 2052 ".amdhsa_exception_fp_ieee_invalid_op", 2053 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 2054 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 2055 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 2056 PRINT_DIRECTIVE( 2057 ".amdhsa_exception_fp_ieee_div_zero", 2058 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 2059 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 2060 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 2061 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 2062 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 2063 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 2064 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 2065 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 2066 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 2067 2068 CHECK_RESERVED_BITS_DESC(COMPUTE_PGM_RSRC2_RESERVED0, "COMPUTE_PGM_RSRC2"); 2069 2070 return true; 2071 } 2072 2073 // NOLINTNEXTLINE(readability-identifier-naming) 2074 Expected<bool> AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC3( 2075 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 2076 using namespace amdhsa; 2077 StringRef Indent = "\t"; 2078 if (isGFX90A()) { 2079 KdStream << Indent << ".amdhsa_accum_offset " 2080 << (GET_FIELD(COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET) + 1) * 4 2081 << '\n'; 2082 2083 PRINT_DIRECTIVE(".amdhsa_tg_split", COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT); 2084 2085 CHECK_RESERVED_BITS_DESC_MSG(COMPUTE_PGM_RSRC3_GFX90A_RESERVED0, 2086 "COMPUTE_PGM_RSRC3", "must be zero on gfx90a"); 2087 CHECK_RESERVED_BITS_DESC_MSG(COMPUTE_PGM_RSRC3_GFX90A_RESERVED1, 2088 "COMPUTE_PGM_RSRC3", "must be zero on gfx90a"); 2089 } else if (isGFX10Plus()) { 2090 // Bits [0-3]. 2091 if (!isGFX12Plus()) { 2092 if (!EnableWavefrontSize32 || !*EnableWavefrontSize32) { 2093 PRINT_DIRECTIVE(".amdhsa_shared_vgpr_count", 2094 COMPUTE_PGM_RSRC3_GFX10_GFX11_SHARED_VGPR_COUNT); 2095 } else { 2096 PRINT_PSEUDO_DIRECTIVE_COMMENT( 2097 "SHARED_VGPR_COUNT", 2098 COMPUTE_PGM_RSRC3_GFX10_GFX11_SHARED_VGPR_COUNT); 2099 } 2100 } else { 2101 CHECK_RESERVED_BITS_DESC_MSG(COMPUTE_PGM_RSRC3_GFX12_PLUS_RESERVED0, 2102 "COMPUTE_PGM_RSRC3", 2103 "must be zero on gfx12+"); 2104 } 2105 2106 // Bits [4-11]. 2107 if (isGFX11()) { 2108 PRINT_PSEUDO_DIRECTIVE_COMMENT("INST_PREF_SIZE", 2109 COMPUTE_PGM_RSRC3_GFX11_INST_PREF_SIZE); 2110 PRINT_PSEUDO_DIRECTIVE_COMMENT("TRAP_ON_START", 2111 COMPUTE_PGM_RSRC3_GFX11_TRAP_ON_START); 2112 PRINT_PSEUDO_DIRECTIVE_COMMENT("TRAP_ON_END", 2113 COMPUTE_PGM_RSRC3_GFX11_TRAP_ON_END); 2114 } else if (isGFX12Plus()) { 2115 PRINT_PSEUDO_DIRECTIVE_COMMENT( 2116 "INST_PREF_SIZE", COMPUTE_PGM_RSRC3_GFX12_PLUS_INST_PREF_SIZE); 2117 } else { 2118 CHECK_RESERVED_BITS_DESC_MSG(COMPUTE_PGM_RSRC3_GFX10_RESERVED1, 2119 "COMPUTE_PGM_RSRC3", 2120 "must be zero on gfx10"); 2121 } 2122 2123 // Bits [12]. 2124 CHECK_RESERVED_BITS_DESC_MSG(COMPUTE_PGM_RSRC3_GFX10_PLUS_RESERVED2, 2125 "COMPUTE_PGM_RSRC3", "must be zero on gfx10+"); 2126 2127 // Bits [13]. 2128 if (isGFX12Plus()) { 2129 PRINT_PSEUDO_DIRECTIVE_COMMENT("GLG_EN", 2130 COMPUTE_PGM_RSRC3_GFX12_PLUS_GLG_EN); 2131 } else { 2132 CHECK_RESERVED_BITS_DESC_MSG(COMPUTE_PGM_RSRC3_GFX10_GFX11_RESERVED3, 2133 "COMPUTE_PGM_RSRC3", 2134 "must be zero on gfx10 or gfx11"); 2135 } 2136 2137 // Bits [14-30]. 2138 CHECK_RESERVED_BITS_DESC_MSG(COMPUTE_PGM_RSRC3_GFX10_PLUS_RESERVED4, 2139 "COMPUTE_PGM_RSRC3", "must be zero on gfx10+"); 2140 2141 // Bits [31]. 2142 if (isGFX11Plus()) { 2143 PRINT_PSEUDO_DIRECTIVE_COMMENT("IMAGE_OP", 2144 COMPUTE_PGM_RSRC3_GFX11_PLUS_IMAGE_OP); 2145 } else { 2146 CHECK_RESERVED_BITS_DESC_MSG(COMPUTE_PGM_RSRC3_GFX10_RESERVED5, 2147 "COMPUTE_PGM_RSRC3", 2148 "must be zero on gfx10"); 2149 } 2150 } else if (FourByteBuffer) { 2151 return createStringError( 2152 std::errc::invalid_argument, 2153 "kernel descriptor COMPUTE_PGM_RSRC3 must be all zero before gfx9"); 2154 } 2155 return true; 2156 } 2157 #undef PRINT_PSEUDO_DIRECTIVE_COMMENT 2158 #undef PRINT_DIRECTIVE 2159 #undef GET_FIELD 2160 #undef CHECK_RESERVED_BITS_IMPL 2161 #undef CHECK_RESERVED_BITS 2162 #undef CHECK_RESERVED_BITS_MSG 2163 #undef CHECK_RESERVED_BITS_DESC 2164 #undef CHECK_RESERVED_BITS_DESC_MSG 2165 2166 /// Create an error object to return from onSymbolStart for reserved kernel 2167 /// descriptor bits being set. 2168 static Error createReservedKDBitsError(uint32_t Mask, unsigned BaseBytes, 2169 const char *Msg = "") { 2170 return createStringError( 2171 std::errc::invalid_argument, "kernel descriptor reserved %s set%s%s", 2172 getBitRangeFromMask(Mask, BaseBytes).c_str(), *Msg ? ", " : "", Msg); 2173 } 2174 2175 /// Create an error object to return from onSymbolStart for reserved kernel 2176 /// descriptor bytes being set. 2177 static Error createReservedKDBytesError(unsigned BaseInBytes, 2178 unsigned WidthInBytes) { 2179 // Create an error comment in the same format as the "Kernel Descriptor" 2180 // table here: https://llvm.org/docs/AMDGPUUsage.html#kernel-descriptor . 2181 return createStringError( 2182 std::errc::invalid_argument, 2183 "kernel descriptor reserved bits in range (%u:%u) set", 2184 (BaseInBytes + WidthInBytes) * CHAR_BIT - 1, BaseInBytes * CHAR_BIT); 2185 } 2186 2187 Expected<bool> AMDGPUDisassembler::decodeKernelDescriptorDirective( 2188 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 2189 raw_string_ostream &KdStream) const { 2190 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 2191 do { \ 2192 KdStream << Indent << DIRECTIVE " " \ 2193 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 2194 } while (0) 2195 2196 uint16_t TwoByteBuffer = 0; 2197 uint32_t FourByteBuffer = 0; 2198 2199 StringRef ReservedBytes; 2200 StringRef Indent = "\t"; 2201 2202 assert(Bytes.size() == 64); 2203 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 2204 2205 switch (Cursor.tell()) { 2206 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 2207 FourByteBuffer = DE.getU32(Cursor); 2208 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 2209 << '\n'; 2210 return true; 2211 2212 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 2213 FourByteBuffer = DE.getU32(Cursor); 2214 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 2215 << FourByteBuffer << '\n'; 2216 return true; 2217 2218 case amdhsa::KERNARG_SIZE_OFFSET: 2219 FourByteBuffer = DE.getU32(Cursor); 2220 KdStream << Indent << ".amdhsa_kernarg_size " 2221 << FourByteBuffer << '\n'; 2222 return true; 2223 2224 case amdhsa::RESERVED0_OFFSET: 2225 // 4 reserved bytes, must be 0. 2226 ReservedBytes = DE.getBytes(Cursor, 4); 2227 for (int I = 0; I < 4; ++I) { 2228 if (ReservedBytes[I] != 0) 2229 return createReservedKDBytesError(amdhsa::RESERVED0_OFFSET, 4); 2230 } 2231 return true; 2232 2233 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 2234 // KERNEL_CODE_ENTRY_BYTE_OFFSET 2235 // So far no directive controls this for Code Object V3, so simply skip for 2236 // disassembly. 2237 DE.skip(Cursor, 8); 2238 return true; 2239 2240 case amdhsa::RESERVED1_OFFSET: 2241 // 20 reserved bytes, must be 0. 2242 ReservedBytes = DE.getBytes(Cursor, 20); 2243 for (int I = 0; I < 20; ++I) { 2244 if (ReservedBytes[I] != 0) 2245 return createReservedKDBytesError(amdhsa::RESERVED1_OFFSET, 20); 2246 } 2247 return true; 2248 2249 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 2250 FourByteBuffer = DE.getU32(Cursor); 2251 return decodeCOMPUTE_PGM_RSRC3(FourByteBuffer, KdStream); 2252 2253 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 2254 FourByteBuffer = DE.getU32(Cursor); 2255 return decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream); 2256 2257 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 2258 FourByteBuffer = DE.getU32(Cursor); 2259 return decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream); 2260 2261 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 2262 using namespace amdhsa; 2263 TwoByteBuffer = DE.getU16(Cursor); 2264 2265 if (!hasArchitectedFlatScratch()) 2266 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 2267 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 2268 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 2269 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 2270 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 2271 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 2272 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 2273 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 2274 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 2275 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 2276 if (!hasArchitectedFlatScratch()) 2277 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 2278 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 2279 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 2280 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 2281 2282 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 2283 return createReservedKDBitsError(KERNEL_CODE_PROPERTY_RESERVED0, 2284 amdhsa::KERNEL_CODE_PROPERTIES_OFFSET); 2285 2286 // Reserved for GFX9 2287 if (isGFX9() && 2288 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 2289 return createReservedKDBitsError( 2290 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32, 2291 amdhsa::KERNEL_CODE_PROPERTIES_OFFSET, "must be zero on gfx9"); 2292 } 2293 if (isGFX10Plus()) { 2294 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 2295 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 2296 } 2297 2298 if (CodeObjectVersion >= AMDGPU::AMDHSA_COV5) 2299 PRINT_DIRECTIVE(".amdhsa_uses_dynamic_stack", 2300 KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK); 2301 2302 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) { 2303 return createReservedKDBitsError(KERNEL_CODE_PROPERTY_RESERVED1, 2304 amdhsa::KERNEL_CODE_PROPERTIES_OFFSET); 2305 } 2306 2307 return true; 2308 2309 case amdhsa::KERNARG_PRELOAD_OFFSET: 2310 using namespace amdhsa; 2311 TwoByteBuffer = DE.getU16(Cursor); 2312 if (TwoByteBuffer & KERNARG_PRELOAD_SPEC_LENGTH) { 2313 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_preload_length", 2314 KERNARG_PRELOAD_SPEC_LENGTH); 2315 } 2316 2317 if (TwoByteBuffer & KERNARG_PRELOAD_SPEC_OFFSET) { 2318 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_preload_offset", 2319 KERNARG_PRELOAD_SPEC_OFFSET); 2320 } 2321 return true; 2322 2323 case amdhsa::RESERVED3_OFFSET: 2324 // 4 bytes from here are reserved, must be 0. 2325 ReservedBytes = DE.getBytes(Cursor, 4); 2326 for (int I = 0; I < 4; ++I) { 2327 if (ReservedBytes[I] != 0) 2328 return createReservedKDBytesError(amdhsa::RESERVED3_OFFSET, 4); 2329 } 2330 return true; 2331 2332 default: 2333 llvm_unreachable("Unhandled index. Case statements cover everything."); 2334 return true; 2335 } 2336 #undef PRINT_DIRECTIVE 2337 } 2338 2339 Expected<bool> AMDGPUDisassembler::decodeKernelDescriptor( 2340 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 2341 2342 // CP microcode requires the kernel descriptor to be 64 aligned. 2343 if (Bytes.size() != 64 || KdAddress % 64 != 0) 2344 return createStringError(std::errc::invalid_argument, 2345 "kernel descriptor must be 64-byte aligned"); 2346 2347 // FIXME: We can't actually decode "in order" as is done below, as e.g. GFX10 2348 // requires us to know the setting of .amdhsa_wavefront_size32 in order to 2349 // accurately produce .amdhsa_next_free_vgpr, and they appear in the wrong 2350 // order. Workaround this by first looking up .amdhsa_wavefront_size32 here 2351 // when required. 2352 if (isGFX10Plus()) { 2353 uint16_t KernelCodeProperties = 2354 support::endian::read16(&Bytes[amdhsa::KERNEL_CODE_PROPERTIES_OFFSET], 2355 llvm::endianness::little); 2356 EnableWavefrontSize32 = 2357 AMDHSA_BITS_GET(KernelCodeProperties, 2358 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 2359 } 2360 2361 std::string Kd; 2362 raw_string_ostream KdStream(Kd); 2363 KdStream << ".amdhsa_kernel " << KdName << '\n'; 2364 2365 DataExtractor::Cursor C(0); 2366 while (C && C.tell() < Bytes.size()) { 2367 Expected<bool> Res = decodeKernelDescriptorDirective(C, Bytes, KdStream); 2368 2369 cantFail(C.takeError()); 2370 2371 if (!Res) 2372 return Res; 2373 } 2374 KdStream << ".end_amdhsa_kernel\n"; 2375 outs() << KdStream.str(); 2376 return true; 2377 } 2378 2379 Expected<bool> AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, 2380 uint64_t &Size, 2381 ArrayRef<uint8_t> Bytes, 2382 uint64_t Address) const { 2383 // Right now only kernel descriptor needs to be handled. 2384 // We ignore all other symbols for target specific handling. 2385 // TODO: 2386 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 2387 // Object V2 and V3 when symbols are marked protected. 2388 2389 // amd_kernel_code_t for Code Object V2. 2390 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 2391 Size = 256; 2392 return createStringError(std::errc::invalid_argument, 2393 "code object v2 is not supported"); 2394 } 2395 2396 // Code Object V3 kernel descriptors. 2397 StringRef Name = Symbol.Name; 2398 if (Symbol.Type == ELF::STT_OBJECT && Name.ends_with(StringRef(".kd"))) { 2399 Size = 64; // Size = 64 regardless of success or failure. 2400 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 2401 } 2402 2403 return false; 2404 } 2405 2406 const MCExpr *AMDGPUDisassembler::createConstantSymbolExpr(StringRef Id, 2407 int64_t Val) { 2408 MCContext &Ctx = getContext(); 2409 MCSymbol *Sym = Ctx.getOrCreateSymbol(Id); 2410 // Note: only set value to Val on a new symbol in case an dissassembler 2411 // has already been initialized in this context. 2412 if (!Sym->isVariable()) { 2413 Sym->setVariableValue(MCConstantExpr::create(Val, Ctx)); 2414 } else { 2415 int64_t Res = ~Val; 2416 bool Valid = Sym->getVariableValue()->evaluateAsAbsolute(Res); 2417 if (!Valid || Res != Val) 2418 Ctx.reportWarning(SMLoc(), "unsupported redefinition of " + Id); 2419 } 2420 return MCSymbolRefExpr::create(Sym, Ctx); 2421 } 2422 2423 //===----------------------------------------------------------------------===// 2424 // AMDGPUSymbolizer 2425 //===----------------------------------------------------------------------===// 2426 2427 // Try to find symbol name for specified label 2428 bool AMDGPUSymbolizer::tryAddingSymbolicOperand( 2429 MCInst &Inst, raw_ostream & /*cStream*/, int64_t Value, 2430 uint64_t /*Address*/, bool IsBranch, uint64_t /*Offset*/, 2431 uint64_t /*OpSize*/, uint64_t /*InstSize*/) { 2432 2433 if (!IsBranch) { 2434 return false; 2435 } 2436 2437 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 2438 if (!Symbols) 2439 return false; 2440 2441 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { 2442 return Val.Addr == static_cast<uint64_t>(Value) && 2443 Val.Type == ELF::STT_NOTYPE; 2444 }); 2445 if (Result != Symbols->end()) { 2446 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 2447 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 2448 Inst.addOperand(MCOperand::createExpr(Add)); 2449 return true; 2450 } 2451 // Add to list of referenced addresses, so caller can synthesize a label. 2452 ReferencedAddresses.push_back(static_cast<uint64_t>(Value)); 2453 return false; 2454 } 2455 2456 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 2457 int64_t Value, 2458 uint64_t Address) { 2459 llvm_unreachable("unimplemented"); 2460 } 2461 2462 //===----------------------------------------------------------------------===// 2463 // Initialization 2464 //===----------------------------------------------------------------------===// 2465 2466 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 2467 LLVMOpInfoCallback /*GetOpInfo*/, 2468 LLVMSymbolLookupCallback /*SymbolLookUp*/, 2469 void *DisInfo, 2470 MCContext *Ctx, 2471 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 2472 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 2473 } 2474 2475 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 2476 const MCSubtargetInfo &STI, 2477 MCContext &Ctx) { 2478 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 2479 } 2480 2481 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 2482 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 2483 createAMDGPUDisassembler); 2484 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 2485 createAMDGPUSymbolizer); 2486 } 2487