1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "SIDefines.h" 22 #include "SIRegisterInfo.h" 23 #include "TargetInfo/AMDGPUTargetInfo.h" 24 #include "Utils/AMDGPUBaseInfo.h" 25 #include "llvm-c/DisassemblerTypes.h" 26 #include "llvm/BinaryFormat/ELF.h" 27 #include "llvm/MC/MCAsmInfo.h" 28 #include "llvm/MC/MCContext.h" 29 #include "llvm/MC/MCDecoderOps.h" 30 #include "llvm/MC/MCExpr.h" 31 #include "llvm/MC/MCInstrDesc.h" 32 #include "llvm/MC/MCRegisterInfo.h" 33 #include "llvm/MC/MCSubtargetInfo.h" 34 #include "llvm/MC/TargetRegistry.h" 35 #include "llvm/Support/AMDHSAKernelDescriptor.h" 36 37 using namespace llvm; 38 39 #define DEBUG_TYPE "amdgpu-disassembler" 40 41 #define SGPR_MAX \ 42 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 43 : AMDGPU::EncValues::SGPR_MAX_SI) 44 45 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 46 47 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 48 MCContext &Ctx, MCInstrInfo const *MCII) 49 : MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), 50 MAI(*Ctx.getAsmInfo()), TargetMaxInstBytes(MAI.getMaxInstLength(&STI)) { 51 // ToDo: AMDGPUDisassembler supports only VI ISA. 52 if (!STI.hasFeature(AMDGPU::FeatureGCN3Encoding) && !isGFX10Plus()) 53 report_fatal_error("Disassembly not yet supported for subtarget"); 54 } 55 56 inline static MCDisassembler::DecodeStatus 57 addOperand(MCInst &Inst, const MCOperand& Opnd) { 58 Inst.addOperand(Opnd); 59 return Opnd.isValid() ? 60 MCDisassembler::Success : 61 MCDisassembler::Fail; 62 } 63 64 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 65 uint16_t NameIdx) { 66 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 67 if (OpIdx != -1) { 68 auto I = MI.begin(); 69 std::advance(I, OpIdx); 70 MI.insert(I, Op); 71 } 72 return OpIdx; 73 } 74 75 static DecodeStatus decodeSOPPBrTarget(MCInst &Inst, unsigned Imm, 76 uint64_t Addr, 77 const MCDisassembler *Decoder) { 78 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 79 80 // Our branches take a simm16, but we need two extra bits to account for the 81 // factor of 4. 82 APInt SignedOffset(18, Imm * 4, true); 83 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 84 85 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2, 0)) 86 return MCDisassembler::Success; 87 return addOperand(Inst, MCOperand::createImm(Imm)); 88 } 89 90 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, 91 const MCDisassembler *Decoder) { 92 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 93 int64_t Offset; 94 if (DAsm->isGFX12Plus()) { // GFX12 supports 24-bit signed offsets. 95 Offset = SignExtend64<24>(Imm); 96 } else if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 97 Offset = Imm & 0xFFFFF; 98 } else { // GFX9+ supports 21-bit signed offsets. 99 Offset = SignExtend64<21>(Imm); 100 } 101 return addOperand(Inst, MCOperand::createImm(Offset)); 102 } 103 104 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, 105 const MCDisassembler *Decoder) { 106 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 107 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 108 } 109 110 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 111 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \ 112 uint64_t /*Addr*/, \ 113 const MCDisassembler *Decoder) { \ 114 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 115 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 116 } 117 118 // Decoder for registers, decode directly using RegClassID. Imm(8-bit) is 119 // number of register. Used by VGPR only and AGPR only operands. 120 #define DECODE_OPERAND_REG_8(RegClass) \ 121 static DecodeStatus Decode##RegClass##RegisterClass( \ 122 MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \ 123 const MCDisassembler *Decoder) { \ 124 assert(Imm < (1 << 8) && "8-bit encoding"); \ 125 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 126 return addOperand( \ 127 Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm)); \ 128 } 129 130 #define DECODE_SrcOp(Name, EncSize, OpWidth, EncImm, MandatoryLiteral, \ 131 ImmWidth) \ 132 static DecodeStatus Name(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \ 133 const MCDisassembler *Decoder) { \ 134 assert(Imm < (1 << EncSize) && #EncSize "-bit encoding"); \ 135 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 136 return addOperand(Inst, \ 137 DAsm->decodeSrcOp(AMDGPUDisassembler::OpWidth, EncImm, \ 138 MandatoryLiteral, ImmWidth)); \ 139 } 140 141 // Decoder for registers. Imm(7-bit) is number of register, uses decodeSrcOp to 142 // get register class. Used by SGPR only operands. 143 #define DECODE_OPERAND_REG_7(RegClass, OpWidth) \ 144 DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0) 145 146 // Decoder for registers. Imm(10-bit): Imm{7-0} is number of register, 147 // Imm{9} is acc(agpr or vgpr) Imm{8} should be 0 (see VOP3Pe_SMFMAC). 148 // Set Imm{8} to 1 (IS_VGPR) to decode using 'enum10' from decodeSrcOp. 149 // Used by AV_ register classes (AGPR or VGPR only register operands). 150 #define DECODE_OPERAND_REG_AV10(RegClass, OpWidth) \ 151 DECODE_SrcOp(Decode##RegClass##RegisterClass, 10, OpWidth, \ 152 Imm | AMDGPU::EncValues::IS_VGPR, false, 0) 153 154 // Decoder for Src(9-bit encoding) registers only. 155 #define DECODE_OPERAND_SRC_REG_9(RegClass, OpWidth) \ 156 DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm, false, 0) 157 158 // Decoder for Src(9-bit encoding) AGPR, register number encoded in 9bits, set 159 // Imm{9} to 1 (set acc) and decode using 'enum10' from decodeSrcOp, registers 160 // only. 161 #define DECODE_OPERAND_SRC_REG_A9(RegClass, OpWidth) \ 162 DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm | 512, false, 0) 163 164 // Decoder for 'enum10' from decodeSrcOp, Imm{0-8} is 9-bit Src encoding 165 // Imm{9} is acc, registers only. 166 #define DECODE_SRC_OPERAND_REG_AV10(RegClass, OpWidth) \ 167 DECODE_SrcOp(decodeOperand_##RegClass, 10, OpWidth, Imm, false, 0) 168 169 // Decoder for RegisterOperands using 9-bit Src encoding. Operand can be 170 // register from RegClass or immediate. Registers that don't belong to RegClass 171 // will be decoded and InstPrinter will report warning. Immediate will be 172 // decoded into constant of size ImmWidth, should match width of immediate used 173 // by OperandType (important for floating point types). 174 #define DECODE_OPERAND_SRC_REG_OR_IMM_9(RegClass, OpWidth, ImmWidth) \ 175 DECODE_SrcOp(decodeOperand_##RegClass##_Imm##ImmWidth, 9, OpWidth, Imm, \ 176 false, ImmWidth) 177 178 // Decoder for Src(9-bit encoding) AGPR or immediate. Set Imm{9} to 1 (set acc) 179 // and decode using 'enum10' from decodeSrcOp. 180 #define DECODE_OPERAND_SRC_REG_OR_IMM_A9(RegClass, OpWidth, ImmWidth) \ 181 DECODE_SrcOp(decodeOperand_##RegClass##_Imm##ImmWidth, 9, OpWidth, \ 182 Imm | 512, false, ImmWidth) 183 184 #define DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(RegClass, OpWidth, ImmWidth) \ 185 DECODE_SrcOp(decodeOperand_##RegClass##_Deferred##_Imm##ImmWidth, 9, \ 186 OpWidth, Imm, true, ImmWidth) 187 188 // Default decoders generated by tablegen: 'Decode<RegClass>RegisterClass' 189 // when RegisterClass is used as an operand. Most often used for destination 190 // operands. 191 192 DECODE_OPERAND_REG_8(VGPR_32) 193 DECODE_OPERAND_REG_8(VGPR_32_Lo128) 194 DECODE_OPERAND_REG_8(VReg_64) 195 DECODE_OPERAND_REG_8(VReg_96) 196 DECODE_OPERAND_REG_8(VReg_128) 197 DECODE_OPERAND_REG_8(VReg_256) 198 DECODE_OPERAND_REG_8(VReg_288) 199 DECODE_OPERAND_REG_8(VReg_352) 200 DECODE_OPERAND_REG_8(VReg_384) 201 DECODE_OPERAND_REG_8(VReg_512) 202 DECODE_OPERAND_REG_8(VReg_1024) 203 204 DECODE_OPERAND_REG_7(SReg_32, OPW32) 205 DECODE_OPERAND_REG_7(SReg_32_XM0_XEXEC, OPW32) 206 DECODE_OPERAND_REG_7(SReg_32_XEXEC_HI, OPW32) 207 DECODE_OPERAND_REG_7(SReg_64, OPW64) 208 DECODE_OPERAND_REG_7(SReg_64_XEXEC, OPW64) 209 DECODE_OPERAND_REG_7(SReg_128, OPW128) 210 DECODE_OPERAND_REG_7(SReg_256, OPW256) 211 DECODE_OPERAND_REG_7(SReg_512, OPW512) 212 213 DECODE_OPERAND_REG_8(AGPR_32) 214 DECODE_OPERAND_REG_8(AReg_64) 215 DECODE_OPERAND_REG_8(AReg_128) 216 DECODE_OPERAND_REG_8(AReg_256) 217 DECODE_OPERAND_REG_8(AReg_512) 218 DECODE_OPERAND_REG_8(AReg_1024) 219 220 DECODE_OPERAND_REG_AV10(AVDst_128, OPW128) 221 DECODE_OPERAND_REG_AV10(AVDst_512, OPW512) 222 223 // Decoders for register only source RegisterOperands that use use 9-bit Src 224 // encoding: 'decodeOperand_<RegClass>'. 225 226 DECODE_OPERAND_SRC_REG_9(VGPR_32, OPW32) 227 DECODE_OPERAND_SRC_REG_9(VReg_64, OPW64) 228 DECODE_OPERAND_SRC_REG_9(VReg_128, OPW128) 229 DECODE_OPERAND_SRC_REG_9(VReg_256, OPW256) 230 DECODE_OPERAND_SRC_REG_9(VRegOrLds_32, OPW32) 231 232 DECODE_OPERAND_SRC_REG_A9(AGPR_32, OPW32) 233 234 DECODE_SRC_OPERAND_REG_AV10(AV_32, OPW32) 235 DECODE_SRC_OPERAND_REG_AV10(AV_64, OPW64) 236 DECODE_SRC_OPERAND_REG_AV10(AV_128, OPW128) 237 238 // Decoders for register or immediate RegisterOperands that use 9-bit Src 239 // encoding: 'decodeOperand_<RegClass>_Imm<ImmWidth>'. 240 241 DECODE_OPERAND_SRC_REG_OR_IMM_9(SReg_64, OPW64, 64) 242 DECODE_OPERAND_SRC_REG_OR_IMM_9(SReg_32, OPW32, 32) 243 DECODE_OPERAND_SRC_REG_OR_IMM_9(SReg_32, OPW32, 16) 244 DECODE_OPERAND_SRC_REG_OR_IMM_9(SRegOrLds_32, OPW32, 32) 245 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32_Lo128, OPW16, 16) 246 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32, OPW32, 16) 247 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32, OPW32, 32) 248 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_64, OPW64, 64) 249 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_64, OPW64, 32) 250 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_64, OPW64, 64) 251 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_128, OPW128, 32) 252 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_256, OPW256, 64) 253 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_512, OPW512, 32) 254 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_1024, OPW1024, 32) 255 256 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_64, OPW64, 64) 257 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_128, OPW128, 32) 258 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_256, OPW256, 64) 259 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_512, OPW512, 32) 260 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_1024, OPW1024, 32) 261 262 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32_Lo128, OPW16, 16) 263 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32, OPW16, 16) 264 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32, OPW32, 32) 265 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(SReg_32, OPW32, 32) 266 267 static DecodeStatus DecodeVGPR_16RegisterClass(MCInst &Inst, unsigned Imm, 268 uint64_t /*Addr*/, 269 const MCDisassembler *Decoder) { 270 assert(isUInt<10>(Imm) && "10-bit encoding expected"); 271 assert((Imm & (1 << 8)) == 0 && "Imm{8} should not be used"); 272 273 bool IsHi = Imm & (1 << 9); 274 unsigned RegIdx = Imm & 0xff; 275 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 276 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 277 } 278 279 static DecodeStatus 280 DecodeVGPR_16_Lo128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, 281 const MCDisassembler *Decoder) { 282 assert(isUInt<8>(Imm) && "8-bit encoding expected"); 283 284 bool IsHi = Imm & (1 << 7); 285 unsigned RegIdx = Imm & 0x7f; 286 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 287 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 288 } 289 290 static DecodeStatus decodeOperand_VSrcT16_Lo128(MCInst &Inst, unsigned Imm, 291 uint64_t /*Addr*/, 292 const MCDisassembler *Decoder) { 293 assert(isUInt<9>(Imm) && "9-bit encoding expected"); 294 295 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 296 bool IsVGPR = Imm & (1 << 8); 297 if (IsVGPR) { 298 bool IsHi = Imm & (1 << 7); 299 unsigned RegIdx = Imm & 0x7f; 300 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 301 } 302 return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(AMDGPUDisassembler::OPW16, 303 Imm & 0xFF, false, 16)); 304 } 305 306 static DecodeStatus decodeOperand_VSrcT16(MCInst &Inst, unsigned Imm, 307 uint64_t /*Addr*/, 308 const MCDisassembler *Decoder) { 309 assert(isUInt<10>(Imm) && "10-bit encoding expected"); 310 311 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 312 bool IsVGPR = Imm & (1 << 8); 313 if (IsVGPR) { 314 bool IsHi = Imm & (1 << 9); 315 unsigned RegIdx = Imm & 0xff; 316 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 317 } 318 return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(AMDGPUDisassembler::OPW16, 319 Imm & 0xFF, false, 16)); 320 } 321 322 static DecodeStatus decodeOperand_KImmFP(MCInst &Inst, unsigned Imm, 323 uint64_t Addr, 324 const MCDisassembler *Decoder) { 325 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 326 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 327 } 328 329 static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val, 330 uint64_t Addr, const void *Decoder) { 331 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 332 return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val)); 333 } 334 335 static bool IsAGPROperand(const MCInst &Inst, int OpIdx, 336 const MCRegisterInfo *MRI) { 337 if (OpIdx < 0) 338 return false; 339 340 const MCOperand &Op = Inst.getOperand(OpIdx); 341 if (!Op.isReg()) 342 return false; 343 344 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); 345 auto Reg = Sub ? Sub : Op.getReg(); 346 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; 347 } 348 349 static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, unsigned Imm, 350 AMDGPUDisassembler::OpWidthTy Opw, 351 const MCDisassembler *Decoder) { 352 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 353 if (!DAsm->isGFX90A()) { 354 Imm &= 511; 355 } else { 356 // If atomic has both vdata and vdst their register classes are tied. 357 // The bit is decoded along with the vdst, first operand. We need to 358 // change register class to AGPR if vdst was AGPR. 359 // If a DS instruction has both data0 and data1 their register classes 360 // are also tied. 361 unsigned Opc = Inst.getOpcode(); 362 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; 363 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 364 : AMDGPU::OpName::vdata; 365 const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo(); 366 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); 367 if ((int)Inst.getNumOperands() == DataIdx) { 368 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); 369 if (IsAGPROperand(Inst, DstIdx, MRI)) 370 Imm |= 512; 371 } 372 373 if (TSFlags & SIInstrFlags::DS) { 374 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); 375 if ((int)Inst.getNumOperands() == Data2Idx && 376 IsAGPROperand(Inst, DataIdx, MRI)) 377 Imm |= 512; 378 } 379 } 380 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); 381 } 382 383 static DecodeStatus decodeOperand_VSrc_f64(MCInst &Inst, unsigned Imm, 384 uint64_t Addr, 385 const MCDisassembler *Decoder) { 386 assert(Imm < (1 << 9) && "9-bit encoding"); 387 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 388 return addOperand( 389 Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm, false, 64, true)); 390 } 391 392 static DecodeStatus 393 DecodeAVLdSt_32RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 394 const MCDisassembler *Decoder) { 395 return decodeOperand_AVLdSt_Any(Inst, Imm, 396 AMDGPUDisassembler::OPW32, Decoder); 397 } 398 399 static DecodeStatus 400 DecodeAVLdSt_64RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 401 const MCDisassembler *Decoder) { 402 return decodeOperand_AVLdSt_Any(Inst, Imm, 403 AMDGPUDisassembler::OPW64, Decoder); 404 } 405 406 static DecodeStatus 407 DecodeAVLdSt_96RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 408 const MCDisassembler *Decoder) { 409 return decodeOperand_AVLdSt_Any(Inst, Imm, 410 AMDGPUDisassembler::OPW96, Decoder); 411 } 412 413 static DecodeStatus 414 DecodeAVLdSt_128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 415 const MCDisassembler *Decoder) { 416 return decodeOperand_AVLdSt_Any(Inst, Imm, 417 AMDGPUDisassembler::OPW128, Decoder); 418 } 419 420 static DecodeStatus 421 DecodeAVLdSt_160RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 422 const MCDisassembler *Decoder) { 423 return decodeOperand_AVLdSt_Any(Inst, Imm, AMDGPUDisassembler::OPW160, 424 Decoder); 425 } 426 427 #define DECODE_SDWA(DecName) \ 428 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 429 430 DECODE_SDWA(Src32) 431 DECODE_SDWA(Src16) 432 DECODE_SDWA(VopcDst) 433 434 #include "AMDGPUGenDisassemblerTables.inc" 435 436 //===----------------------------------------------------------------------===// 437 // 438 //===----------------------------------------------------------------------===// 439 440 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 441 assert(Bytes.size() >= sizeof(T)); 442 const auto Res = 443 support::endian::read<T, llvm::endianness::little>(Bytes.data()); 444 Bytes = Bytes.slice(sizeof(T)); 445 return Res; 446 } 447 448 static inline DecoderUInt128 eat12Bytes(ArrayRef<uint8_t> &Bytes) { 449 assert(Bytes.size() >= 12); 450 uint64_t Lo = 451 support::endian::read<uint64_t, llvm::endianness::little>(Bytes.data()); 452 Bytes = Bytes.slice(8); 453 uint64_t Hi = 454 support::endian::read<uint32_t, llvm::endianness::little>(Bytes.data()); 455 Bytes = Bytes.slice(4); 456 return DecoderUInt128(Lo, Hi); 457 } 458 459 // The disassembler is greedy, so we need to check FI operand value to 460 // not parse a dpp if the correct literal is not set. For dpp16 the 461 // autogenerated decoder checks the dpp literal 462 static bool isValidDPP8(const MCInst &MI) { 463 using namespace llvm::AMDGPU::DPP; 464 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi); 465 assert(FiIdx != -1); 466 if ((unsigned)FiIdx >= MI.getNumOperands()) 467 return false; 468 unsigned Fi = MI.getOperand(FiIdx).getImm(); 469 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1; 470 } 471 472 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 473 ArrayRef<uint8_t> Bytes_, 474 uint64_t Address, 475 raw_ostream &CS) const { 476 bool IsSDWA = false; 477 478 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 479 Bytes = Bytes_.slice(0, MaxInstBytesNum); 480 481 DecodeStatus Res = MCDisassembler::Fail; 482 do { 483 // ToDo: better to switch encoding length using some bit predicate 484 // but it is unknown yet, so try all we can 485 486 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 487 // encodings 488 if (isGFX11Plus() && Bytes.size() >= 12 ) { 489 DecoderUInt128 DecW = eat12Bytes(Bytes); 490 Res = 491 tryDecodeInst(DecoderTableDPP8GFX1196, DecoderTableDPP8GFX11_FAKE1696, 492 MI, DecW, Address, CS); 493 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 494 break; 495 MI = MCInst(); // clear 496 Res = 497 tryDecodeInst(DecoderTableDPP8GFX1296, DecoderTableDPP8GFX12_FAKE1696, 498 MI, DecW, Address, CS); 499 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 500 break; 501 MI = MCInst(); // clear 502 503 const auto convertVOPDPP = [&]() { 504 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3P) { 505 convertVOP3PDPPInst(MI); 506 } else if (AMDGPU::isVOPC64DPP(MI.getOpcode())) { 507 convertVOPCDPPInst(MI); // Special VOP3 case 508 } else { 509 assert(MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3); 510 convertVOP3DPPInst(MI); // Regular VOP3 case 511 } 512 }; 513 Res = tryDecodeInst(DecoderTableDPPGFX1196, DecoderTableDPPGFX11_FAKE1696, 514 MI, DecW, Address, CS); 515 if (Res) { 516 convertVOPDPP(); 517 break; 518 } 519 Res = tryDecodeInst(DecoderTableDPPGFX1296, DecoderTableDPPGFX12_FAKE1696, 520 MI, DecW, Address, CS); 521 if (Res) { 522 convertVOPDPP(); 523 break; 524 } 525 Res = tryDecodeInst(DecoderTableGFX1196, MI, DecW, Address, CS); 526 if (Res) 527 break; 528 529 Res = tryDecodeInst(DecoderTableGFX1296, MI, DecW, Address, CS); 530 if (Res) 531 break; 532 } 533 // Reinitialize Bytes 534 Bytes = Bytes_.slice(0, MaxInstBytesNum); 535 536 if (Bytes.size() >= 8) { 537 const uint64_t QW = eatBytes<uint64_t>(Bytes); 538 539 if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding)) { 540 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address, CS); 541 if (Res) { 542 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) 543 == -1) 544 break; 545 if (convertDPP8Inst(MI) == MCDisassembler::Success) 546 break; 547 MI = MCInst(); // clear 548 } 549 } 550 551 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address, CS); 552 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 553 break; 554 MI = MCInst(); // clear 555 556 Res = tryDecodeInst(DecoderTableDPP8GFX1164, 557 DecoderTableDPP8GFX11_FAKE1664, MI, QW, Address, CS); 558 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 559 break; 560 MI = MCInst(); // clear 561 562 Res = tryDecodeInst(DecoderTableDPP8GFX1264, 563 DecoderTableDPP8GFX12_FAKE1664, MI, QW, Address, CS); 564 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 565 break; 566 MI = MCInst(); // clear 567 568 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address, CS); 569 if (Res) break; 570 571 Res = tryDecodeInst(DecoderTableDPPGFX1164, DecoderTableDPPGFX11_FAKE1664, 572 MI, QW, Address, CS); 573 if (Res) { 574 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC) 575 convertVOPCDPPInst(MI); 576 break; 577 } 578 579 Res = tryDecodeInst(DecoderTableDPPGFX1264, DecoderTableDPPGFX12_FAKE1664, 580 MI, QW, Address, CS); 581 if (Res) { 582 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC) 583 convertVOPCDPPInst(MI); 584 break; 585 } 586 587 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address, CS); 588 if (Res) { IsSDWA = true; break; } 589 590 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address, CS); 591 if (Res) { IsSDWA = true; break; } 592 593 Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address, CS); 594 if (Res) { IsSDWA = true; break; } 595 596 if (STI.hasFeature(AMDGPU::FeatureUnpackedD16VMem)) { 597 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address, CS); 598 if (Res) 599 break; 600 } 601 602 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 603 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 604 // table first so we print the correct name. 605 if (STI.hasFeature(AMDGPU::FeatureFmaMixInsts)) { 606 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address, CS); 607 if (Res) 608 break; 609 } 610 } 611 612 // Reinitialize Bytes as DPP64 could have eaten too much 613 Bytes = Bytes_.slice(0, MaxInstBytesNum); 614 615 // Try decode 32-bit instruction 616 if (Bytes.size() < 4) break; 617 const uint32_t DW = eatBytes<uint32_t>(Bytes); 618 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address, CS); 619 if (Res) break; 620 621 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address, CS); 622 if (Res) break; 623 624 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address, CS); 625 if (Res) break; 626 627 if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts)) { 628 Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address, CS); 629 if (Res) 630 break; 631 } 632 633 if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding)) { 634 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address, CS); 635 if (Res) break; 636 } 637 638 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address, CS); 639 if (Res) break; 640 641 Res = tryDecodeInst(DecoderTableGFX1132, DecoderTableGFX11_FAKE1632, MI, DW, 642 Address, CS); 643 if (Res) break; 644 645 Res = tryDecodeInst(DecoderTableGFX1232, DecoderTableGFX12_FAKE1632, MI, DW, 646 Address, CS); 647 if (Res) 648 break; 649 650 if (Bytes.size() < 4) break; 651 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 652 653 if (STI.hasFeature(AMDGPU::FeatureGFX940Insts)) { 654 Res = tryDecodeInst(DecoderTableGFX94064, MI, QW, Address, CS); 655 if (Res) 656 break; 657 } 658 659 if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts)) { 660 Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address, CS); 661 if (Res) 662 break; 663 } 664 665 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address, CS); 666 if (Res) break; 667 668 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address, CS); 669 if (Res) break; 670 671 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address, CS); 672 if (Res) break; 673 674 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address, CS); 675 if (Res) break; 676 677 Res = tryDecodeInst(DecoderTableGFX1264, DecoderTableGFX12_FAKE1664, MI, QW, 678 Address, CS); 679 if (Res) 680 break; 681 682 Res = tryDecodeInst(DecoderTableGFX1164, DecoderTableGFX11_FAKE1664, MI, QW, 683 Address, CS); 684 if (Res) 685 break; 686 687 Res = tryDecodeInst(DecoderTableWMMAGFX1164, MI, QW, Address, CS); 688 } while (false); 689 690 if (Res && AMDGPU::isMAC(MI.getOpcode())) { 691 // Insert dummy unused src2_modifiers. 692 insertNamedMCOperand(MI, MCOperand::createImm(0), 693 AMDGPU::OpName::src2_modifiers); 694 } 695 696 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 697 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT | SIInstrFlags::SMRD))) { 698 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 699 AMDGPU::OpName::cpol); 700 if (CPolPos != -1) { 701 unsigned CPol = 702 (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ? 703 AMDGPU::CPol::GLC : 0; 704 if (MI.getNumOperands() <= (unsigned)CPolPos) { 705 insertNamedMCOperand(MI, MCOperand::createImm(CPol), 706 AMDGPU::OpName::cpol); 707 } else if (CPol) { 708 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); 709 } 710 } 711 } 712 713 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 714 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) && 715 (STI.hasFeature(AMDGPU::FeatureGFX90AInsts))) { 716 // GFX90A lost TFE, its place is occupied by ACC. 717 int TFEOpIdx = 718 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); 719 if (TFEOpIdx != -1) { 720 auto TFEIter = MI.begin(); 721 std::advance(TFEIter, TFEOpIdx); 722 MI.insert(TFEIter, MCOperand::createImm(0)); 723 } 724 } 725 726 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 727 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF))) { 728 int SWZOpIdx = 729 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); 730 if (SWZOpIdx != -1) { 731 auto SWZIter = MI.begin(); 732 std::advance(SWZIter, SWZOpIdx); 733 MI.insert(SWZIter, MCOperand::createImm(0)); 734 } 735 } 736 737 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 738 int VAddr0Idx = 739 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 740 int RsrcIdx = 741 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 742 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 743 if (VAddr0Idx >= 0 && NSAArgs > 0) { 744 unsigned NSAWords = (NSAArgs + 3) / 4; 745 if (Bytes.size() < 4 * NSAWords) { 746 Res = MCDisassembler::Fail; 747 } else { 748 for (unsigned i = 0; i < NSAArgs; ++i) { 749 const unsigned VAddrIdx = VAddr0Idx + 1 + i; 750 auto VAddrRCID = 751 MCII->get(MI.getOpcode()).operands()[VAddrIdx].RegClass; 752 MI.insert(MI.begin() + VAddrIdx, 753 createRegOperand(VAddrRCID, Bytes[i])); 754 } 755 Bytes = Bytes.slice(4 * NSAWords); 756 } 757 } 758 759 if (Res) 760 Res = convertMIMGInst(MI); 761 } 762 763 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 764 (SIInstrFlags::VIMAGE | SIInstrFlags::VSAMPLE))) 765 Res = convertMIMGInst(MI); 766 767 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::EXP)) 768 Res = convertEXPInst(MI); 769 770 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VINTERP)) 771 Res = convertVINTERPInst(MI); 772 773 if (Res && IsSDWA) 774 Res = convertSDWAInst(MI); 775 776 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 777 AMDGPU::OpName::vdst_in); 778 if (VDstIn_Idx != -1) { 779 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 780 MCOI::OperandConstraint::TIED_TO); 781 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 782 !MI.getOperand(VDstIn_Idx).isReg() || 783 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 784 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 785 MI.erase(&MI.getOperand(VDstIn_Idx)); 786 insertNamedMCOperand(MI, 787 MCOperand::createReg(MI.getOperand(Tied).getReg()), 788 AMDGPU::OpName::vdst_in); 789 } 790 } 791 792 int ImmLitIdx = 793 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm); 794 bool IsSOPK = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::SOPK; 795 if (Res && ImmLitIdx != -1 && !IsSOPK) 796 Res = convertFMAanyK(MI, ImmLitIdx); 797 798 // if the opcode was not recognized we'll assume a Size of 4 bytes 799 // (unless there are fewer bytes left) 800 Size = Res ? (MaxInstBytesNum - Bytes.size()) 801 : std::min((size_t)4, Bytes_.size()); 802 return Res; 803 } 804 805 DecodeStatus AMDGPUDisassembler::convertEXPInst(MCInst &MI) const { 806 if (STI.hasFeature(AMDGPU::FeatureGFX11Insts)) { 807 // The MCInst still has these fields even though they are no longer encoded 808 // in the GFX11 instruction. 809 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vm); 810 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::compr); 811 } 812 return MCDisassembler::Success; 813 } 814 815 DecodeStatus AMDGPUDisassembler::convertVINTERPInst(MCInst &MI) const { 816 if (MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx11 || 817 MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx12 || 818 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx11 || 819 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx12 || 820 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx11 || 821 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx12 || 822 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx11 || 823 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx12) { 824 // The MCInst has this field that is not directly encoded in the 825 // instruction. 826 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::op_sel); 827 } 828 return MCDisassembler::Success; 829 } 830 831 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 832 if (STI.hasFeature(AMDGPU::FeatureGFX9) || 833 STI.hasFeature(AMDGPU::FeatureGFX10)) { 834 if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::sdst)) 835 // VOPC - insert clamp 836 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 837 } else if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) { 838 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 839 if (SDst != -1) { 840 // VOPC - insert VCC register as sdst 841 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 842 AMDGPU::OpName::sdst); 843 } else { 844 // VOP1/2 - insert omod if present in instruction 845 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 846 } 847 } 848 return MCDisassembler::Success; 849 } 850 851 struct VOPModifiers { 852 unsigned OpSel = 0; 853 unsigned OpSelHi = 0; 854 unsigned NegLo = 0; 855 unsigned NegHi = 0; 856 }; 857 858 // Reconstruct values of VOP3/VOP3P operands such as op_sel. 859 // Note that these values do not affect disassembler output, 860 // so this is only necessary for consistency with src_modifiers. 861 static VOPModifiers collectVOPModifiers(const MCInst &MI, 862 bool IsVOP3P = false) { 863 VOPModifiers Modifiers; 864 unsigned Opc = MI.getOpcode(); 865 const int ModOps[] = {AMDGPU::OpName::src0_modifiers, 866 AMDGPU::OpName::src1_modifiers, 867 AMDGPU::OpName::src2_modifiers}; 868 for (int J = 0; J < 3; ++J) { 869 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]); 870 if (OpIdx == -1) 871 continue; 872 873 unsigned Val = MI.getOperand(OpIdx).getImm(); 874 875 Modifiers.OpSel |= !!(Val & SISrcMods::OP_SEL_0) << J; 876 if (IsVOP3P) { 877 Modifiers.OpSelHi |= !!(Val & SISrcMods::OP_SEL_1) << J; 878 Modifiers.NegLo |= !!(Val & SISrcMods::NEG) << J; 879 Modifiers.NegHi |= !!(Val & SISrcMods::NEG_HI) << J; 880 } else if (J == 0) { 881 Modifiers.OpSel |= !!(Val & SISrcMods::DST_OP_SEL) << 3; 882 } 883 } 884 885 return Modifiers; 886 } 887 888 // MAC opcodes have special old and src2 operands. 889 // src2 is tied to dst, while old is not tied (but assumed to be). 890 bool AMDGPUDisassembler::isMacDPP(MCInst &MI) const { 891 constexpr int DST_IDX = 0; 892 auto Opcode = MI.getOpcode(); 893 const auto &Desc = MCII->get(Opcode); 894 auto OldIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::old); 895 896 if (OldIdx != -1 && Desc.getOperandConstraint( 897 OldIdx, MCOI::OperandConstraint::TIED_TO) == -1) { 898 assert(AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src2)); 899 assert(Desc.getOperandConstraint( 900 AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2), 901 MCOI::OperandConstraint::TIED_TO) == DST_IDX); 902 (void)DST_IDX; 903 return true; 904 } 905 906 return false; 907 } 908 909 // Create dummy old operand and insert dummy unused src2_modifiers 910 void AMDGPUDisassembler::convertMacDPPInst(MCInst &MI) const { 911 assert(MI.getNumOperands() + 1 < MCII->get(MI.getOpcode()).getNumOperands()); 912 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 913 insertNamedMCOperand(MI, MCOperand::createImm(0), 914 AMDGPU::OpName::src2_modifiers); 915 } 916 917 // We must check FI == literal to reject not genuine dpp8 insts, and we must 918 // first add optional MI operands to check FI 919 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 920 unsigned Opc = MI.getOpcode(); 921 if (MCII->get(Opc).TSFlags & SIInstrFlags::VOP3P) { 922 convertVOP3PDPPInst(MI); 923 } else if ((MCII->get(Opc).TSFlags & SIInstrFlags::VOPC) || 924 AMDGPU::isVOPC64DPP(Opc)) { 925 convertVOPCDPPInst(MI); 926 } else { 927 if (isMacDPP(MI)) 928 convertMacDPPInst(MI); 929 930 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 931 if (MI.getNumOperands() < DescNumOps && 932 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { 933 auto Mods = collectVOPModifiers(MI); 934 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 935 AMDGPU::OpName::op_sel); 936 } else { 937 // Insert dummy unused src modifiers. 938 if (MI.getNumOperands() < DescNumOps && 939 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) 940 insertNamedMCOperand(MI, MCOperand::createImm(0), 941 AMDGPU::OpName::src0_modifiers); 942 943 if (MI.getNumOperands() < DescNumOps && 944 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers)) 945 insertNamedMCOperand(MI, MCOperand::createImm(0), 946 AMDGPU::OpName::src1_modifiers); 947 } 948 } 949 return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail; 950 } 951 952 DecodeStatus AMDGPUDisassembler::convertVOP3DPPInst(MCInst &MI) const { 953 if (isMacDPP(MI)) 954 convertMacDPPInst(MI); 955 956 unsigned Opc = MI.getOpcode(); 957 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 958 if (MI.getNumOperands() < DescNumOps && 959 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { 960 auto Mods = collectVOPModifiers(MI); 961 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 962 AMDGPU::OpName::op_sel); 963 } 964 return MCDisassembler::Success; 965 } 966 967 // Note that before gfx10, the MIMG encoding provided no information about 968 // VADDR size. Consequently, decoded instructions always show address as if it 969 // has 1 dword, which could be not really so. 970 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 971 auto TSFlags = MCII->get(MI.getOpcode()).TSFlags; 972 973 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 974 AMDGPU::OpName::vdst); 975 976 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 977 AMDGPU::OpName::vdata); 978 int VAddr0Idx = 979 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 980 int RsrcOpName = TSFlags & SIInstrFlags::MIMG ? AMDGPU::OpName::srsrc 981 : AMDGPU::OpName::rsrc; 982 int RsrcIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), RsrcOpName); 983 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 984 AMDGPU::OpName::dmask); 985 986 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 987 AMDGPU::OpName::tfe); 988 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 989 AMDGPU::OpName::d16); 990 991 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 992 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 993 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 994 995 assert(VDataIdx != -1); 996 if (BaseOpcode->BVH) { 997 // Add A16 operand for intersect_ray instructions 998 addOperand(MI, MCOperand::createImm(BaseOpcode->A16)); 999 return MCDisassembler::Success; 1000 } 1001 1002 bool IsAtomic = (VDstIdx != -1); 1003 bool IsGather4 = TSFlags & SIInstrFlags::Gather4; 1004 bool IsVSample = TSFlags & SIInstrFlags::VSAMPLE; 1005 bool IsNSA = false; 1006 bool IsPartialNSA = false; 1007 unsigned AddrSize = Info->VAddrDwords; 1008 1009 if (isGFX10Plus()) { 1010 unsigned DimIdx = 1011 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 1012 int A16Idx = 1013 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16); 1014 const AMDGPU::MIMGDimInfo *Dim = 1015 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 1016 const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm()); 1017 1018 AddrSize = 1019 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); 1020 1021 // VSAMPLE insts that do not use vaddr3 behave the same as NSA forms. 1022 // VIMAGE insts other than BVH never use vaddr4. 1023 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA || 1024 Info->MIMGEncoding == AMDGPU::MIMGEncGfx11NSA || 1025 Info->MIMGEncoding == AMDGPU::MIMGEncGfx12; 1026 if (!IsNSA) { 1027 if (!IsVSample && AddrSize > 12) 1028 AddrSize = 16; 1029 } else { 1030 if (AddrSize > Info->VAddrDwords) { 1031 if (!STI.hasFeature(AMDGPU::FeaturePartialNSAEncoding)) { 1032 // The NSA encoding does not contain enough operands for the 1033 // combination of base opcode / dimension. Should this be an error? 1034 return MCDisassembler::Success; 1035 } 1036 IsPartialNSA = true; 1037 } 1038 } 1039 } 1040 1041 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 1042 unsigned DstSize = IsGather4 ? 4 : std::max(llvm::popcount(DMask), 1); 1043 1044 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 1045 if (D16 && AMDGPU::hasPackedD16(STI)) { 1046 DstSize = (DstSize + 1) / 2; 1047 } 1048 1049 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm()) 1050 DstSize += 1; 1051 1052 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 1053 return MCDisassembler::Success; 1054 1055 int NewOpcode = 1056 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 1057 if (NewOpcode == -1) 1058 return MCDisassembler::Success; 1059 1060 // Widen the register to the correct number of enabled channels. 1061 unsigned NewVdata = AMDGPU::NoRegister; 1062 if (DstSize != Info->VDataDwords) { 1063 auto DataRCID = MCII->get(NewOpcode).operands()[VDataIdx].RegClass; 1064 1065 // Get first subregister of VData 1066 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 1067 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 1068 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 1069 1070 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 1071 &MRI.getRegClass(DataRCID)); 1072 if (NewVdata == AMDGPU::NoRegister) { 1073 // It's possible to encode this such that the low register + enabled 1074 // components exceeds the register count. 1075 return MCDisassembler::Success; 1076 } 1077 } 1078 1079 // If not using NSA on GFX10+, widen vaddr0 address register to correct size. 1080 // If using partial NSA on GFX11+ widen last address register. 1081 int VAddrSAIdx = IsPartialNSA ? (RsrcIdx - 1) : VAddr0Idx; 1082 unsigned NewVAddrSA = AMDGPU::NoRegister; 1083 if (STI.hasFeature(AMDGPU::FeatureNSAEncoding) && (!IsNSA || IsPartialNSA) && 1084 AddrSize != Info->VAddrDwords) { 1085 unsigned VAddrSA = MI.getOperand(VAddrSAIdx).getReg(); 1086 unsigned VAddrSubSA = MRI.getSubReg(VAddrSA, AMDGPU::sub0); 1087 VAddrSA = VAddrSubSA ? VAddrSubSA : VAddrSA; 1088 1089 auto AddrRCID = MCII->get(NewOpcode).operands()[VAddrSAIdx].RegClass; 1090 NewVAddrSA = MRI.getMatchingSuperReg(VAddrSA, AMDGPU::sub0, 1091 &MRI.getRegClass(AddrRCID)); 1092 if (!NewVAddrSA) 1093 return MCDisassembler::Success; 1094 } 1095 1096 MI.setOpcode(NewOpcode); 1097 1098 if (NewVdata != AMDGPU::NoRegister) { 1099 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 1100 1101 if (IsAtomic) { 1102 // Atomic operations have an additional operand (a copy of data) 1103 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 1104 } 1105 } 1106 1107 if (NewVAddrSA) { 1108 MI.getOperand(VAddrSAIdx) = MCOperand::createReg(NewVAddrSA); 1109 } else if (IsNSA) { 1110 assert(AddrSize <= Info->VAddrDwords); 1111 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 1112 MI.begin() + VAddr0Idx + Info->VAddrDwords); 1113 } 1114 1115 return MCDisassembler::Success; 1116 } 1117 1118 // Opsel and neg bits are used in src_modifiers and standalone operands. Autogen 1119 // decoder only adds to src_modifiers, so manually add the bits to the other 1120 // operands. 1121 DecodeStatus AMDGPUDisassembler::convertVOP3PDPPInst(MCInst &MI) const { 1122 unsigned Opc = MI.getOpcode(); 1123 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1124 auto Mods = collectVOPModifiers(MI, true); 1125 1126 if (MI.getNumOperands() < DescNumOps && 1127 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vdst_in)) 1128 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vdst_in); 1129 1130 if (MI.getNumOperands() < DescNumOps && 1131 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) 1132 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 1133 AMDGPU::OpName::op_sel); 1134 if (MI.getNumOperands() < DescNumOps && 1135 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel_hi)) 1136 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSelHi), 1137 AMDGPU::OpName::op_sel_hi); 1138 if (MI.getNumOperands() < DescNumOps && 1139 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_lo)) 1140 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegLo), 1141 AMDGPU::OpName::neg_lo); 1142 if (MI.getNumOperands() < DescNumOps && 1143 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_hi)) 1144 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegHi), 1145 AMDGPU::OpName::neg_hi); 1146 1147 return MCDisassembler::Success; 1148 } 1149 1150 // Create dummy old operand and insert optional operands 1151 DecodeStatus AMDGPUDisassembler::convertVOPCDPPInst(MCInst &MI) const { 1152 unsigned Opc = MI.getOpcode(); 1153 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1154 1155 if (MI.getNumOperands() < DescNumOps && 1156 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::old)) 1157 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 1158 1159 if (MI.getNumOperands() < DescNumOps && 1160 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) 1161 insertNamedMCOperand(MI, MCOperand::createImm(0), 1162 AMDGPU::OpName::src0_modifiers); 1163 1164 if (MI.getNumOperands() < DescNumOps && 1165 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers)) 1166 insertNamedMCOperand(MI, MCOperand::createImm(0), 1167 AMDGPU::OpName::src1_modifiers); 1168 return MCDisassembler::Success; 1169 } 1170 1171 DecodeStatus AMDGPUDisassembler::convertFMAanyK(MCInst &MI, 1172 int ImmLitIdx) const { 1173 assert(HasLiteral && "Should have decoded a literal"); 1174 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 1175 unsigned DescNumOps = Desc.getNumOperands(); 1176 insertNamedMCOperand(MI, MCOperand::createImm(Literal), 1177 AMDGPU::OpName::immDeferred); 1178 assert(DescNumOps == MI.getNumOperands()); 1179 for (unsigned I = 0; I < DescNumOps; ++I) { 1180 auto &Op = MI.getOperand(I); 1181 auto OpType = Desc.operands()[I].OperandType; 1182 bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED || 1183 OpType == AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED); 1184 if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST && 1185 IsDeferredOp) 1186 Op.setImm(Literal); 1187 } 1188 return MCDisassembler::Success; 1189 } 1190 1191 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 1192 return getContext().getRegisterInfo()-> 1193 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 1194 } 1195 1196 inline 1197 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 1198 const Twine& ErrMsg) const { 1199 *CommentStream << "Error: " + ErrMsg; 1200 1201 // ToDo: add support for error operands to MCInst.h 1202 // return MCOperand::createError(V); 1203 return MCOperand(); 1204 } 1205 1206 inline 1207 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 1208 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 1209 } 1210 1211 inline 1212 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 1213 unsigned Val) const { 1214 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 1215 if (Val >= RegCl.getNumRegs()) 1216 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 1217 ": unknown register " + Twine(Val)); 1218 return createRegOperand(RegCl.getRegister(Val)); 1219 } 1220 1221 inline 1222 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 1223 unsigned Val) const { 1224 // ToDo: SI/CI have 104 SGPRs, VI - 102 1225 // Valery: here we accepting as much as we can, let assembler sort it out 1226 int shift = 0; 1227 switch (SRegClassID) { 1228 case AMDGPU::SGPR_32RegClassID: 1229 case AMDGPU::TTMP_32RegClassID: 1230 break; 1231 case AMDGPU::SGPR_64RegClassID: 1232 case AMDGPU::TTMP_64RegClassID: 1233 shift = 1; 1234 break; 1235 case AMDGPU::SGPR_128RegClassID: 1236 case AMDGPU::TTMP_128RegClassID: 1237 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 1238 // this bundle? 1239 case AMDGPU::SGPR_256RegClassID: 1240 case AMDGPU::TTMP_256RegClassID: 1241 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 1242 // this bundle? 1243 case AMDGPU::SGPR_288RegClassID: 1244 case AMDGPU::TTMP_288RegClassID: 1245 case AMDGPU::SGPR_320RegClassID: 1246 case AMDGPU::TTMP_320RegClassID: 1247 case AMDGPU::SGPR_352RegClassID: 1248 case AMDGPU::TTMP_352RegClassID: 1249 case AMDGPU::SGPR_384RegClassID: 1250 case AMDGPU::TTMP_384RegClassID: 1251 case AMDGPU::SGPR_512RegClassID: 1252 case AMDGPU::TTMP_512RegClassID: 1253 shift = 2; 1254 break; 1255 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 1256 // this bundle? 1257 default: 1258 llvm_unreachable("unhandled register class"); 1259 } 1260 1261 if (Val % (1 << shift)) { 1262 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 1263 << ": scalar reg isn't aligned " << Val; 1264 } 1265 1266 return createRegOperand(SRegClassID, Val >> shift); 1267 } 1268 1269 MCOperand AMDGPUDisassembler::createVGPR16Operand(unsigned RegIdx, 1270 bool IsHi) const { 1271 unsigned RCID = 1272 IsHi ? AMDGPU::VGPR_HI16RegClassID : AMDGPU::VGPR_LO16RegClassID; 1273 return createRegOperand(RCID, RegIdx); 1274 } 1275 1276 // Decode Literals for insts which always have a literal in the encoding 1277 MCOperand 1278 AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const { 1279 if (HasLiteral) { 1280 assert( 1281 AMDGPU::hasVOPD(STI) && 1282 "Should only decode multiple kimm with VOPD, check VSrc operand types"); 1283 if (Literal != Val) 1284 return errOperand(Val, "More than one unique literal is illegal"); 1285 } 1286 HasLiteral = true; 1287 Literal = Val; 1288 return MCOperand::createImm(Literal); 1289 } 1290 1291 MCOperand AMDGPUDisassembler::decodeLiteralConstant(bool ExtendFP64) const { 1292 // For now all literal constants are supposed to be unsigned integer 1293 // ToDo: deal with signed/unsigned 64-bit integer constants 1294 // ToDo: deal with float/double constants 1295 if (!HasLiteral) { 1296 if (Bytes.size() < 4) { 1297 return errOperand(0, "cannot read literal, inst bytes left " + 1298 Twine(Bytes.size())); 1299 } 1300 HasLiteral = true; 1301 Literal = Literal64 = eatBytes<uint32_t>(Bytes); 1302 if (ExtendFP64) 1303 Literal64 <<= 32; 1304 } 1305 return MCOperand::createImm(ExtendFP64 ? Literal64 : Literal); 1306 } 1307 1308 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 1309 using namespace AMDGPU::EncValues; 1310 1311 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 1312 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 1313 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 1314 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 1315 // Cast prevents negative overflow. 1316 } 1317 1318 static int64_t getInlineImmVal32(unsigned Imm) { 1319 switch (Imm) { 1320 case 240: 1321 return llvm::bit_cast<uint32_t>(0.5f); 1322 case 241: 1323 return llvm::bit_cast<uint32_t>(-0.5f); 1324 case 242: 1325 return llvm::bit_cast<uint32_t>(1.0f); 1326 case 243: 1327 return llvm::bit_cast<uint32_t>(-1.0f); 1328 case 244: 1329 return llvm::bit_cast<uint32_t>(2.0f); 1330 case 245: 1331 return llvm::bit_cast<uint32_t>(-2.0f); 1332 case 246: 1333 return llvm::bit_cast<uint32_t>(4.0f); 1334 case 247: 1335 return llvm::bit_cast<uint32_t>(-4.0f); 1336 case 248: // 1 / (2 * PI) 1337 return 0x3e22f983; 1338 default: 1339 llvm_unreachable("invalid fp inline imm"); 1340 } 1341 } 1342 1343 static int64_t getInlineImmVal64(unsigned Imm) { 1344 switch (Imm) { 1345 case 240: 1346 return llvm::bit_cast<uint64_t>(0.5); 1347 case 241: 1348 return llvm::bit_cast<uint64_t>(-0.5); 1349 case 242: 1350 return llvm::bit_cast<uint64_t>(1.0); 1351 case 243: 1352 return llvm::bit_cast<uint64_t>(-1.0); 1353 case 244: 1354 return llvm::bit_cast<uint64_t>(2.0); 1355 case 245: 1356 return llvm::bit_cast<uint64_t>(-2.0); 1357 case 246: 1358 return llvm::bit_cast<uint64_t>(4.0); 1359 case 247: 1360 return llvm::bit_cast<uint64_t>(-4.0); 1361 case 248: // 1 / (2 * PI) 1362 return 0x3fc45f306dc9c882; 1363 default: 1364 llvm_unreachable("invalid fp inline imm"); 1365 } 1366 } 1367 1368 static int64_t getInlineImmVal16(unsigned Imm) { 1369 switch (Imm) { 1370 case 240: 1371 return 0x3800; 1372 case 241: 1373 return 0xB800; 1374 case 242: 1375 return 0x3C00; 1376 case 243: 1377 return 0xBC00; 1378 case 244: 1379 return 0x4000; 1380 case 245: 1381 return 0xC000; 1382 case 246: 1383 return 0x4400; 1384 case 247: 1385 return 0xC400; 1386 case 248: // 1 / (2 * PI) 1387 return 0x3118; 1388 default: 1389 llvm_unreachable("invalid fp inline imm"); 1390 } 1391 } 1392 1393 MCOperand AMDGPUDisassembler::decodeFPImmed(unsigned ImmWidth, unsigned Imm) { 1394 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 1395 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 1396 1397 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 1398 // ImmWidth 0 is a default case where operand should not allow immediates. 1399 // Imm value is still decoded into 32 bit immediate operand, inst printer will 1400 // use it to print verbose error message. 1401 switch (ImmWidth) { 1402 case 0: 1403 case 32: 1404 return MCOperand::createImm(getInlineImmVal32(Imm)); 1405 case 64: 1406 return MCOperand::createImm(getInlineImmVal64(Imm)); 1407 case 16: 1408 return MCOperand::createImm(getInlineImmVal16(Imm)); 1409 default: 1410 llvm_unreachable("implement me"); 1411 } 1412 } 1413 1414 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 1415 using namespace AMDGPU; 1416 1417 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1418 switch (Width) { 1419 default: // fall 1420 case OPW32: 1421 case OPW16: 1422 case OPWV216: 1423 return VGPR_32RegClassID; 1424 case OPW64: 1425 case OPWV232: return VReg_64RegClassID; 1426 case OPW96: return VReg_96RegClassID; 1427 case OPW128: return VReg_128RegClassID; 1428 case OPW160: return VReg_160RegClassID; 1429 case OPW256: return VReg_256RegClassID; 1430 case OPW288: return VReg_288RegClassID; 1431 case OPW320: return VReg_320RegClassID; 1432 case OPW352: return VReg_352RegClassID; 1433 case OPW384: return VReg_384RegClassID; 1434 case OPW512: return VReg_512RegClassID; 1435 case OPW1024: return VReg_1024RegClassID; 1436 } 1437 } 1438 1439 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 1440 using namespace AMDGPU; 1441 1442 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1443 switch (Width) { 1444 default: // fall 1445 case OPW32: 1446 case OPW16: 1447 case OPWV216: 1448 return AGPR_32RegClassID; 1449 case OPW64: 1450 case OPWV232: return AReg_64RegClassID; 1451 case OPW96: return AReg_96RegClassID; 1452 case OPW128: return AReg_128RegClassID; 1453 case OPW160: return AReg_160RegClassID; 1454 case OPW256: return AReg_256RegClassID; 1455 case OPW288: return AReg_288RegClassID; 1456 case OPW320: return AReg_320RegClassID; 1457 case OPW352: return AReg_352RegClassID; 1458 case OPW384: return AReg_384RegClassID; 1459 case OPW512: return AReg_512RegClassID; 1460 case OPW1024: return AReg_1024RegClassID; 1461 } 1462 } 1463 1464 1465 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 1466 using namespace AMDGPU; 1467 1468 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1469 switch (Width) { 1470 default: // fall 1471 case OPW32: 1472 case OPW16: 1473 case OPWV216: 1474 return SGPR_32RegClassID; 1475 case OPW64: 1476 case OPWV232: return SGPR_64RegClassID; 1477 case OPW96: return SGPR_96RegClassID; 1478 case OPW128: return SGPR_128RegClassID; 1479 case OPW160: return SGPR_160RegClassID; 1480 case OPW256: return SGPR_256RegClassID; 1481 case OPW288: return SGPR_288RegClassID; 1482 case OPW320: return SGPR_320RegClassID; 1483 case OPW352: return SGPR_352RegClassID; 1484 case OPW384: return SGPR_384RegClassID; 1485 case OPW512: return SGPR_512RegClassID; 1486 } 1487 } 1488 1489 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 1490 using namespace AMDGPU; 1491 1492 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1493 switch (Width) { 1494 default: // fall 1495 case OPW32: 1496 case OPW16: 1497 case OPWV216: 1498 return TTMP_32RegClassID; 1499 case OPW64: 1500 case OPWV232: return TTMP_64RegClassID; 1501 case OPW128: return TTMP_128RegClassID; 1502 case OPW256: return TTMP_256RegClassID; 1503 case OPW288: return TTMP_288RegClassID; 1504 case OPW320: return TTMP_320RegClassID; 1505 case OPW352: return TTMP_352RegClassID; 1506 case OPW384: return TTMP_384RegClassID; 1507 case OPW512: return TTMP_512RegClassID; 1508 } 1509 } 1510 1511 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 1512 using namespace AMDGPU::EncValues; 1513 1514 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN; 1515 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX; 1516 1517 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1518 } 1519 1520 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val, 1521 bool MandatoryLiteral, 1522 unsigned ImmWidth, bool IsFP) const { 1523 using namespace AMDGPU::EncValues; 1524 1525 assert(Val < 1024); // enum10 1526 1527 bool IsAGPR = Val & 512; 1528 Val &= 511; 1529 1530 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1531 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1532 : getVgprClassId(Width), Val - VGPR_MIN); 1533 } 1534 return decodeNonVGPRSrcOp(Width, Val & 0xFF, MandatoryLiteral, ImmWidth, 1535 IsFP); 1536 } 1537 1538 MCOperand AMDGPUDisassembler::decodeNonVGPRSrcOp(const OpWidthTy Width, 1539 unsigned Val, 1540 bool MandatoryLiteral, 1541 unsigned ImmWidth, 1542 bool IsFP) const { 1543 // Cases when Val{8} is 1 (vgpr, agpr or true 16 vgpr) should have been 1544 // decoded earlier. 1545 assert(Val < (1 << 8) && "9-bit Src encoding when Val{8} is 0"); 1546 using namespace AMDGPU::EncValues; 1547 1548 if (Val <= SGPR_MAX) { 1549 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1550 static_assert(SGPR_MIN == 0); 1551 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1552 } 1553 1554 int TTmpIdx = getTTmpIdx(Val); 1555 if (TTmpIdx >= 0) { 1556 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1557 } 1558 1559 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1560 return decodeIntImmed(Val); 1561 1562 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1563 return decodeFPImmed(ImmWidth, Val); 1564 1565 if (Val == LITERAL_CONST) { 1566 if (MandatoryLiteral) 1567 // Keep a sentinel value for deferred setting 1568 return MCOperand::createImm(LITERAL_CONST); 1569 else 1570 return decodeLiteralConstant(IsFP && ImmWidth == 64); 1571 } 1572 1573 switch (Width) { 1574 case OPW32: 1575 case OPW16: 1576 case OPWV216: 1577 return decodeSpecialReg32(Val); 1578 case OPW64: 1579 case OPWV232: 1580 return decodeSpecialReg64(Val); 1581 default: 1582 llvm_unreachable("unexpected immediate type"); 1583 } 1584 } 1585 1586 // Bit 0 of DstY isn't stored in the instruction, because it's always the 1587 // opposite of bit 0 of DstX. 1588 MCOperand AMDGPUDisassembler::decodeVOPDDstYOp(MCInst &Inst, 1589 unsigned Val) const { 1590 int VDstXInd = 1591 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::vdstX); 1592 assert(VDstXInd != -1); 1593 assert(Inst.getOperand(VDstXInd).isReg()); 1594 unsigned XDstReg = MRI.getEncodingValue(Inst.getOperand(VDstXInd).getReg()); 1595 Val |= ~XDstReg & 1; 1596 auto Width = llvm::AMDGPUDisassembler::OPW32; 1597 return createRegOperand(getVgprClassId(Width), Val); 1598 } 1599 1600 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1601 using namespace AMDGPU; 1602 1603 switch (Val) { 1604 // clang-format off 1605 case 102: return createRegOperand(FLAT_SCR_LO); 1606 case 103: return createRegOperand(FLAT_SCR_HI); 1607 case 104: return createRegOperand(XNACK_MASK_LO); 1608 case 105: return createRegOperand(XNACK_MASK_HI); 1609 case 106: return createRegOperand(VCC_LO); 1610 case 107: return createRegOperand(VCC_HI); 1611 case 108: return createRegOperand(TBA_LO); 1612 case 109: return createRegOperand(TBA_HI); 1613 case 110: return createRegOperand(TMA_LO); 1614 case 111: return createRegOperand(TMA_HI); 1615 case 124: 1616 return isGFX11Plus() ? createRegOperand(SGPR_NULL) : createRegOperand(M0); 1617 case 125: 1618 return isGFX11Plus() ? createRegOperand(M0) : createRegOperand(SGPR_NULL); 1619 case 126: return createRegOperand(EXEC_LO); 1620 case 127: return createRegOperand(EXEC_HI); 1621 case 235: return createRegOperand(SRC_SHARED_BASE_LO); 1622 case 236: return createRegOperand(SRC_SHARED_LIMIT_LO); 1623 case 237: return createRegOperand(SRC_PRIVATE_BASE_LO); 1624 case 238: return createRegOperand(SRC_PRIVATE_LIMIT_LO); 1625 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1626 case 251: return createRegOperand(SRC_VCCZ); 1627 case 252: return createRegOperand(SRC_EXECZ); 1628 case 253: return createRegOperand(SRC_SCC); 1629 case 254: return createRegOperand(LDS_DIRECT); 1630 default: break; 1631 // clang-format on 1632 } 1633 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1634 } 1635 1636 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1637 using namespace AMDGPU; 1638 1639 switch (Val) { 1640 case 102: return createRegOperand(FLAT_SCR); 1641 case 104: return createRegOperand(XNACK_MASK); 1642 case 106: return createRegOperand(VCC); 1643 case 108: return createRegOperand(TBA); 1644 case 110: return createRegOperand(TMA); 1645 case 124: 1646 if (isGFX11Plus()) 1647 return createRegOperand(SGPR_NULL); 1648 break; 1649 case 125: 1650 if (!isGFX11Plus()) 1651 return createRegOperand(SGPR_NULL); 1652 break; 1653 case 126: return createRegOperand(EXEC); 1654 case 235: return createRegOperand(SRC_SHARED_BASE); 1655 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1656 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1657 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1658 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1659 case 251: return createRegOperand(SRC_VCCZ); 1660 case 252: return createRegOperand(SRC_EXECZ); 1661 case 253: return createRegOperand(SRC_SCC); 1662 default: break; 1663 } 1664 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1665 } 1666 1667 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 1668 const unsigned Val, 1669 unsigned ImmWidth) const { 1670 using namespace AMDGPU::SDWA; 1671 using namespace AMDGPU::EncValues; 1672 1673 if (STI.hasFeature(AMDGPU::FeatureGFX9) || 1674 STI.hasFeature(AMDGPU::FeatureGFX10)) { 1675 // XXX: cast to int is needed to avoid stupid warning: 1676 // compare with unsigned is always true 1677 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1678 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1679 return createRegOperand(getVgprClassId(Width), 1680 Val - SDWA9EncValues::SRC_VGPR_MIN); 1681 } 1682 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1683 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1684 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1685 return createSRegOperand(getSgprClassId(Width), 1686 Val - SDWA9EncValues::SRC_SGPR_MIN); 1687 } 1688 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1689 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1690 return createSRegOperand(getTtmpClassId(Width), 1691 Val - SDWA9EncValues::SRC_TTMP_MIN); 1692 } 1693 1694 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1695 1696 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1697 return decodeIntImmed(SVal); 1698 1699 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1700 return decodeFPImmed(ImmWidth, SVal); 1701 1702 return decodeSpecialReg32(SVal); 1703 } else if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) { 1704 return createRegOperand(getVgprClassId(Width), Val); 1705 } 1706 llvm_unreachable("unsupported target"); 1707 } 1708 1709 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1710 return decodeSDWASrc(OPW16, Val, 16); 1711 } 1712 1713 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1714 return decodeSDWASrc(OPW32, Val, 32); 1715 } 1716 1717 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1718 using namespace AMDGPU::SDWA; 1719 1720 assert((STI.hasFeature(AMDGPU::FeatureGFX9) || 1721 STI.hasFeature(AMDGPU::FeatureGFX10)) && 1722 "SDWAVopcDst should be present only on GFX9+"); 1723 1724 bool IsWave64 = STI.hasFeature(AMDGPU::FeatureWavefrontSize64); 1725 1726 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1727 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1728 1729 int TTmpIdx = getTTmpIdx(Val); 1730 if (TTmpIdx >= 0) { 1731 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1732 return createSRegOperand(TTmpClsId, TTmpIdx); 1733 } else if (Val > SGPR_MAX) { 1734 return IsWave64 ? decodeSpecialReg64(Val) 1735 : decodeSpecialReg32(Val); 1736 } else { 1737 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1738 } 1739 } else { 1740 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1741 } 1742 } 1743 1744 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1745 return STI.hasFeature(AMDGPU::FeatureWavefrontSize64) 1746 ? decodeSrcOp(OPW64, Val) 1747 : decodeSrcOp(OPW32, Val); 1748 } 1749 1750 bool AMDGPUDisassembler::isVI() const { 1751 return STI.hasFeature(AMDGPU::FeatureVolcanicIslands); 1752 } 1753 1754 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } 1755 1756 bool AMDGPUDisassembler::isGFX90A() const { 1757 return STI.hasFeature(AMDGPU::FeatureGFX90AInsts); 1758 } 1759 1760 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } 1761 1762 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } 1763 1764 bool AMDGPUDisassembler::isGFX10Plus() const { 1765 return AMDGPU::isGFX10Plus(STI); 1766 } 1767 1768 bool AMDGPUDisassembler::isGFX11() const { 1769 return STI.hasFeature(AMDGPU::FeatureGFX11); 1770 } 1771 1772 bool AMDGPUDisassembler::isGFX11Plus() const { 1773 return AMDGPU::isGFX11Plus(STI); 1774 } 1775 1776 bool AMDGPUDisassembler::isGFX12Plus() const { 1777 return AMDGPU::isGFX12Plus(STI); 1778 } 1779 1780 bool AMDGPUDisassembler::hasArchitectedFlatScratch() const { 1781 return STI.hasFeature(AMDGPU::FeatureArchitectedFlatScratch); 1782 } 1783 1784 bool AMDGPUDisassembler::hasKernargPreload() const { 1785 return AMDGPU::hasKernargPreload(STI); 1786 } 1787 1788 //===----------------------------------------------------------------------===// 1789 // AMDGPU specific symbol handling 1790 //===----------------------------------------------------------------------===// 1791 #define GET_FIELD(MASK) (AMDHSA_BITS_GET(FourByteBuffer, MASK)) 1792 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1793 do { \ 1794 KdStream << Indent << DIRECTIVE " " << GET_FIELD(MASK) << '\n'; \ 1795 } while (0) 1796 #define PRINT_PSEUDO_DIRECTIVE_COMMENT(DIRECTIVE, MASK) \ 1797 do { \ 1798 KdStream << Indent << MAI.getCommentString() << ' ' << DIRECTIVE " " \ 1799 << GET_FIELD(MASK) << '\n'; \ 1800 } while (0) 1801 1802 // NOLINTNEXTLINE(readability-identifier-naming) 1803 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1804 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1805 using namespace amdhsa; 1806 StringRef Indent = "\t"; 1807 1808 // We cannot accurately backward compute #VGPRs used from 1809 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1810 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1811 // simply calculate the inverse of what the assembler does. 1812 1813 uint32_t GranulatedWorkitemVGPRCount = 1814 GET_FIELD(COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT); 1815 1816 uint32_t NextFreeVGPR = 1817 (GranulatedWorkitemVGPRCount + 1) * 1818 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI, EnableWavefrontSize32); 1819 1820 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1821 1822 // We cannot backward compute values used to calculate 1823 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1824 // directives can't be computed: 1825 // .amdhsa_reserve_vcc 1826 // .amdhsa_reserve_flat_scratch 1827 // .amdhsa_reserve_xnack_mask 1828 // They take their respective default values if not specified in the assembly. 1829 // 1830 // GRANULATED_WAVEFRONT_SGPR_COUNT 1831 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1832 // 1833 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1834 // are set to 0. So while disassembling we consider that: 1835 // 1836 // GRANULATED_WAVEFRONT_SGPR_COUNT 1837 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1838 // 1839 // The disassembler cannot recover the original values of those 3 directives. 1840 1841 uint32_t GranulatedWavefrontSGPRCount = 1842 GET_FIELD(COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT); 1843 1844 if (isGFX10Plus() && GranulatedWavefrontSGPRCount) 1845 return MCDisassembler::Fail; 1846 1847 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1848 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1849 1850 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1851 if (!hasArchitectedFlatScratch()) 1852 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1853 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1854 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1855 1856 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY) 1857 return MCDisassembler::Fail; 1858 1859 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1860 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1861 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1862 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1863 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1864 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1865 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1866 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1867 1868 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) 1869 return MCDisassembler::Fail; 1870 1871 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 1872 1873 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) 1874 return MCDisassembler::Fail; 1875 1876 PRINT_DIRECTIVE(".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 1877 1878 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) 1879 return MCDisassembler::Fail; 1880 1881 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER) 1882 return MCDisassembler::Fail; 1883 1884 if (isGFX9Plus()) 1885 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL); 1886 1887 if (!isGFX9Plus()) 1888 if (FourByteBuffer & COMPUTE_PGM_RSRC1_GFX6_GFX8_RESERVED0) 1889 return MCDisassembler::Fail; 1890 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED1) 1891 return MCDisassembler::Fail; 1892 if (!isGFX10Plus()) 1893 if (FourByteBuffer & COMPUTE_PGM_RSRC1_GFX6_GFX9_RESERVED2) 1894 return MCDisassembler::Fail; 1895 1896 if (isGFX10Plus()) { 1897 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1898 COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE); 1899 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED); 1900 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS); 1901 } 1902 return MCDisassembler::Success; 1903 } 1904 1905 // NOLINTNEXTLINE(readability-identifier-naming) 1906 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 1907 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1908 using namespace amdhsa; 1909 StringRef Indent = "\t"; 1910 if (hasArchitectedFlatScratch()) 1911 PRINT_DIRECTIVE(".amdhsa_enable_private_segment", 1912 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1913 else 1914 PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset", 1915 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1916 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 1917 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 1918 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 1919 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 1920 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 1921 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 1922 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 1923 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 1924 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 1925 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 1926 1927 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH) 1928 return MCDisassembler::Fail; 1929 1930 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY) 1931 return MCDisassembler::Fail; 1932 1933 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE) 1934 return MCDisassembler::Fail; 1935 1936 PRINT_DIRECTIVE( 1937 ".amdhsa_exception_fp_ieee_invalid_op", 1938 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 1939 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 1940 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 1941 PRINT_DIRECTIVE( 1942 ".amdhsa_exception_fp_ieee_div_zero", 1943 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 1944 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 1945 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 1946 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 1947 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 1948 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 1949 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 1950 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 1951 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 1952 1953 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0) 1954 return MCDisassembler::Fail; 1955 1956 return MCDisassembler::Success; 1957 } 1958 1959 // NOLINTNEXTLINE(readability-identifier-naming) 1960 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC3( 1961 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1962 using namespace amdhsa; 1963 StringRef Indent = "\t"; 1964 if (isGFX90A()) { 1965 KdStream << Indent << ".amdhsa_accum_offset " 1966 << (GET_FIELD(COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET) + 1) * 4 1967 << '\n'; 1968 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX90A_RESERVED0) 1969 return MCDisassembler::Fail; 1970 PRINT_DIRECTIVE(".amdhsa_tg_split", COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT); 1971 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX90A_RESERVED1) 1972 return MCDisassembler::Fail; 1973 } else if (isGFX10Plus()) { 1974 if (!EnableWavefrontSize32 || !*EnableWavefrontSize32) { 1975 PRINT_DIRECTIVE(".amdhsa_shared_vgpr_count", 1976 COMPUTE_PGM_RSRC3_GFX10_PLUS_SHARED_VGPR_COUNT); 1977 } else { 1978 PRINT_PSEUDO_DIRECTIVE_COMMENT( 1979 "SHARED_VGPR_COUNT", COMPUTE_PGM_RSRC3_GFX10_PLUS_SHARED_VGPR_COUNT); 1980 } 1981 1982 if (isGFX11Plus()) { 1983 PRINT_PSEUDO_DIRECTIVE_COMMENT("INST_PREF_SIZE", 1984 COMPUTE_PGM_RSRC3_GFX11_PLUS_INST_PREF_SIZE); 1985 PRINT_PSEUDO_DIRECTIVE_COMMENT("TRAP_ON_START", 1986 COMPUTE_PGM_RSRC3_GFX11_PLUS_TRAP_ON_START); 1987 PRINT_PSEUDO_DIRECTIVE_COMMENT("TRAP_ON_END", 1988 COMPUTE_PGM_RSRC3_GFX11_PLUS_TRAP_ON_END); 1989 } else { 1990 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_RESERVED0) 1991 return MCDisassembler::Fail; 1992 } 1993 1994 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_PLUS_RESERVED1) 1995 return MCDisassembler::Fail; 1996 1997 if (isGFX11Plus()) { 1998 PRINT_PSEUDO_DIRECTIVE_COMMENT("IMAGE_OP", 1999 COMPUTE_PGM_RSRC3_GFX11_PLUS_TRAP_ON_START); 2000 } else { 2001 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_RESERVED2) 2002 return MCDisassembler::Fail; 2003 } 2004 } else if (FourByteBuffer) { 2005 return MCDisassembler::Fail; 2006 } 2007 return MCDisassembler::Success; 2008 } 2009 #undef PRINT_PSEUDO_DIRECTIVE_COMMENT 2010 #undef PRINT_DIRECTIVE 2011 #undef GET_FIELD 2012 2013 MCDisassembler::DecodeStatus 2014 AMDGPUDisassembler::decodeKernelDescriptorDirective( 2015 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 2016 raw_string_ostream &KdStream) const { 2017 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 2018 do { \ 2019 KdStream << Indent << DIRECTIVE " " \ 2020 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 2021 } while (0) 2022 2023 uint16_t TwoByteBuffer = 0; 2024 uint32_t FourByteBuffer = 0; 2025 2026 StringRef ReservedBytes; 2027 StringRef Indent = "\t"; 2028 2029 assert(Bytes.size() == 64); 2030 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 2031 2032 switch (Cursor.tell()) { 2033 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 2034 FourByteBuffer = DE.getU32(Cursor); 2035 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 2036 << '\n'; 2037 return MCDisassembler::Success; 2038 2039 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 2040 FourByteBuffer = DE.getU32(Cursor); 2041 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 2042 << FourByteBuffer << '\n'; 2043 return MCDisassembler::Success; 2044 2045 case amdhsa::KERNARG_SIZE_OFFSET: 2046 FourByteBuffer = DE.getU32(Cursor); 2047 KdStream << Indent << ".amdhsa_kernarg_size " 2048 << FourByteBuffer << '\n'; 2049 return MCDisassembler::Success; 2050 2051 case amdhsa::RESERVED0_OFFSET: 2052 // 4 reserved bytes, must be 0. 2053 ReservedBytes = DE.getBytes(Cursor, 4); 2054 for (int I = 0; I < 4; ++I) { 2055 if (ReservedBytes[I] != 0) { 2056 return MCDisassembler::Fail; 2057 } 2058 } 2059 return MCDisassembler::Success; 2060 2061 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 2062 // KERNEL_CODE_ENTRY_BYTE_OFFSET 2063 // So far no directive controls this for Code Object V3, so simply skip for 2064 // disassembly. 2065 DE.skip(Cursor, 8); 2066 return MCDisassembler::Success; 2067 2068 case amdhsa::RESERVED1_OFFSET: 2069 // 20 reserved bytes, must be 0. 2070 ReservedBytes = DE.getBytes(Cursor, 20); 2071 for (int I = 0; I < 20; ++I) { 2072 if (ReservedBytes[I] != 0) { 2073 return MCDisassembler::Fail; 2074 } 2075 } 2076 return MCDisassembler::Success; 2077 2078 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 2079 FourByteBuffer = DE.getU32(Cursor); 2080 return decodeCOMPUTE_PGM_RSRC3(FourByteBuffer, KdStream); 2081 2082 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 2083 FourByteBuffer = DE.getU32(Cursor); 2084 return decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream); 2085 2086 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 2087 FourByteBuffer = DE.getU32(Cursor); 2088 return decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream); 2089 2090 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 2091 using namespace amdhsa; 2092 TwoByteBuffer = DE.getU16(Cursor); 2093 2094 if (!hasArchitectedFlatScratch()) 2095 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 2096 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 2097 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 2098 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 2099 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 2100 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 2101 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 2102 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 2103 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 2104 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 2105 if (!hasArchitectedFlatScratch()) 2106 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 2107 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 2108 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 2109 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 2110 2111 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 2112 return MCDisassembler::Fail; 2113 2114 // Reserved for GFX9 2115 if (isGFX9() && 2116 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 2117 return MCDisassembler::Fail; 2118 } else if (isGFX10Plus()) { 2119 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 2120 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 2121 } 2122 2123 if (AMDGPU::getAmdhsaCodeObjectVersion() >= AMDGPU::AMDHSA_COV5) 2124 PRINT_DIRECTIVE(".amdhsa_uses_dynamic_stack", 2125 KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK); 2126 2127 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) 2128 return MCDisassembler::Fail; 2129 2130 return MCDisassembler::Success; 2131 2132 case amdhsa::KERNARG_PRELOAD_OFFSET: 2133 using namespace amdhsa; 2134 TwoByteBuffer = DE.getU16(Cursor); 2135 if (TwoByteBuffer & KERNARG_PRELOAD_SPEC_LENGTH) { 2136 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_preload_length", 2137 KERNARG_PRELOAD_SPEC_LENGTH); 2138 } 2139 2140 if (TwoByteBuffer & KERNARG_PRELOAD_SPEC_OFFSET) { 2141 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_preload_offset", 2142 KERNARG_PRELOAD_SPEC_OFFSET); 2143 } 2144 return MCDisassembler::Success; 2145 2146 case amdhsa::RESERVED3_OFFSET: 2147 // 4 bytes from here are reserved, must be 0. 2148 ReservedBytes = DE.getBytes(Cursor, 4); 2149 for (int I = 0; I < 4; ++I) { 2150 if (ReservedBytes[I] != 0) 2151 return MCDisassembler::Fail; 2152 } 2153 return MCDisassembler::Success; 2154 2155 default: 2156 llvm_unreachable("Unhandled index. Case statements cover everything."); 2157 return MCDisassembler::Fail; 2158 } 2159 #undef PRINT_DIRECTIVE 2160 } 2161 2162 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( 2163 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 2164 // CP microcode requires the kernel descriptor to be 64 aligned. 2165 if (Bytes.size() != 64 || KdAddress % 64 != 0) 2166 return MCDisassembler::Fail; 2167 2168 // FIXME: We can't actually decode "in order" as is done below, as e.g. GFX10 2169 // requires us to know the setting of .amdhsa_wavefront_size32 in order to 2170 // accurately produce .amdhsa_next_free_vgpr, and they appear in the wrong 2171 // order. Workaround this by first looking up .amdhsa_wavefront_size32 here 2172 // when required. 2173 if (isGFX10Plus()) { 2174 uint16_t KernelCodeProperties = 2175 support::endian::read16(&Bytes[amdhsa::KERNEL_CODE_PROPERTIES_OFFSET], 2176 llvm::endianness::little); 2177 EnableWavefrontSize32 = 2178 AMDHSA_BITS_GET(KernelCodeProperties, 2179 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 2180 } 2181 2182 std::string Kd; 2183 raw_string_ostream KdStream(Kd); 2184 KdStream << ".amdhsa_kernel " << KdName << '\n'; 2185 2186 DataExtractor::Cursor C(0); 2187 while (C && C.tell() < Bytes.size()) { 2188 MCDisassembler::DecodeStatus Status = 2189 decodeKernelDescriptorDirective(C, Bytes, KdStream); 2190 2191 cantFail(C.takeError()); 2192 2193 if (Status == MCDisassembler::Fail) 2194 return MCDisassembler::Fail; 2195 } 2196 KdStream << ".end_amdhsa_kernel\n"; 2197 outs() << KdStream.str(); 2198 return MCDisassembler::Success; 2199 } 2200 2201 std::optional<MCDisassembler::DecodeStatus> 2202 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 2203 ArrayRef<uint8_t> Bytes, uint64_t Address, 2204 raw_ostream &CStream) const { 2205 // Right now only kernel descriptor needs to be handled. 2206 // We ignore all other symbols for target specific handling. 2207 // TODO: 2208 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 2209 // Object V2 and V3 when symbols are marked protected. 2210 2211 // amd_kernel_code_t for Code Object V2. 2212 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 2213 Size = 256; 2214 return MCDisassembler::Fail; 2215 } 2216 2217 // Code Object V3 kernel descriptors. 2218 StringRef Name = Symbol.Name; 2219 if (Symbol.Type == ELF::STT_OBJECT && Name.ends_with(StringRef(".kd"))) { 2220 Size = 64; // Size = 64 regardless of success or failure. 2221 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 2222 } 2223 return std::nullopt; 2224 } 2225 2226 //===----------------------------------------------------------------------===// 2227 // AMDGPUSymbolizer 2228 //===----------------------------------------------------------------------===// 2229 2230 // Try to find symbol name for specified label 2231 bool AMDGPUSymbolizer::tryAddingSymbolicOperand( 2232 MCInst &Inst, raw_ostream & /*cStream*/, int64_t Value, 2233 uint64_t /*Address*/, bool IsBranch, uint64_t /*Offset*/, 2234 uint64_t /*OpSize*/, uint64_t /*InstSize*/) { 2235 2236 if (!IsBranch) { 2237 return false; 2238 } 2239 2240 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 2241 if (!Symbols) 2242 return false; 2243 2244 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { 2245 return Val.Addr == static_cast<uint64_t>(Value) && 2246 Val.Type == ELF::STT_NOTYPE; 2247 }); 2248 if (Result != Symbols->end()) { 2249 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 2250 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 2251 Inst.addOperand(MCOperand::createExpr(Add)); 2252 return true; 2253 } 2254 // Add to list of referenced addresses, so caller can synthesize a label. 2255 ReferencedAddresses.push_back(static_cast<uint64_t>(Value)); 2256 return false; 2257 } 2258 2259 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 2260 int64_t Value, 2261 uint64_t Address) { 2262 llvm_unreachable("unimplemented"); 2263 } 2264 2265 //===----------------------------------------------------------------------===// 2266 // Initialization 2267 //===----------------------------------------------------------------------===// 2268 2269 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 2270 LLVMOpInfoCallback /*GetOpInfo*/, 2271 LLVMSymbolLookupCallback /*SymbolLookUp*/, 2272 void *DisInfo, 2273 MCContext *Ctx, 2274 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 2275 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 2276 } 2277 2278 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 2279 const MCSubtargetInfo &STI, 2280 MCContext &Ctx) { 2281 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 2282 } 2283 2284 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 2285 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 2286 createAMDGPUDisassembler); 2287 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 2288 createAMDGPUSymbolizer); 2289 } 2290