1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "TargetInfo/AMDGPUTargetInfo.h" 22 #include "Utils/AMDGPUBaseInfo.h" 23 #include "llvm-c/DisassemblerTypes.h" 24 #include "llvm/MC/MCAsmInfo.h" 25 #include "llvm/MC/MCContext.h" 26 #include "llvm/MC/MCExpr.h" 27 #include "llvm/MC/MCFixedLenDisassembler.h" 28 #include "llvm/Support/AMDHSAKernelDescriptor.h" 29 #include "llvm/Support/TargetRegistry.h" 30 31 using namespace llvm; 32 33 #define DEBUG_TYPE "amdgpu-disassembler" 34 35 #define SGPR_MAX \ 36 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 37 : AMDGPU::EncValues::SGPR_MAX_SI) 38 39 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 40 41 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 42 MCContext &Ctx, 43 MCInstrInfo const *MCII) : 44 MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), 45 TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) { 46 47 // ToDo: AMDGPUDisassembler supports only VI ISA. 48 if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10Plus()) 49 report_fatal_error("Disassembly not yet supported for subtarget"); 50 } 51 52 inline static MCDisassembler::DecodeStatus 53 addOperand(MCInst &Inst, const MCOperand& Opnd) { 54 Inst.addOperand(Opnd); 55 return Opnd.isValid() ? 56 MCDisassembler::Success : 57 MCDisassembler::Fail; 58 } 59 60 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 61 uint16_t NameIdx) { 62 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 63 if (OpIdx != -1) { 64 auto I = MI.begin(); 65 std::advance(I, OpIdx); 66 MI.insert(I, Op); 67 } 68 return OpIdx; 69 } 70 71 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, 72 uint64_t Addr, const void *Decoder) { 73 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 74 75 // Our branches take a simm16, but we need two extra bits to account for the 76 // factor of 4. 77 APInt SignedOffset(18, Imm * 4, true); 78 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 79 80 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2)) 81 return MCDisassembler::Success; 82 return addOperand(Inst, MCOperand::createImm(Imm)); 83 } 84 85 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, 86 uint64_t Addr, const void *Decoder) { 87 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 88 int64_t Offset; 89 if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 90 Offset = Imm & 0xFFFFF; 91 } else { // GFX9+ supports 21-bit signed offsets. 92 Offset = SignExtend64<21>(Imm); 93 } 94 return addOperand(Inst, MCOperand::createImm(Offset)); 95 } 96 97 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, 98 uint64_t Addr, const void *Decoder) { 99 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 100 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 101 } 102 103 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 104 static DecodeStatus StaticDecoderName(MCInst &Inst, \ 105 unsigned Imm, \ 106 uint64_t /*Addr*/, \ 107 const void *Decoder) { \ 108 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \ 109 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 110 } 111 112 #define DECODE_OPERAND_REG(RegClass) \ 113 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass) 114 115 DECODE_OPERAND_REG(VGPR_32) 116 DECODE_OPERAND_REG(VRegOrLds_32) 117 DECODE_OPERAND_REG(VS_32) 118 DECODE_OPERAND_REG(VS_64) 119 DECODE_OPERAND_REG(VS_128) 120 121 DECODE_OPERAND_REG(VReg_64) 122 DECODE_OPERAND_REG(VReg_96) 123 DECODE_OPERAND_REG(VReg_128) 124 DECODE_OPERAND_REG(VReg_256) 125 DECODE_OPERAND_REG(VReg_512) 126 DECODE_OPERAND_REG(VReg_1024) 127 128 DECODE_OPERAND_REG(SReg_32) 129 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC) 130 DECODE_OPERAND_REG(SReg_32_XEXEC_HI) 131 DECODE_OPERAND_REG(SRegOrLds_32) 132 DECODE_OPERAND_REG(SReg_64) 133 DECODE_OPERAND_REG(SReg_64_XEXEC) 134 DECODE_OPERAND_REG(SReg_128) 135 DECODE_OPERAND_REG(SReg_256) 136 DECODE_OPERAND_REG(SReg_512) 137 138 DECODE_OPERAND_REG(AGPR_32) 139 DECODE_OPERAND_REG(AReg_64) 140 DECODE_OPERAND_REG(AReg_128) 141 DECODE_OPERAND_REG(AReg_256) 142 DECODE_OPERAND_REG(AReg_512) 143 DECODE_OPERAND_REG(AReg_1024) 144 DECODE_OPERAND_REG(AV_32) 145 DECODE_OPERAND_REG(AV_64) 146 147 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, 148 unsigned Imm, 149 uint64_t Addr, 150 const void *Decoder) { 151 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 152 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 153 } 154 155 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, 156 unsigned Imm, 157 uint64_t Addr, 158 const void *Decoder) { 159 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 160 return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm)); 161 } 162 163 static DecodeStatus decodeOperand_VSrcV232(MCInst &Inst, 164 unsigned Imm, 165 uint64_t Addr, 166 const void *Decoder) { 167 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 168 return addOperand(Inst, DAsm->decodeOperand_VSrcV232(Imm)); 169 } 170 171 static DecodeStatus decodeOperand_VS_16(MCInst &Inst, 172 unsigned Imm, 173 uint64_t Addr, 174 const void *Decoder) { 175 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 176 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 177 } 178 179 static DecodeStatus decodeOperand_VS_32(MCInst &Inst, 180 unsigned Imm, 181 uint64_t Addr, 182 const void *Decoder) { 183 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 184 return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm)); 185 } 186 187 static DecodeStatus decodeOperand_AReg_64(MCInst &Inst, 188 unsigned Imm, 189 uint64_t Addr, 190 const void *Decoder) { 191 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 192 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm | 512)); 193 } 194 195 static DecodeStatus decodeOperand_AReg_128(MCInst &Inst, 196 unsigned Imm, 197 uint64_t Addr, 198 const void *Decoder) { 199 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 200 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512)); 201 } 202 203 static DecodeStatus decodeOperand_AReg_256(MCInst &Inst, 204 unsigned Imm, 205 uint64_t Addr, 206 const void *Decoder) { 207 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 208 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm | 512)); 209 } 210 211 static DecodeStatus decodeOperand_AReg_512(MCInst &Inst, 212 unsigned Imm, 213 uint64_t Addr, 214 const void *Decoder) { 215 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 216 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512)); 217 } 218 219 static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst, 220 unsigned Imm, 221 uint64_t Addr, 222 const void *Decoder) { 223 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 224 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512)); 225 } 226 227 static DecodeStatus decodeOperand_VReg_64(MCInst &Inst, 228 unsigned Imm, 229 uint64_t Addr, 230 const void *Decoder) { 231 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 232 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm)); 233 } 234 235 static DecodeStatus decodeOperand_VReg_128(MCInst &Inst, 236 unsigned Imm, 237 uint64_t Addr, 238 const void *Decoder) { 239 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 240 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm)); 241 } 242 243 static DecodeStatus decodeOperand_VReg_256(MCInst &Inst, 244 unsigned Imm, 245 uint64_t Addr, 246 const void *Decoder) { 247 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 248 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm)); 249 } 250 251 static DecodeStatus decodeOperand_VReg_512(MCInst &Inst, 252 unsigned Imm, 253 uint64_t Addr, 254 const void *Decoder) { 255 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 256 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm)); 257 } 258 259 static DecodeStatus decodeOperand_VReg_1024(MCInst &Inst, 260 unsigned Imm, 261 uint64_t Addr, 262 const void *Decoder) { 263 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 264 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm)); 265 } 266 267 static bool IsAGPROperand(const MCInst &Inst, int OpIdx, 268 const MCRegisterInfo *MRI) { 269 if (OpIdx < 0) 270 return false; 271 272 const MCOperand &Op = Inst.getOperand(OpIdx); 273 if (!Op.isReg()) 274 return false; 275 276 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); 277 auto Reg = Sub ? Sub : Op.getReg(); 278 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; 279 } 280 281 static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, 282 unsigned Imm, 283 AMDGPUDisassembler::OpWidthTy Opw, 284 const void *Decoder) { 285 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 286 if (!DAsm->isGFX90A()) { 287 Imm &= 511; 288 } else { 289 // If atomic has both vdata and vdst their register classes are tied. 290 // The bit is decoded along with the vdst, first operand. We need to 291 // change register class to AGPR if vdst was AGPR. 292 // If a DS instruction has both data0 and data1 their register classes 293 // are also tied. 294 unsigned Opc = Inst.getOpcode(); 295 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; 296 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 297 : AMDGPU::OpName::vdata; 298 const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo(); 299 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); 300 if ((int)Inst.getNumOperands() == DataIdx) { 301 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); 302 if (IsAGPROperand(Inst, DstIdx, MRI)) 303 Imm |= 512; 304 } 305 306 if (TSFlags & SIInstrFlags::DS) { 307 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); 308 if ((int)Inst.getNumOperands() == Data2Idx && 309 IsAGPROperand(Inst, DataIdx, MRI)) 310 Imm |= 512; 311 } 312 } 313 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); 314 } 315 316 static DecodeStatus DecodeAVLdSt_32RegisterClass(MCInst &Inst, 317 unsigned Imm, 318 uint64_t Addr, 319 const void *Decoder) { 320 return decodeOperand_AVLdSt_Any(Inst, Imm, 321 AMDGPUDisassembler::OPW32, Decoder); 322 } 323 324 static DecodeStatus DecodeAVLdSt_64RegisterClass(MCInst &Inst, 325 unsigned Imm, 326 uint64_t Addr, 327 const void *Decoder) { 328 return decodeOperand_AVLdSt_Any(Inst, Imm, 329 AMDGPUDisassembler::OPW64, Decoder); 330 } 331 332 static DecodeStatus DecodeAVLdSt_96RegisterClass(MCInst &Inst, 333 unsigned Imm, 334 uint64_t Addr, 335 const void *Decoder) { 336 return decodeOperand_AVLdSt_Any(Inst, Imm, 337 AMDGPUDisassembler::OPW96, Decoder); 338 } 339 340 static DecodeStatus DecodeAVLdSt_128RegisterClass(MCInst &Inst, 341 unsigned Imm, 342 uint64_t Addr, 343 const void *Decoder) { 344 return decodeOperand_AVLdSt_Any(Inst, Imm, 345 AMDGPUDisassembler::OPW128, Decoder); 346 } 347 348 static DecodeStatus decodeOperand_SReg_32(MCInst &Inst, 349 unsigned Imm, 350 uint64_t Addr, 351 const void *Decoder) { 352 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 353 return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm)); 354 } 355 356 static DecodeStatus decodeOperand_VGPR_32(MCInst &Inst, 357 unsigned Imm, 358 uint64_t Addr, 359 const void *Decoder) { 360 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 361 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW32, Imm)); 362 } 363 364 #define DECODE_SDWA(DecName) \ 365 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 366 367 DECODE_SDWA(Src32) 368 DECODE_SDWA(Src16) 369 DECODE_SDWA(VopcDst) 370 371 #include "AMDGPUGenDisassemblerTables.inc" 372 373 //===----------------------------------------------------------------------===// 374 // 375 //===----------------------------------------------------------------------===// 376 377 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 378 assert(Bytes.size() >= sizeof(T)); 379 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data()); 380 Bytes = Bytes.slice(sizeof(T)); 381 return Res; 382 } 383 384 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table, 385 MCInst &MI, 386 uint64_t Inst, 387 uint64_t Address) const { 388 assert(MI.getOpcode() == 0); 389 assert(MI.getNumOperands() == 0); 390 MCInst TmpInst; 391 HasLiteral = false; 392 const auto SavedBytes = Bytes; 393 if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) { 394 MI = TmpInst; 395 return MCDisassembler::Success; 396 } 397 Bytes = SavedBytes; 398 return MCDisassembler::Fail; 399 } 400 401 static bool isValidDPP8(const MCInst &MI) { 402 using namespace llvm::AMDGPU::DPP; 403 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi); 404 assert(FiIdx != -1); 405 if ((unsigned)FiIdx >= MI.getNumOperands()) 406 return false; 407 unsigned Fi = MI.getOperand(FiIdx).getImm(); 408 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1; 409 } 410 411 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 412 ArrayRef<uint8_t> Bytes_, 413 uint64_t Address, 414 raw_ostream &CS) const { 415 CommentStream = &CS; 416 bool IsSDWA = false; 417 418 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 419 Bytes = Bytes_.slice(0, MaxInstBytesNum); 420 421 DecodeStatus Res = MCDisassembler::Fail; 422 do { 423 // ToDo: better to switch encoding length using some bit predicate 424 // but it is unknown yet, so try all we can 425 426 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 427 // encodings 428 if (Bytes.size() >= 8) { 429 const uint64_t QW = eatBytes<uint64_t>(Bytes); 430 431 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 432 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address); 433 if (Res) { 434 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) 435 == -1) 436 break; 437 if (convertDPP8Inst(MI) == MCDisassembler::Success) 438 break; 439 MI = MCInst(); // clear 440 } 441 } 442 443 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address); 444 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 445 break; 446 447 MI = MCInst(); // clear 448 449 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address); 450 if (Res) break; 451 452 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address); 453 if (Res) { IsSDWA = true; break; } 454 455 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address); 456 if (Res) { IsSDWA = true; break; } 457 458 Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address); 459 if (Res) { IsSDWA = true; break; } 460 461 if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) { 462 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address); 463 if (Res) 464 break; 465 } 466 467 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 468 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 469 // table first so we print the correct name. 470 if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) { 471 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address); 472 if (Res) 473 break; 474 } 475 } 476 477 // Reinitialize Bytes as DPP64 could have eaten too much 478 Bytes = Bytes_.slice(0, MaxInstBytesNum); 479 480 // Try decode 32-bit instruction 481 if (Bytes.size() < 4) break; 482 const uint32_t DW = eatBytes<uint32_t>(Bytes); 483 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address); 484 if (Res) break; 485 486 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address); 487 if (Res) break; 488 489 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address); 490 if (Res) break; 491 492 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 493 Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address); 494 if (Res) 495 break; 496 } 497 498 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 499 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address); 500 if (Res) break; 501 } 502 503 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address); 504 if (Res) break; 505 506 if (Bytes.size() < 4) break; 507 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 508 509 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 510 Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address); 511 if (Res) 512 break; 513 } 514 515 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address); 516 if (Res) break; 517 518 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address); 519 if (Res) break; 520 521 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address); 522 if (Res) break; 523 524 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address); 525 } while (false); 526 527 if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi || 528 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 || 529 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 || 530 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 || 531 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 || 532 MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi || 533 MI.getOpcode() == AMDGPU::V_FMAC_F64_e64_gfx90a || 534 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi || 535 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 || 536 MI.getOpcode() == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 || 537 MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10)) { 538 // Insert dummy unused src2_modifiers. 539 insertNamedMCOperand(MI, MCOperand::createImm(0), 540 AMDGPU::OpName::src2_modifiers); 541 } 542 543 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 544 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT)) && 545 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::glc1) != -1) { 546 insertNamedMCOperand(MI, MCOperand::createImm(1), AMDGPU::OpName::glc1); 547 } 548 549 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 550 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) && 551 (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts])) { 552 // GFX90A lost TFE, its place is occupied by ACC. 553 int TFEOpIdx = 554 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); 555 if (TFEOpIdx != -1) { 556 auto TFEIter = MI.begin(); 557 std::advance(TFEIter, TFEOpIdx); 558 MI.insert(TFEIter, MCOperand::createImm(0)); 559 } 560 } 561 562 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 563 (SIInstrFlags::FLAT | 564 SIInstrFlags::MTBUF | SIInstrFlags::MUBUF))) { 565 if (!isGFX10()) { 566 int DLCOpIdx = 567 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dlc); 568 if (DLCOpIdx != -1) { 569 auto DLCIter = MI.begin(); 570 std::advance(DLCIter, DLCOpIdx); 571 MI.insert(DLCIter, MCOperand::createImm(0)); 572 } 573 } 574 } 575 576 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 577 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF))) { 578 int SWZOpIdx = 579 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); 580 if (SWZOpIdx != -1) { 581 auto SWZIter = MI.begin(); 582 std::advance(SWZIter, SWZOpIdx); 583 MI.insert(SWZIter, MCOperand::createImm(0)); 584 } 585 } 586 587 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 588 int VAddr0Idx = 589 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 590 int RsrcIdx = 591 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 592 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 593 if (VAddr0Idx >= 0 && NSAArgs > 0) { 594 unsigned NSAWords = (NSAArgs + 3) / 4; 595 if (Bytes.size() < 4 * NSAWords) { 596 Res = MCDisassembler::Fail; 597 } else { 598 for (unsigned i = 0; i < NSAArgs; ++i) { 599 MI.insert(MI.begin() + VAddr0Idx + 1 + i, 600 decodeOperand_VGPR_32(Bytes[i])); 601 } 602 Bytes = Bytes.slice(4 * NSAWords); 603 } 604 } 605 606 if (Res) 607 Res = convertMIMGInst(MI); 608 } 609 610 if (Res && IsSDWA) 611 Res = convertSDWAInst(MI); 612 613 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 614 AMDGPU::OpName::vdst_in); 615 if (VDstIn_Idx != -1) { 616 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 617 MCOI::OperandConstraint::TIED_TO); 618 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 619 !MI.getOperand(VDstIn_Idx).isReg() || 620 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 621 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 622 MI.erase(&MI.getOperand(VDstIn_Idx)); 623 insertNamedMCOperand(MI, 624 MCOperand::createReg(MI.getOperand(Tied).getReg()), 625 AMDGPU::OpName::vdst_in); 626 } 627 } 628 629 // if the opcode was not recognized we'll assume a Size of 4 bytes 630 // (unless there are fewer bytes left) 631 Size = Res ? (MaxInstBytesNum - Bytes.size()) 632 : std::min((size_t)4, Bytes_.size()); 633 return Res; 634 } 635 636 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 637 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 638 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 639 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1) 640 // VOPC - insert clamp 641 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 642 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 643 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 644 if (SDst != -1) { 645 // VOPC - insert VCC register as sdst 646 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 647 AMDGPU::OpName::sdst); 648 } else { 649 // VOP1/2 - insert omod if present in instruction 650 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 651 } 652 } 653 return MCDisassembler::Success; 654 } 655 656 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 657 unsigned Opc = MI.getOpcode(); 658 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 659 660 // Insert dummy unused src modifiers. 661 if (MI.getNumOperands() < DescNumOps && 662 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1) 663 insertNamedMCOperand(MI, MCOperand::createImm(0), 664 AMDGPU::OpName::src0_modifiers); 665 666 if (MI.getNumOperands() < DescNumOps && 667 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1) 668 insertNamedMCOperand(MI, MCOperand::createImm(0), 669 AMDGPU::OpName::src1_modifiers); 670 671 return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail; 672 } 673 674 // Note that before gfx10, the MIMG encoding provided no information about 675 // VADDR size. Consequently, decoded instructions always show address as if it 676 // has 1 dword, which could be not really so. 677 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 678 679 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 680 AMDGPU::OpName::vdst); 681 682 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 683 AMDGPU::OpName::vdata); 684 int VAddr0Idx = 685 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 686 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 687 AMDGPU::OpName::dmask); 688 689 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 690 AMDGPU::OpName::tfe); 691 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 692 AMDGPU::OpName::d16); 693 694 assert(VDataIdx != -1); 695 if (DMaskIdx == -1 || TFEIdx == -1) {// intersect_ray 696 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16) > -1) { 697 assert(MI.getOpcode() == AMDGPU::IMAGE_BVH_INTERSECT_RAY_a16_sa || 698 MI.getOpcode() == AMDGPU::IMAGE_BVH_INTERSECT_RAY_a16_nsa || 699 MI.getOpcode() == AMDGPU::IMAGE_BVH64_INTERSECT_RAY_a16_sa || 700 MI.getOpcode() == AMDGPU::IMAGE_BVH64_INTERSECT_RAY_a16_nsa); 701 addOperand(MI, MCOperand::createImm(1)); 702 } 703 return MCDisassembler::Success; 704 } 705 706 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 707 bool IsAtomic = (VDstIdx != -1); 708 bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4; 709 710 bool IsNSA = false; 711 unsigned AddrSize = Info->VAddrDwords; 712 713 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 714 unsigned DimIdx = 715 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 716 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 717 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 718 const AMDGPU::MIMGDimInfo *Dim = 719 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 720 721 AddrSize = BaseOpcode->NumExtraArgs + 722 (BaseOpcode->Gradients ? Dim->NumGradients : 0) + 723 (BaseOpcode->Coordinates ? Dim->NumCoords : 0) + 724 (BaseOpcode->LodOrClampOrMip ? 1 : 0); 725 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA; 726 if (!IsNSA) { 727 if (AddrSize > 8) 728 AddrSize = 16; 729 else if (AddrSize > 4) 730 AddrSize = 8; 731 } else { 732 if (AddrSize > Info->VAddrDwords) { 733 // The NSA encoding does not contain enough operands for the combination 734 // of base opcode / dimension. Should this be an error? 735 return MCDisassembler::Success; 736 } 737 } 738 } 739 740 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 741 unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u); 742 743 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 744 if (D16 && AMDGPU::hasPackedD16(STI)) { 745 DstSize = (DstSize + 1) / 2; 746 } 747 748 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm()) 749 DstSize += 1; 750 751 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 752 return MCDisassembler::Success; 753 754 int NewOpcode = 755 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 756 if (NewOpcode == -1) 757 return MCDisassembler::Success; 758 759 // Widen the register to the correct number of enabled channels. 760 unsigned NewVdata = AMDGPU::NoRegister; 761 if (DstSize != Info->VDataDwords) { 762 auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; 763 764 // Get first subregister of VData 765 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 766 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 767 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 768 769 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 770 &MRI.getRegClass(DataRCID)); 771 if (NewVdata == AMDGPU::NoRegister) { 772 // It's possible to encode this such that the low register + enabled 773 // components exceeds the register count. 774 return MCDisassembler::Success; 775 } 776 } 777 778 unsigned NewVAddr0 = AMDGPU::NoRegister; 779 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10] && !IsNSA && 780 AddrSize != Info->VAddrDwords) { 781 unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg(); 782 unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0); 783 VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0; 784 785 auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass; 786 NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0, 787 &MRI.getRegClass(AddrRCID)); 788 if (NewVAddr0 == AMDGPU::NoRegister) 789 return MCDisassembler::Success; 790 } 791 792 MI.setOpcode(NewOpcode); 793 794 if (NewVdata != AMDGPU::NoRegister) { 795 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 796 797 if (IsAtomic) { 798 // Atomic operations have an additional operand (a copy of data) 799 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 800 } 801 } 802 803 if (NewVAddr0 != AMDGPU::NoRegister) { 804 MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0); 805 } else if (IsNSA) { 806 assert(AddrSize <= Info->VAddrDwords); 807 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 808 MI.begin() + VAddr0Idx + Info->VAddrDwords); 809 } 810 811 return MCDisassembler::Success; 812 } 813 814 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 815 return getContext().getRegisterInfo()-> 816 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 817 } 818 819 inline 820 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 821 const Twine& ErrMsg) const { 822 *CommentStream << "Error: " + ErrMsg; 823 824 // ToDo: add support for error operands to MCInst.h 825 // return MCOperand::createError(V); 826 return MCOperand(); 827 } 828 829 inline 830 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 831 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 832 } 833 834 inline 835 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 836 unsigned Val) const { 837 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 838 if (Val >= RegCl.getNumRegs()) 839 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 840 ": unknown register " + Twine(Val)); 841 return createRegOperand(RegCl.getRegister(Val)); 842 } 843 844 inline 845 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 846 unsigned Val) const { 847 // ToDo: SI/CI have 104 SGPRs, VI - 102 848 // Valery: here we accepting as much as we can, let assembler sort it out 849 int shift = 0; 850 switch (SRegClassID) { 851 case AMDGPU::SGPR_32RegClassID: 852 case AMDGPU::TTMP_32RegClassID: 853 break; 854 case AMDGPU::SGPR_64RegClassID: 855 case AMDGPU::TTMP_64RegClassID: 856 shift = 1; 857 break; 858 case AMDGPU::SGPR_128RegClassID: 859 case AMDGPU::TTMP_128RegClassID: 860 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 861 // this bundle? 862 case AMDGPU::SGPR_256RegClassID: 863 case AMDGPU::TTMP_256RegClassID: 864 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 865 // this bundle? 866 case AMDGPU::SGPR_512RegClassID: 867 case AMDGPU::TTMP_512RegClassID: 868 shift = 2; 869 break; 870 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 871 // this bundle? 872 default: 873 llvm_unreachable("unhandled register class"); 874 } 875 876 if (Val % (1 << shift)) { 877 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 878 << ": scalar reg isn't aligned " << Val; 879 } 880 881 return createRegOperand(SRegClassID, Val >> shift); 882 } 883 884 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { 885 return decodeSrcOp(OPW32, Val); 886 } 887 888 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { 889 return decodeSrcOp(OPW64, Val); 890 } 891 892 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const { 893 return decodeSrcOp(OPW128, Val); 894 } 895 896 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const { 897 return decodeSrcOp(OPW16, Val); 898 } 899 900 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const { 901 return decodeSrcOp(OPWV216, Val); 902 } 903 904 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV232(unsigned Val) const { 905 return decodeSrcOp(OPWV232, Val); 906 } 907 908 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { 909 // Some instructions have operand restrictions beyond what the encoding 910 // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra 911 // high bit. 912 Val &= 255; 913 914 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); 915 } 916 917 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const { 918 return decodeSrcOp(OPW32, Val); 919 } 920 921 MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const { 922 return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255); 923 } 924 925 MCOperand AMDGPUDisassembler::decodeOperand_AReg_64(unsigned Val) const { 926 return createRegOperand(AMDGPU::AReg_64RegClassID, Val & 255); 927 } 928 929 MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const { 930 return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255); 931 } 932 933 MCOperand AMDGPUDisassembler::decodeOperand_AReg_256(unsigned Val) const { 934 return createRegOperand(AMDGPU::AReg_256RegClassID, Val & 255); 935 } 936 937 MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const { 938 return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255); 939 } 940 941 MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const { 942 return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255); 943 } 944 945 MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const { 946 return decodeSrcOp(OPW32, Val); 947 } 948 949 MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const { 950 return decodeSrcOp(OPW64, Val); 951 } 952 953 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { 954 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); 955 } 956 957 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { 958 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); 959 } 960 961 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { 962 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); 963 } 964 965 MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const { 966 return createRegOperand(AMDGPU::VReg_256RegClassID, Val); 967 } 968 969 MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const { 970 return createRegOperand(AMDGPU::VReg_512RegClassID, Val); 971 } 972 973 MCOperand AMDGPUDisassembler::decodeOperand_VReg_1024(unsigned Val) const { 974 return createRegOperand(AMDGPU::VReg_1024RegClassID, Val); 975 } 976 977 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { 978 // table-gen generated disassembler doesn't care about operand types 979 // leaving only registry class so SSrc_32 operand turns into SReg_32 980 // and therefore we accept immediates and literals here as well 981 return decodeSrcOp(OPW32, Val); 982 } 983 984 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC( 985 unsigned Val) const { 986 // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI 987 return decodeOperand_SReg_32(Val); 988 } 989 990 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI( 991 unsigned Val) const { 992 // SReg_32_XM0 is SReg_32 without EXEC_HI 993 return decodeOperand_SReg_32(Val); 994 } 995 996 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const { 997 // table-gen generated disassembler doesn't care about operand types 998 // leaving only registry class so SSrc_32 operand turns into SReg_32 999 // and therefore we accept immediates and literals here as well 1000 return decodeSrcOp(OPW32, Val); 1001 } 1002 1003 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { 1004 return decodeSrcOp(OPW64, Val); 1005 } 1006 1007 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const { 1008 return decodeSrcOp(OPW64, Val); 1009 } 1010 1011 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { 1012 return decodeSrcOp(OPW128, Val); 1013 } 1014 1015 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { 1016 return decodeDstOp(OPW256, Val); 1017 } 1018 1019 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { 1020 return decodeDstOp(OPW512, Val); 1021 } 1022 1023 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { 1024 // For now all literal constants are supposed to be unsigned integer 1025 // ToDo: deal with signed/unsigned 64-bit integer constants 1026 // ToDo: deal with float/double constants 1027 if (!HasLiteral) { 1028 if (Bytes.size() < 4) { 1029 return errOperand(0, "cannot read literal, inst bytes left " + 1030 Twine(Bytes.size())); 1031 } 1032 HasLiteral = true; 1033 Literal = eatBytes<uint32_t>(Bytes); 1034 } 1035 return MCOperand::createImm(Literal); 1036 } 1037 1038 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 1039 using namespace AMDGPU::EncValues; 1040 1041 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 1042 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 1043 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 1044 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 1045 // Cast prevents negative overflow. 1046 } 1047 1048 static int64_t getInlineImmVal32(unsigned Imm) { 1049 switch (Imm) { 1050 case 240: 1051 return FloatToBits(0.5f); 1052 case 241: 1053 return FloatToBits(-0.5f); 1054 case 242: 1055 return FloatToBits(1.0f); 1056 case 243: 1057 return FloatToBits(-1.0f); 1058 case 244: 1059 return FloatToBits(2.0f); 1060 case 245: 1061 return FloatToBits(-2.0f); 1062 case 246: 1063 return FloatToBits(4.0f); 1064 case 247: 1065 return FloatToBits(-4.0f); 1066 case 248: // 1 / (2 * PI) 1067 return 0x3e22f983; 1068 default: 1069 llvm_unreachable("invalid fp inline imm"); 1070 } 1071 } 1072 1073 static int64_t getInlineImmVal64(unsigned Imm) { 1074 switch (Imm) { 1075 case 240: 1076 return DoubleToBits(0.5); 1077 case 241: 1078 return DoubleToBits(-0.5); 1079 case 242: 1080 return DoubleToBits(1.0); 1081 case 243: 1082 return DoubleToBits(-1.0); 1083 case 244: 1084 return DoubleToBits(2.0); 1085 case 245: 1086 return DoubleToBits(-2.0); 1087 case 246: 1088 return DoubleToBits(4.0); 1089 case 247: 1090 return DoubleToBits(-4.0); 1091 case 248: // 1 / (2 * PI) 1092 return 0x3fc45f306dc9c882; 1093 default: 1094 llvm_unreachable("invalid fp inline imm"); 1095 } 1096 } 1097 1098 static int64_t getInlineImmVal16(unsigned Imm) { 1099 switch (Imm) { 1100 case 240: 1101 return 0x3800; 1102 case 241: 1103 return 0xB800; 1104 case 242: 1105 return 0x3C00; 1106 case 243: 1107 return 0xBC00; 1108 case 244: 1109 return 0x4000; 1110 case 245: 1111 return 0xC000; 1112 case 246: 1113 return 0x4400; 1114 case 247: 1115 return 0xC400; 1116 case 248: // 1 / (2 * PI) 1117 return 0x3118; 1118 default: 1119 llvm_unreachable("invalid fp inline imm"); 1120 } 1121 } 1122 1123 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) { 1124 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 1125 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 1126 1127 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 1128 switch (Width) { 1129 case OPW32: 1130 case OPW128: // splat constants 1131 case OPW512: 1132 case OPW1024: 1133 case OPWV232: 1134 return MCOperand::createImm(getInlineImmVal32(Imm)); 1135 case OPW64: 1136 case OPW256: 1137 return MCOperand::createImm(getInlineImmVal64(Imm)); 1138 case OPW16: 1139 case OPWV216: 1140 return MCOperand::createImm(getInlineImmVal16(Imm)); 1141 default: 1142 llvm_unreachable("implement me"); 1143 } 1144 } 1145 1146 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 1147 using namespace AMDGPU; 1148 1149 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1150 switch (Width) { 1151 default: // fall 1152 case OPW32: 1153 case OPW16: 1154 case OPWV216: 1155 return VGPR_32RegClassID; 1156 case OPW64: 1157 case OPWV232: return VReg_64RegClassID; 1158 case OPW96: return VReg_96RegClassID; 1159 case OPW128: return VReg_128RegClassID; 1160 case OPW160: return VReg_160RegClassID; 1161 case OPW256: return VReg_256RegClassID; 1162 case OPW512: return VReg_512RegClassID; 1163 case OPW1024: return VReg_1024RegClassID; 1164 } 1165 } 1166 1167 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 1168 using namespace AMDGPU; 1169 1170 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1171 switch (Width) { 1172 default: // fall 1173 case OPW32: 1174 case OPW16: 1175 case OPWV216: 1176 return AGPR_32RegClassID; 1177 case OPW64: 1178 case OPWV232: return AReg_64RegClassID; 1179 case OPW96: return AReg_96RegClassID; 1180 case OPW128: return AReg_128RegClassID; 1181 case OPW160: return AReg_160RegClassID; 1182 case OPW256: return AReg_256RegClassID; 1183 case OPW512: return AReg_512RegClassID; 1184 case OPW1024: return AReg_1024RegClassID; 1185 } 1186 } 1187 1188 1189 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 1190 using namespace AMDGPU; 1191 1192 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1193 switch (Width) { 1194 default: // fall 1195 case OPW32: 1196 case OPW16: 1197 case OPWV216: 1198 return SGPR_32RegClassID; 1199 case OPW64: 1200 case OPWV232: return SGPR_64RegClassID; 1201 case OPW96: return SGPR_96RegClassID; 1202 case OPW128: return SGPR_128RegClassID; 1203 case OPW160: return SGPR_160RegClassID; 1204 case OPW256: return SGPR_256RegClassID; 1205 case OPW512: return SGPR_512RegClassID; 1206 } 1207 } 1208 1209 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 1210 using namespace AMDGPU; 1211 1212 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1213 switch (Width) { 1214 default: // fall 1215 case OPW32: 1216 case OPW16: 1217 case OPWV216: 1218 return TTMP_32RegClassID; 1219 case OPW64: 1220 case OPWV232: return TTMP_64RegClassID; 1221 case OPW128: return TTMP_128RegClassID; 1222 case OPW256: return TTMP_256RegClassID; 1223 case OPW512: return TTMP_512RegClassID; 1224 } 1225 } 1226 1227 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 1228 using namespace AMDGPU::EncValues; 1229 1230 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN; 1231 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX; 1232 1233 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1234 } 1235 1236 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const { 1237 using namespace AMDGPU::EncValues; 1238 1239 assert(Val < 1024); // enum10 1240 1241 bool IsAGPR = Val & 512; 1242 Val &= 511; 1243 1244 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1245 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1246 : getVgprClassId(Width), Val - VGPR_MIN); 1247 } 1248 if (Val <= SGPR_MAX) { 1249 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1250 static_assert(SGPR_MIN == 0, ""); 1251 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1252 } 1253 1254 int TTmpIdx = getTTmpIdx(Val); 1255 if (TTmpIdx >= 0) { 1256 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1257 } 1258 1259 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1260 return decodeIntImmed(Val); 1261 1262 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1263 return decodeFPImmed(Width, Val); 1264 1265 if (Val == LITERAL_CONST) 1266 return decodeLiteralConstant(); 1267 1268 switch (Width) { 1269 case OPW32: 1270 case OPW16: 1271 case OPWV216: 1272 return decodeSpecialReg32(Val); 1273 case OPW64: 1274 case OPWV232: 1275 return decodeSpecialReg64(Val); 1276 default: 1277 llvm_unreachable("unexpected immediate type"); 1278 } 1279 } 1280 1281 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const { 1282 using namespace AMDGPU::EncValues; 1283 1284 assert(Val < 128); 1285 assert(Width == OPW256 || Width == OPW512); 1286 1287 if (Val <= SGPR_MAX) { 1288 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1289 static_assert(SGPR_MIN == 0, ""); 1290 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1291 } 1292 1293 int TTmpIdx = getTTmpIdx(Val); 1294 if (TTmpIdx >= 0) { 1295 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1296 } 1297 1298 llvm_unreachable("unknown dst register"); 1299 } 1300 1301 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1302 using namespace AMDGPU; 1303 1304 switch (Val) { 1305 case 102: return createRegOperand(FLAT_SCR_LO); 1306 case 103: return createRegOperand(FLAT_SCR_HI); 1307 case 104: return createRegOperand(XNACK_MASK_LO); 1308 case 105: return createRegOperand(XNACK_MASK_HI); 1309 case 106: return createRegOperand(VCC_LO); 1310 case 107: return createRegOperand(VCC_HI); 1311 case 108: return createRegOperand(TBA_LO); 1312 case 109: return createRegOperand(TBA_HI); 1313 case 110: return createRegOperand(TMA_LO); 1314 case 111: return createRegOperand(TMA_HI); 1315 case 124: return createRegOperand(M0); 1316 case 125: return createRegOperand(SGPR_NULL); 1317 case 126: return createRegOperand(EXEC_LO); 1318 case 127: return createRegOperand(EXEC_HI); 1319 case 235: return createRegOperand(SRC_SHARED_BASE); 1320 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1321 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1322 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1323 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1324 case 251: return createRegOperand(SRC_VCCZ); 1325 case 252: return createRegOperand(SRC_EXECZ); 1326 case 253: return createRegOperand(SRC_SCC); 1327 case 254: return createRegOperand(LDS_DIRECT); 1328 default: break; 1329 } 1330 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1331 } 1332 1333 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1334 using namespace AMDGPU; 1335 1336 switch (Val) { 1337 case 102: return createRegOperand(FLAT_SCR); 1338 case 104: return createRegOperand(XNACK_MASK); 1339 case 106: return createRegOperand(VCC); 1340 case 108: return createRegOperand(TBA); 1341 case 110: return createRegOperand(TMA); 1342 case 125: return createRegOperand(SGPR_NULL); 1343 case 126: return createRegOperand(EXEC); 1344 case 235: return createRegOperand(SRC_SHARED_BASE); 1345 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1346 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1347 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1348 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1349 case 251: return createRegOperand(SRC_VCCZ); 1350 case 252: return createRegOperand(SRC_EXECZ); 1351 case 253: return createRegOperand(SRC_SCC); 1352 default: break; 1353 } 1354 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1355 } 1356 1357 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 1358 const unsigned Val) const { 1359 using namespace AMDGPU::SDWA; 1360 using namespace AMDGPU::EncValues; 1361 1362 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1363 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 1364 // XXX: cast to int is needed to avoid stupid warning: 1365 // compare with unsigned is always true 1366 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1367 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1368 return createRegOperand(getVgprClassId(Width), 1369 Val - SDWA9EncValues::SRC_VGPR_MIN); 1370 } 1371 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1372 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1373 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1374 return createSRegOperand(getSgprClassId(Width), 1375 Val - SDWA9EncValues::SRC_SGPR_MIN); 1376 } 1377 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1378 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1379 return createSRegOperand(getTtmpClassId(Width), 1380 Val - SDWA9EncValues::SRC_TTMP_MIN); 1381 } 1382 1383 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1384 1385 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1386 return decodeIntImmed(SVal); 1387 1388 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1389 return decodeFPImmed(Width, SVal); 1390 1391 return decodeSpecialReg32(SVal); 1392 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 1393 return createRegOperand(getVgprClassId(Width), Val); 1394 } 1395 llvm_unreachable("unsupported target"); 1396 } 1397 1398 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1399 return decodeSDWASrc(OPW16, Val); 1400 } 1401 1402 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1403 return decodeSDWASrc(OPW32, Val); 1404 } 1405 1406 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1407 using namespace AMDGPU::SDWA; 1408 1409 assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1410 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) && 1411 "SDWAVopcDst should be present only on GFX9+"); 1412 1413 bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64]; 1414 1415 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1416 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1417 1418 int TTmpIdx = getTTmpIdx(Val); 1419 if (TTmpIdx >= 0) { 1420 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1421 return createSRegOperand(TTmpClsId, TTmpIdx); 1422 } else if (Val > SGPR_MAX) { 1423 return IsWave64 ? decodeSpecialReg64(Val) 1424 : decodeSpecialReg32(Val); 1425 } else { 1426 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1427 } 1428 } else { 1429 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1430 } 1431 } 1432 1433 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1434 return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ? 1435 decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val); 1436 } 1437 1438 bool AMDGPUDisassembler::isVI() const { 1439 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]; 1440 } 1441 1442 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } 1443 1444 bool AMDGPUDisassembler::isGFX90A() const { 1445 return STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]; 1446 } 1447 1448 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } 1449 1450 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } 1451 1452 bool AMDGPUDisassembler::isGFX10Plus() const { 1453 return AMDGPU::isGFX10Plus(STI); 1454 } 1455 1456 //===----------------------------------------------------------------------===// 1457 // AMDGPU specific symbol handling 1458 //===----------------------------------------------------------------------===// 1459 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1460 do { \ 1461 KdStream << Indent << DIRECTIVE " " \ 1462 << ((FourByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1463 } while (0) 1464 1465 // NOLINTNEXTLINE(readability-identifier-naming) 1466 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1467 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1468 using namespace amdhsa; 1469 StringRef Indent = "\t"; 1470 1471 // We cannot accurately backward compute #VGPRs used from 1472 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1473 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1474 // simply calculate the inverse of what the assembler does. 1475 1476 uint32_t GranulatedWorkitemVGPRCount = 1477 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT) >> 1478 COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT; 1479 1480 uint32_t NextFreeVGPR = (GranulatedWorkitemVGPRCount + 1) * 1481 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI); 1482 1483 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1484 1485 // We cannot backward compute values used to calculate 1486 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1487 // directives can't be computed: 1488 // .amdhsa_reserve_vcc 1489 // .amdhsa_reserve_flat_scratch 1490 // .amdhsa_reserve_xnack_mask 1491 // They take their respective default values if not specified in the assembly. 1492 // 1493 // GRANULATED_WAVEFRONT_SGPR_COUNT 1494 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1495 // 1496 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1497 // are set to 0. So while disassembling we consider that: 1498 // 1499 // GRANULATED_WAVEFRONT_SGPR_COUNT 1500 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1501 // 1502 // The disassembler cannot recover the original values of those 3 directives. 1503 1504 uint32_t GranulatedWavefrontSGPRCount = 1505 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT) >> 1506 COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT; 1507 1508 if (isGFX10Plus() && GranulatedWavefrontSGPRCount) 1509 return MCDisassembler::Fail; 1510 1511 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1512 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1513 1514 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1515 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1516 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1517 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1518 1519 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY) 1520 return MCDisassembler::Fail; 1521 1522 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1523 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1524 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1525 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1526 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1527 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1528 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1529 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1530 1531 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) 1532 return MCDisassembler::Fail; 1533 1534 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 1535 1536 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) 1537 return MCDisassembler::Fail; 1538 1539 PRINT_DIRECTIVE(".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 1540 1541 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) 1542 return MCDisassembler::Fail; 1543 1544 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER) 1545 return MCDisassembler::Fail; 1546 1547 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_FP16_OVFL); 1548 1549 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED0) 1550 return MCDisassembler::Fail; 1551 1552 if (isGFX10Plus()) { 1553 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1554 COMPUTE_PGM_RSRC1_WGP_MODE); 1555 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_MEM_ORDERED); 1556 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_FWD_PROGRESS); 1557 } 1558 return MCDisassembler::Success; 1559 } 1560 1561 // NOLINTNEXTLINE(readability-identifier-naming) 1562 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 1563 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1564 using namespace amdhsa; 1565 StringRef Indent = "\t"; 1566 PRINT_DIRECTIVE( 1567 ".amdhsa_system_sgpr_private_segment_wavefront_offset", 1568 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1569 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 1570 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 1571 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 1572 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 1573 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 1574 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 1575 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 1576 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 1577 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 1578 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 1579 1580 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH) 1581 return MCDisassembler::Fail; 1582 1583 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY) 1584 return MCDisassembler::Fail; 1585 1586 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE) 1587 return MCDisassembler::Fail; 1588 1589 PRINT_DIRECTIVE( 1590 ".amdhsa_exception_fp_ieee_invalid_op", 1591 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 1592 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 1593 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 1594 PRINT_DIRECTIVE( 1595 ".amdhsa_exception_fp_ieee_div_zero", 1596 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 1597 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 1598 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 1599 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 1600 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 1601 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 1602 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 1603 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 1604 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 1605 1606 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0) 1607 return MCDisassembler::Fail; 1608 1609 return MCDisassembler::Success; 1610 } 1611 1612 #undef PRINT_DIRECTIVE 1613 1614 MCDisassembler::DecodeStatus 1615 AMDGPUDisassembler::decodeKernelDescriptorDirective( 1616 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 1617 raw_string_ostream &KdStream) const { 1618 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1619 do { \ 1620 KdStream << Indent << DIRECTIVE " " \ 1621 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1622 } while (0) 1623 1624 uint16_t TwoByteBuffer = 0; 1625 uint32_t FourByteBuffer = 0; 1626 uint64_t EightByteBuffer = 0; 1627 1628 StringRef ReservedBytes; 1629 StringRef Indent = "\t"; 1630 1631 assert(Bytes.size() == 64); 1632 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 1633 1634 switch (Cursor.tell()) { 1635 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 1636 FourByteBuffer = DE.getU32(Cursor); 1637 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 1638 << '\n'; 1639 return MCDisassembler::Success; 1640 1641 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 1642 FourByteBuffer = DE.getU32(Cursor); 1643 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 1644 << FourByteBuffer << '\n'; 1645 return MCDisassembler::Success; 1646 1647 case amdhsa::RESERVED0_OFFSET: 1648 // 8 reserved bytes, must be 0. 1649 EightByteBuffer = DE.getU64(Cursor); 1650 if (EightByteBuffer) { 1651 return MCDisassembler::Fail; 1652 } 1653 return MCDisassembler::Success; 1654 1655 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 1656 // KERNEL_CODE_ENTRY_BYTE_OFFSET 1657 // So far no directive controls this for Code Object V3, so simply skip for 1658 // disassembly. 1659 DE.skip(Cursor, 8); 1660 return MCDisassembler::Success; 1661 1662 case amdhsa::RESERVED1_OFFSET: 1663 // 20 reserved bytes, must be 0. 1664 ReservedBytes = DE.getBytes(Cursor, 20); 1665 for (int I = 0; I < 20; ++I) { 1666 if (ReservedBytes[I] != 0) { 1667 return MCDisassembler::Fail; 1668 } 1669 } 1670 return MCDisassembler::Success; 1671 1672 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 1673 // COMPUTE_PGM_RSRC3 1674 // - Only set for GFX10, GFX6-9 have this to be 0. 1675 // - Currently no directives directly control this. 1676 FourByteBuffer = DE.getU32(Cursor); 1677 if (!isGFX10Plus() && FourByteBuffer) { 1678 return MCDisassembler::Fail; 1679 } 1680 return MCDisassembler::Success; 1681 1682 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 1683 FourByteBuffer = DE.getU32(Cursor); 1684 if (decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream) == 1685 MCDisassembler::Fail) { 1686 return MCDisassembler::Fail; 1687 } 1688 return MCDisassembler::Success; 1689 1690 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 1691 FourByteBuffer = DE.getU32(Cursor); 1692 if (decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream) == 1693 MCDisassembler::Fail) { 1694 return MCDisassembler::Fail; 1695 } 1696 return MCDisassembler::Success; 1697 1698 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 1699 using namespace amdhsa; 1700 TwoByteBuffer = DE.getU16(Cursor); 1701 1702 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 1703 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 1704 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 1705 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 1706 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 1707 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 1708 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 1709 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 1710 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 1711 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 1712 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 1713 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 1714 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 1715 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 1716 1717 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 1718 return MCDisassembler::Fail; 1719 1720 // Reserved for GFX9 1721 if (isGFX9() && 1722 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 1723 return MCDisassembler::Fail; 1724 } else if (isGFX10Plus()) { 1725 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 1726 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 1727 } 1728 1729 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) 1730 return MCDisassembler::Fail; 1731 1732 return MCDisassembler::Success; 1733 1734 case amdhsa::RESERVED2_OFFSET: 1735 // 6 bytes from here are reserved, must be 0. 1736 ReservedBytes = DE.getBytes(Cursor, 6); 1737 for (int I = 0; I < 6; ++I) { 1738 if (ReservedBytes[I] != 0) 1739 return MCDisassembler::Fail; 1740 } 1741 return MCDisassembler::Success; 1742 1743 default: 1744 llvm_unreachable("Unhandled index. Case statements cover everything."); 1745 return MCDisassembler::Fail; 1746 } 1747 #undef PRINT_DIRECTIVE 1748 } 1749 1750 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( 1751 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 1752 // CP microcode requires the kernel descriptor to be 64 aligned. 1753 if (Bytes.size() != 64 || KdAddress % 64 != 0) 1754 return MCDisassembler::Fail; 1755 1756 std::string Kd; 1757 raw_string_ostream KdStream(Kd); 1758 KdStream << ".amdhsa_kernel " << KdName << '\n'; 1759 1760 DataExtractor::Cursor C(0); 1761 while (C && C.tell() < Bytes.size()) { 1762 MCDisassembler::DecodeStatus Status = 1763 decodeKernelDescriptorDirective(C, Bytes, KdStream); 1764 1765 cantFail(C.takeError()); 1766 1767 if (Status == MCDisassembler::Fail) 1768 return MCDisassembler::Fail; 1769 } 1770 KdStream << ".end_amdhsa_kernel\n"; 1771 outs() << KdStream.str(); 1772 return MCDisassembler::Success; 1773 } 1774 1775 Optional<MCDisassembler::DecodeStatus> 1776 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 1777 ArrayRef<uint8_t> Bytes, uint64_t Address, 1778 raw_ostream &CStream) const { 1779 // Right now only kernel descriptor needs to be handled. 1780 // We ignore all other symbols for target specific handling. 1781 // TODO: 1782 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 1783 // Object V2 and V3 when symbols are marked protected. 1784 1785 // amd_kernel_code_t for Code Object V2. 1786 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 1787 Size = 256; 1788 return MCDisassembler::Fail; 1789 } 1790 1791 // Code Object V3 kernel descriptors. 1792 StringRef Name = Symbol.Name; 1793 if (Symbol.Type == ELF::STT_OBJECT && Name.endswith(StringRef(".kd"))) { 1794 Size = 64; // Size = 64 regardless of success or failure. 1795 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 1796 } 1797 return None; 1798 } 1799 1800 //===----------------------------------------------------------------------===// 1801 // AMDGPUSymbolizer 1802 //===----------------------------------------------------------------------===// 1803 1804 // Try to find symbol name for specified label 1805 bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst, 1806 raw_ostream &/*cStream*/, int64_t Value, 1807 uint64_t /*Address*/, bool IsBranch, 1808 uint64_t /*Offset*/, uint64_t /*InstSize*/) { 1809 1810 if (!IsBranch) { 1811 return false; 1812 } 1813 1814 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 1815 if (!Symbols) 1816 return false; 1817 1818 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { 1819 return Val.Addr == static_cast<uint64_t>(Value) && 1820 Val.Type == ELF::STT_NOTYPE; 1821 }); 1822 if (Result != Symbols->end()) { 1823 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 1824 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 1825 Inst.addOperand(MCOperand::createExpr(Add)); 1826 return true; 1827 } 1828 return false; 1829 } 1830 1831 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 1832 int64_t Value, 1833 uint64_t Address) { 1834 llvm_unreachable("unimplemented"); 1835 } 1836 1837 //===----------------------------------------------------------------------===// 1838 // Initialization 1839 //===----------------------------------------------------------------------===// 1840 1841 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 1842 LLVMOpInfoCallback /*GetOpInfo*/, 1843 LLVMSymbolLookupCallback /*SymbolLookUp*/, 1844 void *DisInfo, 1845 MCContext *Ctx, 1846 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 1847 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 1848 } 1849 1850 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 1851 const MCSubtargetInfo &STI, 1852 MCContext &Ctx) { 1853 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 1854 } 1855 1856 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 1857 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 1858 createAMDGPUDisassembler); 1859 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 1860 createAMDGPUSymbolizer); 1861 } 1862