xref: /llvm-project/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp (revision 91f503c3af190e19974f8832871e363d232cd64c) 
1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //===----------------------------------------------------------------------===//
10 //
11 /// \file
12 ///
13 /// This file contains definition for AMDGPU ISA disassembler
14 //
15 //===----------------------------------------------------------------------===//
16 
17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)?
18 
19 #include "Disassembler/AMDGPUDisassembler.h"
20 #include "AMDGPU.h"
21 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
22 #include "SIDefines.h"
23 #include "TargetInfo/AMDGPUTargetInfo.h"
24 #include "Utils/AMDGPUBaseInfo.h"
25 #include "llvm-c/Disassembler.h"
26 #include "llvm/ADT/APInt.h"
27 #include "llvm/ADT/ArrayRef.h"
28 #include "llvm/ADT/Twine.h"
29 #include "llvm/BinaryFormat/ELF.h"
30 #include "llvm/MC/MCAsmInfo.h"
31 #include "llvm/MC/MCContext.h"
32 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
33 #include "llvm/MC/MCExpr.h"
34 #include "llvm/MC/MCFixedLenDisassembler.h"
35 #include "llvm/MC/MCInst.h"
36 #include "llvm/MC/MCSubtargetInfo.h"
37 #include "llvm/Support/Endian.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/TargetRegistry.h"
41 #include "llvm/Support/raw_ostream.h"
42 #include <algorithm>
43 #include <cassert>
44 #include <cstddef>
45 #include <cstdint>
46 #include <iterator>
47 #include <tuple>
48 #include <vector>
49 
50 using namespace llvm;
51 
52 #define DEBUG_TYPE "amdgpu-disassembler"
53 
54 #define SGPR_MAX (isGFX10() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \
55                             : AMDGPU::EncValues::SGPR_MAX_SI)
56 
57 using DecodeStatus = llvm::MCDisassembler::DecodeStatus;
58 
59 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI,
60                                        MCContext &Ctx,
61                                        MCInstrInfo const *MCII) :
62   MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()),
63   TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) {
64 
65   // ToDo: AMDGPUDisassembler supports only VI ISA.
66   if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10())
67     report_fatal_error("Disassembly not yet supported for subtarget");
68 }
69 
70 inline static MCDisassembler::DecodeStatus
71 addOperand(MCInst &Inst, const MCOperand& Opnd) {
72   Inst.addOperand(Opnd);
73   return Opnd.isValid() ?
74     MCDisassembler::Success :
75     MCDisassembler::Fail;
76 }
77 
78 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op,
79                                 uint16_t NameIdx) {
80   int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx);
81   if (OpIdx != -1) {
82     auto I = MI.begin();
83     std::advance(I, OpIdx);
84     MI.insert(I, Op);
85   }
86   return OpIdx;
87 }
88 
89 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm,
90                                        uint64_t Addr, const void *Decoder) {
91   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
92 
93   // Our branches take a simm16, but we need two extra bits to account for the
94   // factor of 4.
95   APInt SignedOffset(18, Imm * 4, true);
96   int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue();
97 
98   if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2))
99     return MCDisassembler::Success;
100   return addOperand(Inst, MCOperand::createImm(Imm));
101 }
102 
103 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm,
104                                      uint64_t Addr, const void *Decoder) {
105   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
106   int64_t Offset;
107   if (DAsm->isVI()) {         // VI supports 20-bit unsigned offsets.
108     Offset = Imm & 0xFFFFF;
109   } else {                    // GFX9+ supports 21-bit signed offsets.
110     Offset = SignExtend64<21>(Imm);
111   }
112   return addOperand(Inst, MCOperand::createImm(Offset));
113 }
114 
115 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val,
116                                   uint64_t Addr, const void *Decoder) {
117   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
118   return addOperand(Inst, DAsm->decodeBoolReg(Val));
119 }
120 
121 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \
122 static DecodeStatus StaticDecoderName(MCInst &Inst, \
123                                        unsigned Imm, \
124                                        uint64_t /*Addr*/, \
125                                        const void *Decoder) { \
126   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \
127   return addOperand(Inst, DAsm->DecoderName(Imm)); \
128 }
129 
130 #define DECODE_OPERAND_REG(RegClass) \
131 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass)
132 
133 DECODE_OPERAND_REG(VGPR_32)
134 DECODE_OPERAND_REG(VRegOrLds_32)
135 DECODE_OPERAND_REG(VS_32)
136 DECODE_OPERAND_REG(VS_64)
137 DECODE_OPERAND_REG(VS_128)
138 
139 DECODE_OPERAND_REG(VReg_64)
140 DECODE_OPERAND_REG(VReg_96)
141 DECODE_OPERAND_REG(VReg_128)
142 DECODE_OPERAND_REG(VReg_256)
143 DECODE_OPERAND_REG(VReg_512)
144 
145 DECODE_OPERAND_REG(SReg_32)
146 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC)
147 DECODE_OPERAND_REG(SReg_32_XEXEC_HI)
148 DECODE_OPERAND_REG(SRegOrLds_32)
149 DECODE_OPERAND_REG(SReg_64)
150 DECODE_OPERAND_REG(SReg_64_XEXEC)
151 DECODE_OPERAND_REG(SReg_128)
152 DECODE_OPERAND_REG(SReg_256)
153 DECODE_OPERAND_REG(SReg_512)
154 
155 DECODE_OPERAND_REG(AGPR_32)
156 DECODE_OPERAND_REG(AReg_128)
157 DECODE_OPERAND_REG(AReg_512)
158 DECODE_OPERAND_REG(AReg_1024)
159 DECODE_OPERAND_REG(AV_32)
160 DECODE_OPERAND_REG(AV_64)
161 
162 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst,
163                                          unsigned Imm,
164                                          uint64_t Addr,
165                                          const void *Decoder) {
166   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
167   return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm));
168 }
169 
170 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst,
171                                          unsigned Imm,
172                                          uint64_t Addr,
173                                          const void *Decoder) {
174   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
175   return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm));
176 }
177 
178 static DecodeStatus decodeOperand_VS_16(MCInst &Inst,
179                                         unsigned Imm,
180                                         uint64_t Addr,
181                                         const void *Decoder) {
182   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
183   return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm));
184 }
185 
186 static DecodeStatus decodeOperand_VS_32(MCInst &Inst,
187                                         unsigned Imm,
188                                         uint64_t Addr,
189                                         const void *Decoder) {
190   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
191   return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm));
192 }
193 
194 static DecodeStatus decodeOperand_AReg_128(MCInst &Inst,
195                                            unsigned Imm,
196                                            uint64_t Addr,
197                                            const void *Decoder) {
198   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
199   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512));
200 }
201 
202 static DecodeStatus decodeOperand_AReg_512(MCInst &Inst,
203                                            unsigned Imm,
204                                            uint64_t Addr,
205                                            const void *Decoder) {
206   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
207   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512));
208 }
209 
210 static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst,
211                                             unsigned Imm,
212                                             uint64_t Addr,
213                                             const void *Decoder) {
214   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
215   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512));
216 }
217 
218 static DecodeStatus decodeOperand_SReg_32(MCInst &Inst,
219                                           unsigned Imm,
220                                           uint64_t Addr,
221                                           const void *Decoder) {
222   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
223   return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm));
224 }
225 
226 static DecodeStatus decodeOperand_VGPR_32(MCInst &Inst,
227                                          unsigned Imm,
228                                          uint64_t Addr,
229                                          const void *Decoder) {
230   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
231   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW32, Imm));
232 }
233 
234 #define DECODE_SDWA(DecName) \
235 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName)
236 
237 DECODE_SDWA(Src32)
238 DECODE_SDWA(Src16)
239 DECODE_SDWA(VopcDst)
240 
241 #include "AMDGPUGenDisassemblerTables.inc"
242 
243 //===----------------------------------------------------------------------===//
244 //
245 //===----------------------------------------------------------------------===//
246 
247 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) {
248   assert(Bytes.size() >= sizeof(T));
249   const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data());
250   Bytes = Bytes.slice(sizeof(T));
251   return Res;
252 }
253 
254 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table,
255                                                MCInst &MI,
256                                                uint64_t Inst,
257                                                uint64_t Address) const {
258   assert(MI.getOpcode() == 0);
259   assert(MI.getNumOperands() == 0);
260   MCInst TmpInst;
261   HasLiteral = false;
262   const auto SavedBytes = Bytes;
263   if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) {
264     MI = TmpInst;
265     return MCDisassembler::Success;
266   }
267   Bytes = SavedBytes;
268   return MCDisassembler::Fail;
269 }
270 
271 static bool isValidDPP8(const MCInst &MI) {
272   using namespace llvm::AMDGPU::DPP;
273   int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi);
274   assert(FiIdx != -1);
275   if ((unsigned)FiIdx >= MI.getNumOperands())
276     return false;
277   unsigned Fi = MI.getOperand(FiIdx).getImm();
278   return Fi == DPP8_FI_0 || Fi == DPP8_FI_1;
279 }
280 
281 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
282                                                 ArrayRef<uint8_t> Bytes_,
283                                                 uint64_t Address,
284                                                 raw_ostream &CS) const {
285   CommentStream = &CS;
286   bool IsSDWA = false;
287 
288   unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size());
289   Bytes = Bytes_.slice(0, MaxInstBytesNum);
290 
291   DecodeStatus Res = MCDisassembler::Fail;
292   do {
293     // ToDo: better to switch encoding length using some bit predicate
294     // but it is unknown yet, so try all we can
295 
296     // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2
297     // encodings
298     if (Bytes.size() >= 8) {
299       const uint64_t QW = eatBytes<uint64_t>(Bytes);
300 
301       if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) {
302         Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address);
303         if (Res) {
304           if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8)
305               == -1)
306             break;
307           if (convertDPP8Inst(MI) == MCDisassembler::Success)
308             break;
309           MI = MCInst(); // clear
310         }
311       }
312 
313       Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address);
314       if (Res && convertDPP8Inst(MI) == MCDisassembler::Success)
315         break;
316 
317       MI = MCInst(); // clear
318 
319       Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address);
320       if (Res) break;
321 
322       Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address);
323       if (Res) { IsSDWA = true;  break; }
324 
325       Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address);
326       if (Res) { IsSDWA = true;  break; }
327 
328       Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address);
329       if (Res) { IsSDWA = true;  break; }
330 
331       if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) {
332         Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address);
333         if (Res)
334           break;
335       }
336 
337       // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and
338       // v_mad_mixhi_f16 for FMA variants. Try to decode using this special
339       // table first so we print the correct name.
340       if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) {
341         Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address);
342         if (Res)
343           break;
344       }
345     }
346 
347     // Reinitialize Bytes as DPP64 could have eaten too much
348     Bytes = Bytes_.slice(0, MaxInstBytesNum);
349 
350     // Try decode 32-bit instruction
351     if (Bytes.size() < 4) break;
352     const uint32_t DW = eatBytes<uint32_t>(Bytes);
353     Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address);
354     if (Res) break;
355 
356     Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address);
357     if (Res) break;
358 
359     Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address);
360     if (Res) break;
361 
362     if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) {
363       Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address);
364       if (Res) break;
365     }
366 
367     Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address);
368     if (Res) break;
369 
370     if (Bytes.size() < 4) break;
371     const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW;
372     Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address);
373     if (Res) break;
374 
375     Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address);
376     if (Res) break;
377 
378     Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address);
379     if (Res) break;
380 
381     Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address);
382   } while (false);
383 
384   if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi ||
385               MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 ||
386               MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 ||
387               MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi ||
388               MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi ||
389               MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 ||
390               MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10)) {
391     // Insert dummy unused src2_modifiers.
392     insertNamedMCOperand(MI, MCOperand::createImm(0),
393                          AMDGPU::OpName::src2_modifiers);
394   }
395 
396   if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) {
397     int VAddr0Idx =
398         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
399     int RsrcIdx =
400         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc);
401     unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1;
402     if (VAddr0Idx >= 0 && NSAArgs > 0) {
403       unsigned NSAWords = (NSAArgs + 3) / 4;
404       if (Bytes.size() < 4 * NSAWords) {
405         Res = MCDisassembler::Fail;
406       } else {
407         for (unsigned i = 0; i < NSAArgs; ++i) {
408           MI.insert(MI.begin() + VAddr0Idx + 1 + i,
409                     decodeOperand_VGPR_32(Bytes[i]));
410         }
411         Bytes = Bytes.slice(4 * NSAWords);
412       }
413     }
414 
415     if (Res)
416       Res = convertMIMGInst(MI);
417   }
418 
419   if (Res && IsSDWA)
420     Res = convertSDWAInst(MI);
421 
422   int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
423                                               AMDGPU::OpName::vdst_in);
424   if (VDstIn_Idx != -1) {
425     int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx,
426                            MCOI::OperandConstraint::TIED_TO);
427     if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx ||
428          !MI.getOperand(VDstIn_Idx).isReg() ||
429          MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) {
430       if (MI.getNumOperands() > (unsigned)VDstIn_Idx)
431         MI.erase(&MI.getOperand(VDstIn_Idx));
432       insertNamedMCOperand(MI,
433         MCOperand::createReg(MI.getOperand(Tied).getReg()),
434         AMDGPU::OpName::vdst_in);
435     }
436   }
437 
438   // if the opcode was not recognized we'll assume a Size of 4 bytes
439   // (unless there are fewer bytes left)
440   Size = Res ? (MaxInstBytesNum - Bytes.size())
441              : std::min((size_t)4, Bytes_.size());
442   return Res;
443 }
444 
445 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const {
446   if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
447       STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
448     if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1)
449       // VOPC - insert clamp
450       insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp);
451   } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
452     int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst);
453     if (SDst != -1) {
454       // VOPC - insert VCC register as sdst
455       insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC),
456                            AMDGPU::OpName::sdst);
457     } else {
458       // VOP1/2 - insert omod if present in instruction
459       insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod);
460     }
461   }
462   return MCDisassembler::Success;
463 }
464 
465 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const {
466   unsigned Opc = MI.getOpcode();
467   unsigned DescNumOps = MCII->get(Opc).getNumOperands();
468 
469   // Insert dummy unused src modifiers.
470   if (MI.getNumOperands() < DescNumOps &&
471       AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1)
472     insertNamedMCOperand(MI, MCOperand::createImm(0),
473                          AMDGPU::OpName::src0_modifiers);
474 
475   if (MI.getNumOperands() < DescNumOps &&
476       AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1)
477     insertNamedMCOperand(MI, MCOperand::createImm(0),
478                          AMDGPU::OpName::src1_modifiers);
479 
480   return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail;
481 }
482 
483 // Note that before gfx10, the MIMG encoding provided no information about
484 // VADDR size. Consequently, decoded instructions always show address as if it
485 // has 1 dword, which could be not really so.
486 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {
487 
488   int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
489                                            AMDGPU::OpName::vdst);
490 
491   int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
492                                             AMDGPU::OpName::vdata);
493   int VAddr0Idx =
494       AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
495   int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
496                                             AMDGPU::OpName::dmask);
497 
498   int TFEIdx   = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
499                                             AMDGPU::OpName::tfe);
500   int D16Idx   = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
501                                             AMDGPU::OpName::d16);
502 
503   assert(VDataIdx != -1);
504   if (DMaskIdx == -1 || TFEIdx == -1) {// intersect_ray
505     if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16) > -1) {
506       assert(MI.getOpcode() == AMDGPU::IMAGE_BVH_INTERSECT_RAY_a16_sa ||
507              MI.getOpcode() == AMDGPU::IMAGE_BVH_INTERSECT_RAY_a16_nsa ||
508              MI.getOpcode() == AMDGPU::IMAGE_BVH64_INTERSECT_RAY_a16_sa ||
509              MI.getOpcode() == AMDGPU::IMAGE_BVH64_INTERSECT_RAY_a16_nsa);
510       addOperand(MI, MCOperand::createImm(1));
511     }
512     return MCDisassembler::Success;
513   }
514 
515   const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode());
516   bool IsAtomic = (VDstIdx != -1);
517   bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4;
518 
519   bool IsNSA = false;
520   unsigned AddrSize = Info->VAddrDwords;
521 
522   if (STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
523     unsigned DimIdx =
524         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim);
525     const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
526         AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);
527     const AMDGPU::MIMGDimInfo *Dim =
528         AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm());
529 
530     AddrSize = BaseOpcode->NumExtraArgs +
531                (BaseOpcode->Gradients ? Dim->NumGradients : 0) +
532                (BaseOpcode->Coordinates ? Dim->NumCoords : 0) +
533                (BaseOpcode->LodOrClampOrMip ? 1 : 0);
534     IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA;
535     if (!IsNSA) {
536       if (AddrSize > 8)
537         AddrSize = 16;
538       else if (AddrSize > 4)
539         AddrSize = 8;
540     } else {
541       if (AddrSize > Info->VAddrDwords) {
542         // The NSA encoding does not contain enough operands for the combination
543         // of base opcode / dimension. Should this be an error?
544         return MCDisassembler::Success;
545       }
546     }
547   }
548 
549   unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf;
550   unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u);
551 
552   bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm();
553   if (D16 && AMDGPU::hasPackedD16(STI)) {
554     DstSize = (DstSize + 1) / 2;
555   }
556 
557   // FIXME: Add tfe support
558   if (MI.getOperand(TFEIdx).getImm())
559     return MCDisassembler::Success;
560 
561   if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords)
562     return MCDisassembler::Success;
563 
564   int NewOpcode =
565       AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize);
566   if (NewOpcode == -1)
567     return MCDisassembler::Success;
568 
569   // Widen the register to the correct number of enabled channels.
570   unsigned NewVdata = AMDGPU::NoRegister;
571   if (DstSize != Info->VDataDwords) {
572     auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass;
573 
574     // Get first subregister of VData
575     unsigned Vdata0 = MI.getOperand(VDataIdx).getReg();
576     unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0);
577     Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0;
578 
579     NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0,
580                                        &MRI.getRegClass(DataRCID));
581     if (NewVdata == AMDGPU::NoRegister) {
582       // It's possible to encode this such that the low register + enabled
583       // components exceeds the register count.
584       return MCDisassembler::Success;
585     }
586   }
587 
588   unsigned NewVAddr0 = AMDGPU::NoRegister;
589   if (STI.getFeatureBits()[AMDGPU::FeatureGFX10] && !IsNSA &&
590       AddrSize != Info->VAddrDwords) {
591     unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg();
592     unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0);
593     VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0;
594 
595     auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass;
596     NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0,
597                                         &MRI.getRegClass(AddrRCID));
598     if (NewVAddr0 == AMDGPU::NoRegister)
599       return MCDisassembler::Success;
600   }
601 
602   MI.setOpcode(NewOpcode);
603 
604   if (NewVdata != AMDGPU::NoRegister) {
605     MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata);
606 
607     if (IsAtomic) {
608       // Atomic operations have an additional operand (a copy of data)
609       MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata);
610     }
611   }
612 
613   if (NewVAddr0 != AMDGPU::NoRegister) {
614     MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0);
615   } else if (IsNSA) {
616     assert(AddrSize <= Info->VAddrDwords);
617     MI.erase(MI.begin() + VAddr0Idx + AddrSize,
618              MI.begin() + VAddr0Idx + Info->VAddrDwords);
619   }
620 
621   return MCDisassembler::Success;
622 }
623 
624 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const {
625   return getContext().getRegisterInfo()->
626     getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]);
627 }
628 
629 inline
630 MCOperand AMDGPUDisassembler::errOperand(unsigned V,
631                                          const Twine& ErrMsg) const {
632   *CommentStream << "Error: " + ErrMsg;
633 
634   // ToDo: add support for error operands to MCInst.h
635   // return MCOperand::createError(V);
636   return MCOperand();
637 }
638 
639 inline
640 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const {
641   return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI));
642 }
643 
644 inline
645 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID,
646                                                unsigned Val) const {
647   const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID];
648   if (Val >= RegCl.getNumRegs())
649     return errOperand(Val, Twine(getRegClassName(RegClassID)) +
650                            ": unknown register " + Twine(Val));
651   return createRegOperand(RegCl.getRegister(Val));
652 }
653 
654 inline
655 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID,
656                                                 unsigned Val) const {
657   // ToDo: SI/CI have 104 SGPRs, VI - 102
658   // Valery: here we accepting as much as we can, let assembler sort it out
659   int shift = 0;
660   switch (SRegClassID) {
661   case AMDGPU::SGPR_32RegClassID:
662   case AMDGPU::TTMP_32RegClassID:
663     break;
664   case AMDGPU::SGPR_64RegClassID:
665   case AMDGPU::TTMP_64RegClassID:
666     shift = 1;
667     break;
668   case AMDGPU::SGPR_128RegClassID:
669   case AMDGPU::TTMP_128RegClassID:
670   // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in
671   // this bundle?
672   case AMDGPU::SGPR_256RegClassID:
673   case AMDGPU::TTMP_256RegClassID:
674     // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in
675   // this bundle?
676   case AMDGPU::SGPR_512RegClassID:
677   case AMDGPU::TTMP_512RegClassID:
678     shift = 2;
679     break;
680   // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in
681   // this bundle?
682   default:
683     llvm_unreachable("unhandled register class");
684   }
685 
686   if (Val % (1 << shift)) {
687     *CommentStream << "Warning: " << getRegClassName(SRegClassID)
688                    << ": scalar reg isn't aligned " << Val;
689   }
690 
691   return createRegOperand(SRegClassID, Val >> shift);
692 }
693 
694 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const {
695   return decodeSrcOp(OPW32, Val);
696 }
697 
698 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const {
699   return decodeSrcOp(OPW64, Val);
700 }
701 
702 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const {
703   return decodeSrcOp(OPW128, Val);
704 }
705 
706 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const {
707   return decodeSrcOp(OPW16, Val);
708 }
709 
710 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const {
711   return decodeSrcOp(OPWV216, Val);
712 }
713 
714 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const {
715   // Some instructions have operand restrictions beyond what the encoding
716   // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra
717   // high bit.
718   Val &= 255;
719 
720   return createRegOperand(AMDGPU::VGPR_32RegClassID, Val);
721 }
722 
723 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const {
724   return decodeSrcOp(OPW32, Val);
725 }
726 
727 MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const {
728   return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255);
729 }
730 
731 MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const {
732   return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255);
733 }
734 
735 MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const {
736   return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255);
737 }
738 
739 MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const {
740   return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255);
741 }
742 
743 MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const {
744   return decodeSrcOp(OPW32, Val);
745 }
746 
747 MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const {
748   return decodeSrcOp(OPW64, Val);
749 }
750 
751 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const {
752   return createRegOperand(AMDGPU::VReg_64RegClassID, Val);
753 }
754 
755 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const {
756   return createRegOperand(AMDGPU::VReg_96RegClassID, Val);
757 }
758 
759 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const {
760   return createRegOperand(AMDGPU::VReg_128RegClassID, Val);
761 }
762 
763 MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const {
764   return createRegOperand(AMDGPU::VReg_256RegClassID, Val);
765 }
766 
767 MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const {
768   return createRegOperand(AMDGPU::VReg_512RegClassID, Val);
769 }
770 
771 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const {
772   // table-gen generated disassembler doesn't care about operand types
773   // leaving only registry class so SSrc_32 operand turns into SReg_32
774   // and therefore we accept immediates and literals here as well
775   return decodeSrcOp(OPW32, Val);
776 }
777 
778 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC(
779   unsigned Val) const {
780   // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI
781   return decodeOperand_SReg_32(Val);
782 }
783 
784 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI(
785   unsigned Val) const {
786   // SReg_32_XM0 is SReg_32 without EXEC_HI
787   return decodeOperand_SReg_32(Val);
788 }
789 
790 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const {
791   // table-gen generated disassembler doesn't care about operand types
792   // leaving only registry class so SSrc_32 operand turns into SReg_32
793   // and therefore we accept immediates and literals here as well
794   return decodeSrcOp(OPW32, Val);
795 }
796 
797 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const {
798   return decodeSrcOp(OPW64, Val);
799 }
800 
801 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const {
802   return decodeSrcOp(OPW64, Val);
803 }
804 
805 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const {
806   return decodeSrcOp(OPW128, Val);
807 }
808 
809 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const {
810   return decodeDstOp(OPW256, Val);
811 }
812 
813 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const {
814   return decodeDstOp(OPW512, Val);
815 }
816 
817 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const {
818   // For now all literal constants are supposed to be unsigned integer
819   // ToDo: deal with signed/unsigned 64-bit integer constants
820   // ToDo: deal with float/double constants
821   if (!HasLiteral) {
822     if (Bytes.size() < 4) {
823       return errOperand(0, "cannot read literal, inst bytes left " +
824                         Twine(Bytes.size()));
825     }
826     HasLiteral = true;
827     Literal = eatBytes<uint32_t>(Bytes);
828   }
829   return MCOperand::createImm(Literal);
830 }
831 
832 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) {
833   using namespace AMDGPU::EncValues;
834 
835   assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX);
836   return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ?
837     (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) :
838     (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm)));
839       // Cast prevents negative overflow.
840 }
841 
842 static int64_t getInlineImmVal32(unsigned Imm) {
843   switch (Imm) {
844   case 240:
845     return FloatToBits(0.5f);
846   case 241:
847     return FloatToBits(-0.5f);
848   case 242:
849     return FloatToBits(1.0f);
850   case 243:
851     return FloatToBits(-1.0f);
852   case 244:
853     return FloatToBits(2.0f);
854   case 245:
855     return FloatToBits(-2.0f);
856   case 246:
857     return FloatToBits(4.0f);
858   case 247:
859     return FloatToBits(-4.0f);
860   case 248: // 1 / (2 * PI)
861     return 0x3e22f983;
862   default:
863     llvm_unreachable("invalid fp inline imm");
864   }
865 }
866 
867 static int64_t getInlineImmVal64(unsigned Imm) {
868   switch (Imm) {
869   case 240:
870     return DoubleToBits(0.5);
871   case 241:
872     return DoubleToBits(-0.5);
873   case 242:
874     return DoubleToBits(1.0);
875   case 243:
876     return DoubleToBits(-1.0);
877   case 244:
878     return DoubleToBits(2.0);
879   case 245:
880     return DoubleToBits(-2.0);
881   case 246:
882     return DoubleToBits(4.0);
883   case 247:
884     return DoubleToBits(-4.0);
885   case 248: // 1 / (2 * PI)
886     return 0x3fc45f306dc9c882;
887   default:
888     llvm_unreachable("invalid fp inline imm");
889   }
890 }
891 
892 static int64_t getInlineImmVal16(unsigned Imm) {
893   switch (Imm) {
894   case 240:
895     return 0x3800;
896   case 241:
897     return 0xB800;
898   case 242:
899     return 0x3C00;
900   case 243:
901     return 0xBC00;
902   case 244:
903     return 0x4000;
904   case 245:
905     return 0xC000;
906   case 246:
907     return 0x4400;
908   case 247:
909     return 0xC400;
910   case 248: // 1 / (2 * PI)
911     return 0x3118;
912   default:
913     llvm_unreachable("invalid fp inline imm");
914   }
915 }
916 
917 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) {
918   assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN
919       && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX);
920 
921   // ToDo: case 248: 1/(2*PI) - is allowed only on VI
922   switch (Width) {
923   case OPW32:
924   case OPW128: // splat constants
925   case OPW512:
926   case OPW1024:
927     return MCOperand::createImm(getInlineImmVal32(Imm));
928   case OPW64:
929     return MCOperand::createImm(getInlineImmVal64(Imm));
930   case OPW16:
931   case OPWV216:
932     return MCOperand::createImm(getInlineImmVal16(Imm));
933   default:
934     llvm_unreachable("implement me");
935   }
936 }
937 
938 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const {
939   using namespace AMDGPU;
940 
941   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
942   switch (Width) {
943   default: // fall
944   case OPW32:
945   case OPW16:
946   case OPWV216:
947     return VGPR_32RegClassID;
948   case OPW64: return VReg_64RegClassID;
949   case OPW128: return VReg_128RegClassID;
950   }
951 }
952 
953 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const {
954   using namespace AMDGPU;
955 
956   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
957   switch (Width) {
958   default: // fall
959   case OPW32:
960   case OPW16:
961   case OPWV216:
962     return AGPR_32RegClassID;
963   case OPW64: return AReg_64RegClassID;
964   case OPW128: return AReg_128RegClassID;
965   case OPW256: return AReg_256RegClassID;
966   case OPW512: return AReg_512RegClassID;
967   case OPW1024: return AReg_1024RegClassID;
968   }
969 }
970 
971 
972 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const {
973   using namespace AMDGPU;
974 
975   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
976   switch (Width) {
977   default: // fall
978   case OPW32:
979   case OPW16:
980   case OPWV216:
981     return SGPR_32RegClassID;
982   case OPW64: return SGPR_64RegClassID;
983   case OPW128: return SGPR_128RegClassID;
984   case OPW256: return SGPR_256RegClassID;
985   case OPW512: return SGPR_512RegClassID;
986   }
987 }
988 
989 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const {
990   using namespace AMDGPU;
991 
992   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
993   switch (Width) {
994   default: // fall
995   case OPW32:
996   case OPW16:
997   case OPWV216:
998     return TTMP_32RegClassID;
999   case OPW64: return TTMP_64RegClassID;
1000   case OPW128: return TTMP_128RegClassID;
1001   case OPW256: return TTMP_256RegClassID;
1002   case OPW512: return TTMP_512RegClassID;
1003   }
1004 }
1005 
1006 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const {
1007   using namespace AMDGPU::EncValues;
1008 
1009   unsigned TTmpMin =
1010       (isGFX9() || isGFX10()) ? TTMP_GFX9_GFX10_MIN : TTMP_VI_MIN;
1011   unsigned TTmpMax =
1012       (isGFX9() || isGFX10()) ? TTMP_GFX9_GFX10_MAX : TTMP_VI_MAX;
1013 
1014   return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1;
1015 }
1016 
1017 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const {
1018   using namespace AMDGPU::EncValues;
1019 
1020   assert(Val < 1024); // enum10
1021 
1022   bool IsAGPR = Val & 512;
1023   Val &= 511;
1024 
1025   if (VGPR_MIN <= Val && Val <= VGPR_MAX) {
1026     return createRegOperand(IsAGPR ? getAgprClassId(Width)
1027                                    : getVgprClassId(Width), Val - VGPR_MIN);
1028   }
1029   if (Val <= SGPR_MAX) {
1030     assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning.
1031     return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);
1032   }
1033 
1034   int TTmpIdx = getTTmpIdx(Val);
1035   if (TTmpIdx >= 0) {
1036     return createSRegOperand(getTtmpClassId(Width), TTmpIdx);
1037   }
1038 
1039   if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX)
1040     return decodeIntImmed(Val);
1041 
1042   if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX)
1043     return decodeFPImmed(Width, Val);
1044 
1045   if (Val == LITERAL_CONST)
1046     return decodeLiteralConstant();
1047 
1048   switch (Width) {
1049   case OPW32:
1050   case OPW16:
1051   case OPWV216:
1052     return decodeSpecialReg32(Val);
1053   case OPW64:
1054     return decodeSpecialReg64(Val);
1055   default:
1056     llvm_unreachable("unexpected immediate type");
1057   }
1058 }
1059 
1060 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const {
1061   using namespace AMDGPU::EncValues;
1062 
1063   assert(Val < 128);
1064   assert(Width == OPW256 || Width == OPW512);
1065 
1066   if (Val <= SGPR_MAX) {
1067     assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning.
1068     return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);
1069   }
1070 
1071   int TTmpIdx = getTTmpIdx(Val);
1072   if (TTmpIdx >= 0) {
1073     return createSRegOperand(getTtmpClassId(Width), TTmpIdx);
1074   }
1075 
1076   llvm_unreachable("unknown dst register");
1077 }
1078 
1079 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const {
1080   using namespace AMDGPU;
1081 
1082   switch (Val) {
1083   case 102: return createRegOperand(FLAT_SCR_LO);
1084   case 103: return createRegOperand(FLAT_SCR_HI);
1085   case 104: return createRegOperand(XNACK_MASK_LO);
1086   case 105: return createRegOperand(XNACK_MASK_HI);
1087   case 106: return createRegOperand(VCC_LO);
1088   case 107: return createRegOperand(VCC_HI);
1089   case 108: return createRegOperand(TBA_LO);
1090   case 109: return createRegOperand(TBA_HI);
1091   case 110: return createRegOperand(TMA_LO);
1092   case 111: return createRegOperand(TMA_HI);
1093   case 124: return createRegOperand(M0);
1094   case 125: return createRegOperand(SGPR_NULL);
1095   case 126: return createRegOperand(EXEC_LO);
1096   case 127: return createRegOperand(EXEC_HI);
1097   case 235: return createRegOperand(SRC_SHARED_BASE);
1098   case 236: return createRegOperand(SRC_SHARED_LIMIT);
1099   case 237: return createRegOperand(SRC_PRIVATE_BASE);
1100   case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
1101   case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
1102   case 251: return createRegOperand(SRC_VCCZ);
1103   case 252: return createRegOperand(SRC_EXECZ);
1104   case 253: return createRegOperand(SRC_SCC);
1105   case 254: return createRegOperand(LDS_DIRECT);
1106   default: break;
1107   }
1108   return errOperand(Val, "unknown operand encoding " + Twine(Val));
1109 }
1110 
1111 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const {
1112   using namespace AMDGPU;
1113 
1114   switch (Val) {
1115   case 102: return createRegOperand(FLAT_SCR);
1116   case 104: return createRegOperand(XNACK_MASK);
1117   case 106: return createRegOperand(VCC);
1118   case 108: return createRegOperand(TBA);
1119   case 110: return createRegOperand(TMA);
1120   case 125: return createRegOperand(SGPR_NULL);
1121   case 126: return createRegOperand(EXEC);
1122   case 235: return createRegOperand(SRC_SHARED_BASE);
1123   case 236: return createRegOperand(SRC_SHARED_LIMIT);
1124   case 237: return createRegOperand(SRC_PRIVATE_BASE);
1125   case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
1126   case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
1127   case 251: return createRegOperand(SRC_VCCZ);
1128   case 252: return createRegOperand(SRC_EXECZ);
1129   case 253: return createRegOperand(SRC_SCC);
1130   default: break;
1131   }
1132   return errOperand(Val, "unknown operand encoding " + Twine(Val));
1133 }
1134 
1135 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width,
1136                                             const unsigned Val) const {
1137   using namespace AMDGPU::SDWA;
1138   using namespace AMDGPU::EncValues;
1139 
1140   if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
1141       STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
1142     // XXX: cast to int is needed to avoid stupid warning:
1143     // compare with unsigned is always true
1144     if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) &&
1145         Val <= SDWA9EncValues::SRC_VGPR_MAX) {
1146       return createRegOperand(getVgprClassId(Width),
1147                               Val - SDWA9EncValues::SRC_VGPR_MIN);
1148     }
1149     if (SDWA9EncValues::SRC_SGPR_MIN <= Val &&
1150         Val <= (isGFX10() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10
1151                           : SDWA9EncValues::SRC_SGPR_MAX_SI)) {
1152       return createSRegOperand(getSgprClassId(Width),
1153                                Val - SDWA9EncValues::SRC_SGPR_MIN);
1154     }
1155     if (SDWA9EncValues::SRC_TTMP_MIN <= Val &&
1156         Val <= SDWA9EncValues::SRC_TTMP_MAX) {
1157       return createSRegOperand(getTtmpClassId(Width),
1158                                Val - SDWA9EncValues::SRC_TTMP_MIN);
1159     }
1160 
1161     const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN;
1162 
1163     if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX)
1164       return decodeIntImmed(SVal);
1165 
1166     if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX)
1167       return decodeFPImmed(Width, SVal);
1168 
1169     return decodeSpecialReg32(SVal);
1170   } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
1171     return createRegOperand(getVgprClassId(Width), Val);
1172   }
1173   llvm_unreachable("unsupported target");
1174 }
1175 
1176 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const {
1177   return decodeSDWASrc(OPW16, Val);
1178 }
1179 
1180 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const {
1181   return decodeSDWASrc(OPW32, Val);
1182 }
1183 
1184 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const {
1185   using namespace AMDGPU::SDWA;
1186 
1187   assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
1188           STI.getFeatureBits()[AMDGPU::FeatureGFX10]) &&
1189          "SDWAVopcDst should be present only on GFX9+");
1190 
1191   bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64];
1192 
1193   if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) {
1194     Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK;
1195 
1196     int TTmpIdx = getTTmpIdx(Val);
1197     if (TTmpIdx >= 0) {
1198       auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32);
1199       return createSRegOperand(TTmpClsId, TTmpIdx);
1200     } else if (Val > SGPR_MAX) {
1201       return IsWave64 ? decodeSpecialReg64(Val)
1202                       : decodeSpecialReg32(Val);
1203     } else {
1204       return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val);
1205     }
1206   } else {
1207     return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO);
1208   }
1209 }
1210 
1211 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const {
1212   return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ?
1213     decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val);
1214 }
1215 
1216 bool AMDGPUDisassembler::isVI() const {
1217   return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
1218 }
1219 
1220 bool AMDGPUDisassembler::isGFX9() const {
1221   return STI.getFeatureBits()[AMDGPU::FeatureGFX9];
1222 }
1223 
1224 bool AMDGPUDisassembler::isGFX10() const {
1225   return STI.getFeatureBits()[AMDGPU::FeatureGFX10];
1226 }
1227 
1228 //===----------------------------------------------------------------------===//
1229 // AMDGPUSymbolizer
1230 //===----------------------------------------------------------------------===//
1231 
1232 // Try to find symbol name for specified label
1233 bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst,
1234                                 raw_ostream &/*cStream*/, int64_t Value,
1235                                 uint64_t /*Address*/, bool IsBranch,
1236                                 uint64_t /*Offset*/, uint64_t /*InstSize*/) {
1237 
1238   if (!IsBranch) {
1239     return false;
1240   }
1241 
1242   auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo);
1243   if (!Symbols)
1244     return false;
1245 
1246   auto Result = std::find_if(Symbols->begin(), Symbols->end(),
1247                              [Value](const SymbolInfoTy& Val) {
1248                                 return Val.Addr == static_cast<uint64_t>(Value)
1249                                     && Val.Type == ELF::STT_NOTYPE;
1250                              });
1251   if (Result != Symbols->end()) {
1252     auto *Sym = Ctx.getOrCreateSymbol(Result->Name);
1253     const auto *Add = MCSymbolRefExpr::create(Sym, Ctx);
1254     Inst.addOperand(MCOperand::createExpr(Add));
1255     return true;
1256   }
1257   return false;
1258 }
1259 
1260 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream,
1261                                                        int64_t Value,
1262                                                        uint64_t Address) {
1263   llvm_unreachable("unimplemented");
1264 }
1265 
1266 //===----------------------------------------------------------------------===//
1267 // Initialization
1268 //===----------------------------------------------------------------------===//
1269 
1270 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/,
1271                               LLVMOpInfoCallback /*GetOpInfo*/,
1272                               LLVMSymbolLookupCallback /*SymbolLookUp*/,
1273                               void *DisInfo,
1274                               MCContext *Ctx,
1275                               std::unique_ptr<MCRelocationInfo> &&RelInfo) {
1276   return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo);
1277 }
1278 
1279 static MCDisassembler *createAMDGPUDisassembler(const Target &T,
1280                                                 const MCSubtargetInfo &STI,
1281                                                 MCContext &Ctx) {
1282   return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo());
1283 }
1284 
1285 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() {
1286   TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(),
1287                                          createAMDGPUDisassembler);
1288   TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(),
1289                                        createAMDGPUSymbolizer);
1290 }
1291